ON CAT24C32WE.GT3 32-kb i2c cmos serial eeprom Datasheet

CAT24C32
32-Kb I2C CMOS Serial
EEPROM
Description
The CAT24C32 is a 32−Kb CMOS Serial EEPROM devices,
internally organized as 4096 words of 8 bits each.
It features a 32−byte page write buffer and supports the Standard
(100 kHz), Fast (400 kHz) and Fast−Plus (1 MHz) I2C protocol.
External address pins make it possible to address up to eight
CAT24C32 devices on the same bus.
Features
•
•
•
•
•
•
•
•
•
•
•
Supports Standard, Fast and Fast−Plus I2C Protocol
1.7 V to 5.5 V Supply Voltage Range
32−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Schmitt Triggers and Noise Suppression Filters on I2C Bus Inputs
(SCL and SDA)
Low Power CMOS Technology
1,000,000 Program/Erase Cycles
100 Year Data Retention
Industrial and Extended Temperature Range
PDIP, SOIC, TSSOP, UDFN, US 8−lead, WLCSP 4−ball and 5−ball
Packages
This Device is Pb−Free, Halogen Free/BFR Free, and RoHS
Compliant
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UDFN8
HU4 SUFFIX
CASE 517AZ
SOIC−8
W SUFFIX
CASE 751BD
US8 *
US SUFFIX
CASE 493
PDIP−8
L SUFFIX
CASE 646AA
TSSOP−8
Y SUFFIX
CASE 948AL
WLCSP5
C5A SUFFIX
CASE 567JQ
WLCSP4
C4C SUFFIX
CASE 567JY
PIN CONFIGURATIONS (Top Views)
1
1
2
VCC
VSS
2
3
A
A
VCC
VSS
B
SCL
B
SDA
WLCSP4 (C4C)
SDA
C
WP
SCL
WLCSP5 (C5A)
1
A0
VCC
A1
WP
A2
SCL
VSS
SDA
PDIP (L), SOIC (W), TSSOP (Y),
US (US), UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
* In Development; please contact factory for availability
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 9 of this data sheet.
© Semiconductor Components Industries, LLC, 2015
June, 2015 − Rev. 24
1
Publication Order Number:
CAT24C32/D
CAT24C32
DEVICE MARKINGS
(PDIP−8)
(SOIC−8)
24C32F
AXXX
YYWWG
24C32F
A
XXX
YY
WW
G
2
Y
M
24C32F
AYMXXX
24C32F
A
Y
M
XXX
= Specific Device Code
= Assembly Location
= Last Three Digits of Assembly Lot Number
= Production Year (Last Two Digits)
= Production Week (Two Digits)
= Pd−Free designator
(WLCSP−5)
(WLCSP−4)
2
YM
B
YM
= Specific Device Code
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
B
Y
M
= Specific Device Code
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
(TSSOP−8)
(UDFN−8)
C5U
AXX
YM
C32F
AYMXXX
C32F
A
Y
M
XXX
= Specific Device Code
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of Assembly Lot Number
= Specific Device Code
= Assembly Location
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
= Last Three Digits of Assembly Lot Number
C5U
A
XX
Y
M
= Specific Device Code
= Assembly Location
= Last Two Digits of Assembly Lot Number
= Production Year (Last Digit)
= Production Month (1−9, O, N, D)
VCC
PIN FUNCTION
Pin Name
Function
SCL
A0, A1, A2
CAT24C32
A2, A1, A0
SDA
WP
VSS
Figure 1. Functional Symbol
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2
Device Address
SDA
Serial Data
SCL
Serial Clock
WP
Write Protect
VCC
Power Supply
VSS
Ground
CAT24C32
Table 1. ABSOLUTE MAXIMUM RATINGS
Parameters
Ratings
Units
Storage Temperature
–65 to +150
°C
Voltage on any Pin with Respect to Ground (Note 1)
–0.5 to +6.5
V
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The DC input voltage on any pin should not be lower than −0.5 V or higher than VCC + 0.5 V. During transitions, the voltage on any pin may
undershoot to no less than −1.5 V or overshoot to no more than VCC + 1.5 V, for periods of less than 20 ns.
Table 2. RELIABILITY CHARACTERISTICS (Note 2)
Parameter
Symbol
NEND (Note 3)
TDR
Endurance
Min
Units
1,000,000
Program/Erase Cycles
100
Years
Data Retention
2. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
3. Page Mode, VCC = 5 V, 25°C.
Table 3. D.C. OPERATING CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Test Conditions
ICCR
Read Current
Read, fSCL = 400 kHz
ICCW
Write Current
Write, fSCL = 400 kHz
Standby Current
All I/O Pins at GND or VCC
ISB
IL
I/O Pin Leakage
Min
Max
Units
1
mA
2
mA
TA = −40°C to +85°C
VCC ≤ 3.3 V
1
mA
TA = −40°C to +85°C
VCC > 3.3 V
3
TA = −40°C to +125°C
5
Pin at GND or VCC
2
mA
VIL
Input Low Voltage
VIH
Input High Voltage
−0.5
VCC x 0.3
V
SCL, SDA Inputs
VCC x 0.7
6.5
V
VOL1
Output Low Voltage
WP, A0, A1, A2 Inputs
VCC ≥ 2.5 V, IOL = 3.0 mA
VCC x 0.7
VCC + 0.5
0.4
V
VOL2
Output Low Voltage
VCC < 2.5 V, IOL = 1.0 mA
0.2
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
Table 4. PIN IMPEDANCE CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C, unless otherwise specified.)
Symbol
Parameter
Conditions
Max
Units
8
pF
CIN (Note 4)
SDA I/O Pin Capacitance
VIN = 0 V, TA = 25°C, f = 1.0 MHz
CIN (Note 4)
Input Capacitance (other pins)
VIN = 0 V, TA = 25°C, f = 1.0 MHz
6
pF
IWP (Note 5)
WP Input Current
VIN < VIH, VCC = 5.5 V
130
mA
VIN < VIH, VCC = 3.3 V
120
VIN < VIH, VCC = 1.7 V
80
VIN > VIH
2
VIN < VIH, VCC = 5.5 V
50
VIN < VIH, VCC = 3.3 V
35
VIN < VIH, VCC = 1.7 V
25
VIN > VIH
2
IA (Note 5)
Address Input Current
(A0, A1, A2)
Product Rev F
mA
4. These parameters are tested initially and after a design or process change that affects the parameter according to appropriate AEC−Q100
and JEDEC test methods.
5. When not driven, the WP, A0, A1 and A2 pins are pulled down to GND internally. For improved noise immunity, the internal pull−down is relatively
strong; therefore the external driver must be able to supply the pull−down current when attempting to drive the input HIGH. To conserve power,
as the input level exceeds the trip point of the CMOS input buffer (~ 0.5 x VCC), the strong pull−down reverts to a weak current source.
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3
CAT24C32
Table 5. A.C. CHARACTERISTICS
(VCC = 1.8 V to 5.5 V, TA = −40°C to +125°C and VCC = 1.7 V to 5.5 V, TA = −40°C to +85°C.) (Note 6)
Standard
VCC = 1.7 V − 5.5 V
Symbol
FSCL
Min
Max
Clock Frequency
Min
100
Max
Fast−Plus (Note 9)
VCC = 2.5 V − 5.5 V
TA = −405C to +855C
Min
400
Max
Units
1,000
kHz
4
0.6
0.25
ms
tLOW
Low Period of SCL Clock
4.7
1.3
0.45
ms
tHIGH
High Period of SCL Clock
4
0.6
0.40
ms
tHD:STA
START Condition Hold Time
tSU:STA
START Condition Setup Time
4.7
0.6
0.25
ms
tHD:DAT
Data In Hold Time
0
0
0
ms
tSU:DAT
Data In Setup Time
250
100
50
ns
tR (Note 7)
SDA and SCL Rise Time
1,000
300
100
ns
tF (Note 7)
SDA and SCL Fall Time
300
300
100
ns
tSU:STO
STOP Condition Setup Time
tBUF
Bus Free Time Between STOP
and START
tAA
SCL Low to Data Out Valid
tDH (Note 7)
Ti (Note 7)
Data Out Hold Time
4
0.6
0.25
ms
4.7
1.3
0.5
ms
3.5
100
0.9
100
Noise Pulse Filtered at SCL and
SDA Inputs
100
0.40
50
100
ms
ns
100
ns
tSU:WP
WP Setup Time
0
0
0
ms
tHD:WP
WP Hold Time
2.5
2.5
1
ms
tWR
tPU (Notes 7, 8)
6.
7.
8.
9.
Parameter
Fast
VCC = 1.7 V − 5.5 V
Write Cycle Time
5
5
5
ms
Power−up to Ready Mode
1
1
1
ms
Test conditions according to “A.C. Test Conditions” table.
Tested initially and after a design or process change that affects this parameter.
tPU is the delay between the time VCC is stable and the device is ready to accept commands.
Fast−Plus (1 MHz) speed class available for product revision “F”. The die revision “F” is identified by letter “F” or a dedicated marking code
on top of the package.
Table 6. A.C. TEST CONDITIONS
Input Drive Levels
0.2 x VCC to 0.8 x VCC
Input Rise and Fall Time
≤ 50 ns
Input Reference Levels
0.3 x VCC, 0.7 x VCC
Output Reference Level
0.5 x VCC
Output Test Load
Current Source IOL = 3 mA (VCC ≥ 2.5 V); IOL = 1 mA (VCC < 2.5 V); CL = 100 pF
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CAT24C32
I2C Bus Protocol
Power−On Reset (POR)
Each CAT24C32 incorporates Power−On Reset (POR)
circuitry which protects the internal logic against powering
up in the wrong state. The device will power up into Standby
mode after VCC exceeds the POR trigger level and will
power down into Reset mode when VCC drops below the
POR trigger level. This bi−directional POR behavior
protects the device against ‘brown−out’ failure following a
temporary loss of power.
The 2−wire I2C bus consists of two lines, SCL and SDA,
connected to the VCC supply via pull−up resistors. The
Master provides the clock to the SCL line, and either the
Master or the Slaves drive the SDA line. A ‘0’ is transmitted
by pulling a line LOW and a ‘1’ by letting it stay HIGH. Data
transfer may be initiated only when the bus is not busy (see
A.C. Characteristics). During data transfer, SDA must
remain stable while SCL is HIGH.
START/STOP Condition
Pin Description
SCL: The Serial Clock input pin accepts the clock signal
generated by the Master.
SDA: The Serial Data I/O pin accepts input data and delivers
output data. In transmit mode, this pin is open drain. Data is
acquired on the positive edge, and is delivered on the
negative edge of SCL.
A0, A1 and A2: The Address inputs set the device address
that must be matched by the corresponding Slave address
bits. The Address inputs are hard−wired HIGH or LOW
allowing for up to eight devices to be used (cascaded) on the
same bus. When left floating, these pins are pulled LOW
internally. The Address inputs are not available for use with
WLCSP 4−ball and 5−ball.
WP: When pulled HIGH, the Write Protect input pin
inhibits all write operations. When left floating, this pin is
pulled LOW internally. The WP input is not available for the
WLCSP 4−ball, therefore all write operations are allowed
for the device in this package.
An SDA transition while SCL is HIGH creates a START
or STOP condition (Figure 2). The START consists of a
HIGH to LOW SDA transition, while SCL is HIGH. Absent
the START, a Slave will not respond to the Master. The
STOP completes all commands, and consists of a LOW to
HIGH SDA transition, while SCL is HIGH.
Device Addressing
The Master addresses a Slave by creating a START
condition and then broadcasting an 8−bit Slave address. For
the CAT24C32, the first four bits of the Slave address are set
to 1010 (Ah); the next three bits, A2, A1 and A0, must match
the logic state of the similarly named input pins. The devices
in WLCSP (C5A and C4C) respond only to the Slave
Address with A2 A1 A0 = 0 0 0. The R/W bit tells the Slave
whether the Master intends to read (1) or write (0) data
(Figure 3).
Acknowledge
During the 9th clock cycle following every byte sent to the
bus, the transmitter releases the SDA line, allowing the
receiver to respond. The receiver then either acknowledges
(ACK) by pulling SDA LOW, or does not acknowledge
(NoACK) by letting SDA stay HIGH (Figure 4). Bus timing
is illustrated in Figure 5.
Functional Description
The CAT24C32 supports the Inter−Integrated Circuit
(I2C) Bus protocol. The protocol relies on the use of a Master
device, which provides the clock and directs bus traffic, and
Slave devices which execute requests. The CAT24C32
operates as a Slave device. Both Master and Slave can transmit
or receive, but only the Master can assign those roles.
SCL
SDA
START
CONDITION
STOP
CONDITION
Figure 2. Start/Stop Timing
1
0
1
0
A2
A1
A0
R/W
DEVICE ADDRESS*
* The devices in WLCSP 4−ball and 5−ball respond only to Slave Address byte with A2 A1 A0 = 0 0 0
Figure 3. Slave Address Bits
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5
CAT24C32
BUS RELEASE DELAY (TRANSMITTER)
SCL FROM
MASTER
1
BUS RELEASE DELAY (RECEIVER)
8
9
DATA OUTPUT
FROM TRANSMITTER
DATA OUTPUT
FROM RECEIVER
START
ACK SETUP (≥ tSU:DAT)
ACK DELAY (≤ tAA)
Figure 4. Acknowledge Timing
tHIGH
tF
tLOW
tR
tLOW
SCL
tHD:DAT
tSU:STA
tHD:SDA
tSU:DAT
tSU:STO
SDA IN
tAA
tDH
tBUF
SDA OUT
Figure 5. Bus Timing
WRITE OPERATIONS
Byte Write
Acknowledge Polling
To write data to memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘0’. The Master then sends two
address bytes and a data byte and concludes the session by
creating a STOP condition on the bus. The Slave responds
with ACK after every byte sent by the Master (Figure 6). The
STOP starts the internal Write cycle, and while this
operation is in progress (tWR), the SDA output is tri−stated
and the Slave does not acknowledge the Master (Figure 7).
As soon (and as long) as internal Write is in progress, the
Slave will not acknowledge the Master. This feature enables
the Master to immediately follow−up with a new Read or
Write request, rather than wait for the maximum specified
Write time (tWR) to elapse. Upon receiving a NoACK
response from the Slave, the Master simply repeats the
request until the Slave responds with ACK.
Hardware Write Protection
With the WP pin held HIGH, the entire memory is
protected against Write operations. If the WP pin is left
floating or is grounded, it has no impact on the Write
operation. The state of the WP pin is strobed on the last
falling edge of SCL immediately preceding the 1st data byte
(Figure 9). If the WP pin is HIGH during the strobe interval,
the Slave will not acknowledge the data byte and the Write
request will be rejected.
Page Write
The Byte Write operation can be expanded to Page Write,
by sending more than one data byte to the Slave before
issuing the STOP condition (Figure 8). Up to 32 distinct data
bytes can be loaded into the internal Page Write Buffer
starting at the address provided by the Master. The page
address is latched, and as long as the Master keeps sending
data, the internal byte address is incremented up to the end
of page, where it then wraps around (within the page). New
data can therefore replace data loaded earlier. Following the
STOP, data loaded during the Page Write session will be
written to memory in a single internal Write cycle (tWR).
Delivery State
The CAT24C32 is shipped erased, i.e., all bytes are FFh.
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6
CAT24C32
BUS ACTIVITY: S
T
A
MASTER R
T
ADDRESS
BYTE
SLAVE
ADDRESS
ADDRESS
BYTE
DATA
BYTE
a7 − a0
d7 − d0
a15 − a8
S
S
T
O
P
P
* * * *
A
C
K
A
C
K
SLAVE
*a15 − a12 are don’t care bits
A
C
K
A
C
K
Figure 6. Byte Write Sequence
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
START
CONDITION
ADDRESS
Figure 7. Write Cycle Timing
BUS
ACTIVITY: S
T
A
MASTER R
T
ADDRESS
BYTE
SLAVE
ADDRESS
DATA
BYTE
n
ADDRESS
BYTE
DATA
BYTE
n+1
S
T
O
P
DATA
BYTE
n+P
P
S
n=1
P ≤ 31
A
C
K
A
C
K
A
C
K
SLAVE
A
C
K
A
C
K
Figure 8. Page Write Sequence
ADDRESS
BYTE
DATA
BYTE
1
8
a7
a0
9
1
8
d7
d0
SCL
SDA
tSU:WP
WP
tHD:WP
Figure 9. WP Timing
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7
A
C
K
A
C
K
CAT24C32
READ OPERATIONS
Immediate Read
Write sequence by sending data, the Master then creates a
START condition and broadcasts a Slave address with the
R/W bit set to ‘1’. The Slave responds with ACK after every
byte sent by the Master and then sends out data residing at
the selected address. After receiving the data, the Master
responds with NoACK and then terminates the session by
creating a STOP condition on the bus (Figure 11).
To read data from memory, the Master creates a START
condition on the bus and then broadcasts a Slave address
with the R/W bit set to ‘1’. The Slave responds with ACK
and starts shifting out data residing at the current address.
After receiving the data, the Master responds with NoACK
and terminates the session by creating a STOP condition on
the bus (Figure 10). The Slave then returns to Standby mode.
Sequential Read
Selective Read
If, after receiving data sent by the Slave, the Master
responds with ACK, then the Slave will continue
transmitting until the Master responds with NoACK
followed by STOP (Figure 12). During Sequential Read the
internal byte address is automatically incremented up to the
end of memory, where it then wraps around to the beginning
of memory.
To read data residing at a specific address, the selected
address must first be loaded into the internal address register.
This is done by starting a Byte Write sequence, whereby the
Master creates a START condition, then broadcasts a Slave
address with the R/W bit set to ‘0’ and then sends two
address bytes to the Slave. Rather than completing the Byte
BUS ACTIVITY
MASTER
N
O
S
T
A
R
T
S
A T
CO
K P
SLAVE
ADDRESS
P
S
A
C
K
SLAVE
SCL
8
SDA
DATA
BYTE
9
8th Bit
DATA OUT
NO ACK
STOP
Figure 10. Immediate Read Sequence and Timing
BUS ACTIVITY: S
T
A
MASTER R
T
ADDRESS
BYTE
SLAVE
ADDRESS
S
T
A
R
T
ADDRESS
BYTE
S
N
O
A
C
K
SLAVE
ADDRESS
P
S
A
C
K
SLAVE
A
C
K
A
C
K
A
C
K
DATA
BYTE
Figure 11. Selective Read Sequence
N
O
A
C
K
BUS ACTIVITY:
MASTER
A
C
K
SLAVE
ADDRESS
A
C
K
A
C
K
S
T
O
P
P
SLAVE
A
C
K
DATA
BYTE
n
DATA
BYTE
n+1
DATA
BYTE
n+2
Figure 12. Sequential Read Sequence
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8
S
T
O
P
DATA
BYTE
n+x
CAT24C32
ORDERING INFORMATION
Device Order Number
Specific
Device
Marking
Package
Type
CAT24C32HU4I−GT3
C5U
UDFN8
CAT24C32HU4E−GT3
(Note 12)
C5U
CAT24C32C5ATR
Lead
Finish
Shipping
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel, 3,000 Units / Reel
UDFN8
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel, 3,000 Units / Reel
2
WLCSP5
I = Industrial
(−40°C to +85°C)
SnAgCu
Tape & Reel, 5,000 Units / Reel
CAT24C32C5CTR
P
WLCSP5 with
Die Coat
I = Industrial
(−40°C to +85°C)
SnAgCu
Tape & Reel, 5,000 Units / Reel
CAT24C32C4CTR
B
WLCSP4 with
Die Coat
I = Industrial
(−40°C to +85°C)
SnAg
Tape & Reel, 5,000 Units / Reel
CAT24C32LI−G
24C32F
PDIP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 50 Units / Tube
CAT24C32WI−G
24C32F
SOIC−8,
JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
CAT24C32WI−GT3
24C32F
SOIC−8,
JEDEC
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAT24C32WE−GT3
(Note 12)
24C32F
SOIC−8,
JEDEC
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAT24C32YI−G
C32F
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tube, 100 Units / Tube
CAT24C32YI−GT3
C32F
TSSOP−8
I = Industrial
(−40°C to +85°C)
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAT24C32YE−GT3
(Note 12)
C32F
TSSOP−8
E = Extended
(−40°C to +125°C)
NiPdAu
Tape & Reel, 3,000 Units / Reel
CAT24C32USI−T3
(In Development)
TBD
US8
I = Industrial
(−40°C to +85°C)
Matte−Tin
Tape & Reel, 3,000 Units / Reel
Temperature Range
10. All packages are RoHS−compliant (Lead−free, Halogen−free).
11. The standard lead finish is NiPdAu.
12. Please contact your nearest ON Semiconductor Sales office for availability.
13. For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
14. Caution: The EEPROM devices delivered in WLCSP must never be exposed to ultraviolet light. When exposed to ultraviolet light
the EEPROM cells lose their stored data.
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9
CAT24C32
PACKAGE DIMENSIONS
PDIP−8, 300 mils
CASE 646AA
ISSUE A
SYMBOL
MIN
NOM
A
E1
5.33
A1
0.38
A2
2.92
3.30
4.95
b
0.36
0.46
0.56
b2
1.14
1.52
1.78
c
0.20
0.25
0.36
D
9.02
9.27
10.16
E
7.62
7.87
8.25
E1
6.10
6.35
7.11
e
PIN # 1
IDENTIFICATION
MAX
2.54 BSC
eB
7.87
L
2.92
10.92
3.30
3.80
D
TOP VIEW
E
A2
A
A1
c
b2
L
e
eB
b
SIDE VIEW
END VIEW
Notes:
(1) All dimensions are in millimeters.
(2) Complies with JEDEC MS-001.
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10
CAT24C32
PACKAGE DIMENSIONS
SOIC 8, 150 mils
CASE 751BD
ISSUE O
E1
E
SYMBOL
MIN
A
1.35
1.75
A1
0.10
0.25
b
0.33
0.51
c
0.19
0.25
D
4.80
5.00
E
5.80
6.20
E1
3.80
4.00
MAX
1.27 BSC
e
PIN # 1
IDENTIFICATION
NOM
h
0.25
0.50
L
0.40
1.27
θ
0º
8º
TOP VIEW
D
h
A1
θ
A
c
e
b
L
END VIEW
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
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11
CAT24C32
PACKAGE DIMENSIONS
TSSOP8, 4.4x3
CASE 948AL
ISSUE O
b
SYMBOL
MIN
NOM
1.20
A
E1
E
MAX
A1
0.05
A2
0.80
b
0.19
0.15
0.90
1.05
0.30
c
0.09
D
2.90
3.00
0.20
3.10
E
6.30
6.40
6.50
E1
4.30
4.40
4.50
e
0.65 BSC
L
1.00 REF
L1
0.50
θ
0º
0.60
0.75
8º
e
TOP VIEW
D
A2
c
q1
A
A1
L1
SIDE VIEW
L
END VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MO-153.
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12
CAT24C32
PACKAGE DIMENSIONS
UDFN8, 2x3 EXTENDED PAD
CASE 517AZ
ISSUE O
D
b
A
e
L
DAP SIZE 1.8 x 1.8
E2
E
PIN #1
IDENTIFICATION
A1
PIN #1 INDEX AREA
D2
TOP VIEW
SIDE VIEW
SYMBOL
MIN
NOM
MAX
A
0.45
0.50
0.55
A1
0.00
0.02
0.05
A3
0.127 REF
b
0.20
0.25
0.30
D
1.95
2.00
2.05
D2
1.35
1.40
1.45
E
2.95
3.00
3.05
E2
1.25
1.30
1.35
e
L
BOTTOM VIEW
DETAIL A
0.065 REF
A3 A
FRONT VIEW
0.50 REF
0.25
0.30
0.35
A3
Notes:
(1) All dimensions are in millimeters.
(2) Refer JEDEC MO-236/MO-252.
0.0 - 0.05
DETAIL A
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13
0.065 REF
Copper Exposed
CAT24C32
PACKAGE DIMENSIONS
US8
CASE 493−02
ISSUE B
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION “A” DOES NOT INCLUDE MOLD
FLASH, PROTRUSION OR GATE BURR.
MOLD FLASH. PROTRUSION AND GATE
BURR SHALL NOT EXCEED 0.140 MM
(0.0055”) PER SIDE.
4. DIMENSION “B” DOES NOT INCLUDE
INTER−LEAD FLASH OR PROTRUSION.
INTER−LEAD FLASH AND PROTRUSION
SHALL NOT E3XCEED 0.140 (0.0055”) PER
SIDE.
5. LEAD FINISH IS SOLDER PLATING WITH
THICKNESS OF 0.0076−0.0203 MM.
(300−800 “).
6. ALL TOLERANCE UNLESS OTHERWISE
SPECIFIED ±0.0508 (0.0002 “).
−X−
A
8
J
−Y−
5
DETAIL E
B
L
1
4
R
S
G
P
U
C
−T−
SEATING
PLANE
H
0.10 (0.004) T
K
D
N
0.10 (0.004)
M
R 0.10 TYP
T X Y
V
M
DIM
A
B
C
D
F
G
H
J
K
L
M
N
P
R
S
U
V
F
DETAIL E
SOLDERING FOOTPRINT*
3.8
0.15
0.50
0.0197
1.8
0.07
0.30
0.012
1.0
0.0394
SCALE 8:1
mm Ǔ
ǒinches
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
14
MILLIMETERS
MIN
MAX
1.90
2.10
2.20
2.40
0.60
0.90
0.17
0.25
0.20
0.35
0.50 BSC
0.40 REF
0.10
0.18
0.00
0.10
3.00
3.20
0_
6_
5_
10 _
0.23
0.34
0.23
0.33
0.37
0.47
0.60
0.80
0.12 BSC
INCHES
MIN
MAX
0.075
0.083
0.087
0.094
0.024
0.035
0.007
0.010
0.008
0.014
0.020 BSC
0.016 REF
0.004
0.007
0.000
0.004
0.118
0.126
0_
6_
5_
10 _
0.010
0.013
0.009
0.013
0.015
0.019
0.024
0.031
0.005 BSC
CAT24C32
PACKAGE DIMENSIONS
WLCSP5, 1.34x0.91
CASE 567JQ
ISSUE A
E
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO THE SPHERICAL
CROWNS OF THE SOLDER BALLS.
4. DIMENSION b IS MEASURED AT THE MAXIMUM
BALL DIAMETER PARALLEL TO DATUM C.
A B
ÈÈ
ÈÈ
PIN A1
REFERENCE
D
DIE COAT
(OPTIONAL)
0.10 C
2X
0.10 C
2X
A3
A2
DIM
A
A1
A2
A3
b
D
E
e
e1
TOP VIEW
A2
DETAIL A
DETAIL A
0.10 C
A
0.05 C
A1
SIDE VIEW
NOTE 3
5X
C
RECOMMENDED
SOLDERING FOOTPRINT*
e
b
A1
e1
0.05 C A B
0.03 C
SEATING
PLANE
MILLIMETERS
MIN
MAX
−−−
0.35
0.08
0.12
0.23 REF
0.025 REF
0.16
0.20
1.34 BSC
0.91 BSC
0.40 BSC
0.693 BSC
PACKAGE
OUTLINE
5X
C
0.69
PITCH
B
A
0.18
1 2 3
BOTTOM VIEW
0.40
PITCH
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
www.onsemi.com
15
CAT24C32
PACKAGE DIMENSIONS
WLCSP4, 0.76x0.76
CASE 567JY
ISSUE O
ÈÈ
ÈÈ
A
D
PIN A1
REFERENCE
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
E
2X
0.05 C
2X
0.05 C TOP VIEW
DETAIL A
MILLIMETERS
DIM
MIN
MAX
A
−−−
0.35
A1 0.0415 0.0715
A2
0.255 REF
A3
0.025 REF
b
0.15
0.16
D
0.76 BSC
E
0.76 BSC
e
0.40 BSC
A3
DIE COAT
(OPTIONAL)
A2
DETAIL A
A2
0.05 C
A
RECOMMENDED
SOLDERING FOOTPRINT*
0.05 C
A1
NOTE 3
4X
SIDE VIEW
SEATING
PLANE
A1
PACKAGE
OUTLINE
e
b
0.05 C A B
C
e
0.40
PITCH
B
0.03 C
A
1
4X
0.40
PITCH
0.16
DIMENSIONS: MILLIMETERS
2
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
BOTTOM VIEW
ON Semiconductor is licensed by Philips Corporation to carry the I2C Bus Protocol.
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CAT24C32/D