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FDMF4061 – High Performance 60V Smart Power Stage Module Features General Description Compact size – 6.0 mm x 7.5 mm PQFN High current handling: 25A Next Generation 60V Power MOSFETs: The FDMF4061 is a compact 60V Smart Power Stage (SPS) module that is a fully optimized for use in high current switching applications. The FDMF4061 module integrates a driver IC plus two N-channel Power MOSFETs into a thermally enhanced, 6.0 mm x 7.5 mm PQFN package. The PQFN packaging provides very low package inductance and resistance improving the current handling capability and performance of the part. With an integrated approach, the complete switching power stage is optimized with regards to driver and MOSFET dynamic performance, system parasitic inductance, and Power MOSFET RDS(ON). The FDMF4061 uses Fairchild's high performance PowerTrenchTM MOSFET technology, which reduces high voltage and current stresses in switching applications. The driver IC features a low delay times and matched PWM input propagation delays, which further enhance the performance of the part. Typ. RDS(on)=2.4(HS) / 2.4(LS) mΩ at VGS=10V, ID=25A Wide driver power supply voltage range: 10V to 20V Internal pull-down resistors for PWM inputs (HI,LI) Short PWM propagation delays Under-voltage lockout (UVLO) Fully optimized system efficiency High performance low profile package Integrated 60V Half-Bridge gate driver Fairchild 60V PowerTrench® MOSFETs for clean switching waveforms and reduced ringing Low Inductance and low resistance packaging for minimal Applications Motor Drives (Power tools & Drowns etc.) Telecom Half / Full - Bridge DC-DC converters Buck-Boost Converters High-current DC-DC Point of Load (POL) converters. operating power losses Fairchild green packaging and RoHS compliant Reduced EMI due to low side flip-chip MOSFET Application Diagram RBOOT CBOOT DBOOT VDD VIN VDD HB PH VIN CVIN HI LI MCU FDMF4061 SW HO M RGH LG HO RGL HG VSS PGND Ordering Information Part Number Current Rating [A] Input Voltage [V] Frequency Max [kHz] Device Marking FDMF4061 25 60 200 FDMF4061 © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 1 FDM4061 - High Performance 60V Smart Power Stage Module September 2016 HB HI HG HO VIN UVLO Q1 POWER MOSFET (high side) 500k LEVEL SHIFT PH VDD UVLO SW VDD Q2 POWER MOSFET (low side) LI 500k VSS LO LG PGND Figure 1. Functional Block Diagram N/C 1 VDD 2 HI 3 LI 4 PGND 5 VSS 6 LG 7 LO 8 LG 9 30 VIN 31 32 VIN 33 N/C PGND 34 HG N/C 35 PH BOOT 36 N/C HO Pin Configuration 29 28 27 26 VIN 25 VIN 24 VIN PGND 37 Top View 16 17 18 19 20 21 SW 15 SW 14 SW 13 SW SW 12 SW 22 SW 11 SW PGND SW 10 SW PGND 23 PGND PGND Figure 2. Pin Configuration (6.0mm x 7.5mm Package) © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 2 FDM4061 - High Performance 60V Smart Power Stage Module Functional Block Diagram Pin Name Function 1, 29, 32, 34 N/C No connect 2 VDD Power supply input for low-side gate drive and bootstrap diode. Bypass this pin to VSS with a low impedance capacitor. 3 HI High-side PWM input. 4 LI Low-side PWM input. 5, 10,11, 22, 23, 33, 37 PGND Power return for the power stage. Package header, pin 37 and PGND are internally fused (shorted). 6 VSS Analog ground for driver IC analog circuits. 7,9 LG Low-side MOSFET gate. 8 LO Low-side gate drive output. 12-21 SW Switching node junction between high-side and Low-side MOSFETs. 24-28 VIN Power input for the power stage. Bypass this pin to PGND with low impedance capacitor. 30 HG High-side MOSFET gate. 31 PH High-side source connection (SW node) for the bootstrap capacitor. 35 HB Bootstrap supply for high-side driver. Bypass this pin to PH with low impedance capacitor. 36 HO High-side gate drive output. Table 1. Pin Definitions © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 3 FDM4061 - High Performance 60V Smart Power Stage Module Pin Definitions FDM4061 - High Performance 60V Smart Power Stage Module Typical Application Diagram CBOOT DBOOT RBOOT VDD VIN VDD HB PH VIN CVIN HI LI MCU FDMF4061 SW HO M RGH HG LO RGL LG VSS PGND Figure 3. Half-Bridge DC Motor CBOOT1 RBOOT1 DBOOT1 VDD VIN VDD HB PH VIN CVIN1 CVDD1 HI FDMF4061 LI SW HO RGH1 HG LO RGL1 LG VSS PGND MCU M CBOOT2 RBOOT1 DBOOT2 VDD VIN VDD HB PH VIN CVDD2 CVIN2 HI FDMF4061 LI SW HO RGH2 HG LO RGL2 LG VSS PGND Figure 4. Full-Bridge DC Motor © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 4 FDM4061 - High Performance 60V Smart Power Stage Module Typical Application Diagram (Continued) CBOOT1 RBOOT1 DBOOT1 VDD VIN VDD HB PH VIN CVIN1 CVDD1 HI FDMF4061 LI SW HO RGH1 HG LO RGL1 LG VSS PGND CBOOT2 RBOOT2 DBOOT2 VDD VIN VDD HB PH VIN CVIN2 CVDD2 HI MCU FDMF4061 LI M SW HO RGH2 HG LO RGL2 LG VSS PGND CBOOT3 RBOOT3 DBOOT3 VDD VIN VDD HB PH VIN CVDD3 CVIN3 HI FDMF4061 LI SW HO RGH3 HG LO RGL3 LG VSS PGND Figure 5. 3-Phase DC Motor © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 5 FDM4061 - High Performance 60V Smart Power Stage Module Typical Application Diagram (Continued) RBOOT CBOOT DBOOT VDD VIN VDD HB PH VIN CVIN HI LI PWM Controller FDMF4061 LOUT SW HO COUT RGH RLOAD HG LO RGL LG VSS PGND Figure 6. Buck Converter CBOOT DBOOT RBOOT VDD VIN VDD HB PH VIN CVIN1 HI PWM Controller HO Secondary Side Circuit SW LI FDMF4061 CVIN2 RGH HG LO RGL LG VSS PGND Figure 7. Half-Bridge Converter Typical Application Diagram (Continued) © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 6 VDD VIN VDD HB PH VIN CVIN1 CVDD1 HI FDMF4061 LI SW HO RGH1 HG LO RGL1 LG PWM Controller VSS PGND Secondary Side Circuit CBOOT2 RBOOT2 DBOOT2 VDD VIN VDD HB PH VIN CVDD2 CVIN2 HI FDMF4061 LI SW HO RGH2 HG LO RGL2 LG VSS PGND Figure 8. Full-Bridge Converter © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 7 FDM4061 - High Performance 60V Smart Power Stage Module CBOOT1 RBOOT1 DBOOT1 The “Absolute Maximum Ratings” are those values beyond which the safety of the device cannot be guaranteed. The device should not be operated at these limits. The parametric values defined in the Electrical Characteristics tables are not guaranteed at the absolute maximum ratings. The “Recommended Operating Conditions” table defines the conditions for actual device operation. Thermal resistance rating is measured under board mounted and still air conditions. Symbol Parameter Min. Max. Unit VIN Power Stage Supply Voltage Referenced to VSS -0.3 60 V VPH PH Voltage Referenced to VSS VHB-25 VHB+0.3 V VDD Driver Supply Voltage Referenced to VSS -0.3 25 V VHB Bootstrap to VSS Referenced to VSS, -0.3 85 V VLI, VHI Gate drive Input signals Referenced to VSS -0.3 VDD + 0.3V V VHO High Side driver output Referenced to PHASE VPH - 0.3V VBOOT + 0.3V V VLO Low Side driver output Referenced to VSS - 0.3 VDD + 0.3V V VHG High Side MOSFET gate Referenced to PHASE -26 28 V VLG Low Side MOSFET gate Referenced to VSS -26 28 V (1) Junction to Ambient Thermal Resistance – Q1 - 17 °C/W Junction to Ambient Thermal Resistance – Q2(1) - 15 °C/W TJ Junction Temperature - 150 °C TSTG Storage Temperature -40 150 °C JA Table 2. Module Absolute Maximum ratings (1) Mounted on a 4-layer FR4 PCB with a dissipating copper surface on the top side of 49 cm2, 2oz. Recommended Operating Conditions Symbol Min Max Unit VIN Power Stage Supply Voltage Parameters Test Condition 3 50 V VDD Driver Supply Voltage 10 20 V -0.3 60 V 6-VDD 60 V VPH + 10 VPH + 20 V - 50 V/ns -40 125 °C DC VSW, VPH SW or PHASE Repetitive Pulse (< 20ns, 10uJ) VHB dVSW/dt TJ Voltage on HB Reference to PH Voltage Slew Rate on SW Operating Temperature Table 3. Module Recommended Operating Conditions © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 8 FDM4061 - High Performance 60V Smart Power Stage Module Absolute Maximum Ratings VDD=VHB=15V, VSW =VSS=0V, VIN=30V, TJ= +25°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit Supply Currents IINQ Power Stage Quiescent Current LI = HI = 0V - - 1 uA IDDQ Driver Quiescent Current LI = HI = 0V - 67 180 uA IDDO VDD operating current FSW = 20kHz - 0.3 0.6 mA FSW = 200kHz - 2.1 4.2 mA IHBQ BOOT Quiescent current LI = HI = 0V - 38 120 uA FSW = 20kHz - 0.3 0.6 mA FSW = 200kHz - 2.4 4.8 mA IHBO BOOT Operating current Under-Voltage Protection VDDR, VHBR UVLO rising threshold VDD or VHB-VPH rising threshold 8.2 9.5 10.0 V VDDF, VHBF 7.6 8.9 9.6 V 0.6 - V - - 10 us 1.2 - - V UVLO falling threshold VDD or VHB-VPH falling Threshold VDDH UVLO Hysteresis VDD Hysterisis tD_POR POR delay to Enable IC UVLO rising to internal PWM enable Control Inputs (TTL: LI, HI) VIL Low Level Input Voltage VIH High Level Input Voltage - - 2.9 V VHYS Input Voltage Hysteresis VDD = 10V to 20V - 1.0 - V RIN Input Pull-Down Resistance - 468 - k LI LowHIGH to LO LowHIGH, VIH to 10% LG 100 153 300 ns tLPHL LI HighLow to LO HighLow, VIL to 90% LG 100 208 300 ns tHPLH HI LowHIGH to HO LowHIGH,VIH to 10% HG-PH 100 170 300 ns HI HighLow to HO HighLow, VIL to 90% HG-PH 100 205 300 ns - - 50 ns PWM input (HI,LI) tLPLH LI to LO Propagation Delays HI to HO Propagation Delays tHPHL MT Delay matching, HS and LS turn-on/off tPW Minimum Input Pulse Width that Changes the Output LI/HI Rising to Vth of Q1,Q2 RG=0 75 ns LI/HI Falling to Vth of Q1,Q2 RG=0 130 ns High-Side Driver (HDRV) (VDD = VHB = 15V) ISOURCE_HO ISINK_HO Output Sourcing Peak current VHO=0V 250 350 Output Sinking Peak current VHO=15V - mA 500 650 - mA tR_HG Rise Time GH=10% to 90%, RGH=0 - 356 711 ns tF_HG Fall Time GH=90% to 10%, RGH=0 - 151 302 ns Low-Side Driver (LDRV) (VDD = VHB = 15V) ISOURCE_LO ISINK_LO Output Sourcing Peak current VLO=0V 250 350 - mA Output Sinking Peak current VLO=15V 500 650 - mA tR_LG Rise Time GL=10% to 90%, RGL=0 - 346 692 ns tF_LG Fall Time GL=90% to 10%, RGL=0 - 142 283 ns Table 4. Module Electrical Specifications © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 9 FDM4061 - High Performance 60V Smart Power Stage Module Electrical Specifications: TJ= +25°C unless otherwise noted. Symbol Parameter Condition Min. Typ. Max. Unit 60 - - V High Side MOSFET, Q1 BVDSS Drain-Source Breakdown Voltage IDS=250uA, VGS=0V IDSS Zero Gate Voltage Drain Current VDS=48V, VGS=0V - - 1 uA IGSS Gate-Source Leakage Current VDS=0V, VGS=+/-20V - - 100 nA VGS(th) Gate-Source Threshold Voltage VDS=VGS , IDS=250uA 2.5 3.7 4.5 V RDS(ON) Drain –Source On-Resistance VGS=10V, IDS=25A - 2.4 3.2 mΩ QG Total Gate Charge - 56 78 nC QGS Gate-Source Charge - 23 - nC - 8 - nC VGS=0V to 10V, VDD=30V, IDS=25A QGD Gate-Drain “Miller” Charge QOSS Total Output Charge - 65 - nC RG Series Gate Resistance - 1.0 - Ω VHG-VPH=0V, ISD = 2A - 0.7 1.2 VHG-VPH=0V, ISD = 25A - 0.8 1.3 - 58 117 ns - 51 103 nC - 44 88 ns - 79 158 nC 60 - - V - - 1 uA Drain-Source Diode Characteristics VSD Source to Drain Forward Voltage tRR Reverse Recovery Time QRR Reverse Recovery Charge tRR Reverse Recovery Time QRR Reverse Recovery Charge IF = 25A, diF/dt = 100A/us IF = 25A, diF/dt = 300A/us V Low Side MOSFET, Q2 BVDSS Drain-Source Breakdown Voltage IDS=250uA, VGS=0V IDSS Zero Gate Voltage Drain Current VDS=48V, VGS=0V IGSS Gate-Source Leakage Current VDS=0V, VGS=+/-20V - - 100 nA VGS(th) Gate-Source Threshold Voltage VDS=VGS , IDS=250uA 2.5 3.5 4.5 V RDS(ON) Drain –Source On-Resistance VGS=10V, IDS=25A - 2.4 3.2 mΩ QG Total Gate Charge - 59 82 nC QGS Gate-Source Charge - 25 - nC QGD Gate-Drain “Miller” Charge - 11 - nC QOSS Total Output Charge - 63 - nC RG Series Gate Resistance - 1.0 - Ω VHG-VPH=0V, ISD = 2A - 0.7 1.2 VHG-VPH=0V, ISD = 25A - 0.8 1.3 - 57 114 ns - 52 105 nC - 43 86 ns - 81 161 nC VGS=0V to 10V, VDD=30V, IDS=25A Drain-Source Diode Characteristics VSD Source to Drain Forward Voltage tRR Reverse Recovery Time QRR Reverse Recovery Charge tRR Reverse Recovery Time QRR Reverse Recovery Charge IF = 25A, diF/dt = 100A/us IF = 25A, diF/dt = 300A/us V Table 5. FDMF4061 MOSFET Electrical Specifications © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 10 FDM4061 - High Performance 60V Smart Power Stage Module Power MOSFET specifications (FDMF4061) Tj = 25°C unless otherwise noted. 95 100 90 80 VDD=VHB=15V VSS=0V VIH=VIL=0V 85 70 80 60 75 IDDQ [μA] IDDQ [μA] 90 VHB=15V VSS=0V VIH=VIL=0V 50 40 70 65 30 60 20 55 10 50 45 0 0 5 10 15 20 -40 -20 0 Supply Voltage [V] VDD=15V VSS=0V VIH=VIL=0V 60 IHBQ [μA] IHBQ [μA] 70 50 40 30 20 10 0 0 5 10 15 54 52 50 48 46 44 42 40 38 36 34 32 30 28 26 80 100 120 VDD=15V VSS=0V VIH=VIL=0V -40 20 -20 0 20 40 60 80 100 120 Temperature [℃] Supply Voltage [V] Figure 11. . IHBQ vs. Supply Voltage(VDD) Figure 12. IHBQ vs. Temp. 300 300 VDD=VHB VSS=0V RG=0Ω 275 250 Turn-On Propagation Delay [ns] Turn-On Propagation Delay [ns] 60 Figure 10. IDDQ vs. Temp. 100 80 40 Temperature [℃] Figure 9. IDDQ vs. Supply Voltage(VDD) 90 20 225 200 tHPLH 175 150 tLPLH 125 VDD=VHB=15V VSS=0V RG=0Ω 275 250 225 200 tHPLH 175 150 tLPLH 125 100 75 100 50 10 12 14 16 Supply Voltage [V] 18 20 -40 Figure 13. Turn-On Propagation Delay vs. Supply Voltage(VDD) © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 -20 0 20 40 60 80 Temperature [℃] 100 120 Figure 14. Turn-On Propagation Delay vs. Temp. www.fairchildsemi.com 11 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics Tj = 25°C unless otherwise noted. 300 VDD=VHB VSS=0V RG=0Ω 275 250 225 Turn-Off Propagation Delay [ns] Turn-Off Propagation Delay [ns] 300 tHPHL 200 tLPHL 175 150 125 100 VDD=VHB=15V VSS=0V RG=0Ω 275 250 tHPHL 225 tLPHL 200 175 150 125 10 12 14 16 18 20 -40 -20 0 20 Supply Voltage [V] Figure 15. Turn-Off Propagation Delay vs. Supply Voltage(VDD) 60 80 100 120 Figure 16. Turn-Off Propagation Delay vs. Temp. 400 500 375 Turn-On Rising Time [nsec] Turn-On Rising Time [nsec] 40 Temperature [℃] tR_HG 350 tR_LG 325 300 VDD=VHB VSS=0V RG=0Ω 275 475 VDD=VHB=15V VSS=0V 450 RG=0Ω 425 400 375 tR_LG 350 325 tR_HG 300 275 250 250 10 12 14 16 18 -40 20 -20 0 Supply Voltage [V] 20 40 60 80 100 120 Temperature [℃] Figure 17. Turn-On Rising Time vs. Supply Voltage(VDD) Figure 18. Turn-On Rising Time vs. Temp. 200 240 tF_HG 160 Turn-Off Falling Time [ns] Turn-Off Falling Time [ns] 180 140 tF_LG 120 100 80 60 40 VDD=VHB VSS=0V 20 RG=0Ω VDD=VHB=15V VSS=0V RG=0Ω 220 200 180 tF_HG 160 tF_LG 140 120 100 0 10 12 14 16 Supply Voltage [V] 18 -40 20 Figure 19. Turn-Off Falling Time vs. Supply Voltage(VDD) © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 -20 0 20 40 60 80 Temperature [℃] 100 120 Figure 20. Turn-Off Falling Time vs. Temp. www.fairchildsemi.com 12 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Continued) 440 500 480 460 440 420 400 380 360 340 320 300 280 260 240 220 200 180 VDD=VHB VSS=0V VHO=VLO=0V VDD=VHB=15V VSS=0V VHO=VLO=0V 420 Output Sourcing Current [mA] Output Sourcing Current [mA] Tj = 25°C unless otherwise noted. ISOURCE_LO ISOURCE_HO 400 380 360 ISOURCE_LO 340 ISOURCE_HO 320 300 280 260 10 12 14 16 18 -40 20 -20 0 60 80 100 120 Figure 22. Output Sourcing Current vs. Temp. 700 675 650 625 600 575 550 525 500 475 450 425 400 375 350 325 300 800 VDD=VHB=15V VSS=0V VLO=VDD,VHO=VHB 750 Output Sinking Current [mA] Output Sinking Current [mA] 40 Figure 21. Output Sourcing Current vs. Supply Voltage(VDD) ISINK_HO ISINK_LO VDD=VHB VSS=0V VLO=VDD,VHO=VHB 700 650 600 ISINK_HO 550 ISINK_LO 500 450 400 10 12 14 16 Supply Voltage [V] 18 20 -40 -20 0 20 40 60 80 100 120 Temperature [℃] Figure 23. Output Sinking Current vs. Supply Voltage(VDD) Figure 24. Output Sinking Current vs. Temp. 600 600 VDD=VHB VSS= VPH=0V VIH=VIL=5V VOH=VHB - VHO, (VDD - VLO) IL=20mA 550 525 500 500 475 450 425 VDD=VHB=15V VSS= VPH=0V VIH=VIL=5V VOH=VHB - VHO, (VDD - VLO) IL=20mA 550 VOH [mV] 575 VOH [mV] 20 Temperature [℃] Supply Voltage [V] High-Side 450 High-Side 400 Low-Side 400 350 375 Low-Side 350 300 325 300 250 10 12 14 16 18 20 -40 Supply Voltage [V] -20 0 20 40 60 80 100 120 Temperature [℃] Figure 25. High-Level Output Voltage Deviation Figure 26. High-Level Output Voltage Deviation from the VBH(VDD) vs. Supply Voltage(VDD) from the VBH(VDD) vs. Temp. © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 13 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Continued) Tj = 25°C unless otherwise noted. 200 230 VDD=VHB VSS= VPH=0V VIH=VIL=0V VOL=VHO - VPH, (VLO - VSS) IL=20mA 190 180 190 VOL [mV] VOL [mV] 170 160 High-Side 150 High-Side 150 Low-Side 110 130 120 90 10 12 14 16 Supply Voltage [V] 18 20 -40 -20 0 100 120 Figure 28. Low-Level Output Voltage Deviation from the VPH(VSS) vs. Supply Voltage(VDD) from the VPH(VSS) vs. Temp. 10 10 9.8 9.8 VDDR 9.6 9.4 VHBR 9.4 VDD [V] 9.2 VDDF 9 9.2 9 8.8 8.8 8.6 8.6 8.4 8.4 8.2 8.2 8 VHBF 8 -40 -20 0 20 40 60 80 100 120 -40 -20 0 Temperature [℃] IN+ IN- 5 10 15 20 3.4 3.2 3 2.8 2.6 2.4 2.2 2 1.8 1.6 1.4 1.2 1 0.8 0.6 0.4 0.2 0 60 80 100 120 VIH_HI & VIH_LI VIL_HI & VIL_LI -40 Supply Voltage [V] Figure 31. IN+ IN- vs. Supply Voltage. © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 40 Figure 30. VHB UVLO Threshold Voltage vs. Temp. Input Logic Threshold Voltage [V] 27 25 23 21 19 17 15 13 11 9 7 5 3 1 -1 0 20 Temperature [℃] Figure 29. VDD UVLO Threshold Voltage vs. Temp. IN+/IN- [μA] 20 40 60 80 Temperature [℃] Figure 27. Low-Level Output Voltage Deviation 9.6 VDD [V] 170 130 Low-Side 140 VDD=VHB=15V VSS= VPH=0V VIH=VIL=0V VOL=VHO - VPH, (VLO - VSS) IL=20mA 210 -20 0 20 40 60 80 Temperature [℃] 100 120 Figure 32. Input Logic Threshold Voltage vs. Temp. www.fairchildsemi.com 14 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Continued) Tj = 25°C unless otherwise noted. 45 50 VIN=50V, VDD=10V, 16V VOUT=25V, 35 30 25 20 15 10 50Vi25Vo10Vg 5 50Vi25Vo16Vg VIN=40V, VDD=10V, 16V VOUT=20V, Tj≤125’C 45 Tj≤125’C Module Output Current, IOUT[A] Module Output Current, IOUT[A] 40 40 35 30 25 20 15 40Vi20Vo10Vg 10 40Vi20Vo16Vg 5 0 0 40 80 120 160 Switching Frequency, FSW[kHz] 200 40 Figure 33. Static SOA, VIN=50V 80 120 160 Switching Frequency, FSW[kHz] Figure 34. Static SOA, VIN=40V 8.0 10 VIN=50V, VDD=16V VOUT=25V, FSW=100kHz, IOUT=25A VIN=50V, VOUT=25V, FSW=100kHz, IOUT=20A Module Power Loss, PLMOD[W] Module Power Loss, PLMOD[W] 200 7.5 7.0 6.5 8 6 4 2 0 6.0 30 60 90 Dead-time [ns] 120 10 150 Figure 35. Module Power Loss vs. TDEAD 12 14 Gate Voltage [V] 16 18 Figure 36. Module Power Loss vs. VGS 50 48 Output Current[A] 46 44 42 40 38 36 VIN=48V, VDD=13V, TJ=125°C, TA=25°C, PF=0.78 Sine-Triangle Comparison, DM=1 34 32 30 10 100 Carrier Frequency [kHz] Figure 37. Output Current Vs. Carrier or Modulation Frequency © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 15 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Continued) Tj = 25°C unless otherwise noted. 180 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 150 ID, DRAIN CURRENT (A) 10 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX VGS = 10 V 120 VGS = 8 V 90 VGS = 6 V 60 30 VGS = 5 V 0 0.0 0.5 1.0 1.5 VDS, DRAIN TO SOURCE VOLTAGE (V) 2.0 6 VGS = 6 V 4 VGS = 8 V 2 VGS = 10 V 0 30 60 90 120 150 180 ID, DRAIN CURRENT (A) Figure 39. Normalized On-Resistance vs. Drain Current and Gate Voltage 1.6 50 ID = 25 A 1.5 VGS = 10 V rDS(on), DRAIN TO 1.4 1.3 1.2 1.1 1.0 0.9 0.8 0.7 -75 -50 -25 0 25 50 75 100 125 SOURCE ON-RESISTANCE (m ) NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 8 0 Figure 38. On Region Characteristics 150 IS, REVERSE DRAIN CURRENT (A) VDS = 5 V 120 TJ = 150 oC TJ = 25 oC 30 TJ = -55 oC 3 4 5 6 7 8 9 10 TJ = 125 oC 10 TJ = 25 oC 6 8 10 180 100 VGS = 0 V 10 1 TJ = 150 oC 0.1 TJ = 25 oC 0.01 TJ = -55 oC 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) Figure 42. Transfer Characteristics © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 20 0.001 0.0 0 2 30 Figure 41. On-Resistance vs. Gate to Source Voltage PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 60 ID = 25 A VGS, GATE TO SOURCE VOLTAGE (V) 180 90 40 4 Figure 40. Normalized On Resistance vs. Junction Temperature 150 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 0 TJ, JUNCTION TEMPERATURE (oC) ID, DRAIN CURRENT (A) PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX Figure 43. Source to Drain Diode Forward Voltage vs. Source Current www.fairchildsemi.com 16 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Q1 N-Channel) Tj = 25°C unless otherwise noted. 10000 VDD = 30 V ID = 25 A Ciss 8 VDD = 40 V VDD = 20 V 6 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 4 2 1000 Coss 100 10 Crss f = 1 MHz VGS = 0 V 0 0 10 20 30 40 50 1 0.1 60 1 10 60 VDS, DRAIN TO SOURCE VOLTAGE (V) Qg, GATE CHARGE (nC) Figure 44. Gate Charge Characteristics Figure 45. Capacitance vs. Drain to Source Voltage 100 80 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) 1000 VGS = 10 V 60 40 20 10 us 100 100 us 10 1 1 ms SINGLE PULSE TJ = MAX RATED 10 ms o RJC = 3.42 C/W o RJC = 3.42 C/W 0 25 THIS AREA IS LIMITED BY rDS(on) 50 o TC = 25 C 75 100 125 0.1 0.1 150 o TC, CASE TEMPERATURE ( C) 1 CURVE BENT TO MEASURED DATA DC 10 100 VDS, DRAIN to SOURCE VOLTAGE (V) Figure 47. Forward Bias Safe Operating Area Figure 46. Maximum Continuous Drain Current vs. Case Temperature P(PK), PEAK TRANSIENT POWER (W) 100000 SINGLE PULSE o RJC = 3.48 C/W 10000 o TC = 25 C 1000 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) Figure 48. Single Pulse Maximum Power Dissipation © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 17 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Q1 N-Channel) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE Tj = 25°C unless otherwise noted. 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 -5 10 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 49. Junction-to-Case Transient Thermal Response Curve © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 18 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Q1 N-Channel) Tj = 25°C unless otherwise noted. 20 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE ID, DRAIN CURRENT (A) 200 160 VGS = 10 V 120 VGS = 8 V 80 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX VGS = 6 V 40 0 0.0 0.2 0.4 0.6 0.8 1.0 VGS = 6 V 15 10 5 0 0 100 150 200 Figure 51. Normalized On-Resistance vs. Drain Current and Gate Voltage 50 ID = 25 A 1.7 VGS = 10 V rDS(on), DRAIN TO 1.6 1.5 1.4 1.3 1.2 1.1 1.0 0.9 SOURCE ON-RESISTANCE (m ) 1.8 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 50 ID, DRAIN CURRENT (A) Figure 50. On-Region Characteristics 40 30 20 10 TJ = 125 oC 0.8 0.7 -75 TJ = 25 oC 0 -50 -25 0 25 50 75 4 100 125 150 IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX 160 VDS = 5 V 120 oC 80 TJ = 25 oC 40 TJ = -55 oC 6 7 8 9 7 8 9 10 VGS = 0 V 10 1 TJ = 150 oC TJ = 25 oC 0.1 0.01 TJ = -55 oC 0.2 0.4 0.6 0.8 1.0 1.2 VSD, BODY DIODE FORWARD VOLTAGE (V) VGS, GATE TO SOURCE VOLTAGE (V) Figure 54. Transfer Characteristics © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 200 100 0.001 0.0 0 5 6 Figure 53. On-Resistance vs. Gate to Source Voltage 200 4 5 VGS, GATE TO SOURCE VOLTAGE (V) Figure 52. Normalized On Resistance vs. Junction Temperature TJ = 150 PULSE DURATION = 80 s DUTY CYCLE = 0.5% MAX ID = 25 A TJ, JUNCTION TEMPERATURE (oC) ID, DRAIN CURRENT (A) VGS = 10 V VGS = 8 V VDS, DRAIN TO SOURCE VOLTAGE (V) 3 PULSE DURATION = 80s DUTY CYCLE = 0.5% MAX Figure 55. Source to Drain Diode Forward Voltage vs. Source Current www.fairchildsemi.com 19 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Q2 N-Channel) Tj = 25°C unless otherwise noted. 10000 VDD = 30 V ID = 25 A Ciss 8 CAPACITANCE (pF) VGS, GATE TO SOURCE VOLTAGE (V) 10 VDD = 40 V VDD = 20 V 6 4 2 0 0 12 24 36 48 1000 Coss 100 1 10 60 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 56. Gate Charge Characteristics Figure 57. Capacitance vs. Drain to Source Voltage 1000 100 80 ID, DRAIN CURRENT (A) ID, DRAIN CURRENT (A) f = 1 MHz VGS = 0 V 1 0.1 60 Qg, GATE CHARGE (nC) VGS = 10 V 60 40 20 100 10 1 10 us THIS AREA IS LIMITED BY rDS(on) 100 us SINGLE PULSE TJ = MAX RATED 1 ms 10 ms o RJC = 3.48 C/W o RJC = 3.48 C/W 0 25 Crss 10 50 o TC = 25 C 75 100 125 0.1 0.1 150 o 1 CURVE BENT TO MEASURED DATA DC 10 100 VDS, DRAIN to SOURCE VOLTAGE (V) TC, CASE TEMPERATURE ( C) Figure 59. Forward Bias Safe Operating Area Figure 58. Maximum Continuous Drain Current vs. Case Temperature P(PK), PEAK TRANSIENT POWER (W) 100000 SINGLE PULSE o RJC = 3.48 C/W 10000 o TC = 25 C 1000 100 10 -5 10 -4 10 -3 10 -2 10 -1 10 1 t, PULSE WIDTH (sec) Figure 60. Single Pulse Maximum Power Dissipation © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 20 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Q2 N-Channel) r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE Tj = 25°C unless otherwise noted. 2 1 0.1 DUTY CYCLE-DESCENDING ORDER D = 0.5 0.2 0.1 0.05 0.02 0.01 0.01 SINGLE PULSE 0.001 -5 10 -4 10 -3 -2 10 10 -1 10 1 t, RECTANGULAR PULSE DURATION (sec) Figure 61. Junction-to-Case Transient Thermal Response Curve © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 21 FDMF4061 - High Performance 60V Smart Power Stage Module Typical Performance Characteristics (Q2 N-Channel) Driver Output State (HO/LO) The FDMF4061 is a non-inverting 60V halfbridge Smart Power Stage (SPS) module. The module packages a driver IC die along with pair of equally sized (matched R DSON) 60V TM PowerTrench N-Channel MOSFETs (Standard gate thresholds refer to Table 5). The FDMF4061 module provides separate power input pins; the power stage input (VIN) and the gate driver input (VDD). The power stage input (VIN) accepts a wide operating from 3V to 50V, while the gate driver input (VDD) requires 10V to 20V. The module accepts TTL compatible inputs (HI/LI) along with anti-cross conduction circuitry to protect against over-lapping PWM (HI/LI) pulses. The module (driver IC) also implements UVLO circuitry in both the VDD-VSS and BOOT-PH power domains. Disabled 7.6 10.0 VDD-VSS, BOOT-PH (Volts) Figure 62. Min/Max UVLO thresholds PWM Input Stage The FDMF4061 incorporates a PWM input gate drive design, where the low side drive output (LO) and high side drive output (HO) are controlled through independent PWM inputs (LI and HI, respectively). Power-Up and UVLO Operation UVLO circuits are implemented in both the VDD-VSS and HB-PH power domains. During power-up, the VDD-VSS UVLO circuit forces HO and LO low until the VDD supply voltage exceeds the UVLO rising threshold (9.2V typ.). The module (driver IC) will begin responding to PWM pulses once VDD exceeds the UVLO threshold. The UVLO circuit does contain hysteresis (~0.6V) to prevent noise from interfering with normal operation. An additional UVLO circuit is implemented on the HB-PH pins which will hold HO low until HB-PH > (9.2V typ.). The HB-PH UVLO also incorporates hysteresis (~0.6V). VDD BOOT UVLO UVLO Enabled The module (driver IC) can be used with TTL compatible input signals. The input signals can also be driven with voltage levels that are lower than the VDD supply level. The VDD supply level does NOT affect the input threshold levels (VIH and VIL). VIH VIL Driver State 0 X Disabled (GH, GL=0) 1 0 GL follows PWM , GH=0) 1 1 Enabled (GH/GL follow PWM) HI / LI HG / LG Table 6. UVLO Truth Table Figure 63. PWM threshold definitions - VIH = PWM trip level to flip state from LOW to HIGH. - VIL = PWM trip level to flip state from HIGH to LOW. © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 22 FDMF4061 - High Performance 60V Smart Power Stage Module Functional Description The driver IC output stage is designed to drive a pair of N-channel MOSFETs. The driver outputs (LO, HO) are non-inverting and will follow the PWM input commands (LI, HI respectively). The LO and HO outputs are capable of sinking and sourcing up to 0.65/0.35A peak current respectively. Timing Diagram tHPHL HI 90% tHPLH tR_GH HO tF_GH 10% tLPHL LI tLPLH 90% tR_GL LO tF_GL 10% SW Figure 64. PWM Timing Diagram (LI / HI signals) © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 23 FDMF4061 - High Performance 60V Smart Power Stage Module The driver output stage is also capable of providing a rail (VDD) to rail (VSS) output voltage level when driving the Power MOSFETs. Depending on the end application, the output voltage level can be set to aide in optimizing MOSFET and driver IC power losses. The driver output voltage level can also be used to help adjust SW node edge rates. Driver Output Stage The FDMF4061 is designed as a non-inverting power stage, where the Power MOSFET response (SW node) is designed to follow to HI/LI commands. The device is well-suited to be used in a wide variety of applications, such as: Half and Full-Bridge DC-DC converters, Active Clamp Forward converters, rectifier circuits, and motor drive power stages. However, various applications and topologies can place unique stresses on the module. There are a few basic power-stage requirements needed to ensure proper operation. H-bridge Motor Drive In this operating mode, it allows bi-directional current flow through motor by enabling diagonal MOSFETs to make current flow in one or the other direction. Inductor current will not tolerate abrupt changes either when charged or discharged and alternate path is required to protect switches during dead-time. The path can be made either MOSFET body-diode conducting as soon as switches are disabled or enabling opposite high-side or low-side switch to carry the recirculation current while avoiding shootthrough. Utilizing MOSFET channel is often much more efficient way to handle the decaying current due to lower conduction power loss than body-diode forward drop loss. As previously mentioned, the FDMF4061 is a multi-chip module (MCM). The module consists of three die (HS MOSFET, LS MOSFET and driver IC). Each die dissipates heat in normal operation resulting from power loss. The power MOSFETs can generate power loss from conduction and switching losses while the driver IC dissipated loss from bias, boot diode conduction and from the driver output stage sinking and sourcing power MOSFET gate currents and operating frequency. The amount of heat dissipated by any die is largely dependent on the operating conditions. The close physical placement of the three die inside of the package translates into strong thermal coupling between die. Ideally, a thermal camera should be used to monitor the FDMF4061 during the engineering development phase. This can help ensure the module operates within the absolute maximum ratings specified in this datasheet. FDMF4061 VIN Q1 Q1 SW SW Q2 Q2 PGND Figure 65. H-bridge motor drive FDMF4061 Power Dissipation The maximum motor drive current can be obtained from estimating total power dissipation of motor driver. There are a number of factors which limit actual current level such as motor ratting, driver IC, PCB construction, ambient temperature and given application. All of power dissipation components must be considered to get reliable operation at the specific application. There is obvious power dissipations listed below in single H-bridge motor application. Operating Modes The FDMF4061 can reliably operate while driving various load impedances. However, the relatively large number of applications can result in the module operating in various modes. Common applications such as switching power converters and motor drives can place the FDMF4061 into different operating modes. The various operating modes will change the response of the MOSFET voltage and current stresses and power losses as well as the gate driver dead time response. A few operating modes are listed below. © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 Forward drive Reverse drive Dead-Time(body-conduction) FDMF4061 Module Power Dissipation • Conduction loss – Generally biggest power loss which is dissipated due to the RDSON and its temperature coefficient must be considered in the calculation PCOND (rDS(ON) -HS_temp rDS(ON) -LS_temp ) IOUT 2 www.fairchildsemi.com 24 FDMF4061 - High Performance 60V Smart Power Stage Module Application Information: Switching losses - Rising and falling time by parasitic inductance can be measured in the application, listed below assumed zero inductance. Continuous current flowing out of SW node. Continuous current flowing out of the module SW node is typical of a heavily loaded switchedmode power stage that is operating in a synchronous buck converter topology. In this mode, the power stage is supplying current from VIN into an inductive load. Figure 66 shows and example of a synchronous buck convert operating in CCM with positive inductor current. Switching OFF loss PSW(OFF) ( VIN I DS(OFF) t OFF 2 ) FSW where : t OFF (Q GS2 Q GD )/i G(OFF) ; i G(OFF) VPLATEAU /(R GH R DRV_OFF) Switching ON loss PSW(ON) ( VIN I DS(ON) t ON 2 RBOOT HB where : PH VIN VIN VDD t ON (Q GS2 Q GD )/i G(ON) ; CVIN VDD Q1 i G(ON) VPLATEAU /(R G R DRV_ON) PWM Controller Gate drive loss PGATE QG VDRV FSW HI LI FDMF4061 IL Qoss Output Charge • CBOOT DBOOT Qoss VIN ) FSW 2 SW VOUT LFILTER COUT Q2 RLOAD PGND HO RGH Quiescent current power loss – Current is still drawn from the VDD and HB pins for internal and level shifting circuitry without load (RG=Open). Power loss by quiescent current is LO RGL LG VSS 0A time Figure 66. Synchronous Buck Operating in CCM with positive inductor current PQuiescent VDD I DDQ VHB I HBQ • HG IL (A) • VOUT Supply current power loss(RG=0Ω) is During this operating mode, the HS MOSFET (Q1) will undergo hard-switched inductive turn-on and turn-off events, while LS MOSFET (Q2) will undergo soft switching and body diode recovery. Hard-switching often results in large switching spikes on Q1 and Q2 V DS as well as PH to VSS and BOOT to VSS pins. Peak switching spikes are often positively correlated to load current. Psupply VDD I DDO VHB I HBO • Total power loss in the FDMF4061 is equal to the power dissipation caused by gate driver and Power MOSFETs, Ptotal PCond PSW PGate Psupply Once the designer estimates power dissipation in the gate driver and MOSFETs, junction temperature can be calculated using thermal resistance (JA) and ambient temperature as followings and also can calculate maximum allowable motor current: Continuous current flowing into SW node. Tj TA (JA Ptotal ) Continuous current flowing into the module SW node is typical of a heavily loaded switched-mode power stage that is operating in a synchronous boost converter topology. Continuous inductor current flowing in to the module SW node is typical operation of a synchronous boost converter, as shown in Figure 67. © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 25 FDMF4061 - High Performance 60V Smart Power Stage Module • DBOOT HB PH VIN (pin) VIN Q1 Q1 HI Input from controller RLOAD LI LFILTER DGH_OFF CIN LO RGL_OFF RGH DGL_OFF IL (A) HG LO PGND HG PGND HO RLOAD COUT Q2 RGH_ON RGH_OFF VIN Q2 VOUT LFILTER RGL_ON FDMF4061 SW SW HO IL VOUT CVIN VDD VOUT COUT VDD LI VIN IL VDD HI PH VDD CBOOT DBOOT HB PWM Controller CBOOT FDMF4061 RBOOT RBOOT LG VSS RGL LG VSS 0A time Figure 68. Gate drive resistor-diode circuit Figure 67. Synchronous Boost Converter operating in CCM From a module perspective, the main difference here versus the previous (buck) operating mode is that this situation will cause the LS FET (Q2) to act as the control MOSFET and hard switch while the HS FET (Q1) acts as a synchronous rectifier and undergoes soft switching with body diode recovery. This type of operation can drastically change power losses dissipated in Q1 and Q2 versus buck operating mode. CGD x dVDS/dt turn-on CGD x dVDS/dt turn-on is a false (unwanted) turn-on event that often creates a brief and uncontrolled shoot through current between the HS (Q1) and LS (Q2) MOSFETs. Typically, a C GD x dVDS/dt “shoot-through” condition arises from capacitive feedback current flowing through CGD into C GS inducing a gate-bounce-induced channel turn-on of the MOSFET. Holding the gate below threshold can become challenging because the highfrequency capacitive displacement current from C GD (due to dV DS/dt) couples back to circuit ground through the gate electrode. dVDS/dt control using external gate resistors The FDMF4061 also provides module pins for placing external gate resistors. The module provides pins for the HO and LO signals (driver output signals) and the HG and LG (Power MOSFET gate pins). Resistors can be placed in series with the MOSFET gate to control the SW node edge rates. Ld_LS RDRIVE_LS Independently controlling MOSFET (slower) turn-on and (faster) turn-off slew rates can also be accomplished by using the resistor and diode circuit shown in Figure 68. LG_brd CGD LG_pack RG Q2 CGS ZGate_Drv ~ R + L ZMOS_Gate ~ 1/C Ls_LS Figure 69. CGD x dVDS/dt current flow © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 26 FDMF4061 - High Performance 60V Smart Power Stage Module However, similar operation can arise when a switching converter (such as a synchronous buck) is pulling energy from the output filter capacitors and delivering the energy back to the input filter capacitors. FDMF4061 - High Performance 60V Smart Power Stage Module The gate-to-ground impedance is the parallel combination of the gate drive (Z G_DRV) and the MOSFET gate-to-source (Z MOS_Gate) paths. As dVDS/dt increases, the more favorable path for displacement current is through the capacitive gate-source (CGS) path versus the highly inductive and resistive gate drive loop. So impedence through gate driver should be minimized. The severity of the shoot through current is difficult to predict. © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 27 FDMF4061 - High Performance 60V Smart Power Stage Module Physical Dimensions Figure 70. Clip Bond PQFN 6.0mm x 7.5mm Package Dimensions Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the warranty therein, which covers Fairchild products. Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings: http://www.fairchildsemi.com/packaging/. © 2016 Fairchild Semiconductor Corporation FDMF4061 Rev.1.0 www.fairchildsemi.com 28 ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries. ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein. 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