ATMEL ATV2500H-25JI High-density uv-erasable programmable logic device Datasheet

Features
• Third Generation Programmable Logic Structure
– Easily Achieves Gate Utilization Factors of 80 Percent
• Increased Logic Flexibility
– 86 Inputs and 72 Sum Terms
• Flexible Output Macrocell
•
•
•
•
•
•
•
– 48 Flip-Flops - 2 per Macrocell
– 3 Sum Terms - Can Be OR'ed and Shared
High-Speed
Low-Power — Less than 0.5 mA Typical (ATV2500L)
Multiple Feedback Paths Provide for Buried State Machines
and I/O Bus Compatibility
Asynchronous Clocks and Resets
– Multiple Synchronous Presets - One per Four or Eight Flip-Flops
Proven and Reliable High Speed CMOS EPROM Process
– 2000V ESD Protection
– 200 mA Latchup Immunity
Reprogrammable - Tested 100% for Programmability
40-pin Dual-In-line and 44-Lead Surface Mount Packages
High-Density
UV-Erasable
Programmable
Logic Device
Block Diagram
ATV2500H
ATV2500L
Description
The ATV2500H/L is the most powerful programmable logic device available in a 40pin package. Increased product terms, sum terms, and flip-flops translate into many
more usable gates. High gate utilization is easily obtainable.
The ATV2500H/L is organized around a global bus. All pin and feedback terms are
always available to every logic cell. Each of the 38 logic pins and their complements
are array inputs, as well as the true and false outputs of each of the 48 flip-flops.
(continued)
Pin Configurations
I/O
Bidirectional Buffers
I/O, 0,2,4..
“Even” I/O Buffers
I/O, 1,3,5..
“Odd” I/O Buffers
*
No Internal Connection
VCC
+5V Supply
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
IN
IN
IN
IN
I/O6
I/O7
I/O8
I/O9
I/O10
I/O11
GND
I/O23
I/O22
I/O21
I/O20
I/O19
I/O18
IN
IN
IN
I/O1
I/O0
*
IN
IN
IN
IN
IN
IN
IN
I/O06
Logic Inputs
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
I/O2
I/O3
I/O4
I/O5
VCC
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
6
5
4
3
2
1
44
43
42
41
40
IN
IN
IN
IN
I/O0
I/O1
I/O2
I/O3
I/O4
I/O5
VCC
I/O17
I/O16
I/O15
I/O14
I/O13
I/O12
IN
IN
IN
IN
7
8
9
10
11
12
13
14
15
16
17
39
38
37
36
35
34
33
32
31
30
29
18
19
20
21
22
23
24
25
26
27
28
Function
PLCC/LCC
I/O7
I/O8
I/O9
I/O10
I/O11
GND
GND
I/O23
I/O22
I/O21
I/O20
I/O12
IN
IN
IN
IN
IN
IN
IN
*
I/O18
I/O19
Pin Name
DIP
* = No Connect
Rev. 0025E–05/98
1
There are 416 product terms available. Four product terms
are input to each sum term. The three sum terms per logic
cell can be combined to provide up to twelve product terms,
combinatorial and registered. Independent of output configuration, the two flip-flops are always usable, and always
have at least four product term inputs.
Functional Logic Diagram ATV2500H/L
2
ATV2500H/L
Product terms are available providing asynchronous
resets, flip-flop clocks, and output enables. One reset and
one clock term are provided per flip-flop, with one enable
term per output. Eight product terms provide local synchronous presets, divided up into banks of four and eight flipflops. Register preload and buried register observability
simplify testing. The device has an internal power up clear
function.
ATV2500H/L
Functional Logic Diagram Description
The ATV2500H/L Functional Logic Diagram describes the
interconnections between the input, feedback pins and
logic cells. All interconnections are routed through the global bus.
The ATV2500H/L is a straightforward and uniform PLD.
The twenty-four macrocells are numbered 0 through 23.
Each macrocell contains 17 AND gates. All AND gates
have 172 inputs. The five lower product terms provide AR1,
CK1, CK2, AR2, and OE. These are: one asynchronous
reset and clock per flip-flop, and an output enable. The top
twelve product terms are grouped into three sum terms,
which are used as shown in the macrocell diagrams.
Eight synchronous preset terms are distributed in a 2/4 pattern. The first four macrocells share Preset 0, the next two
share Preset 1, and so on, ending with the last two macrocells sharing Preset 7.
The fourteen dedicated inputs and their complements use
the numbered positions in the global bus as shown. Each
macrocell provides six inputs to the global bus: (left to right)
flip-flop Q2 true and false, flip-flop Q1 true and false, and
the pin true and false. The positions occupied by these signals in the global bus are the six numbers in the bus diagram next to each macrocell.
Absolute Maximum Ratings*
Temperature Under Bias ............................... -55°C to + 125°C
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect device
reliability.
Note:
Minimum voltage is -0.6V dc, which may undershoot to -2.0V for pulses of less than 20 ns. Maximum output pin voltage is Vcc + 0.75V dc, which
may overshoot to 7.0V for pulses of less than 20
ns.
Storage Temperature .................................... -65°C to + 150°C
Voltage on Any Pin with
Respect to Ground .........................................-2.0V to +7.0V(1)
Voltage on Input Pins
with Respect to Ground
During Programming.....................................-2.0V to +14.0V(1)
Programming Voltage with
Respect to Ground .......................................-2.0V to +14.0V(1)
Integrated UV Erase Dose.............................. 7258 W.sec/cm2
1.
3
Output Logic, Registered
Output Logic, Combinatorial
These diagrams show equivalent logic functions, not necessarily the actual circuit implementation.
Terms In
S2
S1
S0
D1
D2
Terms In
Output Configuration
S2
S1
S0
D1
Output Configuration
4
Combinatorial (8 Terms)
0
0
0
8
4
Registered (Q1)
1
0
0
0
1
0
12
4(1)
Registered (Q1)
1
0
1
4
4
Combinatorial (4 Terms)
0
(1)
(1)
Combinatorial (12 Terms)
Note:
1. These 4 terms are shared with D1.
1
1
Note:
S3
Output Configuration
4
D2
(1)
4
4
1. These 4 terms are shared with D1.
S3
Output Configuration
0
Active Low
0
Active Low
1
Active High
1
Active High
DC and AC Operating
Operating
Temperature
(Case)
ATV2500H-25
ATV2500H/L-30
ATV2500H/L-35
0°C - 70°C
0°C - 70°C
0°C - 70°C
Ind.
-40°C - 85°C
-40°C - 85°C
-40°C - 85°C
Mil.
-55°C - 125°C
-55°C - 125°C
-55°C - 125°C
5V ± 10%
5V ± 10%
5V ± 10%
Com.
VCC Power Supply
4
ATV2500H/L
ATV2500H/L
DC Characteristics
Symbol
Parameter
Condition
ILI
Input Load Current
ILO
ICC
Min
Max
Units
VIN = -0.1V to VCC + 1V
10
µA
Output Leakage
Current
VOUT = -0.1V to VCC + 0.1V
10
µA
Power Supply
Current
VCC = MAX,
VIN = GND or VCC
Outputs Open
ATV2500L
ATV2500H
Typ
Com.
0.5
5
mA
Ind.,Mil.
0.5
10
mA
Com.
80
160
mA
Ind.,Mil.
80
180
mA
-120
mA
IOS(1)
Output Short
Circuit Current
VIL
Input Low Voltage
-0.6
0.8
V
VIH
Input High Voltage
2.0
VCC + 0.75
V
VOL
Output Low Voltage
VIN = VIH or VIL,
IOL = 8 mA Com,Ind; 6 mA Mil.
0.5
V
VOH
Output High Voltage
IOH = -100 µA
VCC - 0.3
V
IOH = -4.0 mA
2.4
V
Note:
VOUT = 0.5V
1. Not more than one output at a time should be shorted. Duration of short circuit test should not exceed 30 sec. This parameter is only sampled and is not 100% tested. See Absolute Maximum Ratings.
Pin Capacitance (f = MHz, T = 25°°C)(1)
Typ
Max
Units
Conditions
CIN
4
6
pF
VIN = OV
COUT
8
12
pF
VOUT = OV
Note:
1. Typical values for nominal supply voltage. This parameter is only sampled and is not 100% tested.
5
AC Waveforms(1)
Note:
1.
Timing measurement reference is 1.5V. Input AC driving levels are 0.0V and 3.0V, unless otherwise specified.
AC Characteristics for the ATV2500L
ATV2500L-30
Symbol
Parameter
tPD
Input or Feedback to
Non-Registered Output
tEA
Min
Max
Units
30
35
ns
Input to Output Enable
30
35
ns
tER
Input to Output Disable
30
35
ns
tCO
Clock to Output
5
30
5
35
ns
tCF
Clock to Feedback
10
20
15
20
ns
tSI1
Input Setup Time, Output Register
20
22
ns
tSI2
Input Setup
Time, Buried Register(1)
20
22
ns
tSF
Feedback Setup Time
10
15
ns
tH1
Hold Time, Output Register
10
15
ns
5
5
ns
(1)
Max
ATV2500L-35
Min
tH2
Hold Time, Buried Register
tW
Clock Width
15
17
ns
tP
Clock Period
30
35
ns
FMAX
Maximum Frequency (1/tP)
tAW
Asynchronous Reset Width
18
20
ns
tAR
Asynchronous Reset Recovery Time
18
20
ns
tAP
Asynchronous Reset to
Registered Output Reset
Note:
6
33
30
28
35
MHz
ns
1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial.
ATV2500H/L
ATV2500H/L
AC Characteristics for the ATV2500H
ATV2500H-25
Max
Min
Parameter
Max
Units
tPD
Input or Feedback to
Non-Registered Output
25
30
35
ns
tEA
Input to Output Enable
25
30
35
ns
tER
Input to Output Disable
25
30
35
ns
tCO
Clock to Output
10
25
12
30
15
35
ns
tCF
Clock to Feedback
10
18
12
20
15
20
ns
tSI1
Input Setup
Time, Output Register
10
12
15
ns
tSI2
Input Setup
Time, Buried Register(1)
5
5
5
ns
tSF
Feedback Setup Time
7
10
15
ns
tH1
Hold Time
5
5
5
ns
tW
Clock Width
10
12
15
ns
tP
Clock Period
25
30
35
ns
FMAX
Maximum Frequency (1/tP)
tAW
Asynchronous Reset
Width
15
18
20
ns
tAR
Asynchronous Reset
Recovery Time
15
18
20
ns
tAP
Asynchronous Reset to
Registered Output Reset
40
25
Max
ATV2500H-35
Symbol
Note:
Min
ATV2500H-30
Min
33
30
28
35
MHz
ns
1. Buried registers include all 24 Q2 registers and any of the 24 Q1 registers in macrocells configured as combinatorial.
Input Test Waveforms and
Measurement Levels
Output Test Loads
tR, tF < 5 ns (10% to 90%)
7
Preload and Observability of Registered Outputs
The ATV2500H/L's registers are provided with circuitry to
allow loading of each register asynchronously with either a
high or a low. This feature will simplify testing since any
state can be forced into the registers to control test
sequencing. A VIH level on the Odd I/O pins will force the
appropriate register high; a VIL will force it low, independent
of the polarity or other configuration bit settings.
The preload state is entered by placing an 11V to 14V signal on pin 38 on the DIP and pin 42 on the SMP. When the
Level forced on Odd
I/O pin during
preload cycle.
clock term is pulsed high, (pin 21 on the DIP, pin 23 on the
SMP) the data on the I/O pins is placed into the 12 registers chosen by the Q select and even/odd select pins.
Register 2 observability mode is entered by placing an 11V
to 14V signal on pin 2 (DIP or SMP). In this mode, the contents of the buried register bank will appear on the associated outputs when the OE control signals are active.
Q Select
pin state
Even/
Odd select
Even Q1 state
after cycle
Even Q2 state
after cycle
Odd Q1 state
after cycle
Odd Q2 state
after cycle
VIH
Low
Low
High
X
X
X
VIL
Low
Low
Low
X
X
X
VIH
High
Low
X
High
X
X
VIL
High
Low
X
Low
X
X
VIH
Low
High
X
X
High
X
VIL
Low
High
X
X
Low
X
VIH
High
High
X
X
X
High
VIL
High
High
X
X
X
Low
Power-Up Reset
The registers in the ATV2500H/L are designed to reset during power-up. At a point delayed slightly from VCC crossing
3.8V, all registers will be reset to the low state. The output
state will depend on the polarity of the output buffer.
This feature is critical for state machine initialization. However, due to the asynchronous nature of reset and the
uncertainty of how VCC actually rises in the system, the following conditions are required:
1. The VCC rise must be monotonic,
2. After reset occurs, all input and feedback setup
times must be met before driving the clock term
high,
3. The signals from which the clock is derived must
remain stable during tPR.
8
ATV2500H/L
Parameter
Description
tPR
Power-Up
Reset Time
Min
Typ
Max
Units
600
1000
ns
ATV2500H/L
Security Fuse Usage
A single fuse is provided to prevent unauthorized copying
of the ATV2500H/L fuse patterns. Once programmed, the
outputs will read programmed during verify. The security
fuse should be programmed last, as its effect is immediate.
The security fuse also inhibits preload and Q2 observability.
Atmel CMOS PLDs
Atmel's Erasable Programmable Logic Devices utilize an
advanced 1.25-micron CMOS EPROM technology. This
technology's state of the art features are the optimum combination for PLDs:
• CMOS technology provides high speed, low power, and
high noise immunity.
• EPROM technology is the most cost effective method for
producing PLDs - surpassing bipolar fusible link
technology in low cost, while providing the necessary
reprogrammability.
• EPROM reprogrammability, which is 100% tested before
shipment, provides inherently better programmability and
reliability than one-time fusible PLDs.
• Atmel's EPROM process has proven extremely reliable
in the volume production of a full line of advanced
EPROM memory products, from 64K to one-megabit
devices.
Using the ATV2500H/L's Many
Advanced Features
The ATV2500H/L's flexibility puts more usable gates in 40
pins than other PLDs. Some of the ATV2500H/L's key features are:
• Asynchronous Clocks Each of the flip-flops in the ATV2500H/L has a dedicated
product term driving the clock. The user is no longer constrained to using one clock for all the registers. Buried state
machines, counters, and registers can all coexist in one
device, while running on separate clocks. The ATV2500H/L
clock period matches that of similar synchronous devices.
• A Total of 48 Registers The ATV2500H/L provides two flip-flops for each output
macrocell - a total of 48. Each register has its own clock
and reset product terms, as well as its own sum term.
• Independent I/O Pin and Feedback Paths Each I/O pin on the ATV2500/H has a dedicated input path.
Each of the 48 registers has individual feedback terms into
the array. This feature, combined with individual product
terms for each I/O's output enable, facilitates designs using
bi-directional I/O buses.
• Three Sum Terms per Macrocell The ATV2500H/L macrocell can be configured with one
SUM term feeding the output, and still have two SUM terms
feeding the flip-flops. This is the simplest method for interfacing with an I/O bus, and no flip-flops need be sacrificed.
• Combinable Sum Terms Each output macrocell's three SUM terms can be combined
in an OR gate before the output or the register. This provides up to twelve product terms per output or flip-flop.
When the registered output configuration is chosen, eight
terms are automatically available to D1. The four terms
feeding D2 can also be shared with D1, giving it a total of
twelve. In the combinatorial mode, four, eight, or twelve
terms can feed the output, with the middle four still driving
D1 and the bottom four still driving D2.
Programming Software Support
Software which is capable of transforming Boolean equations, state machine descriptions and truth tables into
JEDEC files for the ATV2500H/L is currently available from
several PLD software vendors. Please refer to the Programmable Logic Development Tools section for a complete listing of the PLD software support.
Erasure Characteristics
The entire memory array of an ATV2500H/L is erased after
exposure to ultraviolet light at a wavelength of 2537 Å.
Complete erasure is assured after a minimum of twenty
minutes exposure using 12,000 µW/cm 2 intensity lamps
spaced one inch away from the chip. Minimum erase time
for lamps at other intensity ratings can be calculated from
the minimum integrated erasure dose of fifteen W•sec/cm2.
To prevent unintentional erasure, an opaque label is recommended to cover the clear window on any UV erasable
PLD which will be subjected to continuous fluorescent
indoor lighting or sunlight.
9
Note:
10
All normalized values referenced to maximum specification in AC characteristics section of datasheet.
ATV2500H/L
ATV2500H/L
11
Ordering Information
tPD
(ns)
tCO
(ns)
fMAX
(MHz)
25
25
40
30
35
25
12
30
35
25
33
28
40
Ordering Code
Package
ATV2500H-25DC
ATV2500H-25JC
ATV2500H-25KC
ATV2500H-25LC
ATV2500H-25PC
40DW6
44J
44KW
44LW
40P6
Commercial
(0°C to 70°C)
ATV2500H-25DI
ATV2500H-25JI
ATV2500H-25KI
ATV2500H-25LI
ATV2500H-25PI
40DW6
44J
44KW
44LW
40P6
Industrial
(-40°C to 85°C)
ATV2500H-25DM
ATV2500H-25KM
ATV2500H-25LM
40DW6
44KW
44LW
Military
(-55°C to 125°C)
ATV2500H-25DM/883
ATV2500H-25KM/883
ATV2500H-25LM/883
40DW6
44KW
44LW
Military/883C
(-55°C to 125°C)
Class B, Fully Compliant
ATV2500H-30DC
ATV2500H-30JC
ATV2500H-30KC
ATV2500H-30LC
ATV2500H-30PC
40DW6
44J
44KW
44LW
40P6
Commercial
(0°C to 70°C)
ATV2500H-30DI
ATV2500H-30JI
ATV2500H-30KI
ATV2500H-30LI
ATV2500H-30PI
40DW6
44J
44KW
44LW
40P6
Industrial
(-40°C to 85°C)
ATV2500H-35DC
ATV2500H-35JC
ATV2500H-35KC
ATV2500H-35LC
ATV2500H-35PC
40DW6
44J
44KW
44LW
40P6
Commercial
(0°C to 70°C)
ATV2500H-35DI
ATV2500H-35JI
ATV2500H-35KI
ATV2500H-35LI
ATV2500H-35PI
40DW6
44J
44KW
44LW
40P6
Industrial
(-40°C to 85°C)
5962-91545 02M QA
5962-91545 02M XX
5962-91545 02M YX
40DW6
44LW
44KW
Military/833C
(-55°C to 125°C)
Class B, Fully Compliant
ATV2500H/L
Operation Range
ATV2500H/L
Ordering Information (Continued)
tPD
(ns)
tCO
(ns)
fMAX
(MHz)
30
30
33
35
30
35
30
28
33
Ordering Code
Package
ATV2500L-30DC
ATV2500L-30JC
ATV2500L-30KC
ATV2500L-30LC
ATV2500L-30PC
40DW6
44J
44KW
44LW
40P6
Operation Range
Commercial
(0°C to 70°C)
ATV2500L-30DI
ATV2500L-30JI
ATV2500L-30KI
ATV2500L-30LI
ATV2500L-30PI
40DW6
44J
44KW
44LW
40P6
Industrial
(-40°C to 85°C)
ATV2500L-30DM
ATV2500L-30KM
ATV2500L-30LM
40DW6
44KW
44LW
Military
(-55°C to 125°C)
ATV2500L-30DM/883
ATV2500L-30KM/883
ATV2500L-30LM/883
40DW6
44KW
44LW
Military
(-55°C to 125°C)
Class B, Fully Compliant
ATV2500L-35DC
ATV2500L-35JC
ATV2500L-35KC
ATV2500L-35LC
ATV2500L-35PC
40DW6
44J
44KW
44LW
40P6
Commercial
(0°C to 70°C)
ATV2500L-35DI
ATV2500L-35JI
ATV2500L-35KI
ATV2500L-35LI
ATV2500L-35PI
40DW6
44J
44KW
44LW
40P6
Industrial
(-40°C to 85°C)
5962-91545 03M QA
5962-91545 03M XX
5962-91545 03M YX
40DW6
44LW
44KW
Military/833C
(-55°C to 125°C)
Class B, Fully Compliant
Package Type
40DW6
40-Lead, 0.600" Wide Windowed, Ceramic Dual In-line Package (Cerdip)
44J
44-Lead, Plastic J-Leaded Chip Carrier OTP (PLCC)
44KW
44-Lead, Windowed, Ceramic J-Leaded Chip Carrier (JLCC)
44LW
44-Pad, Windowed, Ceramic Leadless Chip Carrier (LCC)
40P6
40-Lead, 0.600" Wide Plastic Dual In-line Package OTP (PDIP)
13
Packaging Information
40DW6, 40-Lead, 0.600" Wide Windowed, Ceramic
Dual In-line Package (Cerdip)
Dimensions in Inches and (Millimeters)
44J, 44-Lead, Plastic J-Leaded Chip Carrier OTP
(PLCC)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 D-5 CONFIG A
.045(1.14) X 45°
PIN NO. 1
IDENTIFY
.045(1.14) X 30° - 45°
.012(.305)
.008(.203)
.630(16.0)
.590(15.0)
.656(16.7)
SQ
.650(16.5)
.032(.813)
.026(.660)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
.021(.533)
.013(.330)
.043(1.09)
.020(.508)
.120(3.05)
.090(2.29)
.180(4.57)
.165(4.19)
.022(.559) X 45° MAX (3X)
44KW, 44-Lead, Windowed, Ceramic J-Leaded Chip
Carrier (JLCC)
Dimensions in Inches and (Millimeters)
44LW, 44-Pad, Windowed, Ceramic Leadless Chip
Carrier (LCC)
Dimensions in Inches and (Millimeters)
MIL-STD-1835 C-J1
MIL-STD-1835 C-5
.035(.889) X 45°
.010(.254)
.006(.152)
.045(1.14) X 45°
.032(.813)
.026(.660)
.630(16.0)
.590(15.0)
.665(16.9)
SQ
.645(16.4)
.695(17.7)
SQ
.685(17.4)
.050(1.27) TYP
.500(12.7) REF SQ
.021(.533)
.017(.432)
.045(1.14)
.035(.889)
.120(3.05)
.090(2.29)
.180(4.57)
.156(3.96)
.025(.635) RADIUS MAX (3X)
14
ATV2500H/L
ATV2500H/L
Packaging Information
40P6, 40-Lead, 0.600" Wide Plastic Dual Inline
Package OTP (PDIP)
Dimensions in Inches and (Millimeters)
JEDEC STANDARD MS-001 AC
2.07(52.6)
2.04(51.8)
PIN
1
.566(14.4)
.530(13.5)
.090(2.29)
MAX
1.900(48.26) REF
.220(5.59)
MAX
.005(.127)
MIN
SEATING
PLANE
.065(1.65)
.015(.381)
.022(.559)
.014(.356)
.161(4.09)
.125(3.18)
.110(2.79)
.090(2.29)
.012(.305)
.008(.203)
.065(1.65)
.041(1.04)
.630(16.0)
.590(15.0)
0 REF
15
.690(17.5)
.610(15.5)
15