TI1 ADC12010 12-bit, 10 msps, 160 mw a/d converter with internal sample-and-hold Datasheet

ADC12010
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ADC12010 12-Bit, 10 MSPS, 160 mW A/D Converter with Internal Sample-and-Hold
Check for Samples: ADC12010
FEATURES
DESCRIPTION
•
•
•
The ADC12010 is a monolithic CMOS analog-todigital converter capable of converting analog input
signals into 12-bit digital words at 10 Megasamples
per second (MSPS), minimum. This converter uses a
differential, pipeline architecture with digital error
correction and an on-chip sample-and-hold circuit to
minimize die size and power consumption while
providing excellent dynamic performance. Operating
on a single 5V power supply, this device consumes
just 160 mW at 10 MSPS, including the reference
current. The Power Down feature reduces power
consumption to 25 mW.
1
23
•
•
Internal sample-and-hold
Outputs 2.4V to 5V compatible
Pin compatible with ADC12020, ADC12040,
ADC12L063 and ADC12L066
On-chip reference buffer
Power down mode
APPLICATIONS
•
•
•
•
•
•
•
Image Processing Front End
Instrumentation
PC-Based Data Acquisition
Fax Machines
Wireless Local Loops/Cable Modems
Waveform Digitizers
DSP Front Ends
KEY SPECIFICATIONS
•
•
•
•
•
•
Resolution 12 Bits
Conversion Rate 10 MSPS (min)
DNL ±0.3 LSB (typ)
ENOB (fIN = 10.1 MHz) 11.3 bits (typ)
Supply Voltage +5 / ±5 V / %
Power Consumption, 10 MHz 160 mW (typ)
The differential inputs provide a full scale input swing
equal to 2VREF with the possibility of a single-ended
input. Full use of the differential input is
recommended for optimum performance. For ease of
use, the buffered, high impedance, single-ended
reference input is converted on-chip to a differential
reference for use by the processing circuitry. Output
data format is 12-bit offset binary.
This device is available in the 32-lead LQFP package
and will operate over the industrial temperature range
of −40°C to +85°C.
1
2
3
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
TRI-STATE is a trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
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ADC12010
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Connection Diagram
Block Diagram
2
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Pin Descriptions and Equivalent Circuits
Pin No.
Symbol
Equivalent Circuit
Description
ANALOG I/O
2
VIN+
Non-Inverting analog signal Input. With a 2.0V reference voltage, the groundreferenced input signal level is 2.0 VP-P centered on VCM.
3
VIN
Inverting analog signal Input. With a 2.0V reference voltage the groundreferenced input signal level is 2.0 VP-P centered on VCM. This pin may be
connected to VCM for single-ended operation, but a differential input signal is
required for best performance.
−
VA
1
Reference input. This pin should be bypassed to AGND with a 0.1 µF
monolithic capacitor. VREF is 2.0V nominal and should be between 1.0V to
2.4V.
VREF
AGND
31
VRP
32
VRM
These pins are high impedance reference bypass pins. Connect a 0.1 µF
capacitor from each of these pins to AGND. DO NOT LOAD these pins.
30
VRN
DIGITAL I/O
10
CLK
Digital clock input. The range of frequencies for this input is 100 kHz to 15
MHz (typical) with ensured performance at 10 MHz. The input is sampled on
the rising edge of this input.
11
OE
OE is the output enable pin that, when low, enables the TRI-STATE™ data
output pins. When this pin is high, the outputs are in a high impedance state.
8
PD
PD is the Power Down input pin. When high, this input puts the converter into
the power down mode. When this pin is low, the converter is in the active
mode.
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Pin No.
Symbol
14–19,
22–27
D0–D11
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Equivalent Circuit
Description
Digital data output pins that make up the 12-bit conversion results. D0 is the
LSB, while D11 is the MSB of the offset binary output word. Output levels are
TTL/CMOS compatible.
ANALOG POWER
5, 6, 29
VA
4, 7, 28
AGND
Positive analog supply pins. These pins should be connected to a quiet +5V
voltage source and be bypassed to AGND with 0.1 µF monolithic capacitors
located within 1 cm of these power pins, and with a 10 µF capacitor.
The ground return for the analog supply.
DIGITAL POWER
4
13
VD
9, 12
DGND
Positive digital supply pin. This pin should be connected to the same quiet
+5V source as is VA and bypassed to DGND with a 0.1 µF monolithic
capacitor in parallel with a 10 µF capacitor, both located within 1 cm of the
power pin.
The ground return for the digital supply.
21
VDR
Positive digital supply pin for the ADC12010's output drivers. This pin should
be connected to a voltage source of +2.35V to +5V and be bypassed to DR
GND with a 0.1 µF monolithic capacitor. If the supply for this pin is different
from the supply used for VA and VD, it should also be bypassed with a 10 µF
tantalum capacitor. VDR should never exceed the voltage on VD. All bypass
capacitors should be located within 1 cm of the supply pin.
20
DR GND
The ground return for the digital supply for the ADC12010's output drivers.
This pin should be connected to the system digital ground, but not be
connected in close proximity to the ADC12010's DGND or AGND pins. See
Section 5 (Layout and Grounding) for more details.
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ABSOLUTE MAXIMUM RATINGS
(1) (2)
VA, VD
6.5V
≤VD +0.3V
VDR
≤ 100 mV
|VA–VD|
−0.3V to (VA or VD +0.3V)
Voltage on Any Input or Output Pin
Input Current at Any Pin
(3)
±25 mA
(3)
Package Input Current
±50 mA
Package Dissipation at TA = 25°C
See
(4)
ESD Susceptibility
Human Body Model
Machine Model
(5)
2500V
(5)
Soldering Temperature,
250V
Infrared, 10 sec.
(6)
235°C
−65°C to +150°C
Storage Temperature
(1)
(2)
(3)
(4)
(5)
(6)
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
When the input voltage at any pin exceeds the power supplies (that is, VIN < AGND, or VIN > VA), the current at that pin should be
limited to 25 mA. The 50 mA maximum package input current rating limits the number of pins that can safely exceed the power supplies
with an input current of 25 mA to two.
The absolute maximum junction temperature (TJmax) for this device is 150°C. The maximum allowable power dissipation is dictated by
TJmax, the junction-to-ambient thermal resistance (θJA), and the ambient temperature, (TA), and can be calculated using the formula
PDMAX = (TJmax - TA )/θJA. The values for maximum power dissipation listed above will be reached only when the device is operated in
a severe fault condition (e.g. when input or output pins are driven beyond the power supply voltages, or the power supply polarity is
reversed). Obviously, such conditions should always be avoided.
Human body model is 100 pF capacitor discharged through a 1.5 kΩ resistor. Machine model is 220 pF discharged through 0Ω.
The 235°C reflow temperature refers to infrared reflow. For Vapor Phase Reflow (VPR), the following Conditions apply: Maintain the
temperature at the top of the package body above 183°C for a minimum 60 seconds. The temperature measured on the package body
must not exceed 220°C. Only one excursion above 183°C is allowed per reflow cycle.
OPERATING RATINGS
(1) (2)
Operating Temperature
−40°C ≤ TA ≤ +85°C
Supply Voltage (VA, VD)
+4.75V to +5.25V
Output Driver Supply (VDR)
+2.35V to VD
VREF Input
1.0V to 2.4V
−0.05V to (VD + 0.05V)
CLK, PD, OE
−0V to (VA − 0.5V)
VIN Input
VCM
1.0V to 4.0V
≤100mV
|AGND–DGND|
(1)
(2)
Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not ensure specific performance limits. For ensured specifications and test conditions, see the
Electrical Characteristics. The ensured specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
All voltages are measured with respect to GND = AGND = DGND = 0V, unless otherwise specified.
PACKAGE THERMAL RESISTANCE
Package
θJA
32-Lead LQFP
79°C / W
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CONVERTER ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, VREF = +2.0V, fCLK = 10 MHz, tr = tf = 3 ns, CL = 25 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX:
all other limits TA = TJ = 25°C (1) (2) (3)
Symbol
Parameter
Conditions
Typical
(4)
Limits
(4)
Units
(Limits)
STATIC CONVERTER CHARACTERISTICS
12
Bits (min)
INL
Resolution with No Missing Codes
Integral Non Linearity
(5)
±0.5
±1.5
LSB (max)
DNL
Differential Non Linearity
±0.3
±0.9
LSB (max)
GE
Gain Error
±0.2
2.9
%FS (max)
Offset Error (VIN = VIN−)
%FS (max)
−0.1
1.75
Under Range Output Code
0
0
Over Range Output Code
4095
4095
DYNAMIC CONVERTER CHARACTERISTICS
FPBW
SNR
SINAD
Full Power Bandwidth
Signal-to-Noise Ratio
Signal-to-Noise and Distortion
0 dBFS Input, Output at −3 dB
100
MHz
fIN = 1 MHz, VIN = −0.5 dBFS
70
dB
fIN = 4.4 MHz, VIN = −0.5 dBFS
70
fIN = 10.1 MHz, VIN = −0.5 dBFS
70
fIN = 1 MHz, VIN = −0.5 dBFS
70
dB
fIN = 4.4 MHz, VIN = −0.5 dBFS
70
dB
fIN = 10.1 MHz, VIN = −0.5 dBFS
ENOB
THD
SFDR
IMD
Effective Number of Bits
Total Harmonic Distortion
Spurious Free Dynamic Range
Intermodulation Distortion
69
dB
66
66
dB (min)
dB (min)
fIN = 1 MHz, VIN = −0.5 dBFS
11.4
dB
fIN = 4.4 MHz, VIN = −0.5 dBFS
11.4
dB
fIN = 10.1 MHz, VIN = −0.5 dBFS
11.3
fIN = 1 MHz, VIN = −0.5 dBFS
−88
dB
fIN = 4.4 MHz, VIN = −0.5 dBFS
−86
dB
fIN = 10.1 MHz, VIN = −0.5 dBFS
−79
fIN = 1 MHz, VIN = −0.5 dBFS
92
fIN = 4.4 MHz, VIN = −0.5 dBFS
89
fIN = 10.1 MHz, VIN = −0.5 dBFS
83
fIN = 4.7 MHz and 4.9 MHz, each = −7
dBFS
−75
10.7
−74
dB (min)
dB (min)
dB
dB
69
dB (min)
dBFS
REFERENCE AND ANALOG INPUT CHARACTERISTICS
VCM
Common Mode Input Voltage
CIN
VIN Input Capacitance (each pin to GND)
VREF
Reference Voltage
VIN = 2.5 Vdc + 0.7 Vrms
VA / 2
V
(CLK LOW)
8
pF
(CLK HIGH)
7
pF
(6)
2.00
Reference Input Resistance
(1)
(2)
(3)
(4)
(5)
(6)
6
100
1.0
V (min)
2.4
V (max)
MΩ(min)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per ABSOLUTE MAXIMUM RATINGS (3). However, errors in the A/D conversion can occur if the input goes above VA
or below GND by more than 100 mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate
conversions.
To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.
Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average
Outgoing Quality Level).
Integral Non Linearity is defined as the deviation of the analog value, expressed in LSBs, from the straight line that passes through
positive and negative full-scale.
Optimum performance will be obtained by keeping the reference input in the 1.8V to 2.2V range. The LM4051CIM3-ADJ (SOT-23
package) is recommended for this application.
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DC AND LOGIC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, VREF = +2.0V, fCLK = 10 MHz, tr = tf = 3 ns, CL = 25 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX:
all other limits TA = TJ = 25°C (1) (2) (3)
Symbol
Parameter
Conditions
Typical
(4)
Limits
(4)
Units
(Limits)
CLK, PD, OE DIGITAL INPUT CHARACTERISTICS
VIN(1)
Logical “1” Input Voltage
VD = 5.25V
2.0
V (min)
VIN(0)
Logical “0” Input Voltage
VD = 4.75V
1.0
V (max)
IIN(1)
Logical “1” Input Current
VIN = 5.0V
10
µA
IIN(0)
Logical “0” Input Current
VIN = 0V
−10
µA
CIN
Digital Input Capacitance
5
pF
D0–D11 DIGITAL OUTPUT CHARACTERISTICS
VOUT(1)
Logical “1” Output Voltage
IOUT = −0.5 mA
VOUT(0)
Logical “0” Output Voltage
IOUT = 1.6 mA, VDR = 3V
IOZ
TRI-STATE Output Current
+ISC
Output Short Circuit Source Current
−ISC
Output Short Circuit Sink Current
VDR = 2.5V
2.3
V (min)
VDR = 3V
2.7
V (min)
0.4
V (max)
VOUT = 2.5V or 5V
100
nA
VOUT = 0V
−100
nA
VOUT = 0V
−20
mA (min)
VOUT = VDR
20
mA (min)
POWER SUPPLY CHARACTERISTICS
IA
Analog Supply Current
PD Pin = DGND, VREF = 2.0V
PD Pin = VDR
30
2.8
39
mA (max)
mA
ID
Digital Supply Current
PD Pin = DGND
PD Pin = VDR, fCLK = 0
2
2.2
2.5
mA (max)
mA
Digital Output Supply Current
PD Pin = DGND, CL = 0 pF
PD Pin = VDR, fCLK = 0
(5)
IDR
0
0
PD Pin = DGND, CL = 0 pF
PD Pin = VDR, fCLK = 0
(6)
Total Power Consumption
160
25
PSRR1+
Power Supply Rejection Ratio
Rejection of Positive Full-Scale Error with
VA = 4.75V vs. 5.25V
69
dBFS
PSRR1−
Power Supply Rejection Ratio
Rejection of Negative Full-Scale Error with
VA = 4.75V vs. 5.25V
51
dBFS
PSRR2
Power Supply Rejection Ratio
Rejection of Power Supply Noise with 10
MHz, 250 mVP-P riding on VA
48
dBFS
(1)
(2)
(3)
(4)
(5)
(6)
mA
mA
207
mW
mW
The inputs are protected as shown below. Input voltage magnitudes above V or below GND will not damage this device, provided
current is limited per ABSOLUTE MAXIMUM RATINGS (3). However, errors in the A/D conversion can occur if the input goes above VA
or below GND by more than 100 mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate
conversions.
To ensure accuracy, it is required that |VA–VD| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
With the test condition for VREF = +2.0V (4VP-PA differential input), the 12-bit LSB is 977 µV.
Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average
Outgoing Quality Level).
I is the curDRrent consumed by the switching of the output drivers and is primarily determined by load capacitance on the output pins,
the supply voltage, VDR, and the rate at which the outputs are switching (which is signal dependent). IDR=VDR(C0 x f0 + C1 x f1 +....C11 x
f11) where VDR is the output driver power supply voltage, Cn is total capacitance on the output pin, and fn is the average frequency at
which that pin is toggling.
Excludes IDR. See note 5.
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AC ELECTRICAL CHARACTERISTICS
Unless otherwise specified, the following specifications apply for AGND = DGND = DR GND = 0V, VA = VD = +5V, VDR =
+3.0V, PD = 0V, VREF = +2.0V, fCLK = 10 MHz, tr = tf = 3 ns, CL = 25 pF/pin. Boldface limits apply for TA = TJ = TMIN to TMAX:
all other limits TA = TJ = 25°C (1) (2) (3) (4)
Symbol
Parameter
Conditions
Typical
fCLK1
Maximum Clock Frequency
10
fCLK
Minimum Clock Frequency
100
tCH
(5)
Limits
(5)
Units
(Limits)
15
MHz (min)
Clock High Time
30
ns (min)
tCL
Clock Low Time
30
ns(min)
tCONV
Conversion Latency
6
Clock Cycles
tOD
Data Output Delay after Rising CLK Edge
tAD
Aperture Delay
1.2
ns
tAJ
Aperture Jitter
2
ps rms
tDIS
Data outputs into TRI-STATE Mode
4
ns
tEN
Data Outputs Active after TRI-STATE
4
ns
tPD
Power Down Mode Exit Cycle
500
ns
2
kHz
VDR = 2.5V
11
16.8
ns (max)
VDR = 3.0V
11
16.8
ns (max)
0.1 µF cap on pins 30, 31,32
(1)
The inputs are protected as shown below. Input voltage magnitudes above VA or below GND will not damage this device, provided
current is limited per ABSOLUTE MAXIMUM RATINGS (3). However, errors in the A/D conversion can occur if the input goes above VA
or below GND by more than 100 mV. As an example, if VA is 4.75V, the full-scale input voltage must be ≤4.85V to ensure accurate
conversions.
(2)
(3)
(4)
(5)
To ensure accuracy, it is required that |VA–V| ≤ 100 mV and separate bypass capacitors are used at each power supply pin.
With the test condition for VREF = +2.0V (4VP-P differential input), the 12-bit LSB is 977 µV.
Timing specifications are tested at TTL logic levels, VDIL = 0.4V for a falling edge and VIH = 2.4V for a rising edge.
Typical figures are at TA = TJ = 25°C, and represent most likely parametric norms. Test limits are specified to TI's AOQL (Average
Outgoing Quality Level).
8
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Specification Definitions
APERTURE DELAY is the time after the rising edge of the clock to when the input signal is acquired or held for
conversion.
APERTURE JITTER (APERTURE UNCERTAINTY) is the variation in aperture delay from sample to sample.
Aperture jitter manifests itself as noise in the output.
CLOCK DUTY CYCLE is the ratio of the time during one cycle that a repetitive digital waveform is high to the
total time of one period. The specification here refers to the ADC clock input signal.
COMMON MODE VOLTAGE (VCM) is the d.c. potential present at both signal inputs to the ADC.
CONVERSION LATENCY is the number of clock cycles between initiation of conversion and when that data is
presented to the output driver stage. Data for any given sample is available at the output pins the Pipeline Delay
plus the Output Delay after the sample is taken. New data is available at every clock cycle, but the data lags the
conversion by the pipeline delay.
DIFFERENTIAL NON-LINEARITY (DNL) is the measure of the maximum deviation from the ideal step size of 1
LSB.
EFFECTIVE NUMBER OF BITS (ENOB, or EFFECTIVE BITS) is another method of specifying Signal-to-Noise
and Distortion or SINAD. ENOB is defined as (SINAD - 1.76) / 6.02 and says that the converter is equivalent to a
perfect ADC of this (ENOB) number of bits.
FULL POWER BANDWIDTH is a measure of the frequency at which the reconstructed output fundamental
drops 3 dB below its low frequency value for a full scale input.
GAIN ERROR is the deviation from the ideal slope of the transfer function. It is the difference between the
Positive Full Scale Error and the Negative Full Scale Error:
Gain Error = Pos. Full Scale Error − Neg. Full Scale Error
(1)
INTEGRAL NON LINEARITY (INL) is a measure of the deviation of each individual code from a line drawn from
negative full scale (½ LSB below the first code transition) through positive full scale (½ LSB above the last code
transition). The deviation of any given code from this straight line is measured from the center of that code value.
INTERMODULATION DISTORTION (IMD) is the creation of additional spectral components as a result of two
sinusoidal frequencies being applied to the ADC input at the same time. It is defined as the ratio of the power in
the intermodulation products to the total power in the original frequencies. IMD is usually expressed in dBFS.
MISSING CODES are those output codes that will never appear at the ADC outputs. The ADC12010 is ensured
not to have any missing codes.
NEGATIVE FULL SCALE ERROR is the difference between the actual first code transition and its ideal value of
½ LSB above negative full scale.
OFFSET ERROR is the difference between the two input voltages (VIN+ − VIN−) required to cause a transition
from code 2047 to 2048.
OUTPUT DELAY is the time delay after the rising edge of the clock before the data update is presented at the
output pins.
PIPELINE DELAY (LATENCY) See CONVERSION LATENCY
POSITIVE FULL SCALE ERROR is the difference between the actual last code transition and its ideal value of
1½ LSB below positive full scale.
POWER SUPPLY REJECTION RATIO (PSRR) is a measure of how well the ADC rejects a change in the power
supply voltage. For the ADC12010, PSRR1 is the ratio of the change in Full-Scale Error that results from a
change in the dc power supply voltage, expressed in dB. PSRR2 is a measure of how well an a.c. signal riding
upon the power supply is rejected at the output.
SIGNAL TO NOISE RATIO (SNR) is the ratio, expressed in dB, of the rms value of the input signal to the rms
value of the sum of all other spectral components below one-half the sampling frequency, not including
harmonics or dc.
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SIGNAL TO NOISE PLUS DISTORTION (S/N+D or SINAD) Is the ratio, expressed in dB, of the rms value of the
input signal to the rms value of all of the other spectral components below half the clock frequency, including
harmonics but excluding dc.
SPURIOUS FREE DYNAMIC RANGE (SFDR) is the difference, expressed in dB, between the desired signal
amplitude to the amplitude of the peak spurious spectral component, where a spurious spectral component is
any signal present in the output spectrum that is not present at the input and may or may not be a harmonic.
TOTAL HARMONIC DISTORTION (THD) is the ratio, expressed in dBc, of the rms total of the first nine
harmonic levels at the output to the level of the fundamental at the output. THD is calculated as
(2)
where f1 is the RMS power of the fundamental (output) frequency and f2 through f10 are the RMS power in the
first 9 harmonic frequencies.
Timing Diagram
Figure 1. Output Timing
Transfer Characteristic
Figure 2. Transfer Characteristic
10
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ADC12010 TYPICAL PERFORMANCE CHARACTERISTICS
VA = VD = 5,0V, VDR = 3.0V, fCLK = 10 MHz,fIN = 10.1 MHz, VREF = 2.0V unless otherwise stated
DNL
DNL vs Temperature
Figure 3.
Figure 4.
DNL vs Clock Duty Cycle
DNL vs Sample Rate
Figure 5.
Figure 6.
INL
INL vs Temperature
Figure 7.
Figure 8.
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ADC12010 TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VD = 5,0V, VDR = 3.0V, fCLK = 10 MHz,fIN = 10.1 MHz, VREF = 2.0V unless otherwise stated
12
INL vs Clock Duty Cycle
INL vs Sample Rate
Figure 9.
Figure 10.
SNR vs Temperature
SNR vs Clock Duty Cycle
Figure 11.
Figure 12.
SNR vs Sample Rate
SNR vs FIN
Figure 13.
Figure 14.
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ADC12010 TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VD = 5,0V, VDR = 3.0V, fCLK = 10 MHz,fIN = 10.1 MHz, VREF = 2.0V unless otherwise stated
SNR vs VREF
THD vs Temperature
Figure 15.
Figure 16.
THD vs Clock Duty Cycle
THD vs Sample Rate
Figure 17.
Figure 18.
THD vs FIN
THD vs VREF
Figure 19.
Figure 20.
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ADC12010 TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VD = 5,0V, VDR = 3.0V, fCLK = 10 MHz,fIN = 10.1 MHz, VREF = 2.0V unless otherwise stated
14
SINAD vs Temperature
SINAD vs Clock Duty Cycle
Figure 21.
Figure 22.
SINAD vs Sample Rate
SINAD vs FIN
Figure 23.
Figure 24.
SINAD vs VREF
SFDR vs Temperature
Figure 25.
Figure 26.
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ADC12010 TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VD = 5,0V, VDR = 3.0V, fCLK = 10 MHz,fIN = 10.1 MHz, VREF = 2.0V unless otherwise stated
SFDR vs Clock Duty Cycle
SFDR vs Sample Rate
Figure 27.
Figure 28.
SFDR vs FIN
SFDR vs VREF
Figure 29.
Figure 30.
tOD vs VDR
Spectral Response, 1.1 MHz Input
Figure 31.
Figure 32.
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ADC12010 TYPICAL PERFORMANCE CHARACTERISTICS (continued)
VA = VD = 5,0V, VDR = 3.0V, fCLK = 10 MHz,fIN = 10.1 MHz, VREF = 2.0V unless otherwise stated
16
Spectral Response, 4.4 MHz Input
Spectral Response, 10.1 MHz Input
Figure 33.
Figure 34.
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Functional Description
Operating on a single +5V supply, the ADC12010 uses a pipeline architecture with error correction circuitry to
help ensure maximum performance. The differential analog input signal is digitized to 12 bits.
The reference input is buffered to ease the task of driving that pin. The output word rate is the same as the clock
frequency. The analog input voltage is acquired at the rising edge of the clock and the digital data for a given
sample is delayed by the pipeline for 6 clock cycles.
A logic high on the power down (PD) pin reduces the converter power consumption to 40 mW.
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APPLICATION INFORMATION
OPERATING CONDITIONS
We recommend that the following conditions be observed for operation of the ADC12010:
•
4.75V ≤ VA ≤ 5.25V
•
VD = VA
• 2.35V ≤ VDR ≤ VD
•
100 kHz ≤ fCLK ≤ 15 MHz
• 1.0V ≤ VREF ≤ 2.4V
• 1.0V ≤ VCM ≤ 4.0V
Analog Inputs
The ADC12010 has two analog signal inputs, VIN+ and VIN−. These two pins form a differential input pair. There
is one reference input pin, VREF.
Reference Pins
The ADC12010 is designed to operate with a 2.0V reference, but performs well with reference voltages in the
range of 1.0V to 2.4V. Lower reference voltages will decrease the signal-to-noise ratio (SNR). Increasing the
reference voltage (and the input signal swing) beyond 2.4V will degrade THD for a full-scale input.
It is important that all grounds associated with the reference voltage and the input signal make connection to the
ground plane at a single point to minimize the effects of noise currents in the ground path.
The three Reference Bypass Pins (VRP, VRM and VRN) are made available for bypass purposes. These pins
should each be bypassed to ground with a 0.1 µF capacitor. Smaller capacitor values will allow faster recovery
from the power down mode, but may result in degraded noise performance. DO NOT LOAD these pins.
Signal Inputs
The signal inputs are VIN+ and VIN−. The input signal, VIN, is defined as
VIN = (VIN+) – (VIN−)
(3)
Figure 35 shows the expected input signal range.
Note that the common mode input voltage range is 1V to 3V with a nominal value of VA/2. The input signals
should remain between ground and 4V.
The Peaks of the individual input signals (VIN+ and VIN−) should each never exceed the voltage described as
VIN+, VIN− = VREF + VCM
(4)
to maintain THD and SINAD performance.
Figure 35. Expected Input Signal Range
The ADC12010 performs best with a differential input with each input centered around VCM. The peak-to-peak
voltage swing at both VIN+ and VIN− each should not exceed the value of the reference voltage or the output data
will be clipped. The two input signals should be exactly 180° out of phase from each other and of the same
amplitude. For single frequency inputs, angular errors result in a reduction of the effective full scale input. For a
complex waveform, however, angular errors will result in distortion.
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For angular deviations of up to 10 degrees from these two signals being 180 out of phase, the full scale error in
LSB can be described as approximately
EFS = 4096 ( 1 - sin (90° + dev))
(5)
Where dev is the angular difference, in degrees, between the two signals having a 180° relative phase
relationship to each other (see Figure 36). Drive the analog inputs with a source impedance less than 100Ω.
Figure 36. Angular Errors Between the Two Input Signals Will Reduce the Output Level
For differential operation, each analog input signal should have a peak-to-peak voltage equal to the input
reference voltage, VREF, and be centered around a common mode voltage, VCM.
Table 1. Input to Output Relationship–Differential Input
VIN+
VIN−
Output
VCM − VREF/2
VCM + VREF/2
0000 0000 0000
VCM − VREF/4
VCM + VREF/4
0100 0000 0000
VCM
VCM
1000 0000 0000
VCM + VREF/4
VCM − VREF/4
1100 0000 0000
VCM + VREF/2
VCM − VREF/2
1111 1111 1111
Table 2. Input to Output Relationship–Single-Ended Input
VIN+
VIN−
Output
VCM − VREF
VCM
0000 0000 0000
VCM − VREF/2
VCM
0100 0000 0000
VCM
VCM
1000 0000 0000
VCM + VREF/2
VCM
1100 0000 0000
VCM + VREF
VCM
1111 1111 1111
Single-Ended Operation
Single-ended performance is lower than with differential input signals. For this reason, single-ended operation is
not recommended. However, if single ended-operation is required, and the resulting performance degradation is
acceptable, one of the analog inputs should be connected to the d.c. common mode voltage of the driven input.
The peak-to-peak differential input signal should be twice the reference voltage to maximize SNR and SINAD
performance (Figure 35b). For example, set VREF to 1.0V, bias VIN− to 1.0V and drive VIN+ with a signal range of
0V to 2.0V.
Because very large input signal swings can degrade distortion performance, better performance with a singleended input can be obtained by reducing the reference voltage when maintaining a full-range output. Table 1 and
Table 2 indicate the input to output relationship of the ADC12010.
Driving the Analog Input
The VIN+ and the VIN− inputs of the ADC12010 consist of an analog switch followed by a switched-capacitor
amplifier. The capacitance seen at the analog input pins changes with the clock level, appearing as 8 pF when
the clock is low, and 7 pF when the clock is high. Although this difference is small, a dynamic capacitance is
more difficult to drive than is a fixed capacitance, so choose the driving amplifier carefully. The LMH6550, the
LMH6702 and the LMH6628 are good amplifiers for driving the ADC12010.
The internal switching action at the analog inputs causes energy to be output from the input pins. As the driving
source tries to compensate for this, it adds noise to the signal. To prevent this, use an RC at each of the inputs,
as shown in Figure 38 and Figure 39. These components should be placed close to the ADC because the input
pins of the ADC is the most sensitive part of the system and this is the last opportunity to filter the input. The
capacitors should be eliminated for undersampling applications.
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The LMH6550 and the LMH6552 are excellent devices for driving the ADC12010, especially when single-ended
to differential conversion with d.c. coupling is necessary. An example of the use of the LMH6550 to drive the
analog input of the ADC12010 is shown in Figure 38.
For high frequency, narrow band applications, a transformer is generally the recommended way to drive the
analog inputs, as shown in Figure 39.
Input Common Mode Voltage
The input common mode voltage, VCM, should be in the range of 0.5V to 4.0V and be of a value such that the
peak excursions of the analog signal does not go more negative than ground or more positive than 0.5 Volts
below the VA supply voltage. The nominal VCM should generally be equal to VREF/2, but VRM can be used as a
VCM source as long as VCM need not supply more than 10 µA of current. Figure 38 shows the use of the VRM
output to drive the VCM input of the LMH6550. The common mode output voltage of the LMH6550 is equal to the
VCM input input voltage.
DIGITAL INPUTS
The digital TTL/CMOS compatible inputs consist of CLK, OE and PD.
CLK
The CLK signal controls the timing of the sampling process. Drive the clock input with a stable, low jitter clock
signal in the range of 100 kHz to 15 MHz with rise and fall times of less than 3ns. The trace carrying the clock
signal should be as short as possible and should not cross any other signal line, analog or digital, not even at
90°.
If the CLK is interrupted, or its frequency too low, the charge on internal capacitors can dissipate to the point
where the accuracy of the output data will degrade. This is what limits the lowest sample rate to 100 ksps.
The duty cycle of the clock signal can affect the performance of the A/D Converter. Because achieving a precise
duty cycle is difficult, the ADC12010 is designed to maintain performance over a range of duty cycles. While it is
specified and performance is ensured with a 50% clock duty cycle, performance is typically maintained over a
clock duty cycle range of 30% to 70%.
The clock line should be terminated at its source in the characteristic impedance of that line. It is highly desirable
that the the source driving the ADC CLK pin only drive that pin. However, if that source is used to drive other
things, each driven pin should be a.c. terminated with a series RC to ground, as shown in Figure 37, such that
the resistor value is equal to the characteristic impedance of the clock line and the capacitor value is
(6)
where tPR is the signal propagation rate down the clock line, "L" is the line length and ZO is the characteristic
impedance of the clock line. This termination should be as close as possible to the ADC clock pin but beyond it
as seen from the clock source. Typical tPD is about 150 ps/inch (60 ps/cm) on FR-4 board material. The units of
"L" and tPD should be the same (inches or centimeters).
Take care to maintain a constant clock line impedance throughout the length of the line. Refer to Application
Note AN-905 (SNLA035) or AN-1113 (SNLA011) for information on setting and determining characteristic
impedance.
The OE Input
The OE pin, when high, puts the output pins into a high impedance state. When this pin is low the outputs are in
the active state. The ADC12010 will continue to convert whether this pin is high or low, but the output can not be
read while the OE pin is high.
The OE pin should NOT be used to multiplex devices together to drive a common bus as this will result in
excessive capacitance on the data output pins, reducing SNR and SINAD performance of the converter. See
Section 3.0.
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PD
The PD pin, when high, holds the ADC12010 in a power-down mode to conserve power when the converter is
not being used. The power consumption in this state is 25 mW with a 10 Mhz clock and the output data pins are
undefined in this mode. The data in the pipeline is corrupted while in the power down mode.
The Power Down Mode Exit Cycle time is determined by the value of the capacitors on pins 30, 31 and 32.
These capacitors loose their charge in the Power Down mode and must be charged by on-chip circuitry before
conversions can be accurate.
DATA OUTPUTS
The ADC12010 has 12 TTL/CMOS compatible Data Output pins. Valid offset binary data is present at these
outputs while the OE and PD pins are low. While the tOD time provides information about output timing, a simple
way to capture a valid output is to latch the data on the falling edge of the conversion clock (pin 10).
Be very careful when driving a high capacitance bus. The more capacitance the output drivers must charge for
each conversion, the more instantaneous digital current flows through VDR and DR GND. These large charging
current spikes can cause on-chip noise that can couple into the analog circuitry, degrading dynamic
performance. Adequate power supply bypassing and careful attention to the ground plane will reduce this
problem. Additionally, bus capacitance beyond that specified will cause tOD to increase, making it difficult to
properly latch the ADC output data. The result could be an apparent reduction in dynamic performance.
To minimize noise due to output switching, minimize the load currents at the digital outputs. This can be done by
connecting buffers (74AC541, for example) between the ADC outputs and any other circuitry. Only one driven
input should be connected to each output pin. Additionally, inserting series 100Ω resistors at the digital outputs,
close to the ADC pins, will isolate the outputs from trace and other circuit capacitances and limit the output
currents, which could otherwise result in performance degradation. See Figure 37.
While the ADC12010 will operate with VDR voltages down to 1.8V, tOD increases with reduced VDR. Be careful of
external timing when using reduced VDR.
Figure 37. Simple Application Circuit with Single-Ended to Differential Buffer
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511, 1%
150
255, 1%
50:
SIGNAL
INPUT
To ADC
VIN100 pF
+
49.9,
1%
Amplifier:
LMH6550
VCM
280, 1%
-
100 pF
511, 1%
150
+
LMV321
To ADC
VIN+
From ADC
VRM Pin
511, 1%
Figure 38. Differential Drive Circuit of Figure 37
Figure 39. Driving the Signal Inputs with a Transformer
POWER SUPPLY CONSIDERATIONS
The power supply pins should be bypassed with a 10 µF capacitor and with a 0.1 µF ceramic chip capacitor
within a centimeter of each power pin. Leadless chip capacitors are preferred because they have low series
inductance.
As is the case with all high-speed converters, the ADC12010 is sensitive to power supply noise. Accordingly, the
noise on the analog supply pin should be kept below 100 mVP-P.
No pin should ever have a voltage on it that is in excess of the supply voltages, not even on a transient basis. Be
especially careful of this during turn on and turn off of power.
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The VDR pin provides power for the output drivers and may be operated from a supply in the range of 2.35V to
VD (nominal 5V). This can simplify interfacing to 3V devices and systems. DO NOT operate the VDR pin at a
voltage higher than VD.
LAYOUT AND GROUNDING
Proper grounding and proper routing of all signals are essential to ensure accurate conversion. Maintaining
separate analog and digital areas of the board, with the ADC12010 between these areas, is required to achieve
specified performance.
The ground return for the data outputs (DR GND) carries the ground current for the output drivers. The output
current can exhibit high transients that could add noise to the conversion process. To prevent this from
happening, the DR GND pins should NOT be connected to system ground in close proximity to any of the
ADC12010's other ground pins.
Capacitive coupling between the typically noisy digital circuitry and the sensitive analog circuitry can lead to poor
performance. The solution is to keep the analog circuitry separated from the digital circuitry, and to keep the
clock line as short as possible.
Digital circuits create substantial supply and ground current transients. The logic noise thus generated could
have significant impact upon system noise performance. The best logic family to use in systems with A/D
converters is one which employs non-saturating transistor designs, or has low noise characteristics, such as the
74LS, 74HC(T) and 74AC(T)Q families. The worst noise generators are logic families that draw the largest
supply current transients during clock or signal edges, like the 74F and the 74AC(T) families. In high speed
circuits, however, it is often necessary to use these higher speed devices. Best performance requires careful
attention to PC board layout and to proper signal integrity techniques.
The effects of the noise generated from the ADC output switching can be minimized through the use of 47Ω to
100Ω resistors in series with each data output line. Locate these resistors as close to the ADC output pins as
possible.
Figure 40. Example of a Suitable Layout
Since digital switching transients are composed largely of high frequency components, total ground plane copper
weight will have little effect upon the logic-generated noise. This is because of the skin effect. Total surface area
is more important than is total ground plane volume.
Generally, analog and digital lines should cross each other at 90° to avoid crosstalk. To maximize accuracy in
high speed, high resolution systems, however, avoid crossing analog and digital lines altogether. It is important to
keep clock lines as short as possible and isolated from ALL other lines, including other digital lines. Even the
generally accepted 90° crossing should be avoided with the clock line as even a little coupling can cause
problems at high frequencies. This is because other lines can introduce jitter into the clock line, which can lead to
degradation of SNR. Also, the high speed clock can introduce noise into the analog chain.
Best performance at high frequencies and at high resolution is obtained with a straight signal path. That is, the
signal path through all components should form a straight line wherever possible.
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Be especially careful with the layout of inductors. Mutual inductance can change the characteristics of the circuit
in which they are used. Inductors should not be placed side by side, even with just a small part of their bodies
beside each other.
The analog input should be isolated from noisy signal traces to avoid coupling of spurious signals into the input.
Any external component (e.g., a filter capacitor) connected between the converter's input pins and ground or to
the reference input pin and ground should be connected to a very clean point in the analog ground plane.
Figure 40 gives an example of a suitable layout. A single ground plane is recommended with separate analog
and digital power planes. The analog and digital power planes should NOT overlap each other. All analog
circuitry (input amplifiers, filters, reference components, etc.) should be placed over the analog power plane. All
digital circuitry and I/O lines should be placed over the digital power plane. Furthermore, all components in the
reference circuitry and the input signal chain that are connected to ground should be connected together with
short traces and enter the ground plane at a single point. All ground connections should have a low inductance
path to ground..
DYNAMIC PERFORMANCE
To achieve the best dynamic performance, the clock source driving the CLK input must be free of jitter. Isolate
the ADC clock from any digital circuitry with buffers, as with the clock tree shown in Figure 41.
As mentioned in LAYOUT AND GROUNDING, it is good practice to keep the ADC clock line as short as possible
and to keep it well away from any other signals. Other signals can introduce jitter into the clock signal, which can
lead to reduced SNR performance, and the clock can introduce noise into other lines. Even lines with 90°
crossings have capacitive coupling, so try to avoid even these 90° crossings of the clock line.
Figure 41. Isolating the ADC Clock from other Circuitry with a Clock Tree
COMMON APPLICATION PITFALLS
Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, all inputs should
not go more than 100 mV beyond the supply rails (more than 100 mV below the ground pins or 100 mV above
the supply pins). Exceeding these limits on even a transient basis may cause faulty or erratic operation. It is not
uncommon for high speed digital components (e.g., 74F and 74AC devices) to exhibit overshoot or undershoot
that goes above the power supply or below ground. A resistor of about 47Ω to 100Ω in series with any offending
digital input, close to the signal source, will eliminate the problem.
Do not allow input voltages to exceed the supply voltage, even on a transient basis. Not even during power up or
power down.
Be careful not to overdrive the inputs of the ADC12010 with a device that is powered from supplies outside the
range of the ADC12010 supply. Such practice may lead to conversion inaccuracies and even to device damage.
Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers must
charge for each conversion, the more instantaneous digital current flows through VDR and DR GND. These large
charging current spikes can couple into the analog circuitry, degrading dynamic performance. Adequate
bypassing and maintaining separate analog and digital areas on the pc board will reduce this problem.
Additionally, bus capacitance beyond that specified will cause tOD to increase, making it difficult to properly latch
the ADC output data. The result could, again, be an apparent reduction in dynamic performance.
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The digital data outputs should be buffered (with 74AC541, for example). Dynamic performance can also be
improved by adding series resistors at each digital output, close to the ADC12010, which reduces the energy
coupled back into the converter output pins by limiting the output current. A reasonable value for these resistors
is 100Ω.
Using an inadequate amplifier to drive the analog input. As explained in Signal Inputs, the capacitance seen
at the input alternates between 8 pF and 7 pF, depending upon the phase of the clock. This dynamic load is
more difficult to drive than is a fixed capacitance.
If the amplifier exhibits overshoot, ringing, or any evidence of instability, even at a very low level, it will degrade
performance. A small series resistor and shunt capacitor at each amplifier output (as shown in Figure 38 and
Figure 39) will improve performance. The LMH6550 , the LMH6702 and the LMH6628 have been successfully
used to drive the analog inputs of the ADC12010.
Also, it is important that the signals at the two inputs have exactly the same amplitude and be exactly 180º out of
phase with each other. Board layout, especially equality of the length of the two traces to the input pins, will
affect the effective phase between these two signals. Remember that an operational amplifier operated in the
non-inverting configuration will exhibit more time delay than will the same device operating in the inverting
configuration.
Operating with the reference pins outside of the specified range. As mentioned in Reference Pins, VREF
should be in the range of
1.0V ≤ VREF ≤ 2.4V
(7)
Operating outside of these limits could lead to performance degradation.
Using a clock source with excessive jitter, using excessively long clock signal trace, or having other
signals coupled to the clock signal trace. This will cause the sampling interval to vary, causing excessive
output noise and a reduction in SNR and SINAD performance.
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REVISION HISTORY
Changes from Revision A (March 2013) to Revision B
•
26
Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 25
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PACKAGE OPTION ADDENDUM
www.ti.com
29-Sep-2017
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
ADC12010CIVY/NOPB
ACTIVE
LQFP
NEY
32
250
Green (RoHS
& no Sb/Br)
CU SN
Level-3-260C-168 HR
-40 to 85
ADC12010CIVYX/NOPB
PREVIEW
LQFP
NEY
32
1000
TBD
Call TI
Call TI
-40 to 85
ADC12010
CIVY
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 1
Samples
PACKAGE OUTLINE
NEY0032A
LQFP - 1.6 mm max height
SCALE 1.800
PLASTIC QUAD FLATPACK
7.1
6.9
25
32
PIN 1 ID
B
24
1
7.1
6.9
9.4
TYP
8.6
17
8
A
9
16
0.27
32X
0.17
0.2
OPTIONAL:
SHARP CORNERS EXCEPT
PIN 1 ID CORNER
28X 0.8
4X 5.6
C A B
SEE DETAIL A
1.6 MAX
C
SEATING PLANE
0.09-0.20
TYP
0.25
GAGE PLANE
(1.4)
0.1
0.15
0.05
0.75
0.45
0 -7
DETAIL A
DETAIL A
SCALE: 12
TYPICAL
4219901/A 10/2016
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Reference JEDEC registration MS-026.
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EXAMPLE BOARD LAYOUT
NEY0032A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
25
32
32X (1.6)
1
24
32X (0.4)
SYMM
28X (0.8)
(8.5)
17
8
(R0.05) TYP
16
9
(8.5)
LAND PATTERN EXAMPLE
SCALE:8X
0.07 MAX
ALL AROUND
METAL
SOLDER MASK
OPENING
0.07 MIN
ALL AROUND
SOLDER MASK
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
4219901/A 10/2016
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
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EXAMPLE STENCIL DESIGN
NEY0032A
LQFP - 1.6 mm max height
PLASTIC QUAD FLATPACK
SYMM
25
32
32X (1.6)
1
24
32X (0.4)
SYMM
28X (0.8)
(8.5)
8
17
(R0.05) TYP
16
9
(8.5)
SOLDER PASTE EXAMPLE
SCALE 8X
4219901/A 10/2016
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
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