BLC8G20LS-400AV
Power LDMOS transistor
Rev. 1 — 26 March 2015
Product data sheet
1. Product profile
1.1 General description
400 W LDMOS packaged asymmetric Doherty power transistor for base station
applications at frequencies from 1800 MHz to 2000 MHz.
Table 1.
Typical performance
Typical RF performance at Tcase = 25 C in an asymmetrical Doherty production test circuit.
VDS = 32 V; IDq = 800 mA (main); VGS(amp)peak = 0.4 V, unless otherwise specified.
Test signal
1-carrier W-CDMA
[1]
f
VDS
PL(AV)
Gp
D
ACPR
(MHz)
(V)
(W)
(dB)
(%)
(dBc)
1805 to 1880
32
85
15.5
44
31 [1]
1930 to 1990
32
85
15.5
44
35 [1]
Test signal: 1-carrier W-CDMA; 3GPP test model 1; 64 DPCH; PAR = 9.6 dB at 0.01% probability on CCDF.
1.2 Features and benefits
Excellent ruggedness
Excellent electrical stability
Suitable for conventional and inverted Doherty
High-efficiency
Low thermal resistance providing excellent thermal stability
Lower output capacitance for improved performance in Doherty applications
Designed for low memory effects providing excellent digital pre-distortion capability
Internally matched for ease of use
Integrated ESD protection
Compliant to Directive 2002/95/EC, regarding Restriction of Hazardous Substances
(RoHS)
1.3 Applications
RF power amplifiers for base stations and multi carrier applications in the 1800 MHz to
2000 MHz frequency range
BLC8G20LS-400AV
NXP Semiconductors
Power LDMOS transistor
2. Pinning information
Table 2.
Pinning
Pin
Description
1
drain2 (peak)
2
drain1 (main)
3
gate1 (main)
4
gate2 (peak)
5
source
6
video decoupling (peak)
7
video decoupling (main)
[1]
Simplified outline
Graphic symbol
[1]
DDD
Connected to flange.
3. Ordering information
Table 3.
Ordering information
Type number
Package
BLC8G20LS-400AV
Name Description
Version
-
SOT1258-3
Air cavity plastic earless flanged package; 6 leads
4. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol
Parameter
Min
Max
Unit
VDS
drain-source voltage
-
65
V
VGS(amp)main
main amplifier gate-source voltage
0.5
+13
V
VGS(amp)peak
peak amplifier gate-source voltage
0.5
+13
V
Tstg
storage temperature
65
+150
C
Tj
junction temperature
-
225
C
[1]
Conditions
[1]
Continuous use at maximum temperature will affect the reliability, for details refer to the on-line MTF
calculator.
5. Recommended operating conditions
Table 5.
BLC8G20LS-400AV
Product data sheet
Operating conditions
Symbol
Parameter
Conditions
Tcase
case temperature
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 March 2015
Min
Max
Unit
40
+125
C
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Power LDMOS transistor
6. Thermal characteristics
Table 6.
Thermal characteristics
Symbol Parameter
Rth(j-c)
Conditions
thermal resistance from junction
to case
Typ
Unit
PL = 85 W
0.32
K/W
PL = 110 W
0.31
K/W
VDS = 32 V; IDq = 800 mA (main);
VGS(amp)peak = 0.4 V; Tcase = 80 C.
7. Characteristics
Table 7.
DC characteristics
Tj = 25 C unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Main device
V(BR)DSS
drain-source breakdown voltage
VGS = 0 V; ID = 1.8 mA
65
-
-
V
VGS(th)
gate-source threshold voltage
VDS = 10 V; ID = 180 mA
1.5
1.9
2.3
V
VGSq
gate-source quiescent voltage
VDS = 32 V; ID = 800 mA
1.7
2.1
2.5
V
IDSS
drain leakage current
VGS = 0 V; VDS = 28 V
-
-
2.8
A
IDSX
drain cut-off current
VGS = VGS(th) + 3.75 V; VDS = 10 V
-
34
-
A
IGSS
gate leakage current
VGS = 11 V; VDS = 0 V
-
-
280
nA
gfs
forward transconductance
VDS = 10 V; ID = 9.0 A
-
13
-
S
RDS(on)
drain-source on-state resistance
VGS = VGS(th) + 3.75 V; ID = 6.3 A
-
85
135
m
Peak device
V(BR)DSS
drain-source breakdown voltage
VGS = 0 V; ID = 3.0 mA
65
-
-
V
VGS(th)
gate-source threshold voltage
VDS = 10 V; ID = 300 mA
1.5
1.9
2.3
V
VGSq
gate-source quiescent voltage
VDS = 32 V; ID = 1800 mA
1.7
2.1
2.5
V
IDSS
drain leakage current
VGS = 0 V; VDS = 28 V
-
-
2.8
A
IDSX
drain cut-off current
VGS = VGS(th) + 3.75 V; VDS = 10 V
-
50
-
A
IGSS
gate leakage current
VGS = 11 V; VDS = 0 V
-
-
280
nA
gfs
forward transconductance
VDS = 10 V; ID = 15.0 A
-
19
-
S
RDS(on)
drain-source on-state resistance
VGS = VGS(th) + 3.75 V; ID = 10.5 A
-
55
85
m
Table 8.
RF characteristics
Test signal: 1-carrier W-CDMA; PAR = 9.6 dB at 0.01 % probability on the CCDF; 3GPP test model 1; 1 to 64 DPCH;
f1 = 1807.5 MHz; f2 = 1877.5 MHz; RF performance at VDS = 32 V; IDq = 800 mA (main); VGS(amp)peak = 0.4 V; Tcase = 25 C;
unless otherwise specified; in an asymmetrical Doherty production test circuit in 1805 MHz to 1880 MHz frequency range.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Gp
power gain
PL(AV) = 85 W
14.5
15.5
-
dB
RLin
input return loss
PL(AV) = 85 W
-
11
7
dB
D
drain efficiency
PL(AV) = 85 W
40
44
-
%
ACPR
adjacent channel power ratio
PL(AV) = 85 W
-
31
27
dBc
PARO
output peak-to-average ratio
PL(AV) = 100 W
6.0
6.7
-
dB
PL(M)
peak output power
PL(AV) = 100 W
400
475
-
W
BLC8G20LS-400AV
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 March 2015
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BLC8G20LS-400AV
NXP Semiconductors
Power LDMOS transistor
8. Test information
8.1 Ruggedness in Doherty operation
The BLC8G20LS-400AV is capable of withstanding a load mismatch corresponding to
VSWR = 10 : 1 through all phases under the following conditions:
• VDS = 28 V; IDq = 800 mA; VGS(amp)peak = 0.4 V; f = 1807.5 MHz:
1-carrier W-CDMA; PL = 141 W (5 dB OBO); 100 % clipping
• VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V; f = 1807.5 MHz:
1-carrier W-CDMA; PL = 141 W (5 dB OBO); 100 % clipping
8.2 Impedance information
Table 9.
Typical impedance of main device
Measured load-pull data of main device; IDq = 800 mA (main); VDS = 32 V; pulsed CW (tp = 100 s;
= 10 %).
f
ZS [1]
ZL [1]
PL [2]
D [2]
Gp [2]
(MHz)
()
()
(W)
(%)
(dB)
Maximum power load
1805
1.2 j5.2
1.3 j4.4
252
55.9
18.0
1840
1.2 j5.3
1.2 j4.5
249
55.6
18.1
1880
1.6 j5.9
1.2 j4.4
245
53.1
17.9
Maximum drain efficiency load
1805
1.2 j5.2
2.5 j4.0
178
61.4
20.0
1840
1.2 j5.3
2.5 j4.1
182
61.4
20.2
1880
1.6 j5.9
2.6 j3.9
176
60.8
20.5
[1]
ZS and ZL defined in Figure 1.
[2]
At 3 dB gain compression.
Table 10. Typical impedance of peak device
Measured load-pull data of main device; IDq = 1750 mA (main); VDS = 32 V; pulsed CW (tp = 100 s;
= 10 %).
f
ZS [1]
ZL [1]
PL [2]
D [2]
Gp [2]
(MHz)
()
()
(W)
(%)
(dB)
Maximum power load
1805
1.2 j5.0
2.1 j5.4
394
50.8
19.0
1840
1.5 j5.3
2.5 j5.3
383
53.5
19.5
1880
2.0 j5.9
2.3 j5.5
378
52.1
19.4
Maximum drain efficiency load
BLC8G20LS-400AV
Product data sheet
1805
1.2 j5.0
2.5 j3.8
289
57.8
21.4
1840
1.5 j5.3
2.7 j3.7
289
59.4
21.4
1880
2.0 j5.9
2.4 j3.8
284
60.4
21.7
[1]
ZS and ZL defined in Figure 1.
[2]
At 3 dB gain compression.
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Rev. 1 — 26 March 2015
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Power LDMOS transistor
GUDLQ
=/
JDWH
=6
DDI
Fig 1.
Definition of transistor impedance
8.3 Recommended impedances for Doherty design
Table 11. Typical impedance of main at 1 : 1 load
Measured load-pull data of main device; IDq = 800 mA (main); VDS = 32 V; pulsed CW (tp = 100 s;
= 10 %).
f
ZS [1]
ZL [1]
PL(3dB) [2]
D [2]
Gp [2]
(MHz)
()
()
(W)
(%)
(dB)
1805
1.0 j4.8
1.8 j4.9
179
50.4
18.1
1840
1.1 j5.0
1.7 j4.6
189
51.6
18.3
1880
1.4 j5.2
1.7 j4.3
183
49.3
18.5
[1]
ZS and ZL defined in Figure 1.
[2]
At PL(AV) = 85 W.
Table 12. Typical impedance of main device at 1 : 2.5 load
Measured load-pull data of main device; IDq = 800 mA (main); VDS = 32 V; pulsed CW (tp = 100 s;
= 10 %).
f
ZS [1]
ZL [1]
PL(3dB) [2]
D [2]
Gp [2]
(MHz)
()
()
(W)
(%)
(dB)
1805
1.0 j4.8
3.1 j3.5
132
51.1
19.7
1840
1.1 j5.0
3.3 j4.0
126
50.5
19.9
1880
1.4 j5.2
3.3 j4.2
126
50.7
19.9
[1]
ZS and ZL defined in Figure 1.
[2]
At PL(AV) = 85 W.
Table 13. Typical impedance of peak device at 1 : 1 load
Measured load-pull data of main device; IDq = 1750 mA (main); VDS = 32 V; pulsed CW (tp = 100 s;
= 10 %).
BLC8G20LS-400AV
Product data sheet
f
ZS [1]
ZL [1]
PL(3dB) [2]
D [2]
Gp [2]
(MHz)
()
()
(W)
(%)
(dB)
1805
1.2 j5.0
2.8 j4.8
316
50.0
19.0
1840
1.5 j5.3
2.7 j4.6
313
51.4
19.4
1880
2.0 j5.9
2.6 j4.3
290
52.9
20.0
[1]
ZS and ZL defined in Figure 1.
[2]
At PL(AV) = 85 W.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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NXP Semiconductors
Power LDMOS transistor
Table 14.
Off-state impedances of peak device
f
Zoff
(MHz)
()
1805
0.9 j0.2
1840
0.9 j0.1
1880
0.9 j0.2
8.4 Test circuit
PP
&
&
5
& &
&
&
&
&
&
&
&
&
&
&
PP
;
&
&
&
5
&
5
&
5
&
&
&
&
&
&
&
DDD
Printed-Circuit Board (PCB): Rogers 4350B: r = 3.66; thickness = 0.508 mm; thickness copper
plating = 35 m. See Table 15 for a list of components.
Fig 2.
Component layout
Table 15. List of components
See Figure 2 for component layout.
Component
Description
Product data sheet
Remarks
C1, C2, C13, C14,
C19
multilayer ceramic chip capacitor 10 pF
[1]
C3, C15
multilayer ceramic chip capacitor 2.2 pF
[1]
ATC 100A
multilayer ceramic chip capacitor 2.0 pF
[1]
ATC 100A
C5, C8, C17, C22
multilayer ceramic chip capacitor 100 nF
[2]
Murata
C6, C9, C18, C23
multilayer ceramic chip capacitor 4.7 F
[2]
Murata
C7, C21
multilayer ceramic chip capacitor 10 pF
[3]
ATC 100B
C10, C24
multilayer ceramic chip capacitor 10 F, 50 V
C4, C16
BLC8G20LS-400AV
Value
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 March 2015
ATC 100A
TDK C5750X7
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Power LDMOS transistor
Table 15. List of components …continued
See Figure 2 for component layout.
Component
Description
Value
Remarks
C11; C25
electrolytic capacitor
470 F, 63 V
Vishay 148RUS
C12; C26
multilayer ceramic chip capacitor 4.7 F, 100 V
TDK C5750X7
C20
multilayer ceramic chip capacitor 5.6 pF
R1, R2
SMD resistor
4.7
SMD 0805
R3
SMD resistor
50
SMD 0805
R4
SMD resistor
470
SMD 0805
X1
directional coupler
5 dB
Anaren X3C19P1-05S
[1]
American Technical Ceramics type 100A or capacitor of same quality.
[2]
Murata or capacitor of same quality.
[3]
American Technical Ceramics type 100B or capacitor of same quality.
8.5 Graphical data
8.5.1 Pulsed CW
DDD
$0WR30
GHJ
*S
*S
G%
Ș'
Ș'
3/ :
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V; tp = 100
s; = 10 %.
DDD
3/ :
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
(1) f = 1807.5 MHz
(1) f = 1807.5 MHz
(2) f = 1842.5 MHz
(2) f = 1842.5 MHz
(3) f = 1877.5 MHz
(3) f = 1877.5 MHz
Fig 3.
Power gain and drain efficiency as function of
output power; typical values
BLC8G20LS-400AV
Product data sheet
Fig 4.
AM to PM as a function of output power;
typical values
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Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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BLC8G20LS-400AV
NXP Semiconductors
Power LDMOS transistor
8.5.2 1-Carrier W-CDMA
PAR = 9.6 dB per carrier at 0.01 % probability on the CCDF; 3GPP test model 1 with
64 DPCH (100 % clipping).
DDD
*S
G%
Ș'
*S
DDD
$&350
G%F
Ș'
3/ :
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
(1) f = 1807.5 MHz
(2) f = 1842.5 MHz
(2) f = 1842.5 MHz
(3) f = 1877.5 MHz
(3) f = 1877.5 MHz
Power gain and drain efficiency as function of
output power; typical values
Fig 6.
DDD
3/ :
DDD
3/ :
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
(1) f = 1807.5 MHz
(2) f = 1842.5 MHz
(2) f = 1842.5 MHz
(3) f = 1877.5 MHz
(3) f = 1877.5 MHz
Peak-to-average power ratio as a function of
output power; typical values
Product data sheet
3/ :
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
(1) f = 1807.5 MHz
BLC8G20LS-400AV
Adjacent channel power ratio (5 MHz) as a
function of output power; typical values
5/LQ
G%
3$5
G%
Fig 7.
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
(1) f = 1807.5 MHz
Fig 5.
Fig 8.
Input return loss as a function of output
power; typical values
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Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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BLC8G20LS-400AV
NXP Semiconductors
Power LDMOS transistor
8.5.3 2-Carrier W-CDMA
PAR = 9.6 dB at 0.01 % probability on the CCDF; 3GPP test model 1 with 64 DPCH
(46 % clipping).
DDD
$&350
G%F
*S
G%
Ș'
*S
DDD
$&350
$&350
G%F
$&350
Ș'
3/ :
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
3/ :
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
(1) f = 1807.5 MHz
(1) f = 1807.5 MHz
(2) f = 1842.5 MHz
(2) f = 1842.5 MHz
(3) f = 1877.5 MHz
(3) f = 1877.5 MHz
Fig 9.
Power gain and drain efficiency as function of
output power; typical values
Fig 10. Adjacent channel power ratio (5 MHz) and
adjacent channel power ratio (10 MHz) as
function of output power; typical values
DDD
5/LQ
G%
3/ :
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
(1) f = 1807.5 MHz
(2) f = 1842.5 MHz
(3) f = 1877.5 MHz
Fig 11. Input return loss as a function of output power; typical values
BLC8G20LS-400AV
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
9 of 15
BLC8G20LS-400AV
NXP Semiconductors
Power LDMOS transistor
8.5.4 2-Tone VBW
DDD
,0'
G%F
,0'
,0'
,0'
FDUULHUVSDFLQJ 0+]
VDS = 32 V; IDq = 800 mA; VGS(amp)peak = 0.4 V.
(1) IMD low
(2) IMD high
Fig 12. VBW capability
BLC8G20LS-400AV
Product data sheet
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Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
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Power LDMOS transistor
9. Package outline
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Fig 13. Package outline SOT1258-3
BLC8G20LS-400AV
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
11 of 15
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Power LDMOS transistor
10. Handling information
CAUTION
This device is sensitive to ElectroStatic Discharge (ESD). Observe precautions for handling
electrostatic sensitive devices.
Such precautions are described in the ANSI/ESD S20.20, IEC/ST 61340-5, JESD625-A or
equivalent standards.
11. Abbreviations
Table 16.
Abbreviations
Acronym
Description
3GPP
3rd Generation Partnership Project
AM
Amplitude Modulation
CCDF
Complementary Cumulative Distribution Function
CW
Continuous Wave
DPCH
Dedicated Physical CHannel
ESD
ElectroStatic Discharge
LDMOS
Laterally Diffused Metal-Oxide Semiconductor
MTF
Median Time to Failure
OBO
Output Back Off
PAR
Peak-to-Average Ratio
PM
Phase Modulation
SMD
Surface Mounted Device
VSWR
Voltage Standing Wave Ratio
W-CDMA
Wideband Code Division Multiple Access
12. Revision history
Table 17.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
BLC8G20LS-400AV v.1
20150326
Product data sheet
-
-
BLC8G20LS-400AV
Product data sheet
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Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
12 of 15
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Power LDMOS transistor
13. Legal information
13.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
13.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
Product specification — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to offer functions and qualities beyond those described in the
Product data sheet.
13.3 Disclaimers
Limited warranty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Semiconductors takes no
responsibility for the content in this document if provided by an information
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidental,
punitive, special or consequential damages (including - without limitation - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconductors’ aggregate and cumulative liability towards
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
BLC8G20LS-400AV
Product data sheet
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in personal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconductors products in such equipment or
applications and therefore such inclusion and/or use is at the customer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of their applications
and products using NXP Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suitable and fit for the customer’s applications and
products planned, as well as for the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associated with their
applications and products.
NXP Semiconductors does not accept any liability related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for the customer’s applications and products using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress ratings only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanently and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individual agreement. In case an individual
agreement is concluded only the terms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing in this document may be interpreted or
construed as an offer to sell products that is open for acceptance or the grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
13 of 15
BLC8G20LS-400AV
NXP Semiconductors
Power LDMOS transistor
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors product is automotive qualified,
the product is not suitable for automotive use. It is neither qualified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automotive specifications and standards, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims resulting from customer design and
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
13.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
14. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
BLC8G20LS-400AV
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 1 — 26 March 2015
© NXP Semiconductors N.V. 2015. All rights reserved.
14 of 15
NXP Semiconductors
BLC8G20LS-400AV
Power LDMOS transistor
15. Contents
1
1.1
1.2
1.3
2
3
4
5
6
7
8
8.1
8.2
8.3
8.4
8.5
8.5.1
8.5.2
8.5.3
8.5.4
9
10
11
12
13
13.1
13.2
13.3
13.4
14
15
Product profile . . . . . . . . . . . . . . . . . . . . . . . . . . 1
General description . . . . . . . . . . . . . . . . . . . . . 1
Features and benefits . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Pinning information . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 2
Recommended operating conditions. . . . . . . . 2
Thermal characteristics . . . . . . . . . . . . . . . . . . 3
Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Test information . . . . . . . . . . . . . . . . . . . . . . . . . 4
Ruggedness in Doherty operation . . . . . . . . . . 4
Impedance information . . . . . . . . . . . . . . . . . . . 4
Recommended impedances for Doherty design 5
Test circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Graphical data . . . . . . . . . . . . . . . . . . . . . . . . . 7
Pulsed CW . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
1-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 8
2-Carrier W-CDMA . . . . . . . . . . . . . . . . . . . . . . 9
2-Tone VBW . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
Handling information. . . . . . . . . . . . . . . . . . . . 12
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Revision history . . . . . . . . . . . . . . . . . . . . . . . . 12
Legal information. . . . . . . . . . . . . . . . . . . . . . . 13
Data sheet status . . . . . . . . . . . . . . . . . . . . . . 13
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Contact information. . . . . . . . . . . . . . . . . . . . . 14
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP Semiconductors N.V. 2015.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 26 March 2015
Document identifier: BLC8G20LS-400AV