OKI Semiconductor MSM9811 FEDL9811FULL-04 Issue Date: Sep. 1, 2004 4-Channel Mixing OKI ADPCM Type Voice Synthesis LSI GENERAL DESCRIPTION The MSM9811 is a 4-channel mixing voice synthesis LSI, to which up to 128 Mbits of ROM and/or EPROM storing voice data can directly be connected externally. The device is straight 8-bit PCM playback, non-linear 8-bit PCM playback, 4-bit ADPCM playback, and 4-bit ADPCM2 playback selectable and provides 2-channel stereo output and volume control. The MSM9811 contains a 14-bit D/A converter and LPF. The MSM9811 can easily configure a system by connecting voice data storage memory, power amplifier, and CPU externally. FEATURES • Non-linear 8-bit PCM/straight 8-bit PCM/4-bit ADPCM/4-bit ADPCM2 • Serial input or parallel input selectable • Phrase Control Table function • 4-channel mixing function • Master clock frequency : 4.096 MHz • Sampling frequency : 4.0 kHz, 5.3 kHz, 6.4 kHz, 8.0 kHz, 10.6 kHz, 12.8 kHz, 16.0 kHz, 21.2 kHz, 25.6 kHz, 32.0 kHz • Maximum number of phrases : 256 • Output channel : L/R 2 channels • Built-in volume control function (for each output channel) • Built-in 14-bit D/A converter • Built-in low-pass filter : Digital filter • Package : 64-pin plastic QFP (QFP64-P-1414-0.80-BK) (MSM9811GA) 1/44 XT XT TEST1 TEST2 TEST3 TEST4 D7/SD D6/SI D5/S0 S4/UD D3/SR3 D2/SR2 D1/SR1 D0/SR0 RCS CS WR RD CMD SERIAL NCR/BUSY OSC interface CPU 8 8 DVDD DGND Timing Controller 23-Bit Address Counter 23-Bit Multiplexer 14-Bit DAC 16*9 MPY 16 PCM Synthesizer ADPCM Synthesizer 8 LDAO AVDD AGND RDAO 14-Bit DAC PAN Register RD0 8-Bit LATCH ROE RD7 DATA Controller RA0 OKI Semiconductor RESET RA23 FEDL9811FULL-04 MSM9811 BLOCK DIAGRAM 2/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 49 RA18 50 RA19 51 RA9 52 RA10 53 RA11 54 RA12 55 RA13 56 RA14 58 RA16 57 RA15 59 RA17 60 RA0 61 RA20 62 RA21 63 RA22 64 RA23 PIN CONFIGURATION (TOP VIEW) 2 48 DVDD 47 RA8 4 46 RA7 45 RA6 DGND 1 AGND TEST4 3 LDAO RDAO 5 AVDD 44 RA5 43 RA4 42 RA3 6 7 DVDD RCS 8 41 RA2 33 RD5 DGND 32 34 RD4 RD 16 RD6 31 CMD 15 RESET 29 RD7 30 35 RD3 D6/SI 27 D7/SD 28 36 RD2 SERIAL 14 D4/UD 25 D5/SO 26 TEST3 13 D3/SR3 24 38 RD0 37 RD1 D2/SR2 23 39 ROE XT 11 XT 12 D1/SR1 22 TEST2 10 CS 20 D0/SR0 21 40 RA1 TEST1 NC 17 WR 18 NCR/BUSY 19 9 NC: No connection 64-pin Plastic QFP 3/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 PIN DESCRIPTIONS Pin Symbol Type 40-47, 49-64 RA23-RA0 O 30, 31, 33-38 RD7-RD0 I 39 ROE O 8 RCS I 15 CMD I 16 RD I 18 WR I 20 CS I 14 SERIAL I 28 D7/SD I/O 27 D6/SI I/O 26 D5/SO I/O Description Address pins for external memory. These pins become high impedance when RCS pin is “H“. Data pin for external memory. Pull-down resistors are internally connected to these pins. These pull-down resistors become valid when the RCS pin is “H”, and become invalid when the RCS pin is “L”. Output enable pin for external memory. This pin becomes high impedance when RCS pin is “H”. When this pin is “L”, RA23 to RA0 and ROE pins output address data and output enable signal. When this pin is “H”, RA23 to RA0 and ROE pins become high impedance. Select pin for Command data or Subcommand data for CPU interface. When this pin is “H”, subcommand input is selected. When this pin is “L”, command input is selected. A pull-up resistor is internally connected to this pin. Read pin for CPU interface. A pull-up resistor is internally connected to this pin. Write pin for CPU interface. A pull-up resistor is internally connected to this pin. Chip select pin for CPU interface. When CS is “H”, WR signal is not entered in this LSI. A pull-up resistor is internally connected to this pin. CPU input interface select pin. When SERIAL is “H”, serial input interface is selected. When it is “L”, parallel input interface is selected. Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status data output pin. When serial input interface is selected, this pin serves as serial data input pin. Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, this pin serves as serial clock input pin. Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status serial output pin. 4/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Pin Symbol Type 25 D4/UD I/O 24 23 22 D3/SR3 D2/SR2 D1/SR1 21 D0/SR0 4 5 LDAO RDAO O O 11 XT I 12 XT O 29 RESET I 19 NCR/BUSY I 9 10 13 3 TEST1 TEST2 TEST3 TEST4 I 7, 48 DVDD — 6 AVDD — 1, 32 2 DGND AGND — — I/O Description Data bus pin for CPU interface when parallel interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, fix this pin at GND level. Data bus pin for CPU interface when parallel input interface is selected. When WR is “L”, this pin serves as data input pin. When RD is “L”, this pin serves as channel status output pin. When serial input interface is selected, this pin serves as channel status output pin. Channels 4 thru 1 are output to SR3 thru SR0, respectively. LEFT side D/A output pin. RIGHT side D/A output pin. Crystal or ceramic oscillator connection pin. A feedback resistor of about 1MΩ is connected between XT and XT. If necessary, enter external clocks into this pin. Crystal or ceramic oscillator connection pin. When external clocks are used, leave this pin open. When this pin is “L” level, the LSI is initialized. At that time, oscillation stops and D/A outputs go to GND level. Channel status select pin. When this pin is “H”, NCR signal is output. When it is “L”, BUSY signal is output. Pins for LSI testing. Apply “L” level to these pins. Digital power supply pin. A bypass capacitor of 0.1 µF or more should be connected between the DGND pin and the DVDD pin. Analog power supply pin. A bypass capacitor of 0.1 µF or more should be connected between the AGND pin and the AVDD pin. Digital GND pin. Analog GND pin. 5/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 ABSOLUTE MAXIMUM RATINGS (GND = 0 V) Parameter Symbol Power Supply Voltage VDD Input Voltage VIN Storage Temperature Condition Rating Ta = 25°C TSTG Unit –0.3 to +7.0 V –0.3 to VDD+ 0.3 V –55 to +150 °C — RECOMMENDED OPERATING CONDITIONS (GND = 0 V) Parameter Power Supply Voltage Operating Temperature Symbol VDD Top Condition — — Master Clock Frequency fOSC — Min. 3.5 Range 4.5 to 5.5 –40 to +85 Typ. 4.096 Unit V °C Max. 4.5 MHz ELECTRICAL CHARACTERISTICS DC Characteristics (DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = –40 to +85°C) Parameter High-level Input Voltage Symbol VIH Condition — Min. 0.84 × VDD Typ. — Max. — Unit V Low-level Input Voltage VIL — — — 0.16 × VDD V High-level Output Voltage VOH IOH = –1 mA VDD – 0.4 — — V Low-level Output Voltage VOL IOL = 2 mA — — 0.4 V High-level Input Current 1 I IH1 VIH = VDD — — 10 µA I IH2 Applied to pins with internal pull-down resistor 30 — 300 µA IIL1 VIL = GND –10 — — µA IIL2 Applied to pins with internal pull-up resistor –300 — –30 µA High-level Input Current 2 (Note 1) Low-level Input Current 1 Low-level Input Current 2 (Note 2) Output Leakage Current ILO 0 ≤ VOUT ≤ VDD –10 — +10 µA Operating Current IDD Standby Current IDS fOSC = 4 MHz, No load Ta = –40 to +70°C Ta = –40 to +85°C — — — 6 — — 15 15 50 mA µA µA Notes 1: Applicable to RD7 to RD0 pins (when RCS = “H”). 2: Applicable to CMD, RD, WR, and CS pins. 6/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Analog Characteristics (DVDD = AVDD = 4.5 to 5.5 V, DGND = AGND = 0 V, Ta = –40 to +85°C) Parameter LDAO,RDAO Load Resistance (During OP amplifier output) LDAO,RDAO Output Impedance (When OP amplifier is not used) LDAO,RDAO Output Level Symbol Condition Min. Typ. Max. Unit ROUTA — 50 — — kΩ ROUTD — — 3 — kΩ — No load — 0.7 to 0.94 VDD — V AC Characteristics (VDD = 4.5 to 5.5 V, GND = 0 V, Ta = –40 to +85°C, CL = 5 pF) Parameter Master Clock Duty Cycle RESET Input Pulse Width RESET Delay Time From Raising of Power Supply Set up and Hold Time of CS for RD RD Pulse Width Output Data Valid Time after Fall of RD Data Float Time after Rise of RD Setup and Hold Time of CMD for WR Setup and Hold Time of CS for WR WR Pulse Width Data Setup Time before Rise of WR Data Hold Time after Rise of WR WR - WR Pulse Interval CS - CS Pulse Interval Serial Data Setup Time Serial Data Hold Time Serial Clock Pulse Width Output Data Valid Time after Rise of Serial Clock Setup Time of WR for Serial Data Setup Time of Serial Clock Fall for WR Rise Setup Time of RD for Serial Clock Rise Symbol fduty tW(RST) tD(RST) tCR tRR tDRE tDRF tDW tCW tWW tDWS tDWH tWWS tCC tSDS tSSD tW(SCK) tSDD tSWDS tSIWS tSRIS Min. 40 1 0 30 200 — — 50 30 200 100 30 160 100 30 30 200 — 200 300 300 Typ. 50 — — — — — 10 — — — — — — — — — — — — — — Max. 60 — — — — 100 50 — — — — — — — — — — 200 — — — Unit % µs µs ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 7/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 TIMING DIAGRAMS (PARALLEL INPUT) Data Read Timing CS(I) VIH VIL tCR RD(I) tCR VIH VIL tRR VOH D7 - D0(O) Data out Valid VOL tDRE tDRF Data Write Timing (Sub-command, Command Input) CMD(I) VIH VIL tDW tDW tDW CS(I) tDW VIH tCC VIL tCW tCW WR(I) VIH VIL tWSS tWW VIH D7 - D0(I) Data Stable Data Stable tDWS tDWS VIL tDWH tDWH 8/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 TIMING DIAGRAMS (SERIAL INPUT) Data Write Timing (Sub-command, Command Input) CMD(I) tDW VIH tDW tDW VIL tDW tCC CS(I) VIH VIL tCW WR(I) tCW VIH tWSS VIL SD(I) tSWDS tSIWS tSIWS SI(I) WR(I) VIH VIL tSWDS SD(I) VIH VIL tSDS SI(I) tSSD tSDS tSSD VIH VIL tW(SCK) tW(SCK) tW(SCK) tW(SCK) 9/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Data Read Timing CS(I) VIH VIL tCR tCR RD(I) VIH VIL SO(O) D7 D6 D5 D4 D3 D2 D1 D0 SI(I) RD(I) VIH VIL SO(O) VOH VOL tSRIS SI(I) VIH VIL tSDD tSDD 10/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 TIMING DIAGRAM (COMMON TO PARALLEL AND SERIAL I/O) Power-on Timing · Power-down Timing 4.5V VDD tD(RST) tW(RST) VIH RESET(I) VIL XT XT Oscillating Reset processing Oscillation stabilization Waiting for command Standby LDAO (O) 1/2VDD RDAO (O) 1/2VDD XT XT GND 1/2VDD GND 1/2VDD Oscillating Oscillating tW(RST) RESET (I) Waiting for command Standby Oscillation stabilization time Waiting for command 11/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 BUSYn NCRn Sub-command/ Command LDAO/RDAO FADR1 START FADR2 START FADR1 playback FADR2 playback Continuous Playback Timing When Phrase Control Table is not Used 12/44 FADR1 START Note) FADR2 START FADR2 playback Do not enter the START command and MUON command during playback (BUSY = “L”) when the phrase control table is used. Otherwise, the LSI may malfunction. Enter the START command and MUON command after BUSY = “H”. (Note) BUSYn NCRn Sub-command/ Command LDAO/RDAO FADR1 playback FEDL9811FULL-04 OKI Semiconductor MSM9811 Continuous Playback Timing When Phrase Control Table is Used 13/44 BUSYn NCRn Sub-command/ Command LDAO/RDAO FADR1 START LOOP set FADR1 playback LOOP released FADR1 playback LOOP valid FADR1 playback LOOP valid FEDL9811FULL-04 OKI Semiconductor MSM9811 LOOP Playback Timing (Phrase Control Table is Used/not Used) 14/44 BUSYn NCRn Sub-command/ Command DAOL/ DAOR FADR1 START MUON FADR1 playback FADR2 START Silence (4 to 1020 ms) MUON command FADR2 playback FEDL9811FULL-04 OKI Semiconductor MSM9811 MUON Command Input Timing When Phrase Control Table is not Used 15/44 FADR1 START Note) MUON Silence (4 to 1020 ms) MUON command START Note) FADR2 FADR2 playback (Note) Do not enter the START command and MUON command during playback (BUSY = “L”) when the phrase control table is used. Otherwise, the LSI may malfunction. Enter the START command and MUON command after BUSY = “H”. BUSYn NCRn Sub-command/ Command DAOL/DAOR FADR1 playback FEDL9811FULL-04 OKI Semiconductor MSM9811 MUON Command Input Timing When Phrase Control Table is Used 16/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 FUNCTIONAL DESCRIPTION Microcontroller Interface The microcontroller interface includes two interface circuits, parallel interface and serial interface. The statuses of each pin both in parallel interface mode and in serial interface mode are shown below. SERIAL = “L” Parallel I/O interface D7 (I/O) D6 (I/O) D5 (I/O) D4 (I/O) D3 (I/O) D2 (I/O) D1 (I/O) D0 (I/O) Data I/O pins SD (I) SI (I) SO (O) UD (I) SR3 (O) SR2 (O) SR1 (O) SR0 (O) SERIAL = “H” Serial I/O interface Serial data input pin Serial clock input pin Serial data output pin Fix this pin at GND level Channel status signal output pin 17/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Command List Commands Each command consists of a command and a sub-command. Data is input when the CMD pin is “H”. A command is input when the CMD pin is “L”. NCRn Comman d name Valid only at “H” START None STOP None None LOOP OPT Valid only at “H” MUON None FADR CMD pin 7 6 5 D7 to D0 4 3 2 H 0 0 0 0 L 0 0 0 0 H 0 0 0 0 L 0 0 0 0 H 0 0 0 0 L 0 0 0 H 0 0 0 L 0 0 0 1 O 4 1 H L None None DADR 0 CH4 to CH1 0 X X X CH4 to CH1 1 X X X CH4 to CH1 0 O 3 1 X O 2 X X O 1 X X O0 0 1 0 0 0 0 1 0 1 0 C1 to C0 0 C1 to C0 H H H H H H SA23 to SA16 SA15 to SA8 SA7 to SA0 ST23 to ST16 ST15 to ST8 ST7 to ST0 H P1 to P0 0 0 C1 to C0 S3 to S0 L 0 0 1 1 H X X X X L 0 0 1 1 0 L3 to L0 0 C1 to C0 R3 to R0 PAN L 0 1 0 0 0 0 Selects an option. Selects a silence time at M × 4 ms. (Condition: 1 ≤ M ≤ 255) Selects a channel that outputs a silence and plays a silence. Selects a phrase to be played. Selects a channel that sets up a phrase. Selects a ROM address at which voice synthesis ends. V3 to V0 0 Sets the bit of a voice synthesis start channel to “1”. Starts playback. Sets the bit of a voice synthesis end channel to “1”. Ends playback. Sets the bit of a LOOP channel to “1”. Starts LOOP. Selects a ROM address at which voice synthesis starts. CVOL 1 Description X FA7 to FA0 H None 0 M7 to M0 H L 1 C1 to C0 Selects a sampling frequency using S3 to S0. Selects a voice synthesis method using P1 to P0. Sets the condition to a channel selected by C1 to C0. Sets a playback volume between V3 and V0 × –2 dB. Selects a channel to which a playback volume is set. Selects a left side voice volume using L3 to L0 and selects a right side voice volume using R3 to R0. The volume of output is –2 dB × (L or R). Selects a channel for setting PAN using C1 to C0. X: Don’t Care 18/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Sampling Frequency List S3 to S0 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Sampling Frequency 4.0 kHz 8.0 kHz 16.0 kHz 32.0 kHz Undefined 6.4 kHz 12.8 kHz 25.6 kHz Undefined 5.3 kHz 10.6 kHz 21.2 kHz Undefined Undefined Undefined Undefined Voice Synthesis Algorithm List P1 to P0 0 1 2 3 Voice synthesis algorithm OKI 4-bit ADPCM OKI 4-bit ADPCM2 8-bit Straight PCM OKI 8-bit Nonlinear PCM 19/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 PAN and CVOL List L3 to L0 R3 to R0 V3 to V0 0 1 2 3 4 5 6 7 L3 to L0 R3 to R0 V3 to V0 8 9 10 11 12 13 14 15 Volume 0 dB –2 dB –4 dB –6 dB –8 dB –10 dB –12 dB –14 dB Volume –16 dB –18 dB –20 dB –22 dB –24 dB –26 dB –28 dB –30 dB OPT Command List Default * * * O4 0 0 1 1 x x x x x O3 0 1 0 1 x x x x x O2 x x x x 0 0 1 x x O1 x x x x 0 1 x x x O0 x x x x x x x 0 1 Description Sets the volumes of all channels to VDD (p-p). Sets the volumes of all channels to 1/2 VDD (p-p). Sets the volumes of all channels to 1/4 VDD (p-p). Sets the volumes of all channels to 1/8 VDD (p-p). Secondary digital filtering is performed. Primary digital filtering is performed. An on-chip digital filter is not used. Data is output directly from a D/A converter. (Output Z ≅ 3 kΩ) Data is output via a voltage follower. (Output Z ≅ 500 Ω) (Note) x indicates that data is independent of a function described. 20/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 LPF Frequency Characteristics [dB] This LSI contains a LPF in which a digital filter technology is used. The frequency characteristics when a secondary filter is used at fs = 8 kHz is shown below. The cutoff frequency is directly proportional to the sampling frequency fs. 0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 100 1000 10000 100000 [Hz] LPF Output Frequency Characteristics (fs = 8 kHz) 21/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Power Down Function To enter the power down mode, set the RESET pin to “L”. When an external clock is supplied to the XT pin, fix the XT pin at “L”. If an external clock is supplied via the XT pin during the power down mode, the IDS specification is not satisfied because current flows between the XT pin and the XT pin. The circuit of XT and XT pins is shown below. Internal master clock Approx. 500 kΩ Power down mode RESET XT “L” “L” XT Channel Status The channel status includes NCRn and BUSYn. These two channel statuses can be switched by setting the NCR/BUSY pin. Corresponding channel CH1 CH2 CH3 CH4 NCR/BUSY = “H” NCR/BUSY = “L” NCR1 NCR2 NCR3 NCR4 BUSY1 BUSY2 BUSY3 BUSY4 The n-channel NCR signal is NCRn and the n-channel BUSY signal is BUSYn. When NCRn is “H”, the START command and MUON command can be input for the next message of “n” channel to be played. When the phrase control table is used and BUSYn is “L”, do not enter the START command and MUON command even if NCRn is “H”. Otherwise, the LSI may malfunction. When BUSYn is “H”, the “n” channel does not output a voice. When BUSYn is “L”, the “n” channel outputs a voice. 22/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Parallel I/O (SERIAL = “L”) The outputs of channel statuses in parallel I/O mode are shown below. Pin name D3 D2 D1 D0 NCR/BUSY = “H” NCR4 NCR3 NCR2 NCR1 NCR/BUSY = “L” BUSY4 BUSY3 BUSY2 BUSY1 Serial I/O (SERIAL = “H”) The outputs when channel statuses are serially read during serial I/O mode are shown below. Signal name SO3 SO2 SO1 SO0 NCR/BUSY = “H” NCR4 NCR3 NCR2 NCR1 NCR/BUSY = “L” BUSY4 BUSY3 BUSY2 BUSY1 The outputs when channel statuses are output via SR3 to SR0 during serial I/O mode are shown below. Pin name SR3 SR2 SR1 SR0 NCR/BUSY = “H” NCR4 NCR3 NCR2 NCR1 NCR/BUSY = “L” BUSY4 BUSY3 BUSY2 BUSY1 23/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Voice Synthesis Algorithms The MSM9811 contains 4-bit ADPCM algorithm, 4-bit ADPCM2 algorithm, 8-bit straight PCM algorithm, and 8-bit non-linear PCM algorithm. One of these algorithms can be selected depending on the kind of voices to be played. The features of these algorithms are described below. Voice synthesis algorithm Oki 4-bit ADPCM Applicable waveform Normal voice waveforms Oki 4-bit ADPCM2 Normal voice waveforms Oki 8-bit Nonlinear PCM 8-bit PCM Sound effects including high frequency components Sound effects including high frequency components Feature Oki-original 4-bit ADPCM An improved version of Oki-original 4-bit ADPCM. This algorithm has improved its waveform traceability. This algorithm plays back the center of waveform as a 10-bit sound. Normal 8-bit PCM algorithm Memory Configuration and Voice Data Creation Method The ROM data consists of a voice management area, a voice data area, and a phrase control table area. The voice management area controls the voice data start address, voice data end address, and use of the phrase control table. 256 phrases of voice management data are stored in this area. The voice data area stores actual waveform data. The phrase control table area stores data for effectively using voice data. See “Phrase Control Table Function” for details. The ROM data is created by using a dedicated tool. ROM address 0x000000 0x0007FF Voice management area (16 Kbit fixed) 0x000800 Voice data area max: 0x7ffffff Phrase control table area max: 0x7ffffff This area is used to create ROM data. 24/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Playback Time and Memory Capacity The playback time is determined by external memory capacity, sampling frequency, and voice synthesis algorithm. The relationship is described below. Playback time = 1.024 × (Memory capacity – 16) (Kbits) Sampling frequency (kHz) × bit length (Seconds) (The bit length is 4 bits for ADPCM and ADPCM2 and 8 bits for PCM.) When the sampling frequency is 16 kHz and the voice synthesis algorithm is 4-bit ADPCM and an 8-Mbit ROM is used, the playback time is calculated as shown below. Playback time = 1.024 × (8192 – 16) (Kbits) 16 (kHz ) × 4 (bit) ≅ 131 (Seconds) In the above equation, the playback time when the phrase control table function is not used is shown. 25/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Mixing Function It is possible to mix 4 channels at a time. Moreover, the LSI is capable of starting or stopping voices of each channel separately. • Note on waveform clamping during mixing Increasing the number of channels to be mixed may cause clamping. To prevent clamping, reduce the volumes of all channels using the OPT command. (Note) Mixing using a different sampling frequency cannot be done. Continuous Playback Function The continuous playback function is used to continuously play back the next phrase after playing back a phrase. The next phrase to be played can be previously selected while a phrase is being played back. See “Continuous Playback Flowchart” for details. The continuous playback function is also available in the case of the phase control table. (Note) The following changes of voice synthesis algorithms are not permitted for continuous playback function. These changes may generate noises. • • ADPCM → ADPCM2 ADPCM2 → ADPCM 26/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Phrase Control Table Function The phrase control table function is used to continuously play back multiple phrases and to set up a volume. It is possible to perform the following functions using the phrase control table function. • • • CVOL setting Continuous playback (The number of continuous playbacks can be specified limitlessly, but depends on memory capacity.) Silence insertion function (4 mSec to 124 mSec) The memory capacity of voice ROM is effectively used by using the phrase control table function. Examples of ROM data when the phrase control table function is used are shown below. Example 1) Phrases when the phrase control table function is used Phrase 1 It is fine today Phrase 2 It is rainy today Phrase 3 It is fine tomorrow Phrase 4 It is rainy tomorrow Phrase 5 It is fine today Silence It is rainy tomorrow Example 2) ROM data when the example 1 is converted into ROM Address management area It rainy fine is today tomorrow Phrase control area (Note) In the phrase control table, each message of the playing phrase is provided with a CVOL value. Note that a CVOL value is overwritten over each message. 27/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Volume Function • • • • A volume can be adjusted at the stages of OPT, CVOL and PAN as shown below. A volume is set to all channels at the stage of OPT. A volume is set to each channel at the stage of CVOL. A volume is set to “L” and “R” of each channel at the stage of PAN. CH1 CVOL PAN[L] PAN[R] CH2 CVOL ADPCM Block PAN[L] Left-side Mixing Block Left-side Output Rightside Mixing Block Rightside Output PAN[R] OPT CH3 CVOL PAN[L] PAN[R] CH4 CVOL PAN[L] PAN[R] The output level attenuations when the CVOL, OPT and PAN commands are executed are shown below. <Left-side output volume calculation> Left-side output volume = (V + L) × –2 + (O4 × 2 + O3) × –6 [dB] V: Setting a volume (0 to 15) with the CVOL command L: Setting a left-side volume (0 to 15) with the PAN command O4, O3: Setting a volume (0 or 1) with the OPT command <Right-side output volume calculation> Right-side output volume = (V + L) x –2 + (O4 × 2 + O3) × –6 [dB] V: Setting a volume (0 to 15) with the CVOL command L: Setting a right-side volume (0 to 15) with the PAN command O4, O3: Setting a volume (0 or 1) with the OPT command 28/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 START Command The START command starts voice synthesis of the channel corresponding to the data stored in the TMP register. Table 1 shows the correspondence between data input (D7-D0) and channels. In the case of serial input, all 8 bits of D7 to D0 should be input serially from MSB. Table 1 Correspondence between D7-D0 and Channels Data bus Corresponding channel D7 0 D6 0 D5 0 D4 0 D3 CH4 D2 CH3 D1 CH2 D0 CH1 When the START command is input, data stored in the TMP register is set at the start register, and voice synthesis processing starts. For example, when all “1’s” are written from the data bus to the TMP register and the START command is input, all channels start voice synthesis simultaneously. Input the START command when the status signal (NCR or BUSY) of the channel to be started is at “H”. When NCR is “L”, input is disabled. When the phrase control table is used, input the START command while BUSY is “H”. Otherwise, the LSI may malfunction. Figure 4 shows the flowchart when the START command is input. RD pulse input NCRn=“H” NCRn corresponding to each channel is output to D7-D0 No Yes Subcommand input Check that D7-D0 corresponding to the channel to start voice synthesis is “H”. (BUSYn is “H” when the phrase control table is used.) After setting “L” to D7-D0 corresponding to the channel to start voice synthesis from the data bus, input the WR pulse. (Set CMD to “H”.) START command input Figure 4 START Command Input Flow STOP Command The STOP command stops voice synthesis processing of the channel corresponding to data stored in the TMP register. Table 2 shows the correspondence between data input (D7-D0) and channels. Table 2 Correspondence between D7-D0 and channels Data bus Corresponding channel D7 0 D6 0 D5 0 D4 0 D3 CH4 D2 CH3 D1 CH2 D0 CH1 When the STOP command is input, the LSI stops processing of voice synthesis of the corresponding channel at the rise of the WR pulse. When voice synthesis stops, the PCM value of that channel is cleared to 1/2 VDD, and the NCR and BUSY channel status signals become “H”. When “H” has been set at the START register, the START register is cleared to “L”. 29/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 LOOP Command The LOOP command repeats a playback of voice synthesis of the channel corresponding to data stored in the TMP registers. Table 3 shows the correspondence between data input (D7-D0) and channels. Table 3 Correspondence between D7-D0 and Channels Data bus Corresponding channel D7 0 D6 0 D5 0 D4 0 D3 CH4 D2 CH3 D1 CH2 D0 CH1 When the LOOP command is input, the LSI writes data of the TMP register to the LOOP register at rise of WR pulse, and repeats a playback of the channel where “H” is set. Once “H” is set at the LOOP register, playback continues until “L” is set from the outside. If the phrase control table function has been used for a phrase address, the edited voice is repeatedly played back. To end a repeating playback, set the register of the channel to end the repeat to “L” using the LOOP command again. When the register is set to “L”, repeating ends with the phrase next to the current playback phrase. If the START register has been set to continue the playback of another phrase, another phrase is played back continuously after repeating ends. Figure 5 shows an example. Channel 1 Phrase 1 Phrase 1 LOOP start start Phrase 1 Phrase 1 Phrase 1 LOOP end Phrase 2 start Phrase 2 Figure 5 LOOP Command Execution Example 30/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 OPT Command The OPT command changes the setting inside the LSI according to data stored in the TMP register. Table 4 shows the correspondence between data input (D7 to D0) and options. Table 4 OPT Command List Default * * * O4 0 0 1 1 x x x x x O3 0 1 0 1 x x x x x O2 x x x x 0 0 1 x x O1 x x x x 0 1 x x x O0 x x x x x x x 0 1 Description Sets the volumes of all channels to VDD (p-p). Sets the volumes of all channels to 1/2 VDD (p-p). Sets the volumes of all channels to 1/4 VDD (p-p). Sets the volumes of all channels to 1/8 VDD (p-p). Secondary digital filtering is performed. Primary digital filtering is performed. An on-chip digital filter is not used. Data is output directly from a D/A converter. (Output Z ≅ 3 kΩ) Data is output via a voltage follower. (Output Z ≅ 500 Ω) (Note) x indicates that data is independent of a function described. When the OPT command is input, the LSI changes the option at the rising edge of the WR pulse. When power is turned on, or when the RESET pulse is input, the registers corresponding to D4-D0 have been set to “L”. If the option is changed when voice synthesis is in execution, voice quality may change. Oki recommends to set the option after power is turned on or after RESET is input. 1) Volume Option Volume can be set by the CVOL command and PAN command, but a waveform may be clamped when channel synthesis is executed. If the CVOL command and PAN command are used to prevent a waveform from being clamped, the number of steps used for actual volume decreases, and effective voice synthesis may not be performed. If it is known that a waveform will be clamped, this option can set the volume of all channels to low, so that the number of steps of the volume can be utilized to the maximum level. 2) Digital Filter Processing This LSI has a built-in oversampling circuit for digital filter processing. This oversampling system evenly generates four times more points of sampling frequencies. When power is turned on or if the RESET pulse is input, those pulses have been set to pass through the oversampling circuit. If digital filter processing is unnecessary, change this setting by the OPT command. 31/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 3) Analog Output When power is turned on, it has been set that the output of the D/A converter is output via the voltage follower. To change this setting, use the OPT command. The output impedance of analog signals being output via the voltage follower is about 500 Ω. The output impedance of analog signals directly output from the D/A converter is about 3 kΩ. MUON Command The MUON command inserts silence into the specified channel at the rise of the WR pulse. The length of silence is according to the size of data stored in the TMP register. The length of silence data is input in advance, before executing the MUON command. Silence length can be set for 255 steps, 4 ms to 1020 ms, in 4 ms intervals. Silence time can be set as follows. tmu = (27 × (D7) + 26 × (D6) + 25 × (D5) + 24 × (D4) + 23 × (D3) + 22 × (D2) + 21 × (D1) + 20 × (D0)) × 4.096 ms The operation of the MUON command is similar to the START command to start voice synthesis. When the MUON command is input, “H” is set to the START register, and NCR and BUSY signals becomes “L”. If the MUON command is input when voice synthesis is in execution, silence time is inserted after voice synthesis ends. Input the MUON command when the status signal (NCR or BUSY) of the channel to start voice synthesis is at “H”. When NCR is “L”, input is disabled. When the phrase control table is used, input the MUON command while BUSY is “H”. Otherwise, the LSI may malfunction. Figure 6 shows a flow chart example when the MUON command is input. RD pulse input NCRn = “H” Yes Subcommand input NCRn corresponding to each channel is output to D7-D0. No Check that D7-D0 corresponding to the channel to insert silence is “H”. (BUSYn is “H” when the phrase control table is used.) After setting time of inserting silence from the data bus, input WR pulse (set CMD to “H”). MUON command input Specify channel by MUON command. Figure 6 MUON Command Input Flow 32/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 FADR Command The FADR command transfers data stored in the TMP register to the phrase address register of the corresponding channel at the rise of the WR pulse. For the phrase address, the user specification phrases have been set by an analysis tool, and the playback system, sampling frequency and start and stop address of voice data have been registered to the address management area. When the phrase address is set and the START command is input, the LSI reads data of the address management area, and starts voice synthesis. Since the phrase address is set by D7-D0, a maximum of 256 phrases can be set. The edit function can be used for phrase addresses, so not only one phrase but combinations with other phrases are possible. DADR Command The DADR command transfers data stored in the TMP (1-7) register to the start and stop address register of the corresponding channel at the rise of the WR pulse. For the direct address, the playback system, sampling frequency, and start and stop addresses of voice data are directly input from the microcomputer without using the address management area. Direct address playback system is available with channel 1 to 4, and not available with channel 5 to 8. Since the phrases that can be set at a phrase address is a maximum of 256, if voice data exceeds 256 phrases, use this command. Data on the playback system, sampling frequency, and start and stop address of voice data is displayed when an analysis tool is used. Data on the playback system, sampling frequency, and start and stop address of voice data is input to the TMP1 to TMP7 registers divided in 7 steps, unlike the data input of other commands. Figure 7 shows the input method. CMD(I) CS(I) WR(I) D7-D0(I) Stores TMP1 register data Stores TMP3 register data Stores TMP2 register data Stores TMP5 register data Stores TMP4 register data Stores TMP7 register data Stores TMP6 register data Executes command Figure 7 DADR Input Timing 33/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 As Figure 7 shows, CS and WR pulses are input 7 times when CMD is in “H” status, to input data to the TMP1 to TMP7 registers. The LSI increments the registers at the rise of the WR pulse when CMD is “H”. CMD must not be “L” while inputting data. When CMD becomes “L” while inputting data, the increment of registers is cleared. Table 5 shows the configuration of data to be input to TMP1 to TMP7 registers. Table 5 TMP Register Data Configuration D7 A23 A15 A7 T23 T15 T7 S3 TMP1 register TMP2 register TMP3 register TMP4 register TMP5 register TMP6 register TMP7 register D6 A22 A14 A6 T22 T14 T6 S2 D5 A21 A13 A5 T21 T13 T5 S1 D4 A20 A12 A4 T20 T12 T4 S0 D3 A19 A11 A3 T19 T11 T3 P1 D2 A18 A10 A2 T18 T10 T2 P0 D1 A17 A9 A1 T17 T9 T1 0 D0 A16 A8 A0 T16 T8 T0 0 Input the start address of voice data to TMP1 to TMP3 registers. Input the stop address of voice data to TMP4 to TMP6 registers. Input the playback system and sampling frequency to the TMP7 register. Table 6 shows the input data configuration of the playback system and sampling frequency. Table 6 Data Configuration of Playback System and Sampling Frequency S3 0 0 0 0 0 0 0 1 1 1 S2 0 0 0 0 1 1 1 0 0 0 P1 0 0 1 1 S1 0 0 1 1 0 1 1 0 1 1 S0 0 1 0 1 1 0 1 1 0 1 P0 0 1 0 1 Sampling frequency 4.0 kHz Sampling frequency 8.0 kHz Sampling frequency 16.0 kHz Sampling frequency 32.0 kHz Sampling frequency 6.4 kHz Sampling frequency 12.8 kHz Sampling frequency 25.6 kHz Sampling frequency 5.3 kHz Sampling frequency 10.6 kHz Sampling frequency 21.3 kHz Playback algorithm: 4-bit ADPCM Playback algorithm: 4-bit ADPCM2 Playback algorithm: 8-bit non-linear PCM Playback algorithm: 8-bit straight PCM 34/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 CVOL Command The CVOL command adjusts the volume of the specified channel to the volume which corresponds to the size of data stored in the TMP register at the rise of the WR pulse. Volume can be set in 16 steps up to –30 dB in –2dB step units. Set data as shown in Table 7. Table 7 Volume Setting Data Configuration D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume(dB) 0 dB –2 dB –4 dB –6 dB –8 dB –10 dB –12 dB –14 dB –16 dB –18 dB –20 dB –22 dB –24 dB –26 dB –28 dB –30 dB (D7-D4: Don't care) When power is turned on and the RESET pulse is input, all channels are set to 0dB. 35/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 PAN Command The PAN command adjusts the volume of the specified channel for the left and right respectively, to the volume which corresponds to the size of data stored in the TMP register at the rise of the WR pulse. This command enables stereo output. When volume is controlled by the OPT command and CVOL command, volume to be output is the volume stored in ROM multiplied by volume set by the OPT command, CVOL command, and PAN command respectively. This volume is output from LDAO and RDAO. Volume can be set in 16 steps up to –30 dB in –2 dB step units. Set data as shown in Table 8. Table 8 PAN Data Configuration D7 D3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 D6 D2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D5 D1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D4 D0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Volume at left side Volume at right side 0 dB –2 dB –4 dB –6 dB –8 dB –10 dB –12 dB –14 dB –16 dB –18 dB –20 dB –22 dB –24 dB –26 dB –28 dB –30 dB 36/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 FLOWCHART Monaural Playback Start monaural playback. Select a phrase to start voice synthesis. (FADR command) Set up a volume for each channel. (CVOL command) Set up PAN for each channel. (PAN command) Yes Do mixing with other channels? No Select a channel to start playback. (START command) End playback? Select a channel to end playback. (STOP command) 37/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Stereo Playback Start stereo playback. Select a phrase of a left side channel. (FADR command) Select a phrase of a right side channel. (FADR command) Set up PAN of a left side channel. (PAN command) Set up PAN of a right side channel. (PAN command) Yes Do mixing with other channels? No Start playback. (START command) End playback? Select a channel to end playback. (STOP command) 38/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Continuous Playback Start continuous playback. Select a phrase to start voice synthesis. (FADR command) Set up PAN. (PAN command) Start voice synthesis of the first phrase. Set up CVOL. (CVOL command) Select a channel to start playback. (START command) No NCR = 1? Is it possible to select a phrase to be played next? Yes Select a phrase to be played next. (FADR command) Select a phrase to be played next. Select a channel to start playback. (START command) 39/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 Changing Volume Level It is possible to change the volume level of a channel that is being played. If the CVOL command is issued when voices are not being played, the changed volume level will be valid during the next playback. When the phrase control table function is used, the value of CVOL is changed by the phrase control table function because there are volume setting values in the phrase control table. Voices are being played (BUSY = 0) Change the volume level of the selected channel? No Yes Change the volume level of the selected channel. CVOL command Change PAN of the channel? Yes PAN command No Change the volume level of the selected channel. 40/44 MCU XT XT RDAO LDAO ROE RD7-0 RA18-0 RA20 RA19 AMP AMP 8 19 1G 2G OE D7-0 A18-0 CE MSM27C401CZ OE D7-0 A18-0 CE MSM27C401CZ OE D7-0 A18-0 CE MSM27C401CZ OE D7-0 A18-0 CE MSM27C401CZ OKI Semiconductor Application circuit example when four 4 Mbit OTP ROMs are connected (serial input interface) RCS TEST1 TEST2 TEST3 TEST4 SERIAL NCR/BUSY SD SI SO CMD CS WR RD RESET M9811 74HC139 Y3 Y2 2B Y1 2A Y0 FEDL9811FULL-04 MSM9811 APPLICATION CIRCUITS 41/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 PACKAGE DIMENSIONS (Unit: mm) QFP64-P-1414-0.80-BK Mirror finish 5 Package material Epoxy resin Lead frame material 42 alloy Pin treatment Solder plating ≥5µm) ( Package weight (g) 0.87 TYP. Rev. No./Last Revised 6/Feb. 23, 2001 Notes for Mounting the Surface Mount Type Package The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki’s responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times). 42/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 REVISION HISTORY Page Previous Current Edition Edition Document No. Date FEDL9811FULL-01 Jun. 2000 – – Edition 1 FEDL9811FULL-02 May. 2001 – – Edition 2 7,20,31,32 7,20,31,32 Corrected the output impedance of analog signals. 7 7 Corrected the word ”AOUT” to “LDAO,RDAO” In Analog Characteristics table. – – Edition 4 FEDL9811FULL-03 FEDL9811FULL-04 Description Jun 20, 2003 Sep. 1, 2004 43/44 FEDL9811FULL-04 OKI Semiconductor MSM9811 NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. 3. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. Neither indemnity against nor license of a third party’s industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party’s right which may result from the use thereof. 6. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. 7. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd. 44/44