AP7217 500mA CMOS LDO General Description Features • • • • • • • • • Very Low Dropout Voltage Low Current Consumption: Typ. 50μA Output Voltage: 3.3V Guaranteed 500mA (min) Output Input Range up to 5.5V Current Limiting Stable with either electrolytic capacitor or low-ESR MLCC (multi-layer ceramic capacitor) Low Temperature Coefficient SOP-8L: Available in “Green” Molding Compound (no Br, Sb) Lead Free Finish / RoHS Compliant (Note 1) The AP7217 low-dropout linear regulator operates from a 3.3V to 5.5V supply and delivers a guaranteed 500mA (min) continuous load current. The high-accuracy output voltage is preset to an internally trimmed voltage. An active-low open-drain reset output remains asserted for at least 20ms (TYP) after output voltage reaches VDF. The space-saving SOP-8L package is suitable for “pocket” and hand-held applications. Applications • • • • HD/BlueRay DVD & MP3/4 Players Mobile Handsets and Smartphones Digital Still Camera Hand-Held Computers Ordering Information AP 7217 - XX X X X Output voltage 33 : 3.3V Note: Package Lead free Packing S : SOP-8L G : Green -U : Tube -13 : Tape & Reel 1. RoHS revision 13.2.2003. Glass and High Temperature Solder Exemptions Applied, see EU Directive Annex Notes 5 and 7. Device Package Code Packaging (Note 2) AP7217-XXS S SOP-8L Note: Tube Part Number Quantity Suffix 100 -U 13” Tape and Reel Part Number Quantity Suffix 2500/Tape & Reel -13 2. Pad layout as shown on Diodes Inc. suggested pad layout document AP02001, which can be on our website at http://www.diodes.com/datasheets/ap02001.pdf. AP7217 Rev. 1 1 of 7 www.diodes.com OCTOBER 2007 © Diodes Incorporated AP7217 500mA CMOS LDO Pin Descriptions Pin Assignments ( Top View ) NC 1 Pin Name NC VROUT NC VIN NC VDOUT GND EN 8 EN VROUT 2 7 GND AP7217 NC 3 6 VD OUT VIN 4 5 NC Pin No. Function 1 2 3 4 5 6 7 8 No Connection Voltage Output No Connection Supply Voltage No connection VD Output (Reset on I/P) Ground Enable (VR On/Off) SOP-8L Block Diagram EN Enable VIN On - Off ERROR AMP Bandgap + 1.2V Current Limit VROUT R1 VDOUT + R3 R2 VD Comp. R4 GND Absolute Maximum Ratings Symbol Parameter ESD HBM Human Body Model ESD Protection ESD MM VIN IOUT VROUT TJ TJ(MAX) PD Machine Model ESD Protection Input Voltage Output Current Output Voltage Operating Junction Temperature Range Maximum Junction Temperature Internal Power Dissipation AP7217 Rev. 1 2 of 7 www.diodes.com Rating Unit 2 KV 450 +6 PD/ (VIN-VO) GND - 0.3 ~ VIN+ 0.3 -40 to +125 150 1.2 V V mA V ºC ºC W OCTOBER 2007 © Diodes Incorporated AP7217 500mA CMOS LDO Recommended Operating Conditions Symbol VIN IOUT TA Parameter Min 3.3 0 -40 Input Voltage Output Current Operating Ambient Temperature Max 5.5 500 85 Unit V mA ºC Electrical Characteristics (TA = 25°C, CIN = 1µF, COUT = 1µF, VEN = 2V, unless otherwise noted) Symbol Parameter Test Conditions IQ Quiescent Current IO = 0mA VEN = Off ISTB Standby Current VIN = 5.0V Output Voltage IO = 30mA, VIN = 5V Accuracy VROUT VROUT Temperature -40°C to 85°C, IOUT = 30mA Coefficient VDROPOUT IOUT ILIMIT Ishort ΔVLINE/ΔVIN/VROUT ΔVROUT PSRR VEH VEL IEN Note: Dropout Voltage IOUT = 100mA Output Current VIN = 5.3V Current Limit Short Circuit Current Line Regulation Load Regulation VIN = 5.3V VIN = 5.3V 4.3V ≤ VIN ≤ 5.5V; IOUT = 30mA 1mA ≤ IOUT ≤ 100mA, VIN = 5.3V Power Supply Rejection VIN = 4.3V+0.5Vp-pAC, IOUT = 50mA EN Input Threshold Output ON Output OFF VDF Enable Pin Current Detect fall voltage VHysteresis VD Hysteresis Range IVDOUT VD Supply Current tRP θJA θJC VDOUT Delay Time Thermal Resistance Thermal Resistance Min - 3.234 Max 70 Unit μA 15 30 μA 3.300 3.366 V ppm / oC ±100 100 250 500 F= 1KHz mV mA 600 50 0.01 15 ±0.2 50 55 3.91 VDF x1.05 mA mA %/V mV dB 1.6 -0.1 3.83 VDF x1.02 VDOUT = 0.5V VIN = 2.0V 3.0V VIN = 1.8V to VDF+1V SOP-8L (Note 3) SOP-8L (Note 3) Typ. 50 0.25 0.1 3.98 VDF x1.08 V V μA V V mA 10 20 30 20 134 28 40 mSec ºC/W ºC/W 3. Test conditions for SOP-8L: Devices mounted on FR-4 PC board, MRP, 2oz copper layout, calibrate at TJ=150 ºC, measure at TA=25ºC, minimum recommended pad layout AP7217 Rev. 1 3 of 7 www.diodes.com OCTOBER 2007 © Diodes Incorporated AP7217 500mA CMOS LDO Typical Application U1 4 VIN VIN VROUT 2 VROUT AP7217 100K ON CIN VDOUT 6 VDOUT 1uF 8 EN GND COUT OFF 1uF 7 Typical Performance Characteristics Iout vs. Dropout voltage Vcc vs. Quiescent current 90 900 80 800 70 700 Dropout (mV) 1000 Iccq (uA) 100 60 50 40 30 600 500 400 300 20 200 10 100 0 0 3.6 4 4.3 5 30 5.5 100 Vcc (V) 300 500 Iout (mA) Vcc vs. Standby current Delay time vs. Temperature 24 70 23 60 I-standby (uA) Delay time (mS) 22 21 20 19 18 50 40 30 20 17 10 16 15 0 -40 25 85 100 Temperature(o C) AP7217 Rev. 1 3.6 4 4.3 5 5.5 Vcc (V) 4 of 7 www.diodes.com OCTOBER 2007 © Diodes Incorporated AP7217 500mA CMOS LDO Typical Performance Characteristics (Continued) Load Transient Response (VIN=4.3V, IOUT=0~500mA) Load Transient Response (VIN=5.5V, IOUT=0~500mA) VIN VIN VROUT VROUT IOUT IOUT Load Transient Response (VIN=4.3V, IOUT=100~300mA) Load Transient Response (VIN=5.5V, IOUT=100~300mA) VIN VIN VROUT VROUT IOUT IOUT AP7217 Rev. 1 5 of 7 www.diodes.com OCTOBER 2007 © Diodes Incorporated AP7217 500mA CMOS LDO Timing Diagram tRP 20mSec-TYP. VIN 1.8V VDOUT EN VROUT Application Note Input Capacitor A 1μF ceramic capacitor is recommended to connect between IN and GND pins to decouple input power supply glitch and noise. The amount of the capacitance may be increased without limit. A lower ESR (Equivalent Series Resistance) capacitor allows the use of less capacitance, while higher ESR type requires more capacitance. This input capacitor must be located as close as possible to the device to assure input stability and less noise. For PCB layout, a wide copper trace is required for both IN and GND. Output Capacitor The output capacitor is required to stabilize and help the transient response of the LDO. The AP7217 is designed to have excellent transient response for most applications with a small amount of output capacitance. The AP7217 is stable with any small ceramic output capacitors of 1.0μF or higher value, and the temperature coefficients of X7R or X5R type. Additional capacitance helps to reduce undershoot and overshoot during transient. For PCB layout, the output capacitor must be placed as close as possible to OUT and GND pins, and keep the leads as short as possible. ENABLE/SHUTDOWN Operation The AP7217 is turned on by setting the EN pin high, and is turned off by pulling it low. If this feature is not used, the EN pin should be tied to IN pin to keep the regulator output on at all time. To ensure proper operation, the signal source used to drive the EN pin must be able to swing above and below the specified turn-on/off voltage thresholds listed in the Electrical Characteristics section under VIL and VIH. AP7217 Rev. 1 EN=0 EN=1 VROUT 0V 3.3V VDOUT Φ Φ Current Limit Protection When output current at OUT pin is higher than current limit threshold, the current limit protection will be triggered and clamp the output current to approximately 600mA to prevent over-current and to protect the regulator from damage due to overheating. Short circuit protection When VRout pin is shorted to GND or VRout voltage is less than 200mV, short circuit protection will be triggered and clamp the output current to approximately 50mA. VDOUT (reset output) ---Open-Drain Active-Low reset output--In general, VDOUT is pulled up by a resistor (100Kohm) to VIN. The AP7217 microprocess (uP) supervisory circuitry asserts a guaranteed logic-low reset during power-up and power-down. Reset is asserted asserts when VIN is below the reset threshold and remain asserted for at least tRP after VIN rises above the reset threshold. As long as VIN is lower than the reset threshold, VDOUT remains at logic "0". When VIN become higher than VTH, a logic "1" is asserted after a time delay defined by tRP. 6 of 7 www.diodes.com OCTOBER 2007 © Diodes Incorporated AP7217 500mA CMOS LDO Marking Information ( Top View ) 8 5 Logo Part No. 7217-33 G : Green Internal code Xth week : 01~52 Year : "07" = 2007 "08" = 2008 YY WW X X 4 ~ 1 SOP-8L Package Information (unit: mm) 0.254 0.08/0.25 5.79/6.20 3.70/4.10 Package type: SOP-8L Gauge Plane Seating Plane 0.38/1.27 Detail "A" 7°~9° 7°~9° 0.20typ 1.30/1.50 0.3/0.5 1.27typ 1.75max. 0.35max. 45° Detail "A" 0.78 3.70/4.10 4.80/5.30 5.4 8x-0.60 8x-1.55 6x-1.27 Land Pattern Recommendation (Unit: mm) IMPORTANT NOTICE Diodes Incorporated and its subsidiaries reserve the right to make modifications, enhancements, improvements, corrections or other changes without further notice to any product herein. Diodes Incorporated does not assume any liability arising out of the application or use of any product described herein; neither does it convey any license under its patent rights, nor the rights of others. The user of products in such applications shall assume all risks of such use and will agree to hold Diodes Incorporated and all the companies whose products are represented on our website, harmless against all damages. LIFE SUPPORT Diodes Incorporated products are not authorized for use as critical components in life support devices or systems without the expressed written approval of the President of Diodes Incorporated. AP7217 Rev. 1 7 of 7 www.diodes.com OCTOBER 2007 © Diodes Incorporated