ICST ICS557M-01T Pci-express clock source Datasheet

ICS557-01
PCI-EXPRESS CLOCK SOURCE
Description
Features
The ICS557-01 is a clock chip designed for use in
PCI-Express Cards as a clock source. It provides a pair
of differential outputs at 100 MHz in a small 8-pin SOIC
package.
• Supports PCI-ExpressTM HCSL Outputs
0.7 V current mode differential pair
•
•
•
•
•
•
•
•
•
Using ICS’ patented Phase-Locked Loop (PLL)
techniques, the device takes a 25 MHz crystal input
and produces HCSL (Host Clock Signal Level)
differential outputs at 100 MHz clock frequency. LVDS
signal levels can also be supported via an alternative
termination scheme.
Supports LVDS Output Levels
Packaged in 8-pin SOIC
Available in Pb (lead) free package
Operating voltage of 3.3 V
Low power consumption
Input frequency of 25 MHz
Short term jitter 100 ps (peak-to-peak)
Output Enable via pin selection
Industrial temperature range available
Block Diagram
VDD
CLK
Phase Lock
Loop
X1
25 MHz
crystal /clock
X2
CLK
Clock
Buffer/
Crystal
Oscillator
Crystal Tuning Capacitors
GND
1
MDS 557-01 F
I n t e gra te d C i r c u i t S y s t e m s
RR(IREF)
OE
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
Pin Assignment
OE
1
8
V DD
X1
2
7
CL K
X2
3
6
CL K
GN D
4
5
I RE F
8 P i n ( 1 5 0 mi l ) S OI C
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
1
OE
Input
Output Enable signal
(H = outputs are enabled, L = outputs are disabled/tristated).
Internal pull-up resistor.
2
X1
Input
Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
3
X2
XO
4
GND
Power
5
IREF
Output A 475Ω precision resistor connected between this pin and ground
establishes the external reference current.
6
CLK
Output HCSL differential complementary clock output.
7
CLK
Output HCSL differential clock output.
8
VDD
Power
Crystal Connection. Connect to a parallel mode crystal.
Leave floating if clock input.
Connect to ground.
Connect to +3.3 V.
2
MDS 557-01 F
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Pin Description
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
Applications Information
Output Structures
External Components
A minimum number of external components are
required for proper operation.
6*IREF
IREF
=2.3 mA
Decoupling Capacitors
Decoupling capacitors of 0.01 µF should be connected
between VDD and the ground plane (pin 4) as close to
the VDD pin as possible. Do not share ground vias
between components. Route power from power source
through the capacitor pad and then into ICS pin.
Crystal
R R 475Ω
A 25 MHz fundamental mode parallel resonant crystal
with CL = 16 pF should be used. This crystal must have
less than 300 ppm of error across temperature in order
for the ICS557-01 to meet PCI Express specifications.
See Output Termination
Sections - Pages 3 ~ 5
General PCB Layout Recommendations
Crystal Capacitors
Crystal capacitors are connected from pins X1 to
ground and X2 to ground to optimize the accuracy of
the output frequency.
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Crystal Capacitors (pF) = (CL- 8) * 2
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
2. No vias should be used between decoupling
capacitor and VDD pin.
Current Source (Iref) Reference Resistor - RR
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
CL= Crystal’s load capacitance in pF
If board target trace impedance (Z) is 50Ω, then RR =
475Ω (1%), providing IREF of 2.32 mA. The output
current (IOH) is equal to 6*IREF.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-01 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-01.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
The ICS557-01can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
PCI-Express Layout Guidelines
Recommendations for Differential Routing
as non-coupled 50 ohm trace.
as non-coupled 50 ohm trace.
as non-coupled 50 ohm trace.
Dimension
0.5
0.2
0.2
3
49
ferential Routing on a Single PCB
as coupled microstrip 100 ohm differential trace.
as coupled stripline 100 ohm differential trace.
Dimension
2 min to
1.8 min to
ial Routing to a PCI Express Connector
as coupled microstrip 100 ohm differential trace.
as coupled stripline 100 ohm differential trace.
Dimension
0.25 to
0.225 min t
Figure 1: PCI-Express Device Routing
L1
L2
L4
RS
L1’
L4’
L2’
RS
RT
ICS557-01
Output
Clock
L3’
RT
PCI-Express
Load or
Connector
L3
Typical PCI-Express (HCSL)
Waveform
700 mV
0
tOR
500 ps
500 ps
0.52 V
0.175 V
0.52 V
0.175 V
4
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
RP
RQ
RT
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
Dimension or Value
0.5 max
0.2 max
100
100
150
Unit
inch
inch
ohm
ohm
ohm
Figure 3: LVDS Device Routing
L1
L3
RQ
L3’
L1’
RT
RT
ICS557-01
Clock
Output
RP
L2’
LVDS
Device
Load
L2
Typical LVDS Waveform
1325 mV
1000 mV
tOR
500 ps
500 ps
1250 mV
1150 mV
1250 mV
1150 mV
5
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In te grated Circuit Systems
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-01. These ratings are
stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
Ambient Operating Temperature (commercial)
0 to +70°C
Ambient Operating Temperature (industrial)
-40 to +85°C
Storage Temperature
-65 to +150°C
Junction Temperature
125°C
Soldering Temperature
260°C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Supply Voltage
Conditions
V
1
Min.
Typ.
Max.
3.135
3.465
Units
Input High Voltage
VIH
2.0
VDD +0.3
V
Input Low Voltage1
VIL
VSS-0.3
0.8
V
Input Leakage Current2
IIL
0 < Vin < VDD
-5
5
µA
Operating Supply Current
IDD
With 50Ω and 2 pF load
55
mA
OE =Low
35
mA
Input pin capacitance
7
pF
Output pin capacitance
6
pF
5
nH
IDDOE
Input Capacitance
CIN
Output Capacitance
COUT
Pin Inductance
LPIN
Output Resistance
Rout
CLK outputs
Pull-up Resistor
RPUP
OE
1 Single edge is monotonic when transitioning through
2 Inputs with pull-ups/-downs are not included.
kΩ
60
kΩ
region.
6
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
AC Electrical Characteristics - CLK/CLK
Unless stated otherwise, VDD=3.3 V ±5%, Ambient Temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Input Frequency
Output Frequency
1,2
VOH
1,2
VOL
Output High Voltage
Output Low Voltage
660
Crossing Point
Voltage1,2
Absolute
Crossing Point
Voltage1,2,4
Variation over all edges
Typ.
100
MHz
700
0
250
350
850
mV
mV
550
mV
140
mV
100
1,2
Units
MHz
-150
Jitter, Cycle-to-Cycle1,3
Max.
25
ps
Rise Time
tOR
from 0.175 V to 0.525 V
175
332
700
ps
Fall Time1,2
tOF
from 0.525 V to 0.175 V
175
344
700
ps
125
ps
55
%
Rise/Fall Time
Variation1,2
Duty Cycle1,3
45
5
Output Enable Time
All outputs
30
µs
Output Disable Time5
All outputs
30
µs
From power-up VDD=3.3 V
3.0
ms
3.0
ms
Stabilization Time
tSTABLE
Spread Change Time
tSPREAD Settling period after spread change
1
Test setup is RL=50 ohms with 2 pF, RR = 475Ω (1%).
2
Measurement taken from a single-ended waveform.
3
Measurement taken from a differential waveform.
4
Measured at the crossing point where instantaneous voltages of both CLKOUT and CLKOUT are equal.
5
CLKOUT pins are tri-stated when OE is low asserted. CLKOUT is driven differential when OE is high.
Thermal Characteristics (8-pin SOIC)
Parameter
Thermal Resistance Junction to
Ambient
Thermal Resistance Junction to Case
Conditions
Min.
Typ.
Max. Units
θJA
Still air
150
°C/W
θJA
1 m/s air flow
140
°C/W
θJA
3 m/s air flow
120
°C/W
40
°C/W
θJC
7
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Symbol
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
Marking Diagram (ICS557M-01)
8
Marking Diagram (ICS557MI-01)
8
5
5
557MI01
######
YYWW
557M-01
######
YYWW
1
1
4
Marking Diagram (ICS557M-01LF)
8
4
Marking Diagram (ICS557MI-01LF)
5
8
557M-01L
######
YYWW
1
5
557MI01L
######
YYWW
4
1
4
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “L” designates Pb (lead) free packaging.
4. Bottom marking: (orgin). Origin = country of origin if not USA.
8
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Symbol
Min
Max
Min
Max
A
1.35
1.75
.0532
.0688
A1
0.10
0.25
.0040
.0098
B
0.33
0.51
.013
.020
C
0.19
0.25
.0075
.0098
D
4.80
5.00
.1890
.1968
E
3.80
4.00
.1497
.1574
8
E
Inches*
H
INDEX
AREA
e
1 2
D
1.27 BASIC
0.050 BASIC
H
5.80
6.20
.2284
.2440
h
0.25
0.50
.010
.020
L
0.40
1.27
.016
.050
α
0°
8°
0°
8°
*For reference only. Controlling dimensions in mm.
A
h x 45
A1
C
-Ce
SEATING
PLANE
B
L
.10 (.004)
9
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In te grated Circuit Systems
C
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ICS557-01
PCI-EXPRESS CLOCK SOURCE
Ordering Information
Part / Order Number
Marking
ICS557M-01
See Page 8
Shipping Packaging
Package
Temperature
Tubes
8-pin SOIC
0 to +70° C
ICS557M-01T
Tape and Reel
8-pin SOIC
0 to +70° C
ICS557M-01LF
Tubes
8-pin SOIC
0 to +70° C
ICS557M-01LFT
Tape and Reel
8-pin SOIC
0 to +70° C
ICS557MI-01
Tubes
8-pin SOIC
-40 to +85° C
ICS557MI-01T
Tape and Reel
8-pin SOIC
-40 to +85° C
ICS557MI-01LF
Tubes
8-pin SOIC
-40 to +85° C
ICS557MI-01LFT
Tape and Reel
8-pin SOIC
-40 to +85° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
10
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In te grat ed Circuit Syst ems
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