NOT RECOMMENDED FOR NEW DESIGNS NO RECOMMENDED REPLACEMENT contact our Technical Support Center at 1-888-INTERSIL or www.intersil.com/tsc HIP6021 DATASHEET FN4684 Rev 1.00 March 8, 2005 Advanced PWM and Triple Linear Power Controller The HIP6021 provides the power control and protection for four output voltages in high-performance, graphics intensive microprocessor and computer applications. The IC integrates a voltage-mode PWM controller and three linear controllers, as well as the monitoring and protection functions into a 28pin SOIC package. The PWM controller regulates the microprocessor core voltage with a synchronous-rectified buck converter. The linear controllers regulate the computer system’s AGP 1.5V or 3.3V bus power, the 1.5V GTL bus power, and the 1.8V power for the North/South Bridge core voltage and/or cache memory circuits. The HIP6021 includes an Intel-compatible, TTL 5-input digital-to-analog converter (DAC) that adjusts the core PWM output voltage from 1.3VDC to 2.05VDC in 0.05V steps and from 2.1VDC to 3.5VDC in 0.1V increments. The precision reference and voltage-mode control provide 1% static regulation. The AGP bus power linear controller’s output (VOUT2) is user-selectable, through a TTL-compatible signal applied at the SELECT pin, for levels of 1.5V or 3.3V with 3% accuracy. Based on the status of the FIX pin, the other two linear regulators provide either fixed output voltages of 1.5V3% (VOUT3) and 1.8V3% (VOUT4), or user-adjustable by means of an external resistor divider. All linear controllers can employ either N-channel MOSFETs or bipolar NPNs for the pass transistor. The HIP6021 monitors all the output voltages. A single Power Good signal is issued when the core is within 10% of the DAC setting and all other outputs are above their undervoltage levels. Additional built-in over-voltage protection for the core output uses the lower MOSFET to prevent output voltages above 115% of the DAC setting. The PWM controller’s over-current function monitors the output current by using the voltage drop across the upper MOSFET’s rDS(ON). TEMP. RANGE (oC) HIP6021CB 0 to 70 HIP6021CBZ (Note) HIP6021EVAL1 0 to 70 • Provides 4 Regulated Voltages - Microprocessor Core, AGP Bus, Memory, and GTL Bus Power • Drives N-Channel MOSFETs • Linear Regulator Drives Compatible with both MOSFET and Bipolar Series Pass Transistors • Fixed or Externally Resistor-Adjustable Linear Outputs (FIX Pin) • Simple Single-Loop Control Design - Voltage-Mode PWM Control • Fast PWM Converter Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Ratio • Excellent Output Voltage Regulation - Core PWM Output: 1% Over Temperature - Other Outputs: 3% Over Temperature • TTL-Compatible 5-Bit DAC Microprocessor Core Output Voltage Selection - Wide Range . . . . . . . . . . . . . . . . . . . 1.3VDC to 3.5VDC • Power-Good Output Voltage Monitor • Over-Voltage and Over-Current Fault Monitors - Switching Regulator Does Not Require Extra Current Sensing Element, Uses MOSFET’s rDS(ON) • Small Converter Size - Constant Frequency Operation - 200kHz Free-Running Oscillator; Programmable From 50kHz to Over 1MHz - Small External Component Count • Pb-Free Available (RoHS Compliant) Pinout Ordering Information PART NUMBER Features PACKAGE 28 Ld SOIC M28.3 28 Ld SOIC (Pb-free) M28.3 Evaluation Board Add “-T” suffix for tape and reel. NOTE: Intersil Pb-free products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate termination finish, which are RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. Applications • Motherboard Power Regulation for Computers HIP6021 (SOIC) TOP VIEW PKG. DWG. # DRIVE2 1 27 UGATE VID4 3 26 PHASE VID3 4 25 LGATE VID2 5 24 PGND VID1 6 23 OCSET VID0 7 22 VSEN1 PGOOD 8 21 FB SD 9 20 COMP VSEN2 10 19 VSEN3 SELECT 11 SS 12 FAULT/RT 13 VSEN4 14 FN4684 Rev 1.00 March 8, 2005 28 VCC FIX 2 18 DRIVE3 17 GND 16 VAUX 15 DRIVE4 Page 1 of 15 SELECT VSEN2 DRIVE2 VSEN4 DRIVE4 DRIVE3 - + - + + - 1.5V or 3.3V x 0.75 - + - FN4684 Rev 1.00 March 8, 2005 + VAUX - + 1.26V x 0.75 LUV FIX SD FAULT / RT SS OV 28A VCC SOFTINHIBIT START AND FAULT FAULT LOGIC LINEAR UNDERVOLTAGE OSCILLATOR - + - + VSEN3 4.5V DACOUT FB ERROR AMP1 x 1.15 x 0.90 x 1.10 - + - + - + + - VSEN1 COMP OC1 - PWM1 VID1 POWER-ON VCC SYNCH DRIVE GATE CONTROL DRIVE1 RESET (POR) VID4 VID3 VID2 TTL D/A CONVERTER (DAC) PWM COMP1 VID0 - + + 200A OCSET VCC VCC GND PGND LGATE PHASE UGATE PGOOD VAUX HIP6021 Block Diagram Page 2 of 15 HIP6021 Simplified Power System Diagram +5VIN +3.3VIN Q1 LINEAR CONTROLLER Q3 VOUT1 PWM CONTROLLER Q2 VOUT2 HIP6021 Q4 VOUT3 LINEAR CONTROLLER LINEAR CONTROLLER Q5 VOUT4 Typical Application +12VIN +5VIN LIN CIN VCC OCSET +3.3VIN POWERGOOD PGOOD Q3 VOUT2 DRIVE2 1.5V OR 3.3V UGATE VSEN2 COUT2 LGATE LOUT1 Q2 VOUT1 1.3V TO 3.5V COUT1 PGND SELECT TYPEDET Q1 PHASE VSEN1 VAUX HIP6021 Q4 VOUT3 1.5V DRIVE3 FB COMP VSEN3 COUT3 FIX FAULT / RT VID0 DRIVE4 Q5 VOUT4 1.8V VID1 VID2 VSEN4 VID3 SS COUT4 VID4 CSS GND FN4684 Rev 1.00 March 8, 2005 Page 3 of 15 HIP6021 Absolute Maximum Ratings Thermal Information Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +15V PGOOD, RT/FAULT, DRIVE, PHASE, and GATE Voltage . . . . . . . . . . . . . . . GND - 0.3V to VCC + 0.3V Input, Output or I/O Voltage . . . . . . . . . . . . . . . . . . GND -0.3V to 7V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 1 Thermal Resistance (Typical, Note 1) JA (oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70 Maximum Junction Temperature (Plastic Package) . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only) Operating Conditions Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . +12V 10% Ambient Temperature Range. . . . . . . . . . . . . . . . . . . . 0oC to 70oC Junction Temperature Range . . . . . . . . . . . . . . . . . . 0oC to 125oC CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. NOTE: 1. JA is measured with the component mounted on an evaluation PC board in free air. Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS UGATE, LGATE, DRIVE2, DRIVE3, and DRIVE4 Open - 9 - mA Rising VCC Threshold VOCSET = 4.5V - - 10.4 V Falling VCC Threshold VOCSET = 4.5V 8.2 - - V Rising VAUX Threshold VOCSET = 4.5V - 2.5 - V VAUX Threshold Hysteresis VOCSET = 4.5V - 0.5 - V - 1.26 - V RT = OPEN 185 200 215 kHz 6k < RT to GND < 200k -15 - +15 % - 1.9 - VP-P DAC(VID0-VID4) Input Low Voltage - - 0.8 V DAC(VID0-VID4) Input High Voltage 2.0 - - V DACOUT Voltage Accuracy -1.0 - +1.0 % VCC SUPPLY CURRENT Nominal Supply Current ICC POWER-ON RESET Rising VOCSET Threshold OSCILLATOR Free Running Frequency FOSC Total Variation Ramp Amplitude VOSC RT = Open DAC AND BANDGAP REFERENCE Bandgap Reference Voltage VBG Bandgap Reference Tolerance - 1.265 - V -2.5 - +2.5 % - 3 - % LINEAR REGULATORS (OUT2, OUT3, AND OUT4) Regulation (All Linears) VSEN2 Regulation Voltage VREG2 SELECT < 0.8V - 1.5 - V VSEN2 Regulation Voltage VREG2 SELECT > 2.0V - 3.3 - V VSEN3 Regulation Voltage VREG3 - 1.5 - V VSEN4 Regulation Voltage VREG4 - 1.8 - V VSEN Rising - 75 - % Under-Voltage Hysteresis (VSEN/VREG) VSEN Falling - 7 - % Output Drive Current (All Linears) VAUX-VDRIVE > 0.6V 20 40 - mA Under-Voltage Level (VSEN/VREG) FN4684 Rev 1.00 March 8, 2005 VSENUV Page 4 of 15 HIP6021 Electrical Specifications Recommended Operating Conditions, Unless Otherwise Noted. Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic (Continued) PARAMETER SYMBOL TEST CONDITIONS MIN TYP MAX UNITS - 88 - dB - 15 - MHz COMP = 10pF - 6 - V/s SYNCHRONOUS PWM CONTROLLER ERROR AMPLIFIER DC Gain Gain-Bandwidth Product GBWP Slew Rate SR PWM CONTROLLER GATE DRIVER UGATE Source IUGATE VCC = 12V, VUGATE = 6V - 1 - A UGATE Sink RUGATE VGATE-PHASE = 1V - 1.7 3.5 LGATE Source ILGATE VCC = 12V, VLGATE = 1V - 1 - A LGATE Sink RLGATE VLGATE = 1V - 1.4 3.0 VSEN1 Rising - 115 120 % PROTECTION VSEN1 Over-Voltage (VSEN1/DACOUT) FAULT Sourcing Current IOVP VFAULT/RT = 2.0V - 8.5 - mA OCSET1 Current Source IOCSET VOCSET = 4.5VDC 170 200 230 A - 28 - A Soft-Start Current ISS POWER GOOD VSEN1 Upper Threshold (VSEN1/DACOUT) VSEN1 Rising 108 - 110 % VSEN1 Under-Voltage (VSEN1/DACOUT) VSEN1 Rising 92 - 94 % VSEN1 Hysteresis (VSEN1/DACOUT) Upper/Lower Threshold - 2 - % IPGOOD = -4mA - - 0.8 V PGOOD Voltage Low VPGOOD Typical Performance Curves 100 CUGATE1 = CUGATE2 = CLGATE1 = C C = 4800pF VIN = 5V 80 VCC = 12V RT PULLUP TO +12V ICC (mA) RESISTANCE (k) 1000 100 60 C = 3600pF 40 C = 1500pF 10 RT PULLDOWN TO VSS 10 100 SWITCHING FREQUENCY (kHz) FIGURE 1. RT RESISTANCE vs FREQUENCY FN4684 Rev 1.00 March 8, 2005 20 C = 660pF 1000 0 100 200 300 400 500 600 700 800 SWITCHING FREQUENCY (kHz) 900 FIGURE 2. BIAS SUPPLY CURRENT vs FREQUENCY Page 5 of 15 1000 HIP6021 Functional Pin Descriptions VCC (Pin 28) Provide a 12V bias supply for the IC to this pin. This pin also provides the gate bias charge for all the MOSFETs controlled by the IC. The voltage at this pin is monitored for Power-On Reset (POR) purposes. GND (Pin 17) Signal ground for the IC. All voltage levels are measured with respect to this pin. PGND (Pin 24) This is the power ground connection. Tie the synchronous PWM converter’s lower MOSFET source to this pin. VAUX (Pin 16) This pin provides boost current for the linear regulators’ output drives in the event bipolar NPN transistors (instead of N-channel MOSFETs) are employed as pass elements. The voltage at this pin is monitored for power-on reset (POR) purposes. SS (Pin 12) Connect a capacitor from this pin to ground. This capacitor, along with an internal 28A current source, sets the soft-start interval of the converter. FAULT / RT (Pin 13) This pin provides oscillator switching frequency adjustment. By placing a resistor (RT) from this pin to GND, the nominal 200kHz switching frequency is increased according to the following equation: 6 5 10 Fs 200KHz + --------------------R T k (RT to GND) Conversely, connecting a resistor from this pin to VCC reduces the switching frequency according to the following equation: 7 4 10 Fs 200KHz – --------------------R T k (RT to 12V) Nominally, the voltage at this pin is 1.26V. In the event of an over-voltage or over-current condition, this pin is internally pulled to VCC. PGOOD (Pin 8) PGOOD is an open collector output used to indicate the status of the output voltages. This pin is pulled low when the synchronous regulator output is not within 10%of the DACOUT reference voltage or when any of the other outputs are below their under-voltage thresholds. The PGOOD output is open for ‘11111’ VID code. SD (Pin 9) This pin shuts down all the outputs. A TTL-compatible, logic level high signal applied at this pin immediately discharges the FN4684 Rev 1.00 March 8, 2005 soft-start capacitor, disabling all the outputs. Dedicated internal circuitry insures the core output voltage does not go negative during this process. When re-enabled, the IC undergoes a new soft-start cycle. Left open, this pin is pulled low by an internal pull-down resistor, enabling operation. FIX (Pin 2) Grounding this pin bypasses the internal resistor dividers that set the output voltage of the 1.5V and 1.8V linear regulators. This way, the output voltage of the two regulators can be adjusted from 1.26V up to the input voltage (+3.3V or +5V) by way of an external resistor divider connected at the corresponding VSEN pin. The new output voltage set by the external resistor divider can be determined using the following formula: R OUT V OUT = 1.265V 1 + ----------------- R GND where ROUT is the resistor connected from VSEN to the output of the regulator, and RGND is the resistor connected from VSEN to ground. Left open, the FIX pin is pulled high, enabling fixed output voltage operation. VID0, VID1, VID2, VID3, VID4 (Pins 7, 6, 5, 4 and 3) VID0-4 are the TTL-compatible input pins to the 5-bit DAC. The logic states of these five pins program the internal voltage reference (DACOUT). The level of DACOUT sets the microprocessor core converter output voltage, as well as the coresponding PGOOD and OVP thresholds. OCSET (Pin 23) Connect a resistor from this pin to the drain of the respective upper MOSFET. This resistor, an internal 200A current source, and the upper MOSFET’s on-resistance set the converter over-current trip point. An over-current trip cycles the soft-start function. The voltage at this pin is monitored for power-on reset (POR) purposes and pulling this pin low with an open drain device will shutdown the IC. PHASE (Pin 26) Connect the PHASE pin to the PWM converter’s upper MOSFET source. This pin represents the gate drive return current path and is used to monitor the voltage drop across the upper MOSFET for over-current protection. UGATE (Pin 27) Connect UGATE pin to the PWM converter’s upper MOSFET gate. This pin provides the gate drive for the upper MOSFET. LGATE (Pin 25) Connect LGATE to the PWM converter’s lower MOSFET gate. This pin provides the gate drive for the lower MOSFET. COMP and FB (Pin 20, and 21) COMP and FB are the available external pins of the PWM converter error amplifier. The FB pin is the inverting input of the Page 6 of 15 HIP6021 error amplifier. Similarly, the COMP pin is the error amplifier output. These pins are used to compensate the voltage-mode control feedback loop of the synchronous PWM converter. VSEN1 (Pin 22) This pin is connected to the PWM converter’s output voltage. The PGOOD and OVP comparator circuits use this signal to report output voltage status and for over- voltage protection. DRIVE2 (Pin 1) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the AGP regulator’s pass transistor. VSEN2 (Pin 10) Connect this pin to the output of the AGP linear regulator. The voltage at this pin is regulated to the level predetermined by the logic-level status of the SELECT pin. This pin is also monitored for under-voltage events. SELECT (Pin 11) This pin determines the output voltage of the AGP bus linear regulator. A low TTL input sets the output voltage to 1.5V, while a high input sets the output voltage to 3.3V. DRIVE3 (Pin 18) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.5V regulator’s pass transistor. VSEN3 (Pin 19) Connect this pin to the output of the 1.5V linear regulator. This pin is monitored for under-voltage events. DRIVE4 (Pin 15) Connect this pin to the gate of an external MOSFET. This pin provides the drive for the 1.8V regulator’s pass transistor. VSEN4 (Pin 14) Connect this pin to the output of the linear 1.8V regulator. This pin is monitored for undervoltage events. Description Operation The HIP6021 monitors and precisely controls 4 output voltage levels (Refer to Block and Simplified Power System Diagrams, and Typical Application Schematic). It is designed for microprocessor computer applications with 3.3V, 5V, and 12V bias input from an ATX power supply. The IC has a synchronous PWM controller and three linear controllers. The PWM controller (PWM) is designed to regulate the microprocessor core voltage (VOUT1). PWM controller drives 2 MOSFETs (Q1 and Q2) in a synchronous-rectified buck converter configuration and regulates the microprocessor core voltage to a level programmed by the 5-bit digital-toanalog converter (DAC). One of the linear controllers is designed to regulate the advanced graphics port (AGP) bus voltage (VOUT2) to a digitally-programmable level of 1.5V or 3.3V. Selection of either output voltage is achieved by FN4684 Rev 1.00 March 8, 2005 applying the proper logic level at the SELECT pin. The remaining two linear controllers supply the 1.5V GTL bus power (VOUT3) and the 1.8V memory power (VOUT4). All linear controllers are designed to employ an external pass transistor. Initialization The HIP6021 automatically initializes upon receipt of input power. Special sequencing of the input supplies is not necessary. The Power-On Reset (POR) function continually monitors the input supply voltages. The POR monitors the bias voltage (+12VIN) at the VCC pin, the 5V input voltage (+5VIN) on the OCSET pin, and the 3.3V input voltage (+3.3VIN) at the VAUX pin. The normal level on OCSET is equal to +5VIN less a fixed voltage drop (see over-current protection). The POR function initiates soft-start operation after all supply voltages exceed their POR thresholds. Soft-Start The POR function initiates the soft-start sequence. Initially, the voltage on the SS pin rapidly increases to approximately 1V (this minimizes the soft-start interval). Then an internal 28A current source charges an external capacitor (CSS) on the SS pin to 4.5V. The PWM error amplifier reference input (+ terminal) and output (COMP pin) are clamped to a level proportional to the SS pin voltage. As the SS pin voltage slews from 1V to 4V, the output clamp allows generation of PHASE pulses of increasing width that charge the output capacitor(s). After the output voltage increases to approximately 70% of the set value, the reference input clamp slows the output voltage rate-of-rise and provides a smooth transition to the final set voltage. Additionally, all linear regulators’ reference inputs are clamped to a voltage proportional to the SS pin voltage. This method provides a rapid and controlled output voltage rise. Figure 3 shows the soft-start sequence for the typical application. At T0 the SS voltage rapidly increases to approximately 1V. At T1, the SS pin and error amplifier output voltage reach the valley of the oscillator’s triangle wave. The oscillator’s triangular wave form is compared to the clamped error amplifier output voltage. As the SS pin voltage increases, the pulse-width on the PHASE pin increases. The interval of increasing pulse-width continues until each output reaches sufficient voltage to transfer control to the input reference clamp. If we consider the 2.5V core output (VOUT1) in Figure 3, this time occurs at T2. During the interval between T2 and T3, the error amplifier reference ramps to the final value and the converter regulates the output a voltage proportional to the SS pin voltage. At T3 the input clamp voltage exceeds the reference voltage and the output voltage is in regulation. The remaining outputs are also programmed to follow the SS pin voltage. The PGOOD signal toggles ‘high’ when all output voltage levels have exceeded their under-voltage levels. See the Soft-Start Interval section under Applications Guidelines for a procedure to determine the soft-start interval. Page 7 of 15 HIP6021 increase without fault at start-up. Cycling the bias input voltage (+12VIN on the VCC pin off then on) resets the counter and the fault latch. PGOOD 0V Over-Voltage Protection SOFT-START (1V/DIV) 0V VOUT2 ( = 3.3V) VOUT1 (DAC = 2.5V) VOUT4 ( = 1.8V) OUTPUT VOLTAGES (0.5V/DIV) VOUT3 ( = 1.5V) During operation, a short on the upper MOSFET of the PWM regulator (Q1) causes VOUT1 to increase. When the output exceeds the over-voltage threshold of 115% of DACOUT, the over-voltage comparator trips to set the fault latch and turns Q2 on. This blows the input fuse and reduces VOUT1. The fault latch raises the FAULT/RT pin to VCC. A separate over-voltage circuit provides protection during the initial application of power. For voltages on the VCC pin below the power-on reset (and above ~4V), the output level is monitored for voltages above 1.3V. Should VSEN1 exceed this level, the lower MOSFET, Q2 is driven on. Over-Current Protection 0V T0 T1 T2 TIME T3 T4 FIGURE 3. SOFT-START INTERVAL Fault Protection All four outputs are monitored and protected against extreme overload. A sustained overload on any output or an overvoltage on VOUT1 output (VSEN1) disables all outputs and drives the FAULT/RT pin to VCC. LUV OVERCURRENT LATCH INHIBIT S Q OC1 R 0.15V SS + + 4V COUNTER - - R FAULT LATCH VCC S Q UP POR R FAULT OV FIGURE 4. FAULT LOGIC - SIMPLIFIED SCHEMATIC Figure 4 shows a simplified schematic of the fault logic. An over-voltage detected on VSEN1 immediately sets the fault latch. A sequence of three over-current fault signals also sets the fault latch. The over-current latch is set dependent upon the states of the over-current (OC), linear under-voltage (LUV) and the soft-start signals. A window comparator monitors the SS pin and indicates when CSS is fully charged to 4V (UP signal). An under-voltage on either linear output (VSEN2, VSEN3, or VSEN4) is ignored until after the soft-start interval (T4 in Figure 3). This allows VOUT2 , VOUT3 , and VOUT4 to FN4684 Rev 1.00 March 8, 2005 All outputs are protected against excessive over-currents. The PWM controller uses the upper MOSFET’s on-resistance, rDS(ON) to monitor the current for protection against shorted output. All linear controllers monitor their respective VSEN pins for under-voltage events to protect against excessive currents. Figure 5 illustrates the over-current protection with an overload on OUT1. The overload is applied at T0 and the current increases through the inductor (LOUT1). At time T1, the OVERCURRENT comparator trips when the voltage across Q1 (iD • rDS(ON)) exceeds the level programmed by ROCSET. This inhibits all outputs, discharges the soft-start capacitor (CSS) with a 10mA current sink, and increments the counter. CSS recharges at T2 and initiates a soft-start cycle with the error amplifiers clamped by soft-start. With OUT1 still overloaded, the inductor current increases to trip the overcurrent comparator. Again, this inhibits all outputs, but the softstart voltage continues increasing to 4V before discharging. The counter increments to 2. The soft-start cycle repeats at T3 and trips the over-current comparator. The SS pin voltage increases to 4V at T4 and the counter increments to 3. This sets the fault latch to disable the converter. The fault is reported on the FAULT/RT pin. The linear controllers operate in the same way as the PWM in response to over-current faults. The differentiating factor for the linear controllers is that they monitor the VSEN pins for under-voltage events. Should excessive currents cause the voltage at the VSEN pins to fall below the linear undervoltage threshold, the LUV signal sets the over-current latch if CSS is fully charged. Blanking the LUV signal during the CSS charge interval allows the linear outputs to build above the under-voltage threshold during normal operation. Cycling the bias input power off then on resets the counter and the fault latch. A resistor (ROCSET) programs the over-current trip level for the PWM converter. As shown in Figure 6, the internal 200A current sink, IOCSET develops a voltage across ROCSET Page 8 of 15 FAULT/RT HIP6021 10V 0V COUNT =1 COUNT =2 COUNT =3 4V SOFT-START INDUCTOR CURRENT The OC trip point varies with MOSFET’s rDS(ON) temperature variations. To avoid over-current tripping in the normal operating load range, determine the ROCSET resistor from the equation above with: FAULT REPORTED 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for IPEAK > IOUT(MAX) + (I)/2, where I is the output inductor ripple current. 2V For an equation for the ripple current see the section under component guidelines titled ‘Output Inductor Selection’. 0V OVERLOAD APPLIED OUT1 Voltage Program 0A T0 T1 T2 T3 T4 TIME FIGURE 5. OVER-CURRENT OPERATION (VSET) that is referenced to VIN . The DRIVE signal enables the over-current comparator (OVER-CURRENT). When the voltage across the upper MOSFET (VDS) exceeds VSET , the over-current comparator trips to set the over-current latch. Both VSET and VDS are referenced to VIN and a small capacitor across ROCSET helps VOCSET track the variations of VIN due to MOSFET switching. The over-current function will trip at a peak inductor current (IPEAK) determined by: The output voltage of the PWM converter is programmed to discrete levels between 1.3VDC and 3.5VDC . This output (OUT1) is designed to supply the core voltage of Intel’s advanced microprocessors. The voltage identification (VID) pins program an internal voltage reference (DACOUT) with a TTL-compatible 5-bit digital-to-analog converter. The level of DACOUT also sets the PGOOD and OVP thresholds. Table 1 specifies the DACOUT voltage for the different combinations of connections on the VID pins. The VID pins can be left open for a logic 1 input, because they are internally pulled up to an internal voltage of about 5V by a 10A current source. Changing the VID inputs during operation is not recommended and could toggle the PGOOD signal and exercise the overvoltage protection. ‘11111’ VID pin combination disables the IC and opens the PGOOD pin. I OCSET R OCSET I PEAK = ---------------------------------------------------r DS ON i TABLE 1. OUT1 VOLTAGE PROGRAM PIN NAME OVER-CURRENT TRIP: V DS > V SET D VIN = +5V r DS ON > I OCSET R OCSET ROCSET OCSET IOCSET 200A DRIVE + UGATE + VDS PHASE - PWM iD VCC OVERCURRENT OC VSET + GATE CONTROL V PHASE = V IN – V DS V OCSET = V IN – V SET FIGURE 6. OVER-CURRENT DETECTION FN4684 Rev 1.00 March 8, 2005 VID4 VID3 VID2 VID1 VID0 NOMINAL DACOUT VOLTAGE 0 1 1 1 1 1.30 0 1 1 1 0 1.35 0 1 1 0 1 1.40 0 1 1 0 0 1.45 0 1 0 1 1 1.50 0 1 0 1 0 1.55 0 1 0 0 1 1.60 0 1 0 0 0 1.65 0 0 1 1 1 1.70 0 0 1 1 0 1.75 0 0 1 0 1 1.80 0 0 1 0 0 1.85 0 0 0 1 1 1.90 0 0 0 1 0 1.95 0 0 0 0 1 2.00 0 0 0 0 0 2.05 1 1 1 1 1 0 Page 9 of 15 HIP6021 TABLE 1. OUT1 VOLTAGE PROGRAM (Continued) PIN NAME VID4 VID3 VID2 VID1 VID0 NOMINAL DACOUT VOLTAGE 1 1 1 1 0 2.1 1 1 1 0 1 2.2 1 1 1 0 0 2.3 1 1 0 1 1 2.4 1 1 0 1 0 2.5 1 1 0 0 1 2.6 1 1 0 0 0 2.7 1 0 1 1 1 2.8 1 0 1 1 0 2.9 1 0 1 0 1 3.0 1 0 1 0 0 3.1 1 0 0 1 1 3.2 1 0 0 1 0 3.3 1 0 0 0 1 3.4 1 0 0 0 0 3.5 NOTE: 0 = connected to GND, 1 = open or connected to 5V through pull-up resistors OUT2 Voltage Selection The AGP regulator output voltage is internally set to one of two discrete levels, based on the status of the SELECT pin. SELECT pin is internally pulled ‘high’, such that left open, the AGP output voltage is by default set to 3.3V. The other discrete setting available is 1.5V, which can be obtained by grounding the SELECT pin using a jumper or another suitable method capable of sinking a few tens of microamperes. The status of the SELECT pin cannot be changed during operation of the IC without immediately causing a fault condition. OUT3 and OUT4 Voltage Adjustability The GTL bus voltage (1.5V, OUT3) and the chip set and/or cache memory voltage (1.8V, OUT4) are internally set for simple, low-cost implementation in typical Intel motherboard architectures. However, if different voltage settings are desired for these two outputs, the FIX pin provides the necessary adaptability. Left open (NC), this pin sets the fixed output voltages described above. Grounding this pin allows both output voltages to be set by means of external resistor dividers as shown in Figure 7. VAUX +3.3VIN Q4 DRIVE3 VOUT3 VSEN3 RS3 RP3 COUT3 HIP6021 DRIVE4 Q5 VOUT4 VSEN4 RS4 COUT4 RP4 FIX R S V OUT = V BG 1 + -------- R P FIGURE 7. ADJUSTING THE OUTPUT VOLTAGE OF OUTPUTS 3 AND 4 Application Guidelines Soft-Start Interval Initially, the soft-start function clamps the error amplifier’s output of the PWM converter. This generates PHASE pulses of increasing width that charge the output capacitor(s). After the output voltage increases to approximately 70% of the set value, the reference input of the error amplifier is clamped to a voltage proportional to the SS pin voltage. The resulting output voltages start-up as shown in Figure 3. The soft-start function controls the output voltage rate of rise to limit the current surge at start-up. The soft-start interval and the surge current are programmed by the soft-start capacitor, CSS. Programming a faster soft-start interval increases the peak surge current. The peak surge current occurs during the initial output voltage rise to 70% of the set value. Shutdown The HIP6021 features a dedicated shutdown pin (SD). A TTLcompatible, logic high signal applied to this pin shuts down (disables) all four outputs and discharges the soft-start capacitor. Following a shutdown, a logic low signal re-enables the outputs through initiation of a new soft-start cycle. Left open this pin will asses a logic low state, due to its internal pulldown resistor, thus enabling normal operation of all outputs. The PWM output does not switch until the soft-start voltage (VSS) exceeds the oscillator’s valley voltage. The references on each linear’s error amplifier are clamped to the soft-start voltage. Holding the SS pin low (with an open drain or collector signal) turns off all four regulators. The ‘11111’ VID code also shuts down the IC. FN4684 Rev 1.00 March 8, 2005 Page 10 of 15 HIP6021 Layout Considerations MOSFETs switch very fast and efficiently. The speed with which the current transitions from one device to another causes voltage spikes across the interconnecting impedances and parasitic circuit elements. The voltage spikes can degrade efficiency, radiate noise into the circuit, and lead to device over-voltage stress. Careful component layout and printed circuit design minimizes the voltage spikes in the converter. Consider, as an example, the turn-off transition of the upper PWM MOSFET. Prior to turn-off, the upper MOSFET was carrying the full load current. During the turn-off, current stops flowing in the upper MOSFET and is picked up by the lower MOSFET or Schottky diode. Any inductance in the switched current path generates a large voltage spike during the switching interval. Careful component selection, tight layout of the critical components, and short, wide circuit traces minimize the magnitude of voltage spikes. See the Application Note ANTBD for evaluation board drawings of the component placement and printed circuit board. There are two sets of critical components in a DC-DC converter using a HIP6020 controller. The switching power components are the most critical because they switch large amounts of energy, and as such, they tend to generate equally large amounts of noise. The critical small signal components are those connected to sensitive nodes or those supplying critical bypass current. The power components and the controller IC should be placed first. Locate the input capacitors, especially the high-frequency ceramic decoupling capacitors, close to the power switches. Locate the output inductor and output capacitors between the MOSFETs and the load. Locate the PWM controller close to the MOSFETs. The critical small signal components include the bypass capacitor for VCC and the soft-start capacitor, CSS . Locate these components close to their connecting pins on the control IC. Minimize any leakage current paths from SS node, since the internal current source is only 28A. A multi-layer printed circuit board is recommended. Figure 8shows the connections of the critical components in the converter. Note that the capacitors CIN and COUT each represent numerous physical capacitors. Dedicate one solid layer for a ground plane and make all critical component ground connections with vias to this layer. Dedicate another solid layer as a power plane and break this plane into smaller islands of common voltage levels. The power plane should support the input power and output power nodes. Use copper filled polygons on the top and bottom circuit layers for the PHASE nodes, but do not unnecessarily oversize these particular islands. Since the PHASE nodes are subjected to very high dV/dt voltages, the stray capacitor formed between these islands and the surrounding circuitry will tend to couple switching noise. Use the remaining printed circuit layers for small signal wiring. The wiring traces from the control IC to FN4684 Rev 1.00 March 8, 2005 the MOSFET gate and source should be sized to carry 2A peak currents. PWM Controller Feedback Compensation The PWM controller uses voltage-mode control for output regulation. This section highlights the design consideration for a PWM voltage-mode controller. Apply the methods and considerations only to the PWM controller. Figure 9 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The reference voltage level is the DAC output voltage (DACOUT). The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse-width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain, given by VIN/VOSC , and shaped by the output filter, with a double pole break frequency at FLC and a zero at FESR . Modulator Break Frequency Equations 1 F LC = ---------------------------------------2 L O C O 1 F ESR = ----------------------------------------2 ESR C O The compensation network consists of the error amplifier (internal to the HIP6021) and the impedance networks ZIN and ZFB . The goal of the compensation network is to provide a closed loop transfer function with high 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 8. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC) 3. Place 2ND Zero at Filter’s Double Pole 4. Place 1ST Pole at the ESR Zero 5. Place 2ND Pole at Half the Switching Frequency 6. Check Gain against Error Amplifier’s Open-Loop Gain 7. Estimate Phase Margin - Repeat if Necessary Page 11 of 15 HIP6021 Compensation Break Frequency Equations LIN CIN +12V CVCC COCSET1 VCC GND OCSET1 Q3 ROCSET1 DRIVE2 Q1 LOUT1 UGATE1 VOUT2 SS CSS LOAD VOUT3 COUT1 LGATE1 CR1 Q2 HIP6021 VOUT4 COUT3 DRIVE3 DRIVE4 COUT4 PGND Q4 Q5 +3.3VIN KEY ISLAND ON POWER PLANE LAYER ISLAND ON CIRCUIT PLANE LAYER VIA CONNECTION TO GROUND PLANE FIGURE 8. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS 1 F P1 = ------------------------------------------------------C1 C2 2 R 2 ---------------------- C1 + C2 1 F Z2 = ------------------------------------------------------2 R1 + R3 C3 1 F P2 = ----------------------------------2 R 3 C3 Figure 10 shows an asymptotic plot of the DC-DC converter’s gain vs. frequency. The actual Modulator Gain has a high gain peak dependent on the quality factor (Q) of the output filter, which is not shown in Figure 9. Using the above guidelines should yield a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the log-log graph of Figure 10 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. FZ1 VIN OSC 1 F Z1 = ----------------------------------2 R 2 C1 DRIVER LO DRIVER + VOSC PHASE VOUT CO ESR (PARASITIC) ZFB VE/A - ERROR AMP DETAILED COMPENSATION COMPONENTS ZFB VOUT ZIN C3 R2 R3 R1 COMP - FB + HIP6021 DACOUT FIGURE 9. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN FN4684 Rev 1.00 March 8, 2005 V IN 20 log ------------ V PP COMPENSATION GAIN 20 0 -60 C1 OPEN LOOP ERROR AMP GAIN 40 -40 REFERENCE C2 FP2 60 -20 ZIN + FP1 80 PWM COMP - FZ2 100 GAIN (dB) LOAD PHASE1 COUT2 VOUT1 LOAD +3.3VIN LOAD +5VIN R2 20 log -------- R1 MODULATOR GAIN 10 100 FLC 1K CLOSED LOOP GAIN FESR 10K 100K 1M 10M FREQUENCY (Hz) FIGURE 10. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN Component Selection Guidelines Output Capacitor Selection The output capacitors for each output have unique requirements. In general, the output capacitors should be selected to meet the dynamic regulation requirements. Additionally, the PWM converters require an output capacitor to filter the current ripple. The load transient for the microprocessor core requires high quality capacitors to supply the high slew rate (di/dt) current demands. Page 12 of 15 HIP6021 PWM Output Capacitors Modern microprocessors produce transient load rates above 1A/ns. High frequency capacitors initially supply the transient current and slow the load rate-of-change seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (effective series resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor’s ESR determines the output ripple voltage and the initial voltage drop following a high slew-rate transient’s edge. An aluminum electrolytic capacitor’s ESR value is related to the case size with lower ESR available in larger case sizes. However, the equivalent series inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor’s impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor. Linear Output Capacitors The output capacitors for the linear regulators provide dynamic load current. The linear controllers use dominant pole compensation integrated into the error amplifier and are insensitive to output capacitor selection. Output capacitors should be selected for transient load regulation. PWM Output Inductor Selection required to slew the inductor current from an initial current value to the post-transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor(s). Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load: L O I TRAN t RISE = -------------------------------V IN – V OUT L O I TRAN t FALL = ------------------------------V OUT where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. Be sure to check both of these equations at the minimum and maximum output levels for the worst case response time. Input Capacitor Selection The important parameters for the bulk input capacitors are the voltage rating and the RMS current rating. For reliable operation, select bulk input capacitors with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 of the summation of the DC load current. Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use ceramic capacitance for the high frequency decoupling and bulk capacitors to supply the RMS current. Small ceramic capacitors can be placed very close to the upper MOSFET to suppress the voltage induced in the parasitic circuit impedances. The PWM converter requires an output inductor. The output inductor is selected to meet the output voltage ripple requirements and sets the converter’s response time to a load transient. The inductor value determines the converter’s ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations: For a through-hole design, several electrolytic capacitors (Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX or equivalent) may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX, and the 593D series from Sprague are both surge current tested. V IN – V OUT V OUT I = -------------------------------- ---------------FS L V IN MOSFET Selection/Considerations V OUT = I ESR Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values increase the converter’s response time to a load transient. One of the parameters limiting the converter’s response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the HIP6021 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time interval FN4684 Rev 1.00 March 8, 2005 The HIP6021 requires 5 external transistors. Two N-channel MOSFETs are used in the synchronous-rectified buck topology of PWM1 converter. It is recommended that the AGP linear regulator pass element be a N-channel MOSFET as well. The GTL and memory linear controllers can also each drive a MOSFET or a NPN bipolar as a pass transistor. All these transistors should be selected based upon rDS(ON) , current gain, saturation voltages, gate supply requirements, and thermal management considerations. Page 13 of 15 HIP6021 PWM MOSFET Selection and Considerations In high-current PWM applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. These losses are distributed between the upper and lower MOSFETs according to duty factor (see the equations below). The conduction losses are the main component of power dissipation for the lower MOSFETs. Only the upper MOSFET has significant switching losses, since the lower device turns on and off into near zero voltage. The equations below assume linear voltage-current transitions and do not model power loss due to the reverse-recovery of the lower MOSFET’s body diode. The gate-charge losses are dissipated by the HIP6021 and don't heat the MOSFETs. However, large gate-charge increases the switching time, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow. 2 I O r DS ON V OUT I O V IN t SW F S P UPPER = ------------------------------------------------------------ + ---------------------------------------------------V IN 2 2 I O r DS ON V IN – V OUT P LOWER = --------------------------------------------------------------------------------V IN The rDS(ON) is different for the two equations above even if the same device is used for both. This is because the gate drive applied to the upper MOSFET is different than the lower MOSFET. Figure 11 shows the gate drive where the upper MOSFET’s gate-to-source voltage is approximately VCC less the input supply. For +5V main power and +12VDC for the bias, the gate-to-source voltage of Q1 is 7V. The lower gate drive voltage is +12VDC. A logic-level MOSFET is a good choice for Q1 and a logic-level MOSFET can be used for Q2 if its absolute gate-to-source voltage rating exceeds the maximum voltage applied to VCC. +5V OR LESS +12V VCC HIP6021 UGATE Q1 PHASE - + LGATE NOTE: VGS VCC -5V Q2 PGND CR1 NOTE: VGS VCC GND FIGURE 11. UPPER GATE DRIVE - DIRECT VCC DRIVE OPTION Rectifier CR1 is a clamp that catches the negative inductor swing during the dead time between the turn off of the lower MOSFET and the turn on of the upper MOSFET. The diode must be a Schottky type to prevent the lossy parasitic MOSFET body diode from conducting. It is acceptable to omit the diode and let the body diode of the lower MOSFET clamp the negative inductor swing, but efficiency could drop one or two percent as a result. The diode's rated reverse breakdown voltage must be greater than the maximum input voltage. Linear Controller Transistor Selection The main criteria for selection of transistors for the linear regulators is package selection for efficient removal of heat. The power dissipated in a linear regulator is: P LINEAR = I O V IN – V OUT Select a package and heatsink that maintains the junction temperature below the rating with a the maximum expected ambient temperature. When selecting bipolar NPN transistors for use with the linear controllers, insure the current gain at the given operating VCE is sufficiently large to provide the desired output load current when the base is fed with the minimum driver output current. © Copyright Intersil Americas LLC 1999-2005. All Rights Reserved. All trademarks and registered trademarks are the property of their respective owners. For additional products, see www.intersil.com/en/products.html Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted in the quality certifications found at www.intersil.com/en/support/qualandreliability.html Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com FN4684 Rev 1.00 March 8, 2005 Page 14 of 15 HIP6021 HIP6021 DC-DC Converter Application Circuit (VOUT4) from +3.3V, +5VDC, and +12VDC. For detailed information on the circuit, including a Bill-of-Materials and circuit board description, see Application Note AN9836. Also see Intersil’s web page (http://www.intersil.com). Figure 12 shows an application circuit of a power supply for a microprocessor computer system. The power supply provides the microprocessor core voltage (VOUT1), the AGP bus voltage (VOUT2), the GTL bus voltage (VOUT3), and the memory voltage +12VIN L1 +5VIN 1H GND C1-6 + 6x1000F C7 1F C8 1000pF C9 1F VCC FAULT/RT +3.3VIN VAUX DRIVE2 VOUT2 28 R1 23 13 8 16 C10,11 2x1000F VSEN2 Q3 HUF76121D3S 1.0K 10 POWERGOOD PGOOD Q1,2 2xHUF76143S3S 27 UGATE 1 26 (3.3V or 1.5V) + OCSET PHASE 4.2H 25 C12-19 + 8x1000F LGATE 24 PGND SELECT TYPEDET 11 22 U1 HIP6021 Q4 HUF76107D3S DRIVE3 VOUT3 (1.5V) VSEN3 + 18 21 20 FB COMP VOUT4 VSEN4 (1.8V) + C25,26 2x1000F SD FIX R3 1.62k C21 10pF C20 0.22F 19 7 DRIVE4 R2 10.2K VSEN1 C23,24 2x1000F Q5 HUF76107D3S VOUT1 (1.3V-3.5V) L2 R4 150K R5 499K 6 VID1 VID2 5 4 VID3 15 14 3 VID4 12 SS 9 2 VID0 C22 2.7nF 17 C27 0.1F GND FIGURE 12. POWER SUPPLY APPLICATION CIRCUIT FOR A MICROPROCESSOR COMPUTER SYSTEM FN4684 Rev 1.00 March 8, 2005 Page 15 of 15