NXP ISP1302UK Universal serial bus on-the-go transceiver with carkit support Datasheet

34 .80 7IRELESS
IMPORTANT NOTICE
Dear customer,
As from August 2nd 2008, the wireless operations of NXP have moved to a new company,
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
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rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
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under Contacts.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
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34 .80 7IRELESS
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ISP1302
Universal Serial Bus On-The-Go transceiver with carkit
support
Rev. 01 — 24 May 2007
Product data sheet
1. General description
The ISP1302 is a Universal Serial Bus (USB) On-The-Go (OTG) transceiver device that
supports USB Carkit Specification (CEA-936-A), November 2005. It is fully compliant with
Universal Serial Bus Specification Rev. 2.0 and On-The-Go Supplement to the USB
Specification Rev. 1.2. The ISP1302 can transmit and receive serial data at full-speed
(12 Mbit/s) and low-speed (1.5 Mbit/s) data rates.
The ISP1302 is available in HVQFN24 and WLCSP25 packages.
2. Features
n Fully complies with:
u Universal Serial Bus Specification Rev. 2.0
u On-The-Go Supplement to the USB Specification Rev. 1.2
u On-The-Go Transceiver Specification (CEA-2011)
u USB Carkit Specification (CEA-936-A), November 2005
n Can transmit and receive serial data at full-speed (12 Mbit/s) and low-speed
(1.5 Mbit/s) data rates
n Supports OTG Host Negotiation Protocol (HNP) and Session Request Protocol (SRP)
n Supports I2C-bus (up to 400 kHz) serial interface to access control and status registers
n Supports Universal Asynchronous Receiver-Transmitter (UART) pass-through on the
DP and DM lines
n Supports service mode with 2.8 V UART signaling on the DP and DM lines
n Built-in analog switches to support analog audio signals multiplexed on the DP and DM
lines
n Built-in DC biasing for audio signals on the DP and DM lines
n Supports both 4-wire and 5-wire signaling protocol for carkit application
n Supports data-during-audio mode for smart carkit application
n Built-in charge pump regulator outputs 5 V at current up to 50 mA
n 3.0 V to 4.5 V power supply input range (VCC)
n Supports wide range digital interfacing I/O voltage (VCC(I/O)) 1.4 V to 3.6 V
n Full industrial grade operation from −40 °C to +85 °C
n Available in small HVQFN24 and WLCSP25 halogen-free and lead-free packages
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
3. Applications
n Mobile phones
n Digital camera
n Personal digital assistant
4. Ordering information
Table 1.
Ordering information
Type number
Package
Name
Description
Version
ISP1302HN
HVQFN24 plastic thermal enhanced very thin quad flat package; no leads; 24 terminals;
body 4 × 4 × 0.85 mm
SOT616-3
ISP1302UK
WLCSP25 wafer level chip-size package; 25 bumps; 2.5 × 2.5 × 0.6 mm
ISP1302UK
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
2 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
5. Block diagram
VCC(I/O)
24
ADR/PSW
VREG
7
1
SCL
3
RESET_N
4
INT_N
5
SERVICE_N
8
OE_N/INT_N
9
RCV
12
SE0/VM
13
C_B
21
22
23
VBUS
CHARGE
PUMP
VBUS
COMPARATOR
SERIAL
CONTROLLER
19
18
ID DETECTOR
CARKIT DP
INTERRUPT
DETECTOR
LEVEL SHIFTER
2
20
3.3 V DC-DC
REGULATOR
CLOCK AND
TIMER
SDA
C_A
VCC
6
ID
CR_INT
16
DP
15
14
DIF RX
SE
DETECTOR
DM
PULL-UP AND
PULL-DOWN
RESISTORS
SE D+
10
AUDIO
BYPASS
SE D−
DGND
VBUS
ISP1302HN
AUDIO
DATA
CONTROL
DIF TX
DAT/VP
CPGND
11
SPKR_L
SPKR_R/MIC
die pad
17
004aaa541
AGND
The figure shows the HVQFN pinout. For the WLCSP ballout, see Table 2.
Fig 1. Block diagram
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
6. Pinning information
19 VBUS
20 VCC
21 C_A
22 C_B
terminal 1
index area
23 CPGND
24 VCC(I/O)
6.1 Pinning
ADR/PSW
1
18 ID
SDA
2
17 AGND
SCL
3
RESET_N
4
INT_N
5
14 DAT/VP
CR_INT
6
13 SE0/VM
16 DP
15 DM
RCV 12
9
OE_N/INT_N
SPKR_R/MIC 11
8
SPKR_L 10
7
VREG
SERVICE_N
ISP1302HN
004aaa726
Transparent top view
3
SDA
2
ADR/PSW
1
terminal 1
index area
OE_N/INT_N
9
11 SPKR_R/MIC
SERVICE_N
10 SPKR_L
VREG
8
12 RCV
14 DAT/VP
15 DM
ISP1302HN
16 DP
terminal 1
17 AGND
18 ID
VBUS 19
SCL
VCC 20
4
C_A 21
RESET_N
13 SE0/VM
DGND
(exposed die pad)
C_B 22
5
CPGND 23
6
INT_N
VCC(I/O) 24
CR_INT
7
Fig 2. Pin configuration HVQFN24 (top view)
004aaa727
Bottom view
Fig 3. Pin configuration HVQFN24 (bottom view)
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
4 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
ball A1
index area
ISP1302UK
1
2
3
4
5
A
B
C
D
E
004aaa716
Fig 4. Pin configuration WLCSP25 (top view)
ISP1302UK
ball A1
index area
004aaa706
Fig 5. Pin configuration WLCSP25 (bottom view)
6.2 Pin description
Table 2.
Pin description
Symbol[1]
Pin
Ball
Type[2]
HVQFN24 WLCSP25
Reset
value
Description
ADR/PSW
1
high-Z
ADR input — Sets the least-significant I2C-bus address bit of
the ISP1302; latched on the rising edge of the RESET_N pin
C1
I/O
PSW output — Enables or disables the external charge pump
after reset
An internal series resistor is implemented for this pin. If the
PSW (output) function is not used, then this pin can directly be
connected to DGND or VREG.
This pin will output 3.3 V when driven HIGH.
For details, see Section 7.13.
bidirectional; push-pull input; 3-state output
SDA
2
D2
I/OD
high-Z
serial I2C-bus data input and output
bidirectional; push-pull input; open-drain output
SCL
3
D3
I/OD
high-Z
serial I2C-bus clock input and output
bidirectional; push-pull input; open-drain output
RESET_N
4
C2
I
-
INT_N
5
B1
OD
high-Z
asynchronous reset input, active LOW
interrupt output; active LOW
open-drain output
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
5 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 2.
Pin description …continued
Symbol[1]
Pin
Ball
Type[2]
HVQFN24 WLCSP25
Reset
value
Description
CR_INT
6
C4
AI
-
directly connect to the DP pin of the USB connector; if the
carkit feature is not used, this pin can be connected to ground
VREG
7
A2
P
-
output of the voltage regulator; place a 0.1 µF capacitor
between this pin and ground
SERVICE_N
8
A1
I
-
input; sets default operation mode of the ISP1302:
•
If a LOW is latched on reset (including power-on reset),
default mode is UART with 2.8 V signaling.
•
If a HIGH is latched on reset (including power-on reset),
default mode is USB with 3.3 V signaling.
Operation mode can be changed after reset by changing the
value of the Mode register bits.
OE_N/INT_N
9
B3
I/O
high-Z
this pin can be programmed as:
OE_N input — Enables driving DP and DM when in USB
mode
INT_N output — Indicates interrupt when bit OE_INT_EN = 1
and SUSPEND_REG = 1
bidirectional; push-pull input; 3-state output
SPKR_L
10
A3
AI
-
analog audio input signal for the left speaker channel; connect
to ground if not in use
SPKR_R/MIC
11
A4
AI/O
-
analog audio input signal for the right speaker channel or audio
output signal for the microphone channel; connect to ground if
not in use
RCV
12
A5
O
0
differential receiver output; reflects the differential value of DP
and DM
push-pull output
SE0/VM
13
B4
I/O
high-Z
SE0 input and output — SE0 functions in DAT_SE0 USB
mode
VM input and output — VM functions in VP_VM USB mode
TxD input — UART mode
bidirectional; push-pull input; 3-state output
DAT/VP
14
B5
I/O
high-Z
DAT input and output — DAT functions in DAT_SE0 USB
mode
VP input and output — VP functions in VP_VM USB mode
RxD output — UART mode
bidirectional; push-pull input; 3-state output
DM
15
D5
AI/O
high-Z
this pin can be programmed as:
•
•
•
DP
16
D4
AI/O
high-Z
17
C3
P
-
transparent UART TxD or
transparent audio SPKR_L
this pin can be programmed as:
•
•
•
AGND
USB D− (data minus pin)
USB D+ (data plus pin)
transparent UART RxD or
transparent audio SPKR_R/MIC
analog ground
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
6 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 2.
Pin description …continued
Symbol[1]
Pin
Ball
Type[2]
HVQFN24 WLCSP25
Reset
value
Description
ID
18
C5
AI/O
-
identification detector input and output; connected to the ID pin
of the USB mini receptacle; internal 100 kΩ pull-up resistor
VBUS
19
E5
AI/O
high-Z
VBUS line input and output of the USB interface; charge pump
output; place an external decoupling capacitor of 0.1 µF close
to this pin
VCC
20
E4
P
-
supply voltage (3.0 V to 4.5 V)
C_A
21
E3
AI/O
-
charge pump flying capacitor pin 2; connect a 220 nF capacitor
between C_B and C_A for 50 mA output current
C_B
22
E2
AI/O
-
charge pump flying capacitor pin 1; connect a 220 nF capacitor
between C_B and C_A for 50 mA output current
CPGND
23
E1
P
-
ground for the charge pump
VCC(I/O)
24
D1
P
-
supply voltage for the I/O interface logic signals (1.4 V to 3.6 V)
DGND
exposed
die pad
B2
P
-
digital ground
[1]
Symbol names ending with underscore N (for example, NAME_N) indicate active LOW signals.
[2]
AI = analog input; AI/O = analog input/output; I = input; O = output; I/O = digital input/output; I/OD = input/open-drain output; OD =
open-drain output; P = power or ground.
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
7 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
7. Functional description
7.1 Serial controller
The serial controller includes the following functions:
•
•
•
•
•
Serial controller interface
Device identification registers
Control registers
Interrupt registers
Interrupt generator
The serial controller acts as an I2C-bus slave, and uses the SCL and SDA pins to
communicate with the OTG Controller.
For details on the serial controller, see Section 9.
7.2 VBUS charge pump
The charge pump supplies current to the VBUS line. It can operate in any of the following
modes:
• Output 5 V at current above 50 mA
• Pull-up VBUS to 3.3 V through a resistor (RUP(VBUS)) to initiate VBUS pulsing SRP
• Pull-down VBUS to ground through a resistor (RDN(VBUS)) to discharge VBUS
7.3 VBUS comparators
VBUS comparators provide indications regarding the voltage level on VBUS.
7.3.1 VBUS valid comparator
This comparator is used by an A-device to determine whether the voltage on VBUS is at a
valid level for operation. The minimum threshold for the VBUS valid comparator is 4.4 V.
Any voltage on VBUS below this threshold is considered a fault. A hardware debounce
timer (td(VA_VBUS_VLD)) is implemented for the VBUS valid comparator. This timer is enabled
when the internal charge pump is turned on (bit VBUS_DRV = 1) and is disabled when the
internal charge pump is turned off (bit VBUS_DRV = 0). During power-up, it is expected
that the comparator output will be ignored.
7.3.2 Session valid comparator
The session valid comparator is used to determines when VBUS is high enough for a
session to start. Both the A-device and the B-device use this comparator to detect when a
session is started. These devices also use this comparator to indicate when a session is
completed. The session valid threshold is between 0.8 V to 2.0 V for A-device, and
between 0.8 V to 4.0 V for B-device.
7.3.3 Session end comparator
The session end comparator determines when VBUS is below the B-device session end
threshold of 0.2 V to 0.8 V.
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
7.4 ID detector
In normal power mode (when both VCC and VCC(I/O) are present), the ID detector senses
the condition of the ID line and can differentiate between the following conditions:
• The ID pin is floating (bit ID_FLOAT = 1).
• The ID pin is shorted to ground (bit ID_GND = 1).
• The ID pin is connected to ground through resistor RDN(ID) = 102 kΩ (bit
ID_102K = 1).
• The ID pin is connected to ground through resistor RDN(ID) = 200 kΩ (bit
ID_200K = 1).
• The ID pin is connected to ground through resistor RDN(ID) = 440 kΩ (bit
ID_440K = 1).
In power-down mode, only ID_FLOAT detector is active and can wake-up the chip. The
remaining detectors are turned off.
Table 3 shows the type of device connected, depending on the status of the ID and VBUS
pins.
Table 3.
ID pin status for various applications
SESS_VLD
ID_FLOAT
ID_GND
ID_102K
ID_200K
ID_440K
Device connected
0
1
0
0
X
X
nothing connected
0
0
1
0
0
0
OTG A-device
0
0
0
1
0
0
phone accessory
1
0
0
0
1
0
charger type 1
1
0
0
0
0
1
charger type 2
1
1
0
0
0
0
carkit or PC
The recommended procedure to detect the ID status using software is:
1. When nothing is connected, ID is floating and ID_FLOAT = 1. The chip can be set in
power-down mode.
2. Enable the ID_FLOAT (rising edge and falling edge) and SESS_VLD (rising edge)
interrupts.
3. If a plug that causes a change in ID_FLOAT or SESS_VLD is inserted, an interrupt
occurs. Interrupt Latch register bit ID_FLOAT or SESS_VLD is set.
4. The software waits for sometime, for example: 100 ms, to allow mechanical
debounce.
5. The software reads the Interrupt Source register and the OTG Status register, and
checks bits SESS_VLD, ID_GND, ID_102K, ID_200K and ID_440K.
6. The device type is determined according to Table 3.
The ID detector has a switch that can be used to ground pin ID. This switch is controlled
by bit ID_PULLDN of the OTG Control register, and bits PH_ID_INT and PH_ID_ACK of
the Audio Control register. See Table 4.
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 4.
ID pull-down control
ID_PULLDN PH_ID_ACK PH_ID_INT Switch between ID and ground
0
0
0
off
0
0
1
on for time tPH_ID_INT, then off and bit PH_ID_INT
autoclears to 0
0
1
0
wait for time tPH_ID_WT, turn on the switch for tPH_ID_INT,
then off and bit PH_ID_ACK autoclears to 0
0
1
1
not defined
1
X
X
on
7.5 Pull-up and pull-down resistors
Figure 6 shows the switchable pull-up and pull-down resistors that are internally
connected to the DP and DM lines. The DP pull-up resistor (SW1) is controlled by
bit DP_PULLUP of the OTG Control register.
The pull-up resistor is context variable as described in document ECN_27%_Resistor.
The pull-up resistor value depends on the USB bus condition:
• When the bus is idle, the resistor is 900 Ω to 1575 Ω (SW2 = on).
• When the bus is transmitting or receiving, the resistor is 1425 Ω to 3090 Ω
(SW2 = off).
DP also implements a weak pull-up resistor (RweakUP(DP)) that is controlled using
bit DP_WKPU_EN of the Misc Control register.
The DP pull-down resistor (RDN(DP)) is connected to the DP line, if bit DP_PULLDOWN in
the OTG Control register is set.
The DM pull-down resistor (RDN(DM)) is connected to the DM line, if bit DM_PULLDOWN in
the OTG Control register is set.
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
VREG
0.525 kΩ to
1.515 kΩ
SW2
0.525 kΩ to
1.515 kΩ
RweakUP(DP)
150 kΩ ± 30 %
SW3
SW1
SW2
0.9 kΩ to
1.575 kΩ
SW1
0.9 kΩ to
1.575 kΩ
DP
DM
DM_PULLDOWN
DP_PULLDOWN
15 kΩ
(14.3 kΩ to
24.8 kΩ)
RDN(DP)
RDN(DM)
15 kΩ
(14.3 kΩ to
24.8 kΩ)
004aaa658
AGND
AGND
Fig 6. DP and DM pull-up and pull-down resistors
7.6 3.3 V DC-DC regulator
The built-in DC-DC regulator conditions the input power supply (VCC) for use in the core of
the ISP1302.
When VCC is greater than 3.6 V, the regulator will output 3.3 V ± 10 %.
When VCC is less than 3.6 V and bit REG_BYPASS_DIS = 0, the regulator will be
automatically bypassed so that pin VREG will be shorted to pin VCC.
When VCC is less than 3.6 V and bit REG_BYPASS_DIS = 1, the regulator will output a
voltage between VCC and VCC − 0.2 V.
The output of the regulator can be monitored on pin VREG. A capacitor (0.1 µF) must be
connected between pin VREG and ground.
7.7 Carkit DP interrupt detector
The carkit DP interrupt detector is a comparator that detects the carkit interrupt signal on
the CR_INT pin in analog audio mode. Bit DP_INT will be set if the voltage level on the
CR_INT pin is below the carkit interrupt threshold Vth(DP)L (0.4 V to 0.6 V).
The carkit interrupt detector is enabled in audio mode only (bit AUDIO_EN = 1).
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
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ISP1302
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USB OTG transceiver with carkit support
7.8 Audio bypass
The audio bypass block includes audio switches and DC bias circuits, see Figure 7.
Audio switches provide a low impedance path for analog audio signals from the phone
processor to be routed to the DP and DM lines. The impedance of the switches will be
between 50 Ω and 150 Ω. Figure 7 shows audio switches and DC biasing circuits.
VREG
SPKR_R_
BIAS_EN
RB2
S1
DP
SPKR_R/MIC
RB1
SPKR_MIC_EN
AGND
SW_MIC_
SPKR_L
VREG
SPKR_L_
BIAS_EN
RB2
S3
DM
SPKR_L
RB1
SPKR_L_EN
AGND
004aaa628
Fig 7. Audio bypass
7.9 Audio data control
Figure 8 shows a diagram that includes the audio data controller. Each block within the
audio data controller is described in the following subsections.
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
60 MHz
CLOCK
TXD
SE0/VM
DM
TXD PULSE
GENERATOR
SPRK_L_EN
AUDIO
TIMER
STEREO
INTERRUPT
DETECTOR
RXD PULSE
CONVERTER
DAT/VP
CARKIT
INTERRUPT
DETECTOR
RXD
CR_INT
DP
004aaa629
Fig 8. Audio data control
7.9.1 Audio timer
The audio timer has two main functions. The first function is to generate the timing for the
positive and negative interrupt pulses. The second function is to generate a time base that
can be used to detect a carkit interrupt while in stereo mode, and reset the RxD NRZ
signal during data-during-audio.
7.9.2 TxD pulse generator
The TxD pulse generator is enabled when the OTG carkit transceiver is outputting
data-during-audio.
When a rising or falling edge is detected on SE0/VM, the TxD pulse generator uses the
AUD_TMR_OUT signal to perform the following sequence:
1. 3-state the left speaker buffer.
2. Enable the TxD buffer.
3. Output a HIGH level for the duration of the positive pulse width.
4. Output a LOW level for the duration of the negative pulse width.
5. Disable the TxD buffer.
6. Enable the left speaker buffer.
The delay between a data edge on SE0/VM and a pulse pair being output on DM will jitter
by as much as one audio timer period because the audio timer is free running. This is
acceptable because the audio timer period is between 200 ns to 500 ns, and the UART
data rate is always less than or equal to 115 kbit/s.
ISP1302_1
Product data sheet
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ISP1302
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USB OTG transceiver with carkit support
7.9.3 Stereo interrupt detector
The stereo interrupt detector generates an interrupt when the CR_INT pin has been
continuously below the carkit interrupt detector threshold for a time of tPH_STLO_DET (30 ms
to 100 ms); refer to USB Carkit Specification (CEA-936-A), November 2005.
7.9.4 RxD pulse converter
When data-during-audio mode is enabled, the RxD pulse converter converts the negative
pulses on the DP line to an NRZ signal that is output to the DAT/VP line. Each time a pulse
is received, the output on DAT/VP is inverted. If DAT/VP remains at logic 0 for a time of
tDAT_AUD_POL (20 ms to 30 ms), then the output on DAT/VP will automatically return to
logic 1; refer to USB Carkit Specification (CEA-936-A), November 2005.
7.10 Autoconnect
The HNP in the OTG supplement specifies the following sequence of events to transfer
the role of the host from the A-device to the B-device:
1. The A-device sets the bus in the suspend state.
2. The B-device simulates a disconnect by de-asserting its DP pull-up.
3. The A-device detects SE0 on the bus and asserts its DP pull-up.
4. The B-device detects that the DP line is HIGH and assumes the role of the host.
The OTG supplement specifies that the time between the B-device de-asserting its DP
pull-up and the A-device asserting its pull-up must be less than 3 ms. For an A-device with
a slow interrupt response time, 3 ms may not be enough to write an I2C-bus command to
the ISP1302 to assert DP pull-up. An alternative method is for the A-device transceiver to
automatically assert DP pull-up after detecting an SE0 from the B-device.
The sequence of events is as follows: After finishing data transfers between the A-device
and the B-device and before suspending the bus, the A-device sends SOFs. The B-device
receives these SOFs, and does not transmit any packet back to the A-device. During this
time, the A-device sets the BDIS_ACON_EN bit in the ISP1302. This enables the
ISP1302 to look for SE0 whenever the A-device is not transmitting (that is, whenever the
OE_N/INT_N pin of the ISP1302 is not asserted). After the BDIS_ACON_EN bit is set, the
A-device stops transmitting SOFs and allows the bus to go to the idle state. If the B-device
disconnects, the bus goes to SE0, and the ISP1302 logic automatically turns on the
A-device pull-up. To disable the DP pull-up resistor, clear bit BDIS_ACON_EN.
7.11 USB transceiver
7.11.1 Differential driver
The operation of the driver is described in Table 5.
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 5.
Transceiver driver operating setting
Pin
Bit
Differential driver
RESET_N[1]
OE_N/INT_N SUSPEND DAT_SE0
HIGH
LOW
0
0
output value from DAT/VP to DP and
SE0/VM to DM
HIGH
LOW
0
1
output value from DAT/VP to DP and DM
if SE0/VM is LOW; otherwise drive both
DP and DM to LOW
HIGH
LOW
1
X
output value from DAT/VP to DP and DM
HIGH
HIGH
X
X
high-Z
LOW
X
X
X
high-Z
[1]
Include the internal power-on-reset pulse (active HIGH).
Table 6 shows the behavior of the transmit operation in detail.
Table 6.
USB functional mode: transmit operation
USB mode
Inputs
Outputs
DAT/VP
SE0/VM
DP
DM
DAT_SE0
LOW
LOW
LOW
HIGH
DAT_SE0
HIGH
LOW
HIGH
LOW
DAT_SE0
LOW
HIGH
LOW
LOW
DAT_SE0
HIGH
HIGH
LOW
LOW
VP_VM
LOW
LOW
LOW
LOW
VP_VM
HIGH
LOW
HIGH
LOW
VP_VM
LOW
HIGH
LOW
HIGH
VP_VM
HIGH
HIGH
HIGH
HIGH
7.11.2 Differential receiver
The operation of the differential receiver is described in Table 7.
Table 7.
Differential receiver operation settings
Pin
Bit
Differential receiver
OE_N/INT_N
SUSPEND
DAT_SE0
HIGH
0
1
output differential value from DP and DM to
DAT/VP and RCV
HIGH
0
0
output differential value from DP and DM to RCV
The detailed behavior of the receive transceiver operation is shown in Table 8.
Table 8.
USB functional mode: receive operation
USB mode
Bit SUSPEND
Inputs
Outputs
DP
DM
DAT/VP
SE0/VM
RCV
DAT_SE0
0
LOW
LOW
RCV
HIGH
last value of RCV
DAT_SE0
0
HIGH
LOW
HIGH
LOW
HIGH
DAT_SE0
0
LOW
HIGH
LOW
LOW
LOW
DAT_SE0
0
HIGH
HIGH
RCV
LOW
last value of RCV
DAT_SE0
1
LOW
LOW
LOW
HIGH
X
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ISP1302
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USB OTG transceiver with carkit support
Table 8.
USB functional mode: receive operation …continued
USB mode
Bit SUSPEND
Inputs
Outputs
DP
DM
DAT/VP
SE0/VM
RCV
DAT_SE0
1
HIGH
LOW
HIGH
LOW
X
DAT_SE0
1
LOW
HIGH
LOW
LOW
X
DAT_SE0
1
HIGH
HIGH
HIGH
LOW
X
VP_VM
0
LOW
LOW
LOW
LOW
last value of RCV
VP_VM
0
HIGH
LOW
HIGH
LOW
HIGH
VP_VM
0
LOW
HIGH
LOW
HIGH
LOW
VP_VM
0
HIGH
HIGH
HIGH
HIGH
last value of RCV
VP_VM
1
LOW
LOW
LOW
LOW
X
VP_VM
1
HIGH
LOW
HIGH
LOW
X
VP_VM
1
LOW
HIGH
LOW
HIGH
X
VP_VM
1
HIGH
HIGH
HIGH
HIGH
X
7.12 Power-On Reset (POR)
When VCC is powered on, an internal POR is generated. The internal POR pulse width
(tPORP) will typically be 200 ns. The pulse is started when VCC rises above VPOR(trip).
The power-on reset function can be explained by viewing the dips at t2 to t3 and t4 to t5
on the VCC curve (see Figure 9).
t0 — The internal POR starts with a LOW level.
t1 — The detector will see the passing of the trip level and a delay element will add
another tPORP before it drops to LOW.
t2 to t3 — The internal POR pulse will be generated whenever VCC drops below VPOR(trip)
for more than 11 µs.
t4 to t5 — The dip is too short (< 11 µs) and the internal POR pulse will not react and will
remain LOW.
VCC
VPOR(trip)
t0
t1
t2
t3
t4
tPORP
tPORP
t5
PORP(1)
004aaa582
(1) PORP = Power-On Reset Pulse.
Fig 9. Internal power-on reset timing
7.13 I2C-bus device address and external charge pump control
The ADR/PSW pin has two functions. Both functions are described as follows.
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USB OTG transceiver with carkit support
The first function of the ADR/PSW pin is to set the I2C-bus address. On the rising edge of
the RESET_N pin, the level on ADR/PSW is latched and stored in ADR_REG, which
represents the Least Significant Bit (LSB) of the I2C-bus address. If ADR_REG = 0, the
I2C-bus address for the ISP1302 is 010 1100 (2Ch); if ADR_REG = 1, the I2C-bus
address for the ISP1302 is 010 1101 (2Dh). The power-on reset value of ADR_REG = 0.
The second function of the ADR/PSW pin is to control an external charge pump. The
ADR/PSW pin can be programmed as an active HIGH or active LOW PSW output. The
polarity of the PSW output is determined by ADR_REG. If ADR_REG = 0, then PSW will
be active HIGH; if ADR_REG = 1, then PSW will be active LOW. The PSW output will be
enabled only when Mode Control 2 register bit PSW_OE = 1. By default, PSW can only
drive HIGH if the hardware reset pulse is not issued on RESET_N.
The combinations of I2C-bus address and the PSW polarity are limited, as shown in
Table 9.
Table 9.
Possible combinations of I2C-bus address and the PSW polarity
ADR/PSW level on the rising
edge of RESET_N
I2C-bus address
PSW polarity
LOW
2Ch
active HIGH
HIGH
2Dh
active LOW
The ISP1302 built-in charge pump supports VBUS current at 50 mA. If the application
needs more current support, an external charge pump may be needed. In this case, the
ADR/PSW pin can act as a power switch for the external charge pump. Figure 10 shows
an example of using an external charge pump.
100 kΩ
VREG
ADR/PSW
VBAT
VOUT
VIN
VBUS
4.7 µF
ISP1302
CHARGE PUMP
VBUS
USB
CONNECTOR
ON/OFF
004aaa659
Fig 10. Using an external charge pump
ISP1302_1
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ISP1302
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USB OTG transceiver with carkit support
8. Modes of operation
The ISP1302 supports three types of modes:
• Power modes
• USB modes
• Transparent modes
8.1 Power modes
8.1.1 Normal mode
In this mode, both VCC and VCC(I/O) are connected and their voltage levels are within the
operation range.
There are three levels of power saving schemes in the ISP1302:
• Active-power mode: power is on; all circuits are active.
• USB suspend mode: to reduce power consumption, the USB differential receiver is
powered down.
• Power-down mode: set by writing logic 1 to bit PWR_DN of the Mode Control 2
register. The clock generator and all biasing circuits are turned off to reduce power
consumption to the minimum possible. For details on waking up the clock, see
Section 10.
8.1.2 Disable mode
In disable mode, VCC(I/O) is cut-off and VCC is powered. In this mode, the ISP1302 is in the
power-down state.
The USB differential driver will be 3-stated as long as VCC(I/O) is not present.
8.1.3 Isolate mode
In isolate mode, VCC is cut-off and VCC(I/O) is powered. In this mode, the ISP1302 will drive
a stable level to all digital output pins, and all bidirectional digital pins will be set in 3-state.
Table 10 shows a summary of power modes.
Table 10.
ISP1302 power modes summary
VCC
VCC(I/O)
PWR_DN (bit)
ICC = ICC(pd)
Comment
Off
off
X
yes
power off
Off
on
X
yes
isolate mode
On
off
X
yes
disable mode (power-down)
On
on
0
no
normal mode (full operation)
On
on
1
yes
normal mode (power-down)
Table 11 shows the pin states in disable and isolate modes.
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ISP1302
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USB OTG transceiver with carkit support
Table 11.
ISP1302 pin states in disable and isolate modes
Pin name
Disable mode (VCC = on, VCC(I/O) = off)
Isolate mode (VCC = off, VCC(I/O) = on)
VCC, VREG
powered
not present
VCC(I/O)
not present
powered
DP
15 kΩ pull-down resistor enabled
high-Z
DM
15 kΩ pull-down resistor enabled
high-Z
RCV
high-Z
drive LOW
RESET_N, SDA, SCL, ADR/PSW,
SE0/VM, DAT/VP, INT_N,
OE_N/INT_N, SERVICE_N
high-Z
high-Z
SPKR_R/MIC, SPKR_L, ID, VBUS,
CR_INT, C_A, C_B
high-Z
high-Z
8.2 USB modes
The two USB modes of the ISP1302 are:
• VP_VM bidirectional mode
• DAT_SE0 bidirectional mode
In VP_VM USB mode, pin DAT/VP is used for the VP function, pin SE0/VM is used for the
VM function, and pin RCV is used for the RCV function.
In DAT_SE0 USB mode, pin DAT/VP is used for the DAT function, pin SE0/VM is used for
the SE0 function, and pin RCV is not used.
Table 12 specifies the functionality of the device during the two USB modes.
Table 12.
USB
USB functional modes: I/O values
mode[1]
VP_VM
DAT_SE0
Bit
Pin
DAT_SE0
OE_N/INT_N
DAT/VP
SE0/VM
RCV
0
LOW
TxD+[2]
TxD−[2]
RxD[6]
HIGH
RxD+[3]
RxD−[3]
RxD[6]
LOW
TxD[4]
FSE0[5]
RxD[6]
HIGH
RxD[6]
RSE0[7]
RxD[6]
1
[1]
Some of the modes and signals are provided to achieve backward compatibility with IP cores.
[2]
TxD+ and TxD− are single-ended inputs to drive the DP and DM outputs, respectively, in single-ended
mode.
[3]
RxD+ and RxD− are the outputs of the single-ended receivers connected to DP and DM, respectively.
[4]
TxD is the input to drive DP and DM in DAT_SE0 mode.
[5]
FSE0 is to force an SE0 on the DP and DM lines in DAT_SE0 mode.
[6]
RxD is the output of the differential receiver.
[7]
RSE0 is an output, indicating that an SE0 is received on the DP and DM lines.
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USB OTG transceiver with carkit support
8.3 Transparent modes
8.3.1 Transparent UART mode
When in transparent UART mode, an SoC (with the UART controller) communicates
through the ISP1302 to another UART device that is connected to its DP and DM lines.
The ISP1302 operates as a logic level translator between the following pins:
• For the TxD signal: from SE0/VM (VCC(I/O) level) to DM (VREG level).
• For the RxD signal: from DP (VREG level) to DAT/VP (VCC(I/O) level).
The ISP1302 is in transparent UART mode, if bit UART_EN of the Mode Control 1 register
is set.
8.3.2 Transparent audio mode
In transparent audio mode, the ISP1302 will disable its DP and DM driver. The carkit
interrupt detector is enabled. Built-in analog switches, DC biasing circuits, and the
data-during-audio feature can be enabled by setting corresponding bits in the Carkit
Control register:
• Stereo mode: SPKR_L on DM and SPKR_R on DP.
• Mono and MIC mode: SPKR_L on DM and MIC on DP.
The ISP1302 is in transparent audio mode if bit UART_EN of the Mode Control 1 register
is cleared, bit AUDIO_EN of the Mode Control 2 register is set, and bit TRANSP_EN of
the Mode Control 1 register is cleared.
8.3.3 Transparent general-purpose buffer mode
In transparent general-purpose buffer mode, the DAT/VP and SE0/VM pins are connected
to the DP and DM pins, respectively. The direction of the data transfer can be controlled
using bits TRANSP_BDIR1 and TRANSP_BDIR0 of the Mode Control 2 register as
specified in Table 14.
The ISP1302 is in transparent general-purpose buffer mode, if bit UART_EN = 0, bit
AUDIO_EN = 0, bit DAT_SE0 = 1 and bit TRANSP_EN = 1.
8.3.4 Data-during-audio mode
This mode is a combination of audio mode and UART mode. The SPKR_R, SPKR_L and
MIC audio signals will be bypassed through the DP and DM lines. UART data bytes can
be transmitted or received on the DP and DM lines when the audio signal is running.
To transmit data, if the SE0/VM input changes level (either from HIGH to LOW or from
LOW to HIGH), a HIGH pulse will be generated on the DM line. The pulse voltage is above
2.9 V. The pulse width is between 200 ns and 500 ns. The data-during-audio transmitting
is enabled when the ISP1302 is in transparent audio mode and bit TX_PULSE_EN = 1.
To receive data, if a LOW pulse is detected on the DP line, the ISP1302 will toggle the
level on the DAT/VP pin. The data-during-audio receiving is enabled when the ISP1302 is
in transparent audio mode and bit RX_PULSE_EN = 1.
Table 13 provides a summary of device operating modes.
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ISP1302
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USB OTG transceiver with carkit support
Table 13.
Summary of device operating modes
Mode
Bit
Description
UART_EN
USB mode
AUDIO_EN
TRANSP_EN DAT_SE0
0
0
0
X
USB ATX enabled
Transparent general-purpose 0
buffer mode
0
1
1
USB ATX disabled.
SE0/VM ↔ DM
DAT/VP ↔ DP
see Table 14
Transparent audio mode
0
1
0
X
USB ATX disabled.
SPKR_L → DM
SPKR_R/MIC ↔ DP
Transparent UART mode
1
X
X
X
USB ATX disabled.
SE0/VM → DM
DAT/VP ← DP
Table 14.
Transparent general-purpose buffer mode
Bit TRANSP_BDIR[1:0]
Direction of the data flow
00
DAT/VP → DP
SE0/VM → DM
01
DAT/VP → DP
SE0/VM ← DM
10
DAT/VP ← DP
SE0/VM → DM
11
DAT/VP ← DP
SE0/VM ← DM
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USB OTG transceiver with carkit support
9. Serial controller
9.1 Register map
Table 15 provides an overview of serial controller registers.
Table 15.
Register overview
Register
Width (bits)
Access Memory address[1]
Functionality
Reference
Vendor ID
16
R
00h to 01h
Section 9.1.1 on page 22
Product ID
16
R
02h to 03h
Version ID
16
R
14h to 15h
device
identification
registers
Mode Control 1
8
R/S/C
Set — 04h
Clear — 05h
Mode Control 2
8
R/S/C
Section 9.1.2 on page 23
control and
status registers
Set — 12h
Clear — 13h
Audio Control
8
R/S/C
OTG Control
8
R/S/C
Set — 16h
Clear — 17h
Set — 06h
Clear — 07h
Misc Control
8
R/S/C
Set — 18h
Clear — 19h
Carkit Control
8
R/S/C
Set — 1Ah
Clear — 1Bh
Transmit Positive Width
8
R/W
1Ch
Transmit Negative Width
8
R/W
1Dh
Receive Polarity Recovery
8
R/W
1Eh
Carkit Interrupt Delay
8
R/W
1Fh
OTG Status
8
R
10h
Interrupt Source
8
R
08h
Interrupt Latch
8
R/S/C
Set — 0Ah
interrupt
registers
Section 9.1.3 on page 29
Clear — 0Bh
Interrupt Enable Low
8
R/S/C
Set — 0Ch
Clear — 0Dh
Interrupt Enable High
8
R/S/C
Set — 0Eh
Clear — 0Fh
[1]
The R/W/S/C access type represents a field that can be read, written, set or cleared (set to 0). A register can be read from either of the
set or clear addresses. Writing to a write address indicates that values will be directly written to the register. Writing logic 1 to a set
address sets the associated bit. Writing logic 1 to a clear address clears the associated bit. Writing logic 0 to either a set or clear
address has no effect.
9.1.1 Device identification registers
9.1.1.1
Vendor ID register
Table 16 provides the bit description of the Vendor ID register.
ISP1302_1
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Rev. 01 — 24 May 2007
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ISP1302
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USB OTG transceiver with carkit support
Table 16.
Vendor ID register (address R = 00h to 01h) bit description
Bit
Symbol
Access
Value
Description
15 to 0
VENDORID[15:0]
R
04CCh
NXP Semiconductors’ Vendor ID
9.1.1.2
Product ID register
The bit description of the Product ID register is given in Table 17.
Table 17.
Product ID register (address R = 02h to 03h) bit description
Bit
Symbol
15 to 0
PRODUCTID[15:0] R
9.1.1.3
Access
Value
Description
1302h
Product ID of the ISP1302
Version ID register
Table 18 shows the bit allocation of the register.
Table 18.
Version ID register (address R = 14h to 15h) bit allocation
Bit
15
14
Symbol
13
12
11
PACKAGEID[3:0]
10
9
8
LEGACYID[3:0]
X[1]
Reset
Access
R
R
R
R
R
R
R
R
Bit
7
6
5
4
3
2
1
0
Symbol
MAJORID[3:0]
MINORID[3:0]
X[1]
Reset
Access
[1]
R
R
R
R
R
R
R
R
The reset value depends on the version number of the chip.
Table 19.
Bit
Version ID register (address R = 14h to 15h) bit description
Symbol
Description
15 to 12 PACKAGEID[3:0]
Package information:
0 — HVQFN24
1 — WLCSP25
11 to 8
LEGACYID[3:0]
Legacy version ID:
0 — New method of defining the version ID
1 to 15 — Legacy method of defining the version ID
7 to 4
MAJORID[3:0]
Version ID, major number; this number starts with 1 and increments
by 1 if there is a major update to the chip.
3 to 0
MINORID[3:0]
Version ID, minor number; this number starts with 0 and increments
by 1 if there is a minor update to the chip.
9.1.2 Control registers
9.1.2.1
Mode Control 1 register
The bit allocation of the Mode Control 1 register is given in Table 20.
ISP1302_1
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ISP1302
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USB OTG transceiver with carkit support
Table 20.
Mode Control 1 register (address S = 04h, C = 05h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
reserved
UART_EN
OE_INT_
EN
BDIS_
ACON_EN
TRANSP_
EN
DAT_SE0
SUSPEND
SPEED
0
0/1
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Reset
Access
Table 21.
Mode Control 1 register (address S = 04h, C = 05h) bit description
Bit
Symbol
Description
7
-
reserved
6
UART_EN
When set, the ATX is in transparent UART mode. The default value of this
bit depends on the SERVICE_N pin. On reset, if SERVICE_N = HIGH, the
reset value of UART_EN = 0; if SERVICE_N = LOW, the reset value of
UART_EN = 1.
5
OE_INT_EN
When set and when in suspend mode, pin OE_N/INT_N becomes an
output and is asserted when an interrupt occurs.
4
BDIS_ACON_ This bit has two functions:
EN
For an A-device, this bit works as BDIS_ACON_EN. It enables the A-device
to connect if the B-device disconnect is detected; see Section 7.10.
0 — DP pull-up resistor is controlled by the DP_PULLUP bit in the OTG
Control register.
1 — DP pull-up resistor will connect on the B-device disconnect.
For a B-device, this bit works as ACON_BSE0_EN. It enables the B-device
to drive SE0 on DP and DM, if the A-device connect is detected.
0 — B-device will stop driving SE0.
1 — B-device will start to drive SE0, if the A-device connect is detected.
3
TRANSP_EN
When set, the ATX is in transparent general-purpose buffer mode.
2
DAT_SE0
0 — VP_VM mode
1 — DAT_SE0 mode
1
SUSPEND
Sets the transceiver in low-power mode.
0 — Active-power mode
1 — Low-power mode (differential receiver is disabled if SPEED = 1)
0
SPEED
Set the rise time and the fall time of the transmit driver in USB modes.
0 — Low-speed mode
1 — Full-speed mode
9.1.2.2
Mode Control 2 register
For the bit allocation of this register, see Table 22.
Table 22.
Mode Control 2 register (address S = 12h, C = 13h) bit allocation
Bit
Symbol
7
6
5
4
3
reserved
PSW_OE
AUDIO_EN
TRANSP_
BDIR1
TRANSP_
BDIR0
0
0
0
0
0
1
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Reset
Access
ISP1302_1
Product data sheet
2
1
reserved
0
PWR_DN
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USB OTG transceiver with carkit support
Table 23.
Mode Control 2 register (address S = 12h, C = 13h) bit description
Bit
Symbol
Description
7
-
reserved
6
PSW_OE
0 — ADR/PSW pin acts as an input.
1 — ADR/PSW pin is driven.
5
AUDIO_EN
Enables the ISP1302 in carkit audio mode.
0 — Audio mode disable: DP_INT detector is turned off, and
single-ended receivers are turned on.
1 — Audio mode enable: DP_INT detector is turned on, and
single-ended receivers are turned off.
TRANSP_BDIR Controls the direction of data transfer in transparent general-purpose
[1:0]
buffer mode; see Table 14
4 to 3
9.1.2.3
2 to 1
-
reserved
0
PWR_DN
Set to power-down mode; activities on pin SCL or the interrupt event
can wake-up the chip; see Section 10
Audio Control register
Table 24 provides the bit allocation of the register.
Table 24.
Audio Control register (address S = 16h, C = 17h) bit allocation
Bit
Symbol
7
6
PH_ID_
ACK
PH_ID_INT
Reset
Access
5
4
3
2
reserved
1
0
SW_MIC_
SPKR_L
reserved
0
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 25.
Audio Control register (address S = 16h, C = 17h) bit description
Bit
Symbol
Description
7
PH_ID_ACK
If set, wait for time tPH_ID_WT, turn on the ID pull-down switch for
tPH_ID_INT, then turn off. Bit PH_ID_ACK autoclears to 0. See Table 4.
6
PH_ID_INT
If set, turn on the ID pull-down switch for time tPH_ID_INT and then turn
off. Bit PH_ID_INT autoclears to 0. See Table 4.
5 to 2 1
reserved
SW_MIC_SPKR_ Audio loopback test:
L
0 — Turn off the switch between the SPKR_R/MIC and SPKR_L pins.
1 — Turn on the switch between the SPKR_R/MIC and SPKR_L pins.
0
9.1.2.4
-
reserved
OTG Control register
Table 26 shows the bit allocation of the OTG Control register.
Table 26.
OTG Control register (address S = 06h, C = 07h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
VBUS_
CHRG
VBUS_
DISCHRG
VBUS_
DRV
ID_PULL
DN
DM_PULL
DOWN
DP_PULL
DOWN
DM_PULL
UP
DP_PULL
UP
0
0
0
0
1
1
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Reset
Access
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 27.
OTG Control register (address S = 06h, C = 07h) bit description
Bit
Symbol
Description
7
VBUS_CHRG
Charge VBUS through a pull-up resistor (RUP(VBUS)), which is
connected to VREG.
0 — Disconnect the resistor
1 — Connect the resistor
6
VBUS_DISCHRG
Discharge VBUS through a pull-down resistor (RDN(VBUS)).
0 — Disconnect the resistor
1 — Connect the resistor
5
Drive VBUS to 5 V through the charge pump.
VBUS_DRV
0 — Charge pump is disabled
1 — Charge pump is enabled
4
Connect pin ID to ground. See Table 5.
ID_PULLDN
0 — Disconnected
1 — Connected
3
DM_PULLDOWN
Connect the DM pull-down resistor (RDN(DM)).
0 — DM pull-down resistor is disconnected
1 — DM pull-down resistor is connected
2
DP_PULLDOWN
Connect the DP pull-down resistor (RDN(DP)).
0 — DP pull-down resistor is disconnected
1 — DP pull-down resistor is connected
1
Connect the DM pull-up resistor (RUP(DM)).
DM_PULLUP
0 — DM pull-up resistor is disconnected
1 — DM pull-up resistor is connected
0
Connect the DP pull-up resistor (RUP(DP)).
DP_PULLUP
0 — DP pull-up resistor is disconnected (assuming that bit
BDIS_ACON_EN is logic 0)
1 — DP pull-up resistor is connected
9.1.2.5
Misc Control register
Table 28 shows the bit allocation of the register.
Table 28.
Misc Control register (address S = 18h, C = 19h) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
FORCE_
DP_HIGH
FORCE_
DP_LOW
reserved
UART_2V8
_EN
IDPU_DIS
DP_WKPU
_EN
SRP_INIT
REG_BY
PASS_DIS
0
0
0
1
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Reset
Access
Table 29.
Misc Control register (address S = 18h, C = 19h) bit description
Bit
Symbol
Description
7
FORCE_DP_HIGH Forces the DP pin to be driven to HIGH
6
FORCE_DP_LOW
Forces the DP pin to be driven to LOW
5
-
reserved
ISP1302_1
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 29.
Misc Control register (address S = 18h, C = 19h) bit description …continued
Bit
Symbol
Description
4
UART_2V8_EN
This bit indicates the output voltage level of the internal regulator.
This bit is only valid when bit UART_EN is logic 1.
When this bit and bit UART_EN are logic 1, the internal regulator
bypass switch will always be disabled, ignoring the value of bit
REG_BYPASS_DIS. This is to ensure that the internal regulator
outputs +2.8 V, when VCC is 3.0 V to 4.5 V.
0 — Internal regulator outputs 3.3 V
1 — Internal regulator outputs 2.8 V
3
IDPU_DIS
0 — Internal ID pin pull-up resistor is enabled
1 — Internal ID pin pull-up resistor is disabled
2
DP_WKPU_EN
This bit will enable RweakUP(DP) on the DP line. It is provided to
support the detection of external accessory devices. This bit is
optional.
0 — Disconnect the DP weak pull-up resistor (RweakUP(DP))
1 — Connect the DP weak pull-up resistor (RweakUP(DP))
1
SRP_INIT
0 — No event
1 — Initialize SRP, if this bit is set, the following events occur in
sequence: enable DP pull-up for 7.5 ms, enable the VBUS_CHRG
resistor for 32 ms, enable the VBUS_DISCHRG resistor for 13 ms.
This bit will autoclear when the sequence is complete.
0
9.1.2.6
0 — Internal regulator bypass switch is turned on, when VCC < 3.6 V
REG_BYPASS_
DIS
1 — Internal regulator bypass switch is turned off
Carkit Control register
Table 30 shows the bit allocation of this register.
Table 30.
Carkit Control register (address S = 1Ah, C = 1Bh) bit allocation
Bit
7
Symbol
reserved
Reset
Access
6
5
4
3
2
1
0
SPKR_MIC
_EN
SPKR_L_
EN
SPKR_R_
BIAS_EN
SPKR_L_
BIAS_EN
RX_
PULSE_E
N
TX_PULSE
_EN
0
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 31.
Carkit Control register (address S = 1Ah, C = 1Bh) bit description
Bit
Symbol
Description
7 to 6
-
reserved
5
SPKR_MIC_EN
Enables the speaker right or MIC line switch
4
SPKR_L_EN
Enables the speaker left line switch
3
SPKR_R_BIAS_EN
Enables the DC bias for the speaker right line
2
SPKR_L_BIAS_EN
Enables the DC bias for the speaker left line
1
RX_PULSE_EN
Enables the data-during-audio receive
0
TX_PULSE_EN
Enables the data-during-audio transmit
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
27 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
9.1.2.7
Transmit Positive Width register
This register specifies the width of the positive pulse, that is, the output on the DM line
when the TX_PULSE_EN bit is set. The time is measured in units of 60 MHz clock
periods. The clock has a frequency in the range of fclk(dda). For bit description, see
Table 32.
Table 32. Transmit Positive Width register (address R/W = 1Ch) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
TXPOSIWIDTH[7:0]
R/W
15h*
Transmit positive pulse width
9.1.2.8
Transmit Negative Width register
This register specifies the width of the negative pulse, that is, the output on the DM line
when the TX_PULSE_EN bit is set. The time is measured in units of 60 MHz clock
periods. The clock has a frequency in the range of fclk(dda). For the bit description, see
Table 33.
Table 33. Transmit Negative Width register (address R/W = 1Dh) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
TXNEGWIDTH[7:0]
R/W
2Ah*
Transmit negative pulse width
9.1.2.9
Receive Polarity Recovery register
The bit description of the register is shown in Table 34.
Table 34. Receive Polarity Recovery register (address R/W = 1Eh) bit description
Legend: * reset value
Bit
Symbol
7 to 0 RX_RECOVERY[7:0]
9.1.2.10
Access
Value
Description
R/W
64h*
Sets the RxD polarity recovery time in units of 0.25 ms. The timer
tolerance is dictated by fclk(dda). Valid when bit RX_PULSE_EN is set.
Carkit Interrupt Delay register
The bit description of the register is given in Table 35.
Table 35. Carkit Interrupt Delay register (address R/W = 1Fh) bit description
Legend: * reset value
Bit
Symbol
Access
Value
Description
7 to 0
CR_INT_DELAY[7:0]
R/W
C8h*
Sets the carkit interrupt detection time in units of 0.25 ms. The
timer tolerance is dictated by fclk(dda).
9.1.2.11
OTG Status register
Table 36 shows the bit allocation of the OTG Status register.
Table 36.
OTG Status register (address R = 10h) bit allocation
Bit
7
6
reserved
B_SESS_
END
Reset
0
-[1]
0
Access
R
R
R
Symbol
[1]
5
4
3
2
1
0
ID_102K
ID_440K
ID_200K
reserved
0
-[1]
-[1]
-[1]
0
R
R
R
R
R
reserved
The reset value depends on the status of the respective pin.
ISP1302_1
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ISP1302
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USB OTG transceiver with carkit support
Table 37.
OTG Status register (address R = 10h) bit description
Bit
Symbol
Description
7
-
reserved
6
B_SESS_END
Set when the VBUS voltage is below the B-device session end threshold
(0.2 V to 0.8 V).
In power-down mode, this bit is fixed as logic 0.
5 to 4
-
reserved
3
ID_102K
Indicates that pin ID is connected to ground through RDN(ID) = 102 kΩ.
This bit indicates that the phone accessory is connected. For details,
refer to USB Carkit Specification (CEA-936-A).
In power-down mode, this bit is fixed as logic 0.
2
ID_440K
Indicates that pin ID is connected to ground through RDN(ID) = 440 kΩ.
This bit indicates the default current capability of the connected charger.
For details, refer to USB Carkit Specification (CEA-936-A).
In power-down mode, this bit is fixed as logic 0.
1
Indicates that pin ID is connected to ground through RDN(ID) = 200 kΩ.
This bit indicates the default current capability of the connected charger.
For details, refer to USB Carkit Specification (CEA-936-A).
ID_200K
In power-down mode, this bit is fixed as logic 0.
0
-
reserved
9.1.3 Interrupt registers
9.1.3.1
Interrupt Source register
Table 38 shows the bit allocation of this register that indicates the current state of the
signals that can generate an interrupt.
Table 38.
Interrupt Source register (address R = 08h) bit allocation
Bit
7
6
5
4
3
2
DP_INT
BDIS_
ACON
ID_FLOAT
DM_HI
ID_GND
DP_HI
Reset
-[1]
0
-[1]
-[1]
-[1]
-[1]
-[1]
-[1]
Access
R
R
R
R
R
R
R
R
Symbol
[1]
1
0
SESS_VLD VBUS_VLD
The reset value depends on the status of the respective pin.
ISP1302_1
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 39.
Interrupt Source register (address R = 08h) bit description
Bit
Symbol
7
DP_INT
Description
This bit has two functions:
When the Carkit Interrupt Delay register is 0h and the voltage on the
CR_INT pin is below the carkit interrupt threshold (0.4 V to 0.6 V), this bit
is set.
0 — Voltage on the CR_INT pin is above the carkit interrupt threshold
(0.4 V to 0.6 V).
1 — Voltage on the CR_INT pin is below the carkit interrupt threshold
(0.4 V to 0.6 V).
When the Carkit Interrupt Delay register is nonzero and the voltage on the
CR_INT pin is below the carkit interrupt threshold (0.4 V to 0.6 V) for a
period of time defined in the Carkit Interrupt Delay register, this bit is set.
0 — No event
1 — The carkit stereo interrupt event is detected.
In power-down mode, this bit is fixed as logic 0.
6
BDIS_ACON
Set when bit BDIS_ACON_EN is set, and the ISP1302 enables the DP
pull-up resistor after detecting the B-device disconnect (SE0).
0 — No event
1 — BDIS_ACON is detected.
5
ID_FLOAT
Indicates the status of pin ID.
0 — ID pin is not floating.
1 — ID pin is floating.
4
DM_HI
DM single-ended receiver output.
0 — LOW
1 — HIGH
3
ID_GND
Indicates the status of pin ID:
0 — ID pin is not grounded.
1 — ID pin is grounded.
In power-down mode, this bit is fixed as logic 0.
2
DP_HI
DP single-ended receiver output.
0 — LOW
1 — HIGH
1
SESS_VLD
VBUS session valid detector.
0 — VBUS is lower than VA_SESS_VLD (bit ID_GND = 1) or VB_SESS_VLD (bit
ID_GND = 0).
1 — VBUS is higher than VA_SESS_VLD (bit ID_GND = 1) or VB_SESS_VLD (bit
ID_GND = 0).
0
VBUS_VLD
This bit has two functions:
For the A-device (bit ID_GND = 1), it acts as the VBUS valid detector.
0 — VBUS is lower than the VBUS valid threshold.
1 — VBUS is higher than the VBUS valid threshold.
For the B-device (bit ID_GND = 0), it acts as B_SESS_END (B-device
session end detector).
0 — VBUS is above the B-device session end threshold (0.2 V to 0.8 V).
1 — VBUS is below the B-device session end threshold (0.2 V to 0.8 V).
In power-down mode, this bit is fixed as logic 0.
ISP1302_1
Product data sheet
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30 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
9.1.3.2
Interrupt Latch register
This register indicates the source that generates an interrupt. For the bit allocation, see
Table 40.
Table 40.
Interrupt Latch register (address S = 0Ah, C = 0Bh) bit allocation
Bit
Symbol
7
6
5
4
3
DP_INT_
INT
BDIS_
ACON_INT
ID_FLOAT_
INT
DM_HI_
INT
ID_GND_
INT
Reset
Access
2
1
DP_HI_INT SESS_VLD
_INT
0
VBUS_
VLD_INT
0
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 41.
Interrupt Latch register (address S = 0Ah, C = 0Bh) bit description
Bit
Symbol
Description
7
DP_INT_INT
0 — No interrupt
1 — Interrupt on the DP_INT status change
6
BDIS_ACON_INT 0 — No interrupt
1 — Interrupt on the BDIS_ACON status change
5
ID_FLOAT_INT
0 — No interrupt
4
DM_HI_INT
0 — No interrupt
1 — Interrupt on the ID_FLOAT status change
1 — Interrupt on the DM_HI status change
3
ID_GND_INT
0 — No interrupt
1 — Interrupt on the ID_GND status change
2
DP_HI_INT
0 — No interrupt
1 — Interrupt on the DP_HI status change
1
SESS_VLD_INT
0 — No interrupt
0
VBUS_VLD_INT
0 — No interrupt
1 — Interrupt on the SESS_VLD status change
1 — Interrupt on the VBUS_VLD status change
9.1.3.3
Interrupt Enable Low register
The bits in this register enable interrupts when the corresponding bits in the Interrupt
Source register change from logic 1 to logic 0. Table 42 shows the bit allocation of the
register.
Table 42.
Interrupt Enable Low register (address S = 0Ch, C = 0Dh) bit allocation
Bit
Symbol
7
6
5
4
3
2
1
0
DP_INT_
IEL
reserved
ID_FLOAT
_IEL
DM_HI_IEL
ID_GND_
IEL
DP_HI_IEL
SESS_VLD
_IEL
VBUS_
VLD_IEL
Reset
Access
0
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
ISP1302_1
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 43.
Interrupt Enable Low register (address S = 0Ch, C = 0Dh) bit description
Bit
Symbol
Description
7
DP_INT_IEL
0 — Disable
1 — Enable
6
-
reserved
5
ID_FLOAT_IEL
0 — Disable
1 — Enable
4
DM_HI_IEL
0 — Disable
3
ID_GND_IEL
1 — Enable
0 — Disable
1 — Enable
2
DP_HI_IEL
0 — Disable
1 — Enable
1
SESS_VLD_IEL
0 — Disable
1 — Enable
0
VBUS_VLD_IEL
0 — Disable
1 — Enable
9.1.3.4
Interrupt Enable High register
The bits in this register enable interrupts when the corresponding bits in the Interrupt
Source register change from logic 0 to logic 1. For the bit allocation, see Table 44.
Table 44.
Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit allocation
Bit
Symbol
7
DP_INT_
IEH
Reset
Access
6
5
BDIS_
ID_FLOAT_
ACON_IEH
IEH
4
3
DM_HI_
IEH
ID_GND_
IEH
2
1
DP_HI_IEH SESS_VLD
_IEH
0
VBUS_
VLD_IEH
0
0
0
0
0
0
0
0
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
R/S/C
Table 45.
Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit description
Bit
Symbol
Description
7
DP_INT_IEH
0 — Disable
6
BDIS_ACON_IEH 0 — Disable
1 — Enable
1 — Enable
5
ID_FLOAT_IEH
0 — Disable
1 — Enable
4
DM_HI_IEH
0 — Disable
1 — Enable
3
ID_GND_IEH
0 — Disable
1 — Enable
ISP1302_1
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32 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 45.
Interrupt Enable High register (address S = 0Eh, C = 0Fh) bit description
Bit
Symbol
Description
2
DP_HI_IEH
0 — Disable
1 — Enable
1
SESS_VLD_IEH
0 — Disable
1 — Enable
0
VBUS_VLD_IEH
0 — Disable
1 — Enable
9.2 Interrupts
Any of the Interrupt Source register signals given in Table 38 can generate an interrupt,
when the signal becomes either LOW or HIGH. After an interrupt is generated, the SoC
should be able to read the status of each signal and the bit that indicates whether that
signal generated the interrupt. A bit in the Interrupt Latch register is set when any of the
following events occurs:
• Writing logic 1 to a set address sets the corresponding bit.
• The corresponding bit in the Interrupt Enable High register is set, and the associated
signal changes from LOW to HIGH.
• The corresponding bit in the Interrupt Enable Low register is set, and the associated
signal changes from HIGH to LOW.
• The INT_N pin will be asserted if one or more bits in the Interrupt Latch register are
set. The INT_N pin will be de-asserted if all the bits in the Interrupt Latch register are
cleared by software.
9.3 I2C-bus protocol
For detailed information, refer to The I2C-bus specification; ver. 2.1.
9.3.1 I2C-bus byte transfer format
Table 46.
S[1]
I2C-bus byte transfer format
Byte 1
A[2]
Byte 2
8 bits
[1]
S = Start.
[2]
A = Acknowledge.
[3]
P = Stop.
A[2]
Byte 3
8 bits
A[2]
A[2]
..
8 bits
P[3]
..
9.3.2 I2C-bus device address
Table 47.
Bit
Symbol
Value
[1]
I2C-bus slave address bit allocation
7
6
5
4
3
2
1
0
A6
A5
A4
A3
A2
A1
A0
R/W
0
1
0
1
1
0
[1]
X
Determined by the status of the ADR/PSW pin on the rising edge of RESET_N. If ADR/PSW = HIGH,
bit A0 = 1; if ADR/PSW = LOW, bit A0 = 0. Bit A0 will be zero if there is no hardware reset pulse on the
RESET_N pin after power on.
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ISP1302
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USB OTG transceiver with carkit support
Table 48.
I2C-bus slave address bit description
Bit
Symbol
Description
7 to 1
A[6:0]
Device Address: The device address of the ISP1302 is 01 0110 (A0), where
A0 is determined by pin ADR/PSW.
0
R/W
Read or write command.
0 — Write
1 — Read
9.3.3 Write format
A write operation can be performed as:
• One-byte write to the specified register address.
• Multiple-byte write to N consecutive registers, starting from the specified start
address. N defines the number of registers to write. If N = 1, only the start register is
written.
9.3.3.1
One-byte write
Table 49 describes the transfer format for a one-byte write.
Table 49.
9.3.3.2
Transfer format description for a one-byte write
Byte
Description
S
master starts with a START condition
Device select
master transmits the device address and write command bit R/W = 0
ACK
slave generates an acknowledgment
Register address K
master transmits the address of register K
ACK
slave generates an acknowledgment
Write data K
master writes data to register K
ACK
slave generates an acknowledgment
P
master generates a STOP condition
Multiple-byte write
Table 50 describes the transfer format for multiple-byte write.
Table 50.
Transfer format description for a multiple-byte write
Byte
Description
S
master starts with a START condition
Device select
master transmits the device address and write command bit R/W = 0
ACK
slave generates an acknowledgment
Register address K
master transmits the address of register K. This is the start address for
writing multiple data bytes to consecutive registers. After a byte is written,
the register address is automatically incremented by 1.
Remark: If the master writes to a nonexistent register, the slave must send
a 'not ACK' and also must not increment the index address.
ACK
slave generates an acknowledgment
Write data K
master writes data to register K
ACK
slave generates an acknowledgment
Write data K + 1
master writes data to register K + 1
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ISP1302
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USB OTG transceiver with carkit support
Table 50.
Transfer format description for a multiple-byte write …continued
Byte
Description
ACK
slave generates an acknowledgment
:
:
Write data K + N − 1 master writes data to register K + N − 1. When the incremented address
K + N − 1 becomes > 255, the register address rolls over to 0. Therefore, it
is possible that some registers may be overwritten, if the transfer is not
stopped before the rollover.
ACK
slave generates an acknowledgment
P
master generates a STOP condition
Figure 11 illustrates the write format for a one-byte write and a multiple-byte write.
ACK
ACK
S
device select
P
write data K
register address K
wr
ACK
one-byte write
ACK
ACK
S
device select
wr
write data K
register address K
ACK
ACK
write data K + 3
write data K + 2
ACK
ACK
write data K + 1
ACK
ACK
.... maximum, rollover to 0
write data K + N - 1
P
004aaa569
multiple-byte write
Fig 11. Writing data to the ISP1302 registers
9.3.4 Read format
A read operation can be performed in two ways:
• Current address read: To read the register at the current address.
– Single register read
• Random address read: To read N registers starting at a specified address. N defines
the number of registers to be read. If N = 1, only the start register is read.
– Single register read
– Multiple register read
9.3.4.1
Current address read
The transfer format description for a current address read is given in Table 51. For the
illustration, see Figure 12.
ISP1302_1
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35 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 51.
Transfer format description for current address read
Byte
Description
S
master starts with a START condition
Device select
master transmits the device address and read command bit R/W = 1
ACK
slave generates an acknowledgment
Read data K
slave transmits and master reads data from register K. If the start address is
not specified, the read operation starts from where the index register is
pointing to because of a previous read or write operation.
No ACK
master terminates the read operation by generating a no acknowledgement
P
master generates a stop condition
ACK
S
device select
rd
no ACK
P
read data K
current address read
004aaa570
Fig 12. Current address read
9.3.4.2
Random address read: single read
Table 52 describes the transfer format for a single-byte read. Figure 13 illustrates the byte
sequence.
Table 52.
9.3.4.3
Transfer format description for a single-byte read
SDA line
Description
S
master starts with a START condition
Device select
master transmits the device address and write command bit R/W = 0
ACK
slave generates an acknowledgment
Register address K
master transmits (start) address of register K from which to be read
ACK
slave generates an acknowledgment
S
master restarts with a START condition
Device select
master transmits the device address and read command bit R/W = 1
ACK
slave generates an acknowledgment
Read data K
slave transmits and master reads data from register K
No ACK
master terminates the read operation by generating a no acknowledgement
P
master generates a STOP condition
Random address read: multiple read
The transfer format description for a multiple-byte read is given in Table 53. Figure 13
illustrates the byte sequence.
Table 53.
Transfer format description for a multiple-byte read
SDA line
Description
S
master starts with a START condition
Device select
master transmits the device address and write command bit R/W = 0
ACK
slave generates an acknowledgment
Register address K
master transmits (start) address of register K from which to be read
ISP1302_1
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 53.
Transfer format description for a multiple-byte read …continued
SDA line
Description
ACK
slave generates an acknowledgment
S
master restarts with a START condition
Device select
master transmits the device address and read command bit R/W = 1
ACK
slave generates an acknowledgment
Read data K
slave transmits and master reads data from register K. After a byte is read,
the address is automatically incremented by 1.
ACK
master generates an acknowledgment
Read data K + 1
slave transmits and master reads data from register K + 1
ACK
master generates an acknowledgment
:
:
Read data K + N − 1 slave transmits and master reads data register K + N − 1. This is the last
register to read. After incrementing, the address rolls over to 0. Here, N
represents the number of addresses available in the slave.
No ACK
master terminates the read operation by generating a no acknowledgement
P
master generates a STOP condition
ACK
ACK
S
device select
wr
S
register address K
no ACK
ACK
rd
device select
P
read data K
random address single read
ACK
ACK
device select
S
wr
read data K + 2
rd
device select
ACK
ACK
read data K + 1
S
register address K
ACK
read data K
ACK
.... maximum, rollover to 0
random access multiple read
ACK
no ACK
write data K + N - 1
P
004aaa571
Fig 13. Random address read
10. Clock wake-up scheme
The following subsections explain the ISP1302 clock stop timing, events triggering the
clock to wake up, and the timing of the clock wake-up.
10.1 Power-down event
The internal clock (LazyClock and/or I2C-bus clock) is stopped when bit PWR_DN is set. It
takes td(clkstp) for the clock to stop from the time the power-down condition is detected. The
clock always stops at its falling edge.
The internal clock must be woken up first before any register read or write operation.
ISP1302_1
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ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
10.2 Clock wake-up event
The clock wakes up when any of the following events occurs on the ISP1302 pins:
• Pin SCL goes LOW.
• Pin VBUS goes above the session valid threshold, provided bit SESS_VLD_IEH of the
Interrupt Enable High register is set.
• Status bit ID_FLOAT changes from logic 1 to logic 0, provided bit ID_FLOAT_IEL of
the Interrupt Enable Low register is set.
• Status bit ID_FLOAT changes from logic 0 to logic 1, provided bit ID_FLOAT_IEH of
the Interrupt Enable High register is set.
• DP goes HIGH provided the DP_HI_IEH bit in the Interrupt Enable High register is
set.
• DM goes HIGH provided the DM_HI_IEH bit in the Interrupt Enable High register is
set.
The event triggers the clock to start. The clock start-up time is tstartup(lclk). A stable clock is
guaranteed after six clock cycles. The clock will always start at its rising edge.
When an event is triggered and the clock is started, the clock will remain active for td(clkstp).
If bit PWR_DN is not cleared within this period, the clock will stop. If the clock wakes up
because of any event other than SCL going LOW, an interrupt will be generated once the
clock is active.
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
38 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
11. Limiting values
Table 54. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
Symbol Parameter
Conditions
Min
Max
Unit
Voltage
VCC
supply voltage
−0.5
+5.5[1]
V
VCC(I/O)
input/output supply voltage
−0.5
+4.6
V
VI
input voltage
−0.5
+4.6
V
on digital pins ADR/PSW, SERVICE_N
and RESET_N
on all other digital pins
−0.5
VCC(I/O) + 0.5
V
on analog pins DP and DM
−0.5
+4.6[2]
V
on analog pins SPKR_L and
SPKR_R/MIC
−0.5
+4.6
V
VI(VBUS)
input voltage on pin VBUS
−0.5
+7.0[3]
V
VI(ID)
input voltage on pin ID
−0.5
+5.5
V
VESD
electrostatic discharge voltage
−2
+2
kV
Machine Model (JESD22-A115-A)
−200
+200
V
Charge Device Model (JESD22-C101-C)
−500
+500
V
-
100
mA
ILI < 1 µA
Human Body Model (JESD22-A114D)
[4]
Current
latch-up current
Ilu
Temperature
Tstg
storage temperature
−60
+125
°C
Tj
junction temperature
−40
+125
°C
[1]
When the charge pump is enabled, +5.5 V is only allowed for short period of time ≤ 1 second.
[2]
The ISP1302 has been tested according to Universal Serial Bus Specification Rev. 2.0, Section 7.1.1. The DP and DM lines were
shorted to VBUS/GND for 24 hours with 50 % transmit/receive duty cycle. The ISP1302 operated normally after this test and is therefore
compliant to the requirement.
[3]
When an external series resistor is added to the VBUS pin, it can withstand higher voltages for longer periods of time because the
resistor limits the current flowing into the VBUS pad. For example, with an external 1 kΩ resistor, VBUS can tolerate 10 V for at least
5 seconds. If an external resistor is used, the internal charge pump must never be used, and other OTG functions must be verified in the
customer application.
[4]
Equivalent to discharging a 100 pF capacitor through a 1.5 kΩ resistor (Human Body Model).
12. Recommended operating conditions
Table 55.
Recommended operating conditions
Symbol Parameter
Conditions
Min
Typ
Max
Unit
Voltage
VCC
supply voltage
3.0
-
4.5
V
VCC(I/O)
input/output supply voltage
1.4
-
3.6[1]
V
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
39 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 55.
Recommended operating conditions …continued
Symbol Parameter
Conditions
Min
Typ
Max
Unit
VI
digital pins ADR/PSW, SERVICE_N
and RESET_N
0
-
3.6
V
on all other digital pins
0
-
VCC(I/O)
V
input voltage
V(pu)OD
on analog pins DP and DM
0
-
3.6
V
on analog pins SPKR_L and
SPKR_R/MIC
0
-
3.6
V
1.4
-
3.6
V
−40
-
+85
°C
open-drain pull-up voltage
Temperature
Tamb
[1]
ambient temperature
VCC(I/O) should be less than or equal to VCC.
13. Static characteristics
Table 56. Static characteristics: supply pins
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
output voltage on pin VREG
bit UART_2V8_EN = 0;
Iload ≤ 300 µA[1]
3.0[2]
-
3.6
V
bit UART_2V8_EN = 1 and
bit UART_EN = 1; Iload ≤ 10 mA
2.35
-
2.85
V
1.5
-
2.5
V
Voltage
VO(VREG)
VPOR(trip)
power-on reset trip voltage
Current
ICC
supply current
transmitting and receiving at
12 Mbit/s; CL = 50 pF on
pins DP and DM
[3]
-
5
8
mA
ICC(I/O)
supply current on pin VCC(I/O)
transmitting and receiving at
12 Mbit/s
[3]
-
1
2
mA
ICC(I/O)(isol)
isolate mode supply current on VCC not connected
pin VCC(I/O)
-
-
10
µA
ICC(idle)
idle and SE0 supply current
idle: VDP > 2.7 V, VDM < 0.3 V;
SE0: VDP < 0.3 V, VDM < 0.3 V
-
0.5
1
mA
ICC(I/O)(stat)
static supply current on
pin VCC(I/O)
idle, SE0 or suspend
-
-
20
µA
ICC(stat)
static supply current
bit PWR_DN = 1, bit
SUSPEND = 1 or VCC(I/O) = 0 V
-
12
25
µA
[4]
[4]
[1]
Iload includes the DP pull-up resistor current.
[2]
In power-down mode, the minimum voltage is 2.7 V.
[3]
Maximum value characterized only, not tested in production.
[4]
Excluding any load current to the 1.5 kΩ and 15 kΩ pull-up and pull-down resistors (200 µA typical).
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
40 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 57. Static characteristics: digital pins
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input level voltage
VIL
LOW-level input voltage
-
-
0.3VCC(I/O)
V
VIH
HIGH-level input voltage
0.7VCC(I/O)
-
-
V
-
-
0.4
V
-
-
0.15
V
VCC(I/O) − 0.4
-
-
V
VCC(I/O) − 0.15
-
-
V
−1
-
+1
µA
−5
-
+5
µA
-
-
10
pF
Output level voltage
LOW-level output voltage
VOL
IOL = 2 mA
IOL = 100 µA
VOH
HIGH-level output voltage
IOH = 2 mA
[1]
IOH = 100 µA
Leakage current
input leakage current
ILI
Open-drain output current
off-state output current
IOZ
Capacitance
input capacitance
Cin
[1]
pin to ground
Not applicable for open-drain outputs.
Table 58. Static characteristics: analog I/O pins DP and DM
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Input level voltage
VDI
differential input sensitivity
|VDP − VDM|
0.2
-
-
V
VCM
differential common mode voltage
range
includes VDI range
0.8
-
2.35
V
VIL
LOW-level input voltage
-
-
0.8
V
VIH
HIGH-level input voltage
2.0
-
-
V
Output level voltage
VOL
LOW-level output voltage
RL of 1.5 kΩ to +3.6 V
-
-
0.3
V
VOH
HIGH-level output voltage
RL of 15 kΩ to ground
2.8
-
3.6
V
0.4
-
0.6
V
3.0
-
3.6
V
−1
-
+1
µA
-
-
10
pF
Voltage
Vth(DP)L
VTERM
DP LOW threshold voltage
[1]
termination voltage
Leakage current
ILZ
off-state leakage current
Capacitance
Cin
input capacitance
pin to AGND
Resistance
RDN(DP)
pull-down resistance on pin DP
14.25
-
24.8
kΩ
RDN(DM)
pull-down resistance on pin DM
14.25
-
24.8
kΩ
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
41 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 58. Static characteristics: analog I/O pins DP and DM …continued
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
RUP(DP)
pull-up resistance on pin DP
bus idle
900
-
1575
Ω
RweakUP(DP)
weak pull-up resistance on pin DP
bus driven
ZDRV
driver output impedance
ZINP
input impedance
steady-state drive
[1]
For the upstream port pull-up resistance (RPU).
[2]
Includes external series resistances of 33 Ω ± 5 % each on DP and DM.
[2]
1425
-
3090
Ω
105
150
195
kΩ
34
-
44
Ω
1
-
-
MΩ
Table 59. Static characteristics: analog I/O pin ID
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Resistance
RUP(int)(ID)
internal pull-up
resistance on pin ID
70
-
130
kΩ
RDN(ID)
pull-down resistance on bit ID_PULLDOWN = 1; output
pin ID
pull-down resistance
-
-
50
Ω
bit ID_102K = 1; external 102 kΩ
pull-down resistance
101
102
103
kΩ
bit ID_200K = 1; external 200 kΩ
pull-down resistance
198
200
202
kΩ
bit ID_440K = 1; external 440 kΩ
pull-down resistance
436
440
444
kΩ
bit ID_FLOAT = 1; external
pull-down resistance on pin ID for
mini-B plug
105
-
-
kΩ
bit ID_GND = 1; external pull-down
resistance on pin ID for mini-A plug
-
-
10
Ω
Table 60. Static characteristics: charge pump
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
load current
Cext = 220 nF;
VBUS > VA_VBUS_VLD
50
-
-
mA
VO(VBUS)
output voltage on
pin VBUS
Iload = 50 mA; Cext = 220 nF
4.4
5
5.25
V
VL(VBUS)
leakage voltage on
pin VBUS
charge pump disabled
-
-
0.2
V
VA_VBUS_VLD
A-device VBUS valid
voltage
4.4
-
4.7
V
Current
Iload
Voltage
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
42 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 60. Static characteristics: charge pump …continued
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
VB_SESS_END
B-device session end
voltage
VA_SESS_VLD
A-device session valid
voltage
VB_SESS_VLD
B-device session valid
voltage
Vhys(A_SESS_VLD)
Conditions
Min
Typ
Max
Unit
0.2
-
0.8
V
bit ID_GND = 1
0.8
-
2.0
V
bit ID_GND = 0
0.8
-
4.0
V
A-device session valid
hysteresis voltage
-
80
-
mV
Vhys(B_SESS_VLD)
B-device session valid
hysteresis voltage
-
80
-
mV
ηcp
charge pump efficiency
Iload = 50 mA; VCC = 3 V
-
75
-
%
RUP(VBUS)
pull-up resistance on
pin VBUS
connect to VREG when bit
VBUS_CHRG = 1
460
-
1000
Ω
RDN(VBUS)
pull-down resistance on
pin VBUS
connect to ground when bit
VBUS_DISCHRG = 1
660
-
1200
Ω
RI(idle)(VBUS)
idle input resistance on
pin VBUS
bit ID_GND = 1 and bit
VBUS_DRV = 0
52.5
70
100
kΩ
bit ID_GND = 0, bit
VBUS_DRV = 1, or VCC and
VCC(I/O) are not powered
130
200
270
kΩ
Iload = 8 mA
20
-
-
nF
Iload = 20 mA
61
-
-
nF
Iload = 25 mA
90
-
-
nF
Iload = 50 mA
198
-
-
nF
[1]
Resistance
Capacitance
external capacitance
Cext
[1]
Efficiency when loaded.
Table 61. Static characteristics: analog I/O pins SPKR_R/MIC and SPKR_L
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
pin to AGND
-
-
10
pF
Capacitance
Cin
input capacitance
Resistance
Zasw(on)
audio switch ON state impedance
50
-
150
Ω
Zasw(off)
audio switch OFF state impedance
2
-
-
MΩ
RB1
bias resistance 1
7
10
13
kΩ
RB2
bias resistance 2
14
20
26
kΩ
MR
resistance matching
-
-
1
%
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
43 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
14. Dynamic characteristics
Table 62. Dynamic characteristics: reset and clock
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
10
-
-
µs
70
110
150
kHz
3.5
5.0
7.0
MHz
35
-
80
MHz
5.6
8
10.4
ms
Reset
tW(RESET_N)
external RESET_N pulse width
Internal clock
fclk
clock frequency
bit PWR_DN = 0
fclk_I2C
I2C-bus
fclk(dda)
data-during-audio clock frequency
clock frequency
TX_PULSE_EN = 1
td(PD-CLKstop) delay time from power-down to clock
stop
[1]
tstartup(lclk)
LazyClock start-up time
7
10
13
µs
td(clkstp)
clock stop delay time
5.6
8
10.4
ms
[1]
LazyClock for interrupts, registers, and power-down and wake-up timer.
Table 63. Dynamic characteristics: VBUS comparator timing
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; Tamb = −40 °C to +85 °C; unless otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
td(VA_VBUS_VLD)
VA_VBUS_VLD delay time
Min
Typ
Max
Unit
20
-
300
µs
Table 64. Dynamic characteristics: bus turnaround timing (USB bidirectional mode)
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
tTOI
bus turnaround time (O/I)
OE_N/INT_N to DAT/VP and
SE0/VM; see Figure 18
0
-
5
ns
tTIO
bus turnaround time (I/O)
OE_N/INT_N to DAT/VP and
SE0/VM; see Figure 18
0
-
5
ns
Table 65. Dynamic characteristics: analog I/O pins DP and DM
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
Driver characteristics (low-speed)
tLR
transition time: rise time
CL = 200 pF to 600 pF;
1.5 kΩ pull-up on pin DM enabled;
10 % to 90 % of |VOH − VOL|; see
Figure 14
75
-
300
ns
tLF
transition time: fall time
CL = 200 pF to 600 pF;
1.5 kΩ pull-up on pin DM enabled;
90 % to 10 % of |VOH − VOL|; see
Figure 14
75
-
300
ns
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
44 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 65. Dynamic characteristics: analog I/O pins DP and DM …continued
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
[1]
Min
Typ
Max
Unit
80
-
125
%
FRFM
differential rise time/fall
time matching
excluding the first transition from
idle state
VCRS
output signal crossover
voltage
excluding the first transition from
idle state; see Figure 15
1.3
-
2.0
V
Driver characteristics (full-speed)
tFR
rise time
CL = 50 pF; 10 % to 90 % of
|VOH − VOL|; see Figure 14
4
-
20
ns
tFF
fall time
CL = 50 pF; 90 % to 10 % of
|VOH − VOL|; see Figure 14
4
-
20
ns
FRFM
differential rise time/fall
time matching
excluding the first transition from
idle state
90
-
111.1
%
VCRS
output signal crossover
voltage
excluding the first transition from
idle state; see Figure 15
1.3
-
2.0
V
[1]
Driver timing
tPLH(drv)
driver propagation delay
(LOW to HIGH)
DAT/VP, SE0/VM to DP, DM;
see Figure 15 and Figure 19
-
-
18
ns
tPHL(drv)
driver propagation delay
(HIGH to LOW)
DAT/VP, SE0/VM to DP, DM;
see Figure 15 and Figure 19
-
-
18
ns
tPHZ
HIGH to OFF-state
propagation delay
OE_N/INT_N to DP, DM;
see Figure 16 and Figure 20
-
-
15
ns
tPLZ
LOW to OFF-state
propagation delay
OE_N/INT_N to DP, DM;
see Figure 16 and Figure 20
-
-
15
ns
tPZH
OFF-state to HIGH
propagation delay
OE_N/INT_N to DP, DM;
see Figure 16 and Figure 20
-
-
15
ns
tPZL
OFF-state to LOW
propagation delay
OE_N/INT_N to DP, DM;
see Figure 16 and Figure 20
-
-
15
ns
Receiver timing
Differential receiver
tPLH(rcv)
receiver propagation
delay (LOW to HIGH)
DP, DM to RCV; see Figure 17 and
Figure 21
-
-
15
ns
tPHL(rcv)
receiver propagation
delay (HIGH to LOW)
DP, DM to RCV; see Figure 17 and
Figure 21
-
-
15
ns
Single-ended receiver
tPLH(se)
single-ended propagation DP, DM to DAT/VP, SE0/VM;
delay (LOW to HIGH)
see Figure 17 and Figure 21
-
-
18
ns
tPHL(se)
single-ended propagation DP, DM to DAT/VP, SE0/VM;
delay (HIGH to LOW)
see Figure 17 and Figure 21
-
-
18
ns
[1]
tFR/tFF.
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
45 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 66. Dynamic characteristics: analog I/O pin ID
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
tPH_ID_INT
tPH_ID_WT
Conditions
Min
Typ
Max
Unit
ID interrupt pulse width
4
-
8
ms
ID interrupt wait time
4
-
8
ms
Table 67. Dynamic characteristics: audio switches
VCC = 3.0 V to 4.5 V; VCC(I/O) = 1.4 V to 3.6 V; CL = 50 pF; RPU = 1.5 kΩ on DP to VTERM; Tamb = −40 °C to +85 °C; unless
otherwise specified.
Typical values are at VCC = 3.3 V; VCC(I/O) = 3.3 V; Tamb = +25 °C; unless otherwise specified.
Symbol
Parameter
Conditions
Min
Typ
Max
Unit
PSRR
power supply rejection
ratio
noise on VCC = 0.5 V (p-p) at
f = 217 Hz over audio range
of 20 Hz to 20 kHz;
see Section 14.1
-
-
−80
dB
αct(audio)
crosstalk audio
audio voltage = 1 V, f = 1 kHz;
see Section 14.2
-
-
−66
dB
THD
total harmonic distortion
audio voltage = 2.3 V,
f = 1 kHz; see Section 14.1
-
-
1
%
audio voltage = 2.0 V,
f = 1 kHz; see Section 14.1
-
-
0.3
%
USB 12 Mbit/s active on DP
and DM, < 20 kHz signal
components observed on the
SPKR_L and SPKR_R/MIC
pins; see Section 14.3
-
-
−70
dB
0.1
-
2.3
V
αiso(d-a)
data to audio isolation
Vio(aud)
audio input or output
voltage range
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
46 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
1.8 V
0.9 V
logic input 0.9 V
tFR, tLR
VOH
VOL
tFF, tLF
90 %
0V
tPLH(drv)
90 %
10 %
differential
data lines
10 %
004aaa572
Fig 14. Rise time and fall time
differential
data lines
VOL
VCRS
VOL
004aaa573
2.0 V
logic 0.9 V
input
VOH
VCRS
Fig 15. Timing of DAT/VP and SE0/VM to DP and DM
1.8 V
0V
tPHL(drv)
VOH
differential
data lines
0.9 V
VCRS
VCRS
0.8 V
tPLH(rcv)
tPLH(se)
tPHZ
tPLZ
tPZH
tPZL
tPHL(rcv)
tPHL(se)
VOH
VOH − 0.3 V
VOL + 0.3 V
004aaa574
Fig 16. Timing of OE_N/INT_N to DP and DM
0.9 V
0.9 V
logic output
VCRS
VOL
004aaa575
Fig 17. Timing of DP and DM to RCV, DAT/VP and
SE0/VM
OE_N/INT_N
tTOI
tTIO
DAT/VP
SE0/VM
output
input
output
004aaa545
Fig 18. SIE interface bus turnaround timing
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
47 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
VTERM
VREG
D.U.T.
1.5 kΩ
DP or
DM
test point
33 Ω
CL
15 kΩ
004aaa725
Load capacitance CL = 50 pF (minimum or maximum timing).
Fig 19. Load on pins DP and DM
33 Ω
D.U.T.
test point
500 Ω
DP or
DM
50 pF
V
004aaa517
V = 0 V for tPZH and tPHZ.
V = VREG for tPZL and tPLZ.
Fig 20. Load on pins DP and DM for enable time and disable time
test point
D.U.T.
10 pF
004aaa669
Fig 21. Load on pins SE0/VM, DAT/VP and RCV
14.1 Test configurations
Table 68.
Test configurations
Parameter
Pins or switches
Configuration 1
Configuration 2
Termination
impedances
DP
60 kΩ
200 Ω, 1.4 V DC
DM
60 kΩ
60 kΩ
SPKR_R
200 Ω
200 Ω, 1.4 V DC
SPKR_L
200 Ω
200 Ω, 1.4 V DC
MIC
10 kΩ
10 kΩ
S1
on
off
S2
off
on
S3
on
on
-
DP
MIC
-
DM
DM
Switch positions
Measured ports
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
48 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
4.6 ms
577 µs
Vmax = 3.4 V to 4.2 V
500 mV
Vmin = 2.9 V to 3.7 V
30 µs
004aaa519
Fig 22. VCC with 217 Hz noise
14.2 Audio crosstalk test conditions
VCC sweeps from 2.9 V to 4.2 V (DC waveform).
14.2.1 Test 1
• SW2 = on and SW3 = on.
• DP is terminated using a 200 Ω resistor, and DM is terminated using a 60 kΩ resistor.
• MIC is terminated using a 10 kΩ resistor, and SPKR_L is terminated using a 200 Ω
resistor, 1.4 V DC.
• Drive f = 1 kHz, V = 1 V (p-p) to DP; signal on DM must be 66 dB below.
14.2.2 Test 2
•
•
•
•
SW1 = on and SW3 = on.
DP and DM are terminated using a 60 kΩ resistor.
SPKR_L and SPKR_R are terminated using a 200 Ω resistor, 1.4 V DC.
Drive f = 1 kHz, V = 1 V (p-p) to SPKR_R; signal on DM must be 66 dB below.
14.2.3 Test 3
•
•
•
•
SW1 = on and SW3 = on.
DP and DM terminated using a 60 kΩ resistor.
SPKR_L and SPKR_R terminated using a 200 Ω resistor, 1.4 V DC.
Drive f = 1 kHz, V = 1 V (p-p) to SPKR_L; signal on DP must be 66 dB below.
14.3 Data to audio isolation test conditions
•
•
•
•
•
•
VCC is swept from 2.9 V to 4.2 V (DC waveform).
12 Mbit/s USB data is to be active on the DP and DM pins.
All audio switches must be left open.
MIC must be terminated using a 10 kΩ resistor.
SPKR_L and SPKR_R are each to be terminated using a 200 Ω resistor.
Taking an FFT on the SPKR_R/MIC and SPKR_L pins, USB data components below
20 kHz will be < −70 dB below the USB data level (3.6 V).
ISP1302_1
Product data sheet
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Rev. 01 — 24 May 2007
49 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
14.4 I2C-bus characteristics
SDA
tf
tLOW
tSU;DAT
tr
tf
tHD;STA
tSP
tr
tBUF
SCL
tHD;STA
S
tHD;DAT
tHIGH
tSU;STA
tSU;STO
Sr
P
S
004aaa216
Fig 23. Definition of timing for standard mode or fast mode devices on the I2C-bus
Table 69.
Characteristics of I/O stages of I2C-bus lines (SDA, SCL)
Symbol Parameter
Conditions
Standard mode
Fast mode
Unit
Min
Max
Min
Max
0
100
0
400
fSCL
SCL clock frequency
kHz
tHD;STA
hold time (repeated) START
condition
4.0
-
0.6
-
µs
tLOW
LOW period of the SCL clock
4.7
-
1.3
-
µs
tHIGH
HIGH period of the SCL clock
4.0
-
0.6
-
µs
tSU;STA
set-up time for a repeated START
condition
4.7
-
0.6
-
µs
tSU;DAT
data set-up time
250
-
100
-
ns
tHD;DAT
data hold time
0
-
0
0.9
µs
0.1Cb[1]
300
ns
tr
rise time of both SDA and SCL
signals
-
1000
20 +
tf
fall time of both SDA and SCL
signals
-
300
20 + 0.1Cb[1]
300
ns
tSU;STO
set-up time for STOP condition
4.0
-
0.6
-
µs
tBUF
bus free time between a STOP and
START condition
4.7
-
1.3
-
µs
tSP
pulse width of spikes that must be
suppressed by the input filter
not
applicable
not
applicable
0
50
ns
[1]
Cb is the capacitance load for each bus line in pF. If mixed with high-speed mode devices, faster fall times are allowed.
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
50 of 63
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
R1
10 kΩ
C1
1 µF
VCC(I/O)
VCC(I/O)
SW1
VCC
SW-PB
C10
0.1 µF
C2
0.1 µF
VCC(I/O)
OTG
CONTROLLER
R8
100 kΩ
R2
3.3 kΩ
R3
3.3 kΩ
R4
10 kΩ
R5
10 kΩ
ADR/PSW
Rev. 01 — 24 May 2007
SDA
SDA
SCL
SCL
RESET_N
INT_N
INT_N
CR_INT
VREG
SERVICE_N
OE_N
OE_N/INT_N
SPKR_L
DAT
SPKR_R/MIC
RCV
CODEC
C11
C12
C13
C5
0.47 µF
0.47 µF
0.47 µF
0.1 µF
24
2
23
3
22
4
21
20
5
6 ISP1302HN 19
18
7
8
17
9
16
10
15
11
14
12
SPKR_L
DGND
13
VCC(I/O)
CPGND
SHIELD
C_B
SHIELD
C_A
C4
220 nF
SHIELD
VCC
SHIELD
VBUS
GND
ID
AGND
DP
DM
DAT/VP
ID
R6
D+
33 Ω
D−
R7
VBUS
33 Ω
9
8
7
6
USB MINI-AB
5 RECEPTACLE
4
3
2
1
SE0/VM
C6
C9
0.1 µF
4.7 µF
(LOW ESR)
SPKR_R
MIC
Fig 24. Application diagram
ISP1302
51 of 63
© NXP B.V. 2007. All rights reserved.
The figure shows the HVQFN pinout. For the WLCSP ballout, see Table 2.
004aaa816
USB OTG transceiver with carkit support
SE0
1
NXP Semiconductors
15. Application information
ISP1302_1
Product data sheet
VCC(I/O)
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
16. Package outline
HVQFN24: plastic thermal enhanced very thin quad flat package; no leads;
24 terminals; body 4 x 4 x 0.85 mm
A
B
D
SOT616-3
terminal 1
index area
A
A1
E
c
detail X
e1
C
1/2 e
e
12
y
y1 C
v M C A B
w M C
b
7
L
13
6
e
e2
Eh
1/2 e
1
18
terminal 1
index area
24
19
X
Dh
0
2.5
5 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A(1)
max.
A1
b
c
D (1)
Dh
E (1)
Eh
e
e1
e2
L
v
w
y
y1
mm
1
0.05
0.00
0.30
0.18
0.2
4.1
3.9
2.75
2.45
4.1
3.9
2.75
2.45
0.5
2.5
2.5
0.5
0.3
0.1
0.05
0.05
0.1
Note
1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.
REFERENCES
OUTLINE
VERSION
IEC
JEDEC
JEITA
SOT616-3
---
MO-220
---
EUROPEAN
PROJECTION
ISSUE DATE
04-11-19
05-03-10
Fig 25. Package outline SOT616-3 (HVQFN24)
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
52 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
WLCSP25: wafer level chip-size package; 25 bumps; 2.5 x 2.5 x 0.6 mm
B
D
ISP1302UK
A
bump A1
index area
A2
E
A
A1
detail X
e1
∅v
∅w
b
e
M
M
C
C A B
C
y
E
D
e
e2
C
B
A
1
2
3
4
5
X
0
1
2
3 mm
scale
DIMENSIONS (mm are the original dimensions)
UNIT
A
max
A1
A2
b
D
E
e
e1
e2
v
w
y
mm
0.64
0.26
0.22
0.38
0.34
0.34
0.30
2.5
2.4
2.5
2.4
0.5
2
2
0.01
0.04
0.02
OUTLINE
VERSION
REFERENCES
IEC
JEDEC
JEITA
EUROPEAN
PROJECTION
ISSUE DATE
05-09-28
05-09-30
ISP1302UK
Fig 26. Package outline ISP1302UK (WLCSP25)
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
53 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
17. Soldering
This text provides a very brief insight into a complex technology. A more in-depth account
of soldering ICs can be found in Application Note AN10365 “Surface mount reflow
soldering description”.
17.1 Introduction to soldering
Soldering is one of the most common methods through which packages are attached to
Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both
the mechanical and the electrical connection. There is no single soldering method that is
ideal for all IC packages. Wave soldering is often preferred when through-hole and
Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not
suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high
densities that come with increased miniaturization.
17.2 Wave and reflow soldering
Wave soldering is a joining technology in which the joints are made by solder coming from
a standing wave of liquid solder. The wave soldering process is suitable for the following:
• Through-hole components
• Leaded or leadless SMDs, which are glued to the surface of the printed circuit board
Not all SMDs can be wave soldered. Packages with solder balls, and some leadless
packages which have solder lands underneath the body, cannot be wave soldered. Also,
leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered,
due to an increased probability of bridging.
The reflow soldering process involves applying solder paste to a board, followed by
component placement and exposure to a temperature profile. Leaded packages,
packages with solder balls, and leadless packages are all reflow solderable.
Key characteristics in both wave and reflow soldering are:
•
•
•
•
•
•
Board specifications, including the board finish, solder masks and vias
Package footprints, including solder thieves and orientation
The moisture sensitivity level of the packages
Package placement
Inspection and repair
Lead-free soldering versus PbSn soldering
17.3 Wave soldering
Key characteristics in wave soldering are:
• Process issues, such as application of adhesive and flux, clinching of leads, board
transport, the solder wave parameters, and the time during which components are
exposed to the wave
• Solder bath specifications, including temperature and impurities
ISP1302_1
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Rev. 01 — 24 May 2007
54 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
17.4 Reflow soldering
Key characteristics in reflow soldering are:
• Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to
higher minimum peak temperatures (see Figure 27) than a PbSn process, thus
reducing the process window
• Solder paste printing issues including smearing, release, and adjusting the process
window for a mix of large and small components on one board
• Reflow temperature profile; this profile includes preheat, reflow (in which the board is
heated to the peak temperature) and cooling down. It is imperative that the peak
temperature is high enough for the solder to make reliable solder joints (a solder paste
characteristic). In addition, the peak temperature must be low enough that the
packages and/or boards are not damaged. The peak temperature of the package
depends on package thickness and volume and is classified in accordance with
Table 70 and 71
Table 70.
SnPb eutectic process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
≥ 350
< 2.5
235
220
≥ 2.5
220
220
Table 71.
Lead-free process (from J-STD-020C)
Package thickness (mm)
Package reflow temperature (°C)
Volume (mm3)
< 350
350 to 2000
> 2000
< 1.6
260
260
260
1.6 to 2.5
260
250
245
> 2.5
250
245
245
Moisture sensitivity precautions, as indicated on the packing, must be respected at all
times.
Studies have shown that small packages reach higher temperatures during reflow
soldering, see Figure 27.
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
55 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
maximum peak temperature
= MSL limit, damage level
temperature
minimum peak temperature
= minimum soldering temperature
peak
temperature
time
001aac844
MSL: Moisture Sensitivity Level
Fig 27. Temperature profiles for large and small components
For further information on temperature profiles, refer to Application Note AN10365
“Surface mount reflow soldering description”.
18. Additional soldering information
A more in-depth account of soldering WLCSP (Wafer-Level Chip-Size Package) can be
found in Application Note AN10439 “Wafer Level Chip Scale Package”.
19. Abbreviations
Table 72.
Abbreviations
Acronym
Description
ATX
Analog USB Transceiver
FFT
Fast Fourier Transform
HNP
Host Negotiation Protocol
I2C-bus
Inter IC-bus
LSB
Least Significant Bit
MIC
Microphone
NRZ
Non-Return-to-Zero
OTG
On-The-Go
POR
Power-On Reset
PORP
Power-On Reset Pulse
RxD
Receive Data
SE0
Single-Ended Zero
SIE
Serial Interface Engine
SoC
System-on-a-Chip
SOF
Start-Of-Frame
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
56 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 72.
Abbreviations …continued
Acronym
Description
SRP
Session Request Protocol
TxD
Transmit Data
UART
Universal Asynchronous Receiver-Transmitter
USB
Universal Serial Bus
WLCSP
Wafer-Level Chip-Scale Package
20. References
[1]
Universal Serial Bus Specification Rev. 2.0
[2]
On-The-Go Supplement to the USB Specification Rev. 1.2
[3]
On-The-Go Transceiver Specification (CEA-2011)
[4]
USB Carkit Specification (CEA-936-A), November 2005
[5]
ECN_27%_Resistor (Pull-up/pull-down Resistors ECN)
[6]
The I2C-bus specification; ver. 2.1
[7]
Human Body Model (JESD22-A114D)
[8]
Machine Model (JESD22-A115-A)
[9]
Charge Device Model (JESD22-C101-C)
21. Revision history
Table 73.
Revision history
Document ID
Release date
Data sheet status
Change notice
Supersedes
ISP1302_1
20070524
Product data sheet
-
-
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
57 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
22. Legal information
22.1 Data sheet status
Document status[1][2]
Product status[3]
Definition
Objective [short] data sheet
Development
This document contains data from the objective specification for product development.
Preliminary [short] data sheet
Qualification
This document contains data from the preliminary specification.
Product [short] data sheet
Production
This document contains the product specification.
[1]
Please consult the most recently issued document before initiating or completing a design.
[2]
The term ‘short data sheet’ is explained in section “Definitions”.
[3]
The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
22.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or completeness of
information included herein and shall have no liability for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and title. A short data sheet is intended
for quick reference only and should not be relied upon to contain detailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conflict with the short data sheet, the
full data sheet shall prevail.
22.3 Disclaimers
General — Information in this document is believed to be accurate and
reliable. However, NXP Semiconductors does not give any representations or
warranties, expressed or implied, as to the accuracy or completeness of such
information and shall have no liability for the consequences of use of such
information.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descriptions, at any time and without
notice. This document supersedes and replaces all information supplied prior
to the publication hereof.
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in medical, military, aircraft,
space or life support equipment, nor in applications where failure or
malfunction of a NXP Semiconductors product can reasonably be expected to
result in personal injury, death or severe property or environmental damage.
NXP Semiconductors accepts no liability for inclusion and/or use of NXP
Semiconductors products in such equipment or applications and therefore
such inclusion and/or use is at the customer’s own risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty that such applications will be suitable for the
specified use without further testing or modification.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) may cause permanent
damage to the device. Limiting values are stress ratings only and operation of
the device at these or any other conditions above those given in the
Characteristics sections of this document is not implied. Exposure to limiting
values for extended periods may affect device reliability.
Terms and conditions of sale — NXP Semiconductors products are sold
subject to the general terms and conditions of commercial sale, as published
at http://www.nxp.com/profile/terms, including those pertaining to warranty,
intellectual property rights infringement and limitation of liability, unless
explicitly otherwise agreed to in writing by NXP Semiconductors. In case of
any inconsistency or conflict between information in this document and such
terms and conditions, the latter will prevail.
No offer to sell or license — Nothing in this document may be interpreted
or construed as an offer to sell products that is open for acceptance or the
grant, conveyance or implication of any license under any copyrights, patents
or other industrial or intellectual property rights.
22.4 Trademarks
Notice: All referenced brands, product names, service names and trademarks
are the property of their respective owners.
I2C-bus — logo is a trademark of NXP B.V.
23. Contact information
For additional information, please visit: http://www.nxp.com
For sales office addresses, send an email to: [email protected]
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
58 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
24. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10.
Table 11.
Table 12.
Table 13.
Table 14.
Table 15.
Table 16.
Table 17.
Table 18.
Table 19.
Table 20.
Table 21.
Table 22.
Table 23.
Table 24.
Table 25.
Table 26.
Table 27.
Table 28.
Table 29.
Table 30.
Table 31.
Ordering information . . . . . . . . . . . . . . . . . . . . .2
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .5
ID pin status for various applications . . . . . . . . .9
ID pull-down control . . . . . . . . . . . . . . . . . . . . .10
Transceiver driver operating setting . . . . . . . . .15
USB functional mode: transmit operation . . . .15
Differential receiver operation settings . . . . . . .15
USB functional mode: receive operation . . . . .15
Possible combinations of I2C-bus address
and the PSW polarity . . . . . . . . . . . . . . . . . . . .17
ISP1302 power modes summary . . . . . . . . . . .18
ISP1302 pin states in disable and isolate
modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
USB functional modes: I/O values . . . . . . . . . .19
Summary of device operating modes . . . . . . .21
Transparent general-purpose buffer mode . . . .21
Register overview . . . . . . . . . . . . . . . . . . . . . .22
Vendor ID register (address R = 00h to 01h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
Product ID register (address R = 02h to 03h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
Version ID register (address R = 14h to 15h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . .23
Version ID register (address R = 14h to 15h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . .23
Mode Control 1 register (address S = 04h,
C = 05h) bit allocation . . . . . . . . . . . . . . . . . . .24
Mode Control 1 register (address S = 04h,
C = 05h) bit description . . . . . . . . . . . . . . . . . .24
Mode Control 2 register (address S = 12h,
C = 13h) bit allocation . . . . . . . . . . . . . . . . . . .24
Mode Control 2 register (address S = 12h,
C = 13h) bit description . . . . . . . . . . . . . . . . . .25
Audio Control register (address S = 16h,
C = 17h) bit allocation . . . . . . . . . . . . . . . . . . .25
Audio Control register (address S = 16h,
C = 17h) bit description . . . . . . . . . . . . . . . . . .25
OTG Control register (address S = 06h,
C = 07h) bit allocation . . . . . . . . . . . . . . . . . . .25
OTG Control register (address S = 06h,
C = 07h) bit description . . . . . . . . . . . . . . . . . .26
Misc Control register (address S = 18h,
C = 19h) bit allocation . . . . . . . . . . . . . . . . . . .26
Misc Control register (address S = 18h,
C = 19h) bit description . . . . . . . . . . . . . . . . . .26
Carkit Control register (address S = 1Ah,
C = 1Bh) bit allocation . . . . . . . . . . . . . . . . . . .27
Carkit Control register (address S = 1Ah,
C = 1Bh) bit description . . . . . . . . . . . . . . . . . . 27
Table 32. Transmit Positive Width register (address
R/W = 1Ch) bit description . . . . . . . . . . . . . . . 28
Table 33. Transmit Negative Width register (address
R/W = 1Dh) bit description . . . . . . . . . . . . . . . 28
Table 34. Receive Polarity Recovery register (address
R/W = 1Eh) bit description . . . . . . . . . . . . . . . 28
Table 35. Carkit Interrupt Delay register (address
R/W = 1Fh) bit description . . . . . . . . . . . . . . . 28
Table 36. OTG Status register (address R = 10h) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Table 37. OTG Status register (address R = 10h) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 38. Interrupt Source register (address R = 08h)
bit allocation . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Table 39. Interrupt Source register (address R = 08h)
bit description . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 40. Interrupt Latch register (address S = 0Ah,
C = 0Bh) bit allocation . . . . . . . . . . . . . . . . . . . 31
Table 41. Interrupt Latch register (address S = 0Ah,
C = 0Bh) bit description . . . . . . . . . . . . . . . . . . 31
Table 42. Interrupt Enable Low register (address
S = 0Ch, C = 0Dh) bit allocation . . . . . . . . . . . 31
Table 43. Interrupt Enable Low register (address
S = 0Ch, C = 0Dh) bit description . . . . . . . . . . 32
Table 44. Interrupt Enable High register (address
S = 0Eh, C = 0Fh) bit allocation . . . . . . . . . . . 32
Table 45. Interrupt Enable High register (address
S = 0Eh, C = 0Fh) bit description . . . . . . . . . . 32
Table 46. I2C-bus byte transfer format . . . . . . . . . . . . . . 33
Table 47. I2C-bus slave address bit allocation . . . . . . . . 33
Table 48. I2C-bus slave address bit description . . . . . . . 34
Table 49. Transfer format description for a one-byte
write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Table 50. Transfer format description for a
multiple-byte write . . . . . . . . . . . . . . . . . . . . . . 34
Table 51. Transfer format description for current
address read . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 52. Transfer format description for a single-byte
read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table 53. Transfer format description for a
multiple-byte read . . . . . . . . . . . . . . . . . . . . . . 36
Table 54. Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . 39
Table 55. Recommended operating conditions . . . . . . . . 39
Table 56. Static characteristics: supply pins . . . . . . . . . . 40
Table 57. Static characteristics: digital pins . . . . . . . . . . 41
Table 58. Static characteristics: analog I/O pins
DP and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
continued >>
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
59 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
Table 59. Static characteristics: analog I/O pin ID . . . . . .42
Table 60. Static characteristics: charge pump . . . . . . . . .42
Table 61. Static characteristics: analog I/O pins
SPKR_R/MIC and SPKR_L . . . . . . . . . . . . . . .43
Table 62. Dynamic characteristics: reset and clock . . . . .44
Table 63. Dynamic characteristics: VBUS
comparator timing . . . . . . . . . . . . . . . . . . . . . .44
Table 64. Dynamic characteristics: bus turnaround
timing (USB bidirectional mode) . . . . . . . . . . .44
Table 65. Dynamic characteristics: analog I/O pins DP
and DM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
Table 66. Dynamic characteristics: analog I/O pin ID . . .46
Table 67. Dynamic characteristics: audio switches . . . . .46
Table 68. Test configurations . . . . . . . . . . . . . . . . . . . . . .48
Table 69. Characteristics of I/O stages of I2C-bus
lines (SDA, SCL) . . . . . . . . . . . . . . . . . . . . . . .50
Table 70. SnPb eutectic process (from J-STD-020C) . . .55
Table 71. Lead-free process (from J-STD-020C) . . . . . .55
Table 72. Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .56
Table 73. Revision history . . . . . . . . . . . . . . . . . . . . . . . .57
continued >>
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
60 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
25. Figures
Fig 1.
Fig 2.
Fig 3.
Fig 4.
Fig 5.
Fig 6.
Fig 7.
Fig 8.
Fig 9.
Fig 10.
Fig 11.
Fig 12.
Fig 13.
Fig 14.
Fig 15.
Fig 16.
Fig 17.
Fig 18.
Fig 19.
Fig 20.
Fig 21.
Fig 22.
Fig 23.
Fig 24.
Fig 25.
Fig 26.
Fig 27.
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .3
Pin configuration HVQFN24 (top view) . . . . . . . . .4
Pin configuration HVQFN24 (bottom view) . . . . . .4
Pin configuration WLCSP25 (top view) . . . . . . . . .5
Pin configuration WLCSP25 (bottom view) . . . . . .5
DP and DM pull-up and pull-down resistors. . . . .11
Audio bypass . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
Audio data control . . . . . . . . . . . . . . . . . . . . . . . .13
Internal power-on reset timing . . . . . . . . . . . . . . .16
Using an external charge pump . . . . . . . . . . . . . .17
Writing data to the ISP1302 registers . . . . . . . . .35
Current address read . . . . . . . . . . . . . . . . . . . . . .36
Random address read . . . . . . . . . . . . . . . . . . . . .37
Rise time and fall time . . . . . . . . . . . . . . . . . . . . .47
Timing of DAT/VP and SE0/VM to DP and DM . .47
Timing of OE_N/INT_N to DP and DM . . . . . . . .47
Timing of DP and DM to RCV, DAT/VP and
SE0/VM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
SIE interface bus turnaround timing. . . . . . . . . . .47
Load on pins DP and DM. . . . . . . . . . . . . . . . . . .48
Load on pins DP and DM for enable time and
disable time . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Load on pins SE0/VM, DAT/VP and RCV . . . . . .48
VCC with 217 Hz noise . . . . . . . . . . . . . . . . . . . . .49
Definition of timing for standard mode or fast
mode devices on the I2C-bus. . . . . . . . . . . . . . . .50
Application diagram . . . . . . . . . . . . . . . . . . . . . . .51
Package outline SOT616-3 (HVQFN24) . . . . . . .52
Package outline ISP1302UK (WLCSP25) . . . . . .53
Temperature profiles for large and small
components . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56
continued >>
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
61 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
26. Contents
1
2
3
4
5
6
6.1
6.2
7
7.1
7.2
7.3
7.3.1
7.3.2
7.3.3
7.4
7.5
7.6
7.7
7.8
7.9
7.9.1
7.9.2
7.9.3
7.9.4
7.10
7.11
7.11.1
7.11.2
7.12
7.13
8
8.1
8.1.1
8.1.2
8.1.3
8.2
8.3
8.3.1
8.3.2
8.3.3
8.3.4
9
9.1
9.1.1
General description . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering information . . . . . . . . . . . . . . . . . . . . . 2
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning information . . . . . . . . . . . . . . . . . . . . . . 4
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5
Functional description . . . . . . . . . . . . . . . . . . . 8
Serial controller. . . . . . . . . . . . . . . . . . . . . . . . . 8
VBUS charge pump . . . . . . . . . . . . . . . . . . . . . . 8
VBUS comparators. . . . . . . . . . . . . . . . . . . . . . . 8
VBUS valid comparator . . . . . . . . . . . . . . . . . . . 8
Session valid comparator . . . . . . . . . . . . . . . . . 8
Session end comparator. . . . . . . . . . . . . . . . . . 8
ID detector . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pull-up and pull-down resistors. . . . . . . . . . . . 10
3.3 V DC-DC regulator . . . . . . . . . . . . . . . . . . 11
Carkit DP interrupt detector . . . . . . . . . . . . . . 11
Audio bypass . . . . . . . . . . . . . . . . . . . . . . . . . 12
Audio data control. . . . . . . . . . . . . . . . . . . . . . 12
Audio timer . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
TxD pulse generator . . . . . . . . . . . . . . . . . . . . 13
Stereo interrupt detector . . . . . . . . . . . . . . . . . 14
RxD pulse converter . . . . . . . . . . . . . . . . . . . . 14
Autoconnect . . . . . . . . . . . . . . . . . . . . . . . . . . 14
USB transceiver . . . . . . . . . . . . . . . . . . . . . . . 14
Differential driver. . . . . . . . . . . . . . . . . . . . . . . 14
Differential receiver . . . . . . . . . . . . . . . . . . . . . 15
Power-On Reset (POR) . . . . . . . . . . . . . . . . . 16
I2C-bus device address and external charge
pump control . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Modes of operation . . . . . . . . . . . . . . . . . . . . . 18
Power modes . . . . . . . . . . . . . . . . . . . . . . . . . 18
Normal mode . . . . . . . . . . . . . . . . . . . . . . . . . 18
Disable mode . . . . . . . . . . . . . . . . . . . . . . . . . 18
Isolate mode . . . . . . . . . . . . . . . . . . . . . . . . . . 18
USB modes. . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Transparent modes . . . . . . . . . . . . . . . . . . . . . 20
Transparent UART mode . . . . . . . . . . . . . . . . 20
Transparent audio mode . . . . . . . . . . . . . . . . . 20
Transparent general-purpose buffer mode . . . 20
Data-during-audio mode . . . . . . . . . . . . . . . . . 20
Serial controller . . . . . . . . . . . . . . . . . . . . . . . . 22
Register map . . . . . . . . . . . . . . . . . . . . . . . . . 22
Device identification registers . . . . . . . . . . . . . 22
9.1.1.1
Vendor ID register . . . . . . . . . . . . . . . . . . . . .
9.1.1.2
Product ID register . . . . . . . . . . . . . . . . . . . . .
9.1.1.3
Version ID register . . . . . . . . . . . . . . . . . . . . .
9.1.2
Control registers. . . . . . . . . . . . . . . . . . . . . . .
9.1.2.1
Mode Control 1 register . . . . . . . . . . . . . . . . .
9.1.2.2
Mode Control 2 register . . . . . . . . . . . . . . . . .
9.1.2.3
Audio Control register. . . . . . . . . . . . . . . . . . .
9.1.2.4
OTG Control register . . . . . . . . . . . . . . . . . . .
9.1.2.5
Misc Control register . . . . . . . . . . . . . . . . . . .
9.1.2.6
Carkit Control register . . . . . . . . . . . . . . . . . .
9.1.2.7
Transmit Positive Width register . . . . . . . . . . .
9.1.2.8
Transmit Negative Width register . . . . . . . . . .
9.1.2.9
Receive Polarity Recovery register . . . . . . . .
9.1.2.10 Carkit Interrupt Delay register . . . . . . . . . . . .
9.1.2.11 OTG Status register . . . . . . . . . . . . . . . . . . . .
9.1.3
Interrupt registers . . . . . . . . . . . . . . . . . . . . . .
9.1.3.1
Interrupt Source register . . . . . . . . . . . . . . . .
9.1.3.2
Interrupt Latch register . . . . . . . . . . . . . . . . . .
9.1.3.3
Interrupt Enable Low register . . . . . . . . . . . . .
9.1.3.4
Interrupt Enable High register . . . . . . . . . . . .
9.2
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3
I2C-bus protocol . . . . . . . . . . . . . . . . . . . . . . .
9.3.1
I2C-bus byte transfer format . . . . . . . . . . . . . .
9.3.2
I2C-bus device address . . . . . . . . . . . . . . . . .
9.3.3
Write format . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3.3.1
One-byte write . . . . . . . . . . . . . . . . . . . . . . . .
9.3.3.2
Multiple-byte write . . . . . . . . . . . . . . . . . . . . .
9.3.4
Read format . . . . . . . . . . . . . . . . . . . . . . . . . .
9.3.4.1
Current address read . . . . . . . . . . . . . . . . . . .
9.3.4.2
Random address read: single read . . . . . . . .
9.3.4.3
Random address read: multiple read . . . . . . .
10
Clock wake-up scheme . . . . . . . . . . . . . . . . . .
10.1
Power-down event . . . . . . . . . . . . . . . . . . . . .
10.2
Clock wake-up event . . . . . . . . . . . . . . . . . . .
11
Limiting values . . . . . . . . . . . . . . . . . . . . . . . .
12
Recommended operating conditions . . . . . .
13
Static characteristics . . . . . . . . . . . . . . . . . . .
14
Dynamic characteristics . . . . . . . . . . . . . . . . .
14.1
Test configurations . . . . . . . . . . . . . . . . . . . . .
14.2
Audio crosstalk test conditions . . . . . . . . . . . .
14.2.1
Test 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.2
Test 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.2.3
Test 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14.3
Data to audio isolation test conditions . . . . . .
14.4
I2C-bus characteristics . . . . . . . . . . . . . . . . . .
15
Application information . . . . . . . . . . . . . . . . .
16
Package outline . . . . . . . . . . . . . . . . . . . . . . . .
22
23
23
23
23
24
25
25
26
27
28
28
28
28
28
29
29
31
31
32
33
33
33
33
34
34
34
35
35
36
36
37
37
38
39
39
40
44
48
49
49
49
49
49
50
51
52
continued >>
ISP1302_1
Product data sheet
© NXP B.V. 2007. All rights reserved.
Rev. 01 — 24 May 2007
62 of 63
ISP1302
NXP Semiconductors
USB OTG transceiver with carkit support
17
17.1
17.2
17.3
17.4
18
19
20
21
22
22.1
22.2
22.3
22.4
23
24
25
26
Soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Introduction to soldering . . . . . . . . . . . . . . . . .
Wave and reflow soldering . . . . . . . . . . . . . . .
Wave soldering . . . . . . . . . . . . . . . . . . . . . . . .
Reflow soldering . . . . . . . . . . . . . . . . . . . . . . .
Additional soldering information . . . . . . . . . .
Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . .
References . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Revision history . . . . . . . . . . . . . . . . . . . . . . . .
Legal information. . . . . . . . . . . . . . . . . . . . . . .
Data sheet status . . . . . . . . . . . . . . . . . . . . . .
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . .
Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contact information. . . . . . . . . . . . . . . . . . . . .
Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
54
54
54
54
55
56
56
57
57
58
58
58
58
58
58
59
61
62
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
© NXP B.V. 2007.
All rights reserved.
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: [email protected]
Date of release: 24 May 2007
Document identifier: ISP1302_1
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