LMH6703 1.2 GHz, Low Distortion Op Amp with Shutdown General Description Features The LMH™6703 is a very wideband, DC coupled monolithic operational amplifier designed specifically for ultra high resolution video systems as well as wide dynamic range systems requiring exceptional signal fidelity. Benefiting from National’s current feedback architecture, the LMH6703 offers a practical gain range of ± 1 to ± 10 while providing stable operation without external compensation, even at unity gain. At a gain of +2 the LMH6703 supports ultra high resolution video systems with a 750 MHz 2 VPP −3 dB Bandwidth. With 12-bit distortion levels through 10 MHz (RL = 100Ω), and a input referred noise, the LMH6703 is the ideal 2.3nV/ driver or buffer for high speed flash A/D and D/A converters. Wide dynamic range systems such as radar and communication receivers requiring a wideband amplifier offering exceptional signal purity will find the LMH6703’s low input referred noise and low harmonic distortion an attractive solution. n n n n n n n −3 dB bandwidth (VOUT = 0.5 VPP, AV = +2) 1.2 GHz 2nd/3rd harmonics (20 MHz, SOT23-6) −69/−90 dBc Low noise 2.3nV/ Fast slew rate 4500 V/µs Supply current 11 mA Output current 90 mA Low differential gain and phase 0.01%/0.02˚ Applications n n n n n n n n RGB video driver High resolution projectors Flash A/D driver D/A transimpedance buffer Wide dynamic range IF amp Radar/communication receivers DDS post-amps Line driver Connection Diagrams 8-pin SOIC 6-pin SOT23 20110601 Top View 20110602 Top View Ordering Information Package 8-Pin SOIC 6-Pin SOT23 Part Number Package Marking LMH6703MA LMH6703MA LMH6703MAX LMH6703MF AR1A LMH6703MFX Transport Media 95 Units/Rail 2.5k Units Tape and Reel 1k Units Tape and Reel 3k Units Tape and Reel NSC Drawing M08A MF06A LMH™ is a trademark of National Semiconductor Corporation. © 2005 National Semiconductor Corporation DS201106 www.national.com LMH6703 1.2 GHz, Low Distortion Op Amp with Shutdown May 2005 LMH6703 Absolute Maximum Ratings (Note 1) Soldering Information If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. ESD Tolerance (Note 5) Human Body Model IOUT (Note 3) V− to V+ Maximum Junction Temperature Storage Temperature Range −40˚C to +85˚C ± 4V to ± 6V Supply Voltage Range ± 6.75V Common Mode Input Voltage 260˚C Operating Temperature Range 200V VS 235˚C Wave Soldering (10 sec.) Operating Ratings (Note 1) 2000V Machine Model Infrared or Convection (20 sec.) Package Thermal Resistance (θJA) (Note 4) +150˚C 6-Pin SOT23 208˚C/W 8-Pin SOIC 160˚C/W −65˚C to +150˚C Electrical Characteristics (Note 2) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, AV = +2, VS = ± 5V, RL = 100Ω, RF = 560Ω, SD = Floating. Boldface limits apply at the temperature extremes. Symbol Parameter Conditions Min (Note 8) Typ (Note 7) Max (Note 8) Units Frequency Domain Performance SSBW -3 dB Bandwidth LSBW GF 0.1 dB Gain Flatness VOUT = 0.5 VPP, AV = +1 1800 VOUT = 0.5 VPP, AV = +2 1200 VOUT = 2 VPP 750 VOUT = 4 VPP 500 VOUT = 0.5 VPP 150 VOUT = 2 VPP 150 MHz MHz DG Differential Gain RL = 150Ω, 4.43 MHz 0.01 % DP Differential Phase RL = 150Ω, 4.43 MHz 0.02 deg 2V Step, 10% to 90% 0.5 ns 6V Step, 10% to 90% 1.05 ns 2V Step, 10% to 90% 0.5 ns 6V Step, 10% to 90% 1.05 ns 4V Step, 10% to 90% (Note 6) 4200 V/µs 6V Step, 10% to 90% (Note 6) 4500 V/µs 2V Step, VOUT within 0.1% 10 ns 2 VPP, 5 MHz, SOT23-6 −87 2 VPP, 20 MHz, SOT23-6 −69 2 VPP, 50 MHz, SOT23-6 −60 2 VPP, 5 MHz, SOT23-6 −100 2 VPP, 20 MHz, SOT23-6 −90 2 VPP, 50 MHz, SOT23-6 −70 50 MHz, PO = 5 dBm/ tone −80 Time Domain Response tr tf SR ts Rise Time Fall Time Slew Rate Settling Time Distortion And Noise Response HD2 HD3 2nd Harmonic Distortion 3rd Harmonic Distortion dBc dBc IMD 3rd Order Intermodulation Products en Input Referred Voltage Noise > 1 MHz 2.3 nV/ in Input Referred Noise Current Inverting Pin > 1 MHz 18.5 pA/ Input Referred Noise Current Non-Inverting Pin > 1 MHz 3 pA/ dBc Static, DC Performance VOS ± 1.5 Input Offset Voltage www.national.com 2 ±7 ±9 mV LMH6703 Electrical Characteristics (Note 2) (Continued) Unless otherwise specified, all limits guaranteed for TJ = 25˚C, AV = +2, VS = ± 5V, RL = 100Ω, RF = 560Ω, SD = Floating. Boldface limits apply at the temperature extremes. Symbol TCVOS Parameter Conditions Min (Note 8) Typ (Note 7) Input Offset Voltage Average Drift (Note 10) 22 Input Bias Current Non-Inverting (Note 9) −7 Inverting (Note 9) −2 Non-Inverting (Note 10) +30 Inverting (Note 10) −70 IB TCIB Input Bias Current Average Drift VO Output Voltage Range RL = ∞ RL = 100Ω ± 3.3 ± 3.2 ± 3.14 ± 3.45 ± 3.4 Max (Note 8) Units µV/˚C ± 20 ± 23 ± 35 ± 44 µA nA/˚C V PSRR Power Supply Rejection Ratio VS = ± 4.0V to ± 6.0V 48 46 52 CMRR Common Mode Rejection Ratio VCM = −1.0V to +1.0V 45 44 47 IS Supply Current (Enabled) SD = 2V, RL = ∞ 11 12.5 15.0 mA Supply Current (Disabled) SD = 0.8V, RL = ∞ 0.2 0.900 0.935 mA 1 MΩ Output Impedance of Input Buffer 30 Ω 0.8 pF 0.05 Ω dB dB Miscellaneous Performance RIN+ Non-Inverting Input Resistance RIN− Inverting Input Resistance CIN Non-Inverting Input Capacitance RO Output Resistance Closed Loop CMVR Input Common Mode Voltage Range CMRR ≥ 40 dB ± 1.9 IO Linear Output Current VIN = 0V, VOUT ≤ ± 80 mV ± 55 V ± 90 mA Enable/Disable Performance (Disabled Low) TON Enable Time 10 ns TOFF Disable Time 10 ns 50 mVPP Output Glitch VIH Enable Voltage SD ≥ VIH VIL Disable Voltage SD ≤ VIL IIH Disable Pin Bias Current, High SD = V+ (Note 9) IIL Disable Pin Bias Current, Low SD = 0V (Note 9) IOZ Disabled Output Leakage Current VOUT = ± 1.8V 2.0 −50 V 0.8 V −7 ± 70 µA −240 −400 µA 0.07 ± 25 ± 40 µA Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications, see the Electrical Characteristics tables. Note 2: Electrical Table values apply only for factory testing conditions at the temperature indicated. Factory testing conditions result in very limited self-heating of the device such that TJ = TA. No guarantee of parametric performance is indicated in the electrical tables under conditions of internal self-heating where TJ > TA. Note 3: The maximum output current (IOUT) is determined by device power dissipation limitations. Note 4: The maximum power dissipation is a function of TJ(MAX), θJA and TA. The maximum allowable power dissipation at any ambient temperature is PD = (TJ(MAX) — TA)/ θJA. All numbers apply for package soldered directly into a 2 layer PC board with zero air flow. Note 5: Human body model: 1.5 kΩ in series with 100 pF. Machine model: 0Ω in series with 200 pF. Note 6: Slew Rate is the average of the rising and falling edges. Note 7: Typical numbers are the most likely parametric norm. Note 8: Limits are 100% production tested at 25˚C. Limits over the operating temperature range are guaranteed through correlation using Statistical Quality Control (SQC) methods. Note 9: Negative input current implies current flowing out of the device. Note 10: Drift determined by dividing the change in parameter at temperature extremes by the total temperature change. 3 www.national.com LMH6703 Typical Performance Characteristics (AV = +2, RL = 100Ω, VS = ± 5V, RF = 560Ω, TA = +25˚C, SOT23-6; unless otherwise specified). Small Signal Non-Inverting Frequency Response (SOT23) Large Signal Frequency Response (SOT23) 20110618 20110620 Large Signal Frequency Response (SOT23) Small Signal Inverting Frequency Response (SOT23) 20110621 20110619 Small Signal Non-Inverting Frequency Response (SOIC) Large Signal Frequency Response (SOIC) 20110615 www.national.com 20110616 4 Large Signal Frequency Response (SOIC) Small Signal Pulse Response 20110622 20110617 Large Signal Pulse Response Harmonic Distortion vs. Frequency 20110623 20110624 Harmonic Distortion vs. Output Voltage Harmonic Distortion vs. Load 20110627 20110625 5 www.national.com LMH6703 Typical Performance Characteristics (AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25˚C, SOT23-6; unless otherwise specified). (Continued) LMH6703 Typical Performance Characteristics (AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25˚C, SOT23-6; unless otherwise specified). (Continued) 2-Tone 3rd Order Intermodulation Differential Gain 20110626 20110613 Differential Phase Noise 20110632 20110614 CMRR vs. Frequency PSRR vs. Frequency 20110629 20110628 www.national.com 6 Disable Timing Disable Output Glitch 20110631 20110630 RISO vs. CLOAD (See Applications Section) Non-Inverting Input Bias vs. Temperature 20110638 20110608 Inverting Input Bias vs. Temperature Input Offset vs. Temperature 20110609 20110610 7 www.national.com LMH6703 Typical Performance Characteristics (AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25˚C, SOT23-6; unless otherwise specified). (Continued) LMH6703 Typical Performance Characteristics (AV = +2, RL = 100Ω, VS = ±5V, RF = 560Ω, TA = +25˚C, SOT23-6; unless otherwise specified). (Continued) Supply Current vs. Temperature Voltage Swing vs. Temperature 20110611 www.national.com 20110612 8 An Evaluation Board is shipped upon request when a sample order is placed with National Semiconductor. FEEDBACK RESISTOR SELECTION One of the key benefits of a current feedback operational amplifier is the ability to maintain optimum frequency response independent of gain by using appropriate values for the feedback resistor (RF). The Electrical Characteristics and Typical Performance plots specify an RF of 560Ω (390Ω for the SOIC package), a gain of +2 V/V and ± 5V power supplies (unless otherwise specified). Generally, lowering RF from it’s recommended value will peak the frequency response and extend the bandwidth while increasing the value of RF will cause the frequency response to roll off faster. Reducing the value of RF too far below it’s recommended value will cause overshoot, ringing and, eventually, oscillation. 20110603 FIGURE 1. Recommended Non-Inverting Gain Circuit (SOIC Pinout Shown) 20110639 FIGURE 3. Recommended RF vs. Gain 20110604 Since a current feedback amplifier is dependant on the value of RF to provide frequency compensation and since the value of RF can be used to optimize the frequency response, different packages use different RF values. As shown in Figure 3, Recommended RF vs. Gain, the SOT23-6 and the SOIC package use different values for the feedback resistor, RF. Since each application is slightly different, it is worth some experimentation to find the optimal RF for a given circuit. In general, a value of RF that produces ≈0.1 dB of peaking is the best compromise between stability and maximum bandwidth. Note that it is not possible to use a current feedback amplifier with the output shorted directly to the inverting input. The buffer configuration of the LMH6703 requires a 560Ω (390Ω for SOIC package) feedback resistor for stable operation. The LMH6703 was optimized for high speed operation. As shown in Figure 3, the suggested value for RF decreases for higher gains. Due to the output impedance of the input buffer, there is a practical limit for how small RF can go, based on the lowest practical value of RG. This limitation applies to both inverting and non inverting configurations. For the LMH6703 the input resistance of the inverting input is approximately 30Ω and 20Ω is a practical (but not hard and fast) lower limit for RG. The LMH6703 begins to operate in a gain bandwidth limited fashion in the region when RG is nearly equal to the input buffer impedance. Note that the FIGURE 2. Recommended Inverting Gain Circuit (SOIC Pinout Shown) GENERAL DESCRIPTION The LMH6703 is a high speed current feedback amplifier, optimized for excellent bandwidth, gain flatness, and low distortion. The loop gain for a current feedback op amp, and hence the frequency response, is predominantly set by the feedback resistor value. The LMH6703 in the SOT23-6 package is optimized for use with a 560Ω feedback resistor. The LMH6703 in the SOIC package is optimized for use with a 390Ω feedback resistor. Using lower values can lead to excessive ringing in the pulse response while a higher value will limit the bandwidth. Application Note OA-13 discusses this in detail along with the occasions where a different RF might be advantageous. EVALUATION BOARDS Device Package Evaluation Board Part Number LMH6703MF SOT23-6 CLC730216 LMH6703MA SOIC CLC730227 9 www.national.com LMH6703 Application Section LMH6703 Application Section DC ACCURACY AND NOISE (Continued) Example below shows the output offset computation equation for the non-inverting configuration (see Figure 1) using the typical bias current and offset specifications for AV = + 2: amplifier will operate with RG values well below 20Ω, however results may be substantially different than predicted from ideal models. In particular the voltage potential between the Inverting and Non-Inverting inputs cannot be expected to remain small. Inverting gain applications that require impedance matched inputs may limit gain flexibility somewhat (especially if maximum bandwidth is required). The impedance seen by the source is RG || RT (RT is optional). The value of RG is RF /Gain. Thus for a SOT23 in a gain of — 5V/V, an RF of 460Ω is optimum and RG is 92Ω. Without a termination resistor, RT, the input impedance would equal RG, 92Ω. Using an RT of 109Ω will set the input resistance to match a 50Ω source. Note that source impedances greater then RG cannot be matched in the inverting configuration. Output Offset : VO = (IBN · RIN ± VOS) (1 + RF/RG) ± IBI · RF Where RIN is the equivalent input impedance on the noninverting input. Example computation for AV = +2, RF = 560Ω, RIN = 25Ω: VO = (7 µA · 25Ω ± 1.5 mV) (1 + 560/560) ± 2µA · 560≈ −3.7 mV to 4.5 mV A good design, however, should include a worst case calculation using Min/Max numbers in the data sheet tables, in order to ensure "worst case" operation. Further improvement in the output offset voltage and drift is possible using the composite amplifiers described in Application Note OA-7. The two input bias currents are physically unrelated in both magnitude and polarity for the current feedback topology. It is not possible, therefore, to cancel their effects by matching the source impedance for the two inputs (as is commonly done for matched input bias current devices). For more information see Application Note OA-13 which describes the relationship between RF and closed-loop frequency response for current feedback operational amplifiers. The value for the inverting input impedance for the LMH6703 is approximately 30Ω. The LMH6703 is designed for optimum performance at gains of +1 to +10 V/V and −1 to −9 V/V. Higher gain configurations are still useful, however, the bandwidth will fall as gain is increased, much like a typical voltage feedback amplifier. The LMH6703 data sheet shows both SOT23-6 and SOIC data in the Electrical Characteristic section to aid in selecting the right package. The Typical Performance Characteristics section shows SOT23-6 package plots only. The total output noise is computed in a similar fashion to the output offset voltage. Using the input noise voltage and the two input noise currents, the output noise is developed through the same gain equations for each term but combined as the square root of the sum of squared contributing elements. See Application Note OA-12 for a full discussion of noise calculations for current feedback amplifiers. PRINTED CIRCUIT LAYOUT CAPACITIVE LOAD DRIVE Whenever questions about layout arise, use the evaluation board as a guide. The CLC730216 is the evaluation board supplied with SOT23-6 samples of the LMH6703 and the CLC730227 is the evaluation board supplied with SOIC samples of the LMH6703. To reduce parasitic capacitances, ground and power planes should be removed near the input and output pins. Components in the feedback path should be placed as close to the device as possible to minimize parasitic capacitance. For long signal paths controlled impedance lines should be used, along with impedance matching elements at both ends. Bypass capacitors should be placed as close to the device as possible. Bypass capacitors from each voltage rail to ground are applied in pairs. The larger electrolytic bypass capacitors can be located further from the device, the smaller ceramic bypass capacitors should be placed as close to the device as possible. In Figure 1 and Figure 2 CSS is optional, but is recommended for best second order harmonic distortion. 20110635 FIGURE 4. Decoupling Capacitive Loads Capacitive output loading applications will benefit from the use of a series output resistor RISO. Figure 4 shows the use of a series output resistor, RISO, to stabilize the amplifier output under capacitive loading. Capacitive loads from 5 to 120 pF are the most critical, causing ringing, frequency response peaking and possible oscillation. The chart “Suggested RISO vs. Cap Load” gives a recommended value for selecting a series output resistor for mitigating capacitive loads. The values suggested in the charts are selected for 0.5 dB or less of peaking in the frequency response. This produces a good compromise between settling time and bandwidth. For applications where maximum frequency response is needed and some peaking is tolerable, the value of RISO can be reduced slightly from the recommended values. www.national.com 10 For ± 5V supplies only the LMH6703 has a TTL logic compatible disable function. Apply a logic low ( < .8V) to the SD pin and the LMH6703 is disabled. Apply a logic high ( > 2.0V), or let the pin float and the LMH6703 is enabled. Voltage, not current, at the Shutdown pin (SD) determines the enable/ disable state. Care must be exercised to prevent the shutdown pin voltage from going more than 0.8V below the midpoint of the supply voltages (0V with split supplies, V+/2 with single supply biasing). Doing so could cause transistor Q1 to Zener resulting in damage to the disable circuit (See Figure 6). The core amplifier is unaffected by this, but the shutdown operation could become permanently slower as a result. (Continued) VIDEO PERFORMANCE Disabled, the LMH6703 inputs and output become high impedances. While disabled the LMH6703 quiescent current is approximately 200 µA. Because of the pull up resistor on the shutdown circuit, the ICC and IEE currents (positive and negative supply currents respectively) are not balanced in the disabled state. The positive supply current (ICC) is approximately 300 µA while the negative supply current (IEE) is only 200 µA. The remaining IEE current of 100 µA flows through the shutdown pin. The disable function can be used to create analog switches or multiplexers. Implement a single analog switch with one LMH6703 positioned between an input and output. Create an analog multiplexer with several LMH6703’s and tie the outputs together. 20110633 FIGURE 5. Typical Video Application The LMH6703 has been designed to provide excellent performance with production quality video signals in a wide variety of formats such as HDTV and High Resolution VGA. NTSC and PAL performance is nearly flawless with DG of 0.01% and DP of 0.02˚. Best performance will be obtained with back terminated loads. The back termination reduces reflections from the transmission line and effectively masks transmission line and other parasitic capacitance from the amplifier output stage. Figure 5 shows a typical configuration for driving 75Ω cable. The amplifier is configured for a gain of two compensating for the 6 dB loss due to ROUT. ENABLE/DISABLE 20110637 FIGURE 6. SD Pin Simplified Schematic (SOT23 Pinout Shown) 11 www.national.com LMH6703 Application Section LMH6703 Physical Dimensions inches (millimeters) unless otherwise noted 8-Pin SOIC NS Package Number M08A 6-Pin SOT23 NS Package Number M06A www.national.com 12 LMH6703 1.2 GHz, Low Distortion Op Amp with Shutdown Notes National does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and National reserves the right at any time without notice to change said circuitry and specifications. For the most current product information visit us at www.national.com. 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