Diodes DMP21D5UFD P-channel enhancement mode mosfet Datasheet

NOT RECOMMENDED FOR NEW DESIGN
USE DMP21D6UFD
DMP21D5UFD
P-CHANNEL ENHANCEMENT MODE MOSFET
Product Summary
BVDSS
Features
-600mA
ADVANCE INFORMATION
1.0 @ VGS = -4.5V
1.5 @ VGS = -2.5V
-20V
2.0 @ VGS = -1.8V








ID
TA = +25°C
Package
RDS(ON) MAX
-500mA
X1-DFN1212-3
-400mA
-250mA
3.0 @ VGS = -1.5V
Description
This new generation MOSFET is designed to minimize the on-state
resistance (RDS(ON)) and yet maintain superior switching performance,
making it ideal for high efficiency power management applications.


Mechanical Data




Applications
DC-DC Converters
Power Management Functions
Low On-Resistance
Very Low Gate Threshold Voltage VGS(TH), 1.0V Max
Low Input Capacitance
Fast Switching Speed
ESD Protected Gate
Totally Lead-Free & Fully RoHS Compliant (Notes 1 & 2)
Halogen and Antimony Free. “Green” Device (Note 3)
Qualified to AEC-Q101 Standards for High Reliability


Case: X1-DFN1212-3
Case Material: Molded Plastic. UL Flammability Classification
Rating 94V-0
Moisture Sensitivity: Level 1 per J-STD-020
Terminals: NiPdAu over Copper Leadframe. Solderable per MILSTD-202, Method 208 e4
Terminal Connections: See Diagram
Weight: 0.005 grams (Approximate)
Drain
Gate
Gate
Protection
Diode
Top View
ESD PROTECTED
Bottom View
Source
Equivalent Circuit
Pin-Out Top View
Ordering Information (Note 4)
Part Number
DMP21D5UFD-7
Notes:
Case
X1-DFN1212-3
Packaging
3000/Tape & Reel
1. No purposely added lead. Fully EU Directive 2002/95/EC (RoHS) & 2011/65/EU (RoHS 2) compliant.
2. See http://www.diodes.com/quality/lead_free.html for more information about Diodes Incorporated’s definitions of Halogen- and Antimony-free, "Green"
and Lead-free.
3. Halogen- and Antimony-free "Green” products are defined as those which contain <900ppm bromine, <900ppm chlorine (<1500ppm total Br + Cl) and
<1000ppm antimony compounds.
4. For packaging details, go to our website at https://www.diodes.com/design/support/packaging/diodes-packaging/.
Marking Information
KP2 = Product Type Marking Code
YM = Date Code Marking
Y = Year (ex: E = 2017)
M = Month (ex: 9 = September)
KP2
YM
Date Code Key
Year
Code
Month
Code
2011
Y
Jan
1
2012
Z
Feb
2
DMP21D5UFD
Document number: DS35931 Rev. 5 - 3
Mar
3
2013
A
Apr
4
May
5
2014
B
Jun
6
1 of 6
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2015
C
Jul
7
Aug
8
2016
D
Sep
9
Oct
O
2017
E
Nov
N
Dec
D
December 2017
© Diodes Incorporated
NOT RECOMMENDED FOR NEW DESIGN
USE DMP21D6UFD
DMP21D5UFD
Maximum Ratings (@TA = +25°C, unless otherwise specified.)
Characteristic
Symbol
VDSS
VGSS
ADVANCE INFORMATION
Drain-Source Voltage
Gate-Source Voltage
Continuous Drain Current (Note 6) VGS = -4.5V
Steady
State
Continuous Drain Current (Note 6) VGS = -1.8V
Steady
State
TA = +25°C
TA = +70°C
TA = +25°C
TA = +70°C
Value
-20
±8
-600
-500
ID
mA
-400
-300
-2
-800
ID
Pulsed Drain Current (10μs Pulse, Duty Cycle = 1%)
Maximum Body Diode Continuous Current
Unit
V
V
IDM
IS
mA
A
mA
Thermal Characteristics
Characteristic
Total Power Dissipation (Note 5)
Thermal Resistance, Junction to Ambient (Note 5)
Total Power Dissipation (Note 6)
Thermal Resistance, Junction to Ambient (Note 6)
Operating and Storage Temperature Range
Electrical Characteristics
Steady State
Steady State
Symbol
PD
RJA
PD
RJA
TJ, TSTG
Value
0.4
280
0.8
140
-55 to +150
(@TA = +25°C, unless otherwise specified.)
Characteristic
OFF CHARACTERISTICS (Note 7)
Drain-Source Breakdown Voltage
Symbol
Min
Typ
Max
Unit
BVDSS
-20
—
V
Zero Gate Voltage Drain Current TJ = +25°C
IDSS
—
—
Gate-Source Leakage
ON CHARACTERISTICS (Note 7)
Gate Threshold Voltage
IGSS
—
—
—
-80
-100
±10.0
VGS(TH)
Static Drain-Source On-Resistance
RDS(ON)
-0.5
—
—
—
—
—
—
—
—
0.7
0.9
1.2
1.5
5
0.7
-0.75
-1.0
1.0
1.5
2.0
3.0
—
—
-1.2
—
—
—
—
—
—
—
—
—
—
—
46.1
7.2
4.9
0.5
0.8
0.1
0.1
8.5
4.3
20.2
19.2
—
—
—
—
—
—
—
—
—
—
—
Forward Transfer Admittance
Diode Forward Voltage
DYNAMIC CHARACTERISTICS (Note 8)
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge VGS = -4.5V
Total Gate Charge VGS = -8V
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Turn-On Rise Time
Turn-Off Delay Time
Turn-Off Fall Time
Notes:
Unit
W
°C/W
W
°C/W
°C
|Yfs|
VSD
Ciss
Coss
Crss
Qg
Qg
Qgs
Qgd
tD(ON)
tR
tD(OFF)
tF
nA
µA
V

s
V
Test Condition
VGS = 0V, ID = -1mA
VDS = -4.5V, VGS = 0V
VDS = -20V, VGS = 0V
VGS = ±8V, VDS = 0V
VDS = VGS, ID = -250μA
VGS = -4.5V, ID = -100mA
VGS = -2.5V, ID = -80mA
VGS = -1.8V, ID = -40mA
VGS = -1.5V, ID = -30mA
VGS = -1.2V, ID = -1mA
VDS = -3V, ID = -100mA
VGS = 0V, IS = -330mA
pF
VDS = -10V, VGS = 0V,
f = 1.0MHz
nC
VDS = -10V, ID = -250mA
ns
VDD = -3V, VGS = -2.5V,
RL = 300Ω, Rg = 25Ω,
ID = -100mA
5. Device mounted on FR-4 substrate PC board, 2oz copper, with minimum recommended pad layout.
6. Device mounted on FR-4 substrate PC board, 2oz copper, with 1inch square copper plate.
7. Short duration pulse test used to minimize self-heating effect.
8. Guaranteed by design. Not subject to product testing.
DMP21D5UFD
Document number: DS35931 Rev. 5 - 3
2 of 6
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December 2017
© Diodes Incorporated
NOT RECOMMENDED FOR NEW DESIGN
USE DMP21D6UFD
1.0
1.0
0.8
0.8
DMP21D5UFD
-ID, DRAIN CURRENT (A)
-ID, DRAIN CURRENT (A)
0.6
0.4
0
1
2
3
4
-VDS, DRAIN -SOURCE VOLTAGE (V)
Fig. 1 Typical Output Characteristics
0.4
0
5
2.0
)

(E
C
N
A
T
S
IS
E
R
-N
O
E
C
R
U
O
S
-N
I
A
R
D
, )N
1.6
1.4
VGS = -1.8V
1.2
1.0
VGS = -2.5V
0.8
0.6
VGS = -4.5V
0.4
0.2
0.4
0.6
0.8
-ID, DRAIN SOURCE CURRENT
Fig. 3 Typical On-Resistance vs.
Drain Current and Gate Voltage
TA = 150°C
1.0
TA = 125°C
0.8
0.6
0.4
1.5
1.3
1.1
0.9
0.7
0.5
-50
-25
0
25
50
75 100 125 150
TJ, JUNCTION TEMPERATURE (C)
Fig. 5 On-Resistance Variation with Temperature
DMP21D5UFD
Document number: DS35931 Rev. 5 - 3
TA = 85°C
TA = 25°C
TA = -55°C
0.2
0
0
1.0
1.7
3.0
1.2
R
0
0.5
1.0
1.5
2.0
2.5
-VGS, GATE SOURCE VOLTAGE(V)
Fig. 2 Typical Transfer Characteristics
1.4
O
(S
D
0.2
0
1.6
RDS(ON), DRAIN-SOURCE ON-RESISTANCE ()
1.8
0
TA = -55 C
0.6
0.2
RDS(ON), DRAIN-SOURCE ON-RESISTANCE ()
RDS(ON),DRAIN-SOURCE ON-RESISTANCE()
0
TA = 85C
TA = 125C
TA = 25 C
0.2
RDS(ON), DRAIN-SOURCE
ON-RESISTANCE (NORMALIZED)
ADVANCE INFORMATION
TA = 150 C
VDS = -5V
0.2
0.4
0.6
0.8
-ID , DRAIN SOURCE CURRENT (A)
Fig. 4 Typical On-Resistance vs.
Drain Current and Temperature
1
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
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0
-50
-25
0
25
50
75 100 125
TJ, JUNCTION TEMPERATURE (C)
Fig. 6 On-Resistance vs.Temperature
150
December 2017
© Diodes Incorporated
NOT RECOMMENDED FOR NEW DESIGN
USE DMP21D6UFD
V
-
1.0
1.2
0.8
-IS, SOURCE CURRENT (A)
-VGS(TH), GATE THRESHOLD VOLTAGE (V)
t(
S
G
1.0
ID = -1mA
0.8
ID = -250µA
0.6
0.4
0.6
TA= 25C
0.4
0.2
0.2
0
0.4
0
-50
-25
0
25
50
75 100 125 150
TJ , JUNCTION TEMPERATURE (°C)
Fig. 7 Gate Threshold Variation vs. Ambient Temperature
Ciss
-IDSS, LEAKAGE CURRENT (nA)
CT, JUNCTION CAPACITANCE (pF)
0.6
0.8
1.0
-VSD, SOURCE-DRAIN VOLTAGE (V)
Fig. 8 Diode Forward Voltage vs. Current
1.2
1,000
100
10
C oss
Crss
TA = 150C
100
TA = 125C
TA = 85C
10
TA = 25C
f = 1MHz
1
0
1
5
10
15
-VDS, DRAIN-SOURCE VOLTAGE (V)
Fig. 9 Typical Junction Capacitance
20
1
0
4
8
12
16
20
-VDS, DRAIN-SOURCE VOLTAGE(V)
Fig. 10 Typical Drain-Source Leakage Current vs. Voltage
8
P
= 100祍
PW
W =100s
RDS(ON)
Limited
-VGS, GATE-SOURCE VOLTAGE (V)
7
DC
-ID, DRAIN CURRENT (A)
ADVANCE INFORMATION
1.4
)V
(
E
G
A
T
L
O
V
D
L
O
H
S
E
R
H
T
E
T
A
G
, )h
DMP21D5UFD
PW = 10s
0.1
PW = 1s
PW = 100ms
PW = 10ms
PW = 1ms
0.01
T J(MAX) = 150C
T A = 25C
Single Pulse
0.001
0.1
1
10
-VDS, DRAIN-SOURCE VOLTAGE (V)
Fig. 11 SOA, Safe Operation Area
DMP21D5UFD
Document number: DS35931 Rev. 5 - 3
100
4 of 6
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6
5
4
3
2
1
0
0
0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0
Qg , TOTAL GATE CHARGE (nC)
Fig. 12 Gate-Charge Characteristics
December 2017
© Diodes Incorporated
NOT RECOMMENDED FOR NEW DESIGN
USE DMP21D6UFD
DMP21D5UFD
Package Outline Dimensions
Please see http://www.diodes.com/package-outlines.html for the latest version.
X1-DFN1212-3
ADVANCE INFORMATION
A
A1
A3
Seating Plane
D
e
b1(2x)
E
X1-DFN1212-3
Dim Min Max Typ
A
0.47 0.53 0.50
A1
0 0.05 0.02
A3
0.13
b
0.27 0.37 0.32
b1
0.17 0.27 0.22
D
1.15 1.25 1.20
E
1.15 1.25 1.20
e
0.80
L
0.25 0.35 0.30
All Dimensions in mm
L(3x)
b
Suggested Pad Layout
Please see http://www.diodes.com/package-outlines.html for the latest version.
X1-DFN1212-3
X
Y
Dimensions
C
X
X1
Y
Y1
Y2
X1
(2x)
Y2
Y1
(2x)
Value (in mm)
0.80
0.42
0.32
0.50
0.50
1.50
C
DMP21D5UFD
Document number: DS35931 Rev. 5 - 3
5 of 6
www.diodes.com
December 2017
© Diodes Incorporated
NOT RECOMMENDED FOR NEW DESIGN
USE DMP21D6UFD
DMP21D5UFD
IMPORTANT NOTICE
ADVANCE INFORMATION
DIODES INCORPORATED MAKES NO WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, WITH REGARDS TO THIS DOCUMENT,
INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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written approval of the Chief Executive Officer of Diodes Incorporated. As used herein:
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Copyright © 2017, Diodes Incorporated
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DMP21D5UFD
Document number: DS35931 Rev. 5 - 3
6 of 6
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December 2017
© Diodes Incorporated
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