Aplus APE6312 Very low cost voice and melody synthesizer with 4-bits cpu Datasheet

A
PLUS MAKE YOUR PRODUCTION A-PLUS
APExx12 Series
DATA SHEET
APLUS
INTEGRATED CIRCUITS INC.
Address:
3 F-10, No. 32, Sec. 1, Chenggung Rd., Taipei,
Taiwan 115, R.O.C.
(115)台北市南港區成功路㆒段 32 號 3 樓之 10.
Sales E-mail:
[email protected]
TEL: 886-2-2782-9266
Technology E-mail:
[email protected]
FAX: 886-2-2782-9255
WEBSITE : http: //www.aplusinc.com.tw
APExx12 Series
1.0 General Description
The APExx12 series are very low cost voice and melody synthesizer with 4-bits CPU. They have various
features including 4-bits ALU, ROM, RAM, I/O ports, timers, clock generator, voice and melody
synthesizer, and PWM (Direct drive) or D/A current outputs, etc. The audio synthesizer contains one
voice-channel and two melody-channels. Furthermore, they consist of 27 instructions in these devices.
With CMOS technology and halt function can minimize power dissipation. Their architectures are similar
to RISC, with two stages of instruction pipeline. They allow all instructions to be executed in a single
cycle, except for program branches and data table read instructions (which need two instruction cycles).
2.0 Features
(1) Single power supply can operate from 2.4V to 5.5V at 4MHz or 8MHz.
(2) Program ROM: 16k x 10 bits
(3) 1 set of 16-bits DPR can access up to 64k x 10 bits melody data memory space, and 1 set of 18-bits
VPR can access up to 256k x 10 bits voice data memory space.
Product
Voice Duration (sec) Voice Pointer (VPR) ROM Size (10-bit)
APE0612
6
14-bits
20k
APE1012
10
15-bits
32k
APE1512
15
16-bits
48k
APE2012
20
16-bits
64k
APE3112
31
17-bits
96k
APE4112
41
17-bits
128k
APE5212
52
18-bits
160k
APE6312
63
18-bits
192k
APE7312
73
18-bits
224k
APE8412
84
18-bits
256k
(4) Data Registers:
a). 128 x 4-bit data RAM (00-7Fh)
b). Unbanked special function registers (SFR) range: 00h-2Fh
(5) I/O Ports:
a). PRA: 4-bits I/O Port A (10h) can be programmed to input/output individually. (Register control)
b). PRB: 4-bits I/O Port B (13h) can be configured to input/output individually. (Mask option)
c). PRD: 4-bits I/O Port D (15h) can be programmed to input/output individually. (Register control)
(6) On-chip clock generator: Resistive Clock Drive (RM)
(7) Timer: 1-set Voice Interrupt (Timer0: a 9-bits auto-reload timer/counter).
(8) Stack: 2-level subroutine nesting.
(9) Built-in 4 Level Volume Control can be programmed.
1
Rev 1.3
2003/8/18
APExx12 Series
(10) Built-in 8 Level DAC current output can be configured. (Mask option)
(11) Built-in IR Carry Output: Port B[1] can be configured as IR pin by 38k / 56kHz. (Mask option)
(12) External Reset: Port B[3] can be configured as reset pin. (Mask opton)
(13) HALT and Release from HALT function to reduce power consumption
(14) Watch Dog Timer (WDT)
(15) Instruction: 1-cycle instruction except for table read and program branches which are 2-cycles
(16) Number of instruction: 27
(17) DAC: 1 channel voice and dual tone melody synthesizer (One 9-bits Cout or 8-bits PWM output).
FIGURE 1 : ROM Map of APExx12 Series
PC[13:0]
14-bit x 2 STACK
16-bit Data Pointer
18-bit Voice Pointer
Reset Vector
00000h
Reserved for Testing
000FEh
000FFh-00400h
00401h
00000h-03FFFh
Program ROM
00000h-0FFFFh
Data ROM for Melody
00000h-5FFFFh
Voice ROM for Voice
2
Rev 1.3
2003/8/18
APExx12 Series
3.0 Pin Description
Pad Name
PWM2/Cout
Pin Attr.
PWM1
Vdd1~2
O
Power
PRA0~3
PRD0~3
I/O
I/O port can be programmed to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
PRB0, PRB2
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
Mask option selected as an IR Carrier Output with 38k / 56kHz
PRB3 / Reset
I/O
I/O port can be configured to input/output individually.
Input type with weak pull-low or fix-input-floating capability.
Buffer Output type.
Mask option selected as an external RESET pin with weak pull-low
capability.
OSC
GND1~3
I
Power
O
PRB1 / IR
Description
PWM2 output, or Current Output of Audio.
PWM1 output.
Power supply during operation.
RM mode Oscillator input
Ground Potential
4.0 DC Characteristics
Symbol
Vdd
Isb
Iop
Parameter
Operating voltage
Supply
current
Standby
Operating
Iih
Input current
(Internal pull low)
Ioh
Output-high current
Vdd
Min.
2.4
3
4.5
3
4.5
3
4.5
3
4.5
3
4.5
3
4.5
Typ.
3
Max.
5.5
1
1
2
7
3
10
-3
-10
7
19
0.8 ~ 4.8
0.9 ~ 6.5
Unit
V
uA
Condition
depending on Freq.
4MHz, RM,
in HALT Mode
mA
4MHz, RM,
IO Floating
uA
Input ports with weak
pull-low
mA
4MHz, RM
(IO ports)
mA
4MHz, RM
(Full scale)
Iol
Output-low current
Cout
DAC output current
(8-level option)
dF/F
Frequency stability
-5
5
%
Fosc(3v- 2.4v)
Fosc (3v)
dF/F
Fosc lot variation
-10
10
%
Vdd=3V, Rosc=180k,
4MHz
3
Rev 1.3
2003/8/18
APExx12 Series
FIGURE 2 : Frequency vs. Rosc (at 3V)
Resistor (Rosc ohms)
110k
200k
300k
430k
Frequency (MHz)
14.84
8.25
5.54
3.92
R o sc vs F re q.
Freq. (MHz)
20
1 4 .8 4
15
10
8 .25
5 .54
5
3 .92
0
0
100
200
300
400
500
R os c (k o h m )
5.0 Application Circuit
4
Rev 1.3
2003/8/18
APExx12 Series
6.0 Bonding Diagram
ROM
1
PWM1
2
Vdd2
Y
Pad Size : 80 um x 80 um
PRD3
20
PRD2
19
PRD1
18
PRD0
17
OSC
16
GND1
15
* The IC substrate must be connected to GND.
3
4
PWM2/Cout
GND3
GND2
PRA0
PRA1
PRA2
5
6
7
8
PRA3
9
PRB0
PRB1
PRB2
PRB3
Vdd1
10
11
12
13
14
(0,0)
X
Pad #
1
Pad Name
PWM1
57
865
2
3
Vdd2
PWM2/ Cout
GND3
58
58
58
670
386
235
GND2
PRA0
65
175
87
87
PRA1
PRA2
285
395
87
87
16
17
18
PRA3
PRB0
505
615
87
87
19
20
4
5
6
7
8
9
10
X
Y
Pad #
11
Pad Name
12
13
14
15
X
Y
PRB1
725
87
PRB2
PRB3
Vdd1
835
945
1055
87
87
87
GND1
OSC
1059
1059
241
351
PRD0
PRD1
1059
1059
461
571
PRD2
PRD3
1059
1059
681
791
Chip Size :
APE0612 : 1230 um x 1530 um,
APE1012 : 1230 um x 1530 um
APE1512 : 1230 um x 1758 um,
APE2012 : 1230 um x 1758 um
APE3112 : 1230 um x 2210 um,
APE4112 : 1230 um x 2210 um
APE5212 : 1230 um x 3116 um,
APE6312 : 1230 um x 3116 um
APE7312 : 1230 um x 3116 um,
APE8412 : 1230 um x 3116 um
5
Rev 1.3
2003/8/18
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