IRFR224, IRFU224, SiHFR224, SiHFU224 Power MOSFET FEATURES PRODUCT SUMMARY VDS (V) • Dynamic dV/dt Rating 250 RDS(on) (Ω) VGS = 10 V Qg (Max.) (nC) 14 Qgs (nC) 2.7 Qgd (nC) 7.8 Configuration RoHS* • Surface Mount (IRFR224/SiHFR224) COMPLIANT • Straight Lead (IRFU224/SiHFU224) • Available in Tape and Reel • Fast Switching Single • Ease of Paralleling D DPAK (TO-252) Available • Repetitive Avalanche Rated 1.1 • Lead (Pb)-free Available IPAK (TO-251) DESCRIPTION Third generation Power MOSFETs form Vishay provide the designer with the best combination of fast switching, ruggedized device design, low on-resistance and cost-effectiveness. The DPAK is designed for surface mounting using vapor phase, infrared, or wave solderig techniques. The straight lead version (IRFU/SiHFU series) is for through-hole mounting applications. Power dissipation levels up to 1.5 W are possible in typical surface mount applications. G S N-Channel MOSFET ORDERING INFORMATION Package Lead (Pb)-free SnPb DPAK (TO-252) DPAK (TO-252) DPAK (TO-252) IPAK (TO-251) IRFR224PbF IRFR224TRPbFa IRFR224TRLPbFa IRFU224PbF SiHFR224-E3 SiHFR224T-E3a SiHFR224TL-E3a SiHFU224-E3 IRFR224 IRFR224TRa IRFR224TRLa IRFU224 SiHFR224 SiHFR224Ta SiHFR224TLa SiHFU224 Note a. See device orientation. ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER SYMBOL LIMIT Drain-Source Voltage VDS 250 Gate-Source Voltage VGS ± 20 Continuous Drain Current Pulsed Drain VGS at 10 V TC = 25 °C TC = 100 °C Currenta ID IDM UNIT V 3.8 2.4 A 15 Linear Derating Factor 0.33 Linear Derating Factor (PCB Mount)e 0.020 W/°C Single Pulse Avalanche Energyb EAS 130 mJ Repetitive Avalanche Currenta IAR 3.8 A EAR 4.2 mJ Repetitive Avalanche Energya Maximum Power Dissipation TC = 25 °C Maximum Power Dissipation (PCB Mount)e TA = 25 °C Peak Diode Recovery dV/dtc PD dV/dt 42 2.5 4.8 W V/ns www.kersemi.com 1 IRFR224, IRFU224, SiHFR224, SiHFU224 ABSOLUTE MAXIMUM RATINGS TC = 25 °C, unless otherwise noted PARAMETER Operating Junction and Storage Temperature Range Soldering Recommendations (Peak Temperature) SYMBOL LIMIT UNIT TJ, Tstg - 55 to + 150 °C 260d for 10 s Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. VDD = 50 V; starting TJ = 25 °C, L = 14 mH, RG = 25 Ω, IAS = 3.8 A (see fig. 12). c. ISD ≤ 3.8 A, dI/dt ≤ 90 A/µs, VDD ≤ VDS, TJ ≤ 150 °C. d. 1.6 mm from case. e. When mounted on 1” square PCB (FR-4 or G-10 material). THERMAL RESISTANCE RATINGS PARAMETER SYMBOL TYP. MAX. Maximum Junction-to-Ambient (PCB Mount)a RthJA - 50 Maximum Junction-to-Ambient RthJA - 110 Maximum Junction-to-Case RthJC - 3.0 UNIT °C/W Note a. When mounted on 1" square PCB ( FR-4 or G-10 material). SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Static Drain-Source Breakdown Voltage VDS Temperature Coefficient VDS VGS = 0 V, ID = 250 µA 250 - - V ΔVDS/TJ Reference to 25 °C, ID = 1 mA - 0.36 - V/°C VGS(th) VDS = VGS, ID = 250 µA 2.0 - 4.0 V Gate-Source Leakage IGSS VGS = ± 20 V - - ± 100 nA Zero Gate Voltage Drain Current IDSS VDS = 250 V, VGS = 0 V - - 25 VDS = 200 V, VGS = 0 V, TJ = 125 °C - - 250 - - 1.1 Ω 1.5 - - S - 260 - - 77 - - 15 - - - 14 Gate-Source Threshold Voltage Drain-Source On-State Resistance Forward Transconductance RDS(on) gfs ID = 2.3 Ab VGS = 10 V VDS = 50 V, ID = 2.3 Ab µA Dynamic Input Capacitance Ciss Output Capacitance Coss VGS = 0 V, VDS = 25 V, f = 1.0 MHz, see fig. 5c Reverse Transfer Capacitance Crss Total Gate Charge Qg Gate-Source Charge Qgs - - 2.7 Gate-Drain Charge Qgd - - 7.8 Turn-On Delay Time td(on) - 7.0 - tr - 13 - - 20 - - 12 - - 4.5 - - 7.5 - Rise Time Turn-Off Delay Time Fall Time td(off) ID = 4.4 A, VDS = 200 V, see fig. 6 and 13b, c VDD = 125 V, ID = 4.4 A, RG = 18 Ω, RD = 28 Ω, see fig. 10b, c tf Internal Drain Inductance LD Internal Source Inductance LS www.kersemi.com 2 VGS = 10 V Between lead, 6 mm (0.25") from package and center of die contact D pF nC ns nH G S IRFR224, IRFU224, SiHFR224, SiHFU224 SPECIFICATIONS TJ = 25 °C, unless otherwise noted PARAMETER SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT - - 3.8 - - 15 - - 1.8 - 200 400 ns - 0.93 1.9 µC Drain-Source Body Diode Characteristics Continuous Source-Drain Diode Current IS Pulsed Diode Forward Currenta ISM Body Diode Voltage VSD Body Diode Reverse Recovery Time trr Body Diode Reverse Recovery Charge Qrr Forward Turn-On Time ton MOSFET symbol showing the integral reverse p - n junction diode D A G S TJ = 25 °C, IS = 3.8 A, VGS = 0 Vb TJ = 25 °C, IF = 4.4 A, dI/dt = 100 A/µsb V Intrinsic turn-on time is negligible (turn-on is dominated by LS and LD) Notes a. Repetitive rating; pulse width limited by maximum junction temperature (see fig. 11). b. Pulse width ≤ 300 µs; duty cycle ≤ 2 %. TYPICAL CHARACTERISTICS 25 °C, unless otherwise noted Fig. 1 - Typical Output Characteristics, TC = 25 °C Fig. 2 - Typical Output Characteristics, TC = 150 °C Fig. 3 - Typical Transfer Characteristics Fig. 4 - Normalized On-Resistance vs. Temperature www.kersemi.com 3 IRFR224, IRFU224, SiHFR224, SiHFU224 Fig. 5 - Typical Capacitance vs. Drain-to-Source Voltage Fig. 6 - Typical Gate Charge vs. Gate-to-Source Voltage Fig. 7 - Typical Source-Drain Diode Forward Voltage Fig. 8 - Maximum Safe Operating Area www.kersemi.com 4 IRFR224, IRFU224, SiHFR224, SiHFU224 RD VDS VGS D.U.T. RG + - VDD 10 V Pulse width ≤ 1 µs Duty factor ≤ 0.1 % Fig. 10a - Switching Time Test Circuit VDS 90 % 10 % VGS td(on) Fig. 9 - Maximum Drain Current vs. Case Temperature td(off) tf tr Fig. 10b - Switching Time Waveforms Fig. 11 - Maximum Effective Transient Thermal Impedance, Junction-to-Case L Vary tp to obtain required IAS VDS VDS tp VDD D.U.T. RG + - I AS V DD VDS 10 V tp 0.01 Ω Fig. 12a - Unclamped Inductive Test Circuit IAS Fig. 12b - Unclamped Inductive Waveforms www.kersemi.com 5 IRFR224, IRFU224, SiHFR224, SiHFU224 Fig. 12c - Maximum Avalanche Energy vs. Drain Current Current regulator Same type as D.U.T. 50 kΩ QG 10 V 12 V 0.2 µF 0.3 µF QGS QGD + D.U.T. VG - VDS VGS 3 mA Charge IG ID Current sampling resistors Fig. 13a - Basic Gate Charge Waveform www.kersemi.com 6 Fig. 13b - Gate Charge Test Circuit IRFR224, IRFU224, SiHFR224, SiHFU224 Peak Diode Recovery dV/dt Test Circuit + D.U.T. Circuit layout considerations • Low stray inductance • Ground plane • Low leakage inductance current transformer + - - RG • • • • dV/dt controlled by RG Driver same type as D.U.T. ISD controlled by duty factor "D" D.U.T. - device under test Driver gate drive P.W. + Period D= + - VDD P.W. Period VGS = 10 V* D.U.T. ISD waveform Reverse recovery current Body diode forward current dI/dt D.U.T. VDS waveform Diode recovery dV/dt Re-applied voltage VDD Body diode forward drop Inductor current Ripple ≤ 5 % ISD * VGS = 5 V for logic level devices Fig. 14 - For N-Channel www.kersemi.com 7