Freescale MC9S08MM128VMB Advanced information Datasheet

Freescale Semiconductor
Data Sheet: Advanced Information
Document Number: MC9S08MM128
Rev. 2, 04/2010
MC9S08MM128 series
Covers: MC9S08MM128, and MC9S08MM64, MC9S08MM32,
and MC9S08MM32A
64-LQFP 10mm x 10mm
8-Bit HCS08 Central Processor Unit (CPU)
–
–
–
Up to 48-MHz CPU above 2.4 V, 40 MHz CPU above 2.1 V, and
20 MHz CPU above 1.8 V across temperature of -40°C to 105°C
HCS08 instruction set with added BGND instruction
Support for up to 32 interrupt/reset sources
On-Chip Memory
–
–
–
128 K Dual Array Flash read/program/erase over full operating
voltage and temperature
12 KB Random-access memory (RAM)
Security circuitry to prevent unauthorized access to RAM and
Flash
–
–
–
Power-Saving Modes
–
–
–
Two ultra-low power stop modes. Peripheral clock enable register
can disable clocks to unused modules to reduce currents
Time of Day (TOD) — Ultra-low power 1/4 sec counter with up to
64s timeout.
Ultra-low power external oscillator that can be used in stop modes
to provide accurate clock source to the TOD. 6 usec typical wake
up time from stop3 mode
Clock Source Options
–
–
–
Oscillator (XOSC1) — Loop-control Pierce oscillator; 32.768 kHz
crystal or ceramic resonator dedicated for TOD operation.
Oscillator (XOSC2) — for high frequency crystal input for MCG
reference to be used for system clock and USB operations.
Multipurpose Clock Generator (MCG) — PLL and FLL; precision
trimming of internal reference allows 0.2% resolution and 2%
deviation over temperature and voltage; supports CPU
frequencies from 4 kHz to 48 MHz.
–
–
–
–
System Protection
–
–
–
–
–
Watchdog computer operating properly (COP) reset Watchdog
computer operating properly (COP) reset with option to run from
dedicated 1-kHz internal clock source or bus clock
Low-voltage detection with reset or interrupt; selectable trip points;
separate low-voltage warning with optional interrupt; selectable
trip points
Illegal opcode and illegal address detection with reset
Flash block protection for each array to prevent accidental
write/erasure
Hardware CRC to support fast cyclic redundancy checks
–
–
–
–
Development Support
–
–
–
Single-wire background debug interface
Real-time debug with 6 hardware breakpoints (4 PC, 1 address
and 1 data) Breakpoint capability to allow single breakpoint setting
during in-circuit debugging
On-chip in-circuit emulator (ICE) debug module containing 3
comparators and 9 trigger modes
Peripherals
–
–
80-LQFP 12mm x 12mm
81-MapBGA 10mm x10mm
byte-by-byte data transfer; supports broadcast mode and 11-bit
addressing
PRACMP — Analog comparator with selectable interrupt;
compare option to programmable internal reference voltage;
operation in stop3
SCI — Two serial communications interfaces with optional 13-bit
break; option to connect Rx input to PRACMP output on SCI1 and
SCI2; High current drive on Tx on SCI1 and SCI2; wake-up from
stop3 on Rx edge
SPI1— Serial peripheral interface (SPI) with 64-bit FIFO buffer;
16-bit or 8-bit data transfers; full-duplex or single-wire
bidirectional; double-buffered transmit and receive; master or
slave mode; MSB-first or LSB-first shifting
SPI2— Serial peripheral interface with full-duplex or single-wire
bidirectional; Double-buffered transmit and receive; Master or
Slave mode; MSB-first or LSB-first shifting
TPM — Two 4-channel Timer/PWM Module; Selectable input
capture, output compare, or buffered edge- or center-aligned
PWM on each channel; external clock input/pulse accumulator
USB — Supports USB in full-speed device configuration. On-chip
transceiver and 3.3V regulator help save system cost, fully
compliant with USB Specification 2.0. Allows control, bulk,
interrupt and isochronous transfers. Not available on
MC9S08MM32A devices.
ADC16 — 16-bit Successive approximation ADC with up to 4
dedicated differential channels and 8 single-ended channels;
range compare function; 1.7 mV/°C temperature sensor; internal
bandgap reference channel; operation in stop3; fully functional
from 3.6V to 1.8V, Configurable hardware trigger for 8 Channel
select and result registers
PDB — Programmable delay block with 16-bit counter and
modulus and prescale to set reference clock to bus divided by 1 to
bus divided by 2048; 8 trigger outputs for ADC16 module provides
periodic coordination of ADC sampling sequence with sequence
completion interrupt; Back-to-Back mode and Timed mode
DAC — 12-bit resolution; 16-word data buffers with configurable
watermark.
OPAMP — Two flexible operational amplifiers configurable for
general operations; Low offset and temperature drift.
TRIAMP — Two trans-impedance amplifiers dedicated for
converting current inputs into voltages.
Input/Output
–
–
–
–
Up to 47 GPIOs and 2 output-only pin and 1 input-only pin.
Voltage Reference output (VREFO).
Dedicated infrared output pin (IRO) with
high current sink capability.
Up to 16 KBI pins with selectable polarity.
Package Options
CMT— Carrier Modulator timer for remote control
communications. Carrier generator, modulator and driver for
dedicated infrared out. Can be used as an output compare timer.
IIC— Up to 100 kbps with maximum bus loading; Multi-master
operation; Programmable slave address; Interrupt driven
–
–
–
81-MBGA (10x10x1.6) mm
80-LQFP (12x12x1.6) mm
64-LQFP (10x10x1.6) mm
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
An Energy-Efficient Solution from Freescale
1 Devices in the MC9S08MM128 series ................ 3
2 Preliminary Electrical Characteristics............. 13
2.1 Parameter Classification .........................................................
2.2 Absolute Maximum Ratings ....................................................
2.3 Thermal Characteristics ..........................................................
2.4 Electrostatic Discharge (ESD) Protection Characteristics ......
2.5 DC Characteristics ..................................................................
2.6 Supply Current Characteristics ...............................................
2.7 Comparator (PRACMP) Electricals.........................................
2.8 12-Bit Digital-to-Analog Converter (DAC12LV) Electricals ......
2.9 ADC Characteristics................................................................
2.10 MCG and External Oscillator (XOSC) Characteristics ..........
2.11 AC Characteristics ................................................................
2.12 SPI Characteristics ...............................................................
2.13 Flash Specifications ..............................................................
2.14 USB Electricals .....................................................................
13
13
14
15
17
19
21
22
23
28
31
32
35
36
2.15 VREF Specifications............................................................. 35
2.16 TRIAMP Electrical Parameters............................................. 45
2.17 OPAMP Electrical Parameters.............................................. 40
3 Ordering Information......................................... 47
3.1 Device Numbering System..................................................... 47
3.2 Package Information............................................................... 47
3.3 Mechanical Drawings ............................................................. 47
4 Revision History ................................................ 48
Related Documentation
Find the most current versions of all documents at: http://www.freescale.com.
Reference Manual
—MC9S08MM128RM
Contains extensive product information including modes of operation, memory,
resets and interrupts, register definition, port pins, CPU, and all module
information.
–
This document contains information on a new product. Specifications and information herein are subject to change without notice.
© Freescale Semiconductor, Inc., 2009-2010. All rights reserved.
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
Contents
Devices in the MC9S08MM128 series
1
Devices in the MC9S08MM128 series
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
The following table summarizes the feature set available in the MC9S08MM128 series of MCUs.
Table 1. MC9S08MM128 series Features by MCU and Package
Feature
MC9S08MM128
Pin quantity
81
64
64
64
131072
65535
32768
32768
RAM size (bytes)
12K
12K
4K
2K
FLASH size (bytes)
80
64
MC9S08MM64 MC9S08MM32 MC9S08MM32A
Programmable Analog Comparator (PRACMP)
yes
yes
yes
yes
Debug Module (DBG)
yes
yes
yes
yes
Multipurpose Clock Generator (MCG)
yes
yes
yes
yes
Inter-Integrated Communication (IIC)
yes
yes
yes
yes
Interrupt Request Pin (IRQ)
yes
Keyboard Interrupt (KBI)
Port I/O
1
yes
yes
yes
16
16
7
7
7
7
47
46
33
33
33
33
12
12
12
Dedicated Analog Input Pins
12
Power and Ground Pins
8
8
8
8
Time Of Day (TOD)
yes
yes
yes
yes
Serial Communications (SCI1)
yes
yes
yes
yes
Serial Communications (SCI2)
yes
yes
yes
yes
Serial Peripheral Interface 1 (SPI1 (FIFO))
yes
yes
yes
yes
Serial Peripheral Interface 2 (SPI2)
yes
yes
yes
yes
Carrier Modulator Timer pin (IRO)
yes
yes
yes
yes
TPM input clock pin (TPMCLK)
yes
yes
yes
yes
TPM1 channels
TPM2 channels
4
4
4
2
4
4
4
2
2
2
XOSC1
yes
yes
yes
yes
XOSC2
yes
yes
yes
yes
USB
yes
yes
yes
no
Programmable Delay Block (PDB)
yes
yes
yes
yes
SAR ADC differential channels2
4
4
3
3
3
3
SAR ADC single-ended channels
8
8
6
6
6
6
DAC ouput pin (DACO)
yes
yes
yes
yes
Voltage reference output pin (VREFO)
yes
yes
yes
yes
General Purpose OPAMP (OPAMP)
yes
yes
yes
yes
Trans-Impedance Amplifier (TRIAMP)
yes
yes
yes
yes
1
2
Port I/O count does not include two (2) output-only and one (1) input-only pins.
Each differential channel is comprised of 2 pin inputs.
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Devices in the MC9S08MM128 series
Table 2. Versions of On-Chip Modules
Module
Analog-to-Digital Converter (ADC16)
1
General Purpose Operational Amplifier (OPAMP)
1
Trans-Impedance Operational Amplifier (TRIAMP)
1
Digital to Analog Converter (DAC)
1
Programmable Delay Block
1
Inter-Integrated Circuit (IIC)
3
Central Processing Unit (CPU)
5
On-Chip In-Circuit Debug/Emulator (DBG)
3
Multi-Purpose Clock Generator (MCG)
3
Low Power Oscillator (XOSCVLP)
1
Carrier Modulator Timer (CMT)
1
Programable Analog Comparator (PRACMP)
2
Serial Communications Interface (SCI)
4
Serial Peripheral Interface (SPI)
5
Time of Day (TOD)
1
1
1
Universal Serial Bus (USB)
1
Version
Timer Pulse-Width Modulator (TPM)
3
System Integration Module (SIM)
1
Cyclic Redundancy Check (CRC)
3
Keyboard Interrupt (KBI)
2
Voltage Reference (VREF)
1
Voltage Regulator (VREG)
1
Interrupt Request (IRQ)
3
Flash Wrapper
1
GPIO
2
Port Control
1
USB Module not available on MC9S08MM32A devices.
The block diagram in Figure 1 shows the structure of the MC9S08MM128 series MCU.
4
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not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
A complete description of the modules included on each device is provided in the following table.
Figure 1. MC9S08MM128 series Block Diagram
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Devices in the MC9S08MM128 series
5
Devices in the MC9S08MM128 series
1.1
Pin Assignments
1.1.1
64-Pin LQFP
PTA0/SS1
IRO
PTA4/INP1+
PTA5
PTA6
PTA7/INP2+
PTB0
PTB1/BLMS
VSSA
VREFL
INP1OUT1TRIOUT1/DADP2
VINP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTD7/RX1
PTD6/TX1
PTD5/SCL/TPM1CH3
PTD4/SDA/TPM1CH2
PTD3/TPM1CH1
PTD2/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2
PTC0/MOSI2
Figure 2. 64-Pin LQFP for MC9S08MM128,
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
OUT2DACO
TRIOUT2/DADP3
VINP2
VINN2/DADM3
DADP0
DADM0
VREFO
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VINN1/DADM2
INP2-
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF2/TX2/TPM2CH0
PTF1/RX2/TPM2CH1
PTE6/RX2
PTE5/TX2
VDD3
VSS3
PTE4/CMPP3/TPMCLK/IRQ
The following two figures show the 64-pin LQFP pinout configuration. The first illustrates the pinout configuration for
MC9S08MM128, MC9S08MM64, and MC9S08MM32 devices.
MC9S08MM64, and MC9S08MM32 devices
For MC9S08MM32A devices, pins 56, 57, 58, and 59 are no connects (NC) as illustrated in the following figure.
6
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Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
This section shows the pin assignments for the MC9S08MM128 series devices.
PTA0/SS1
IRO
PTA4/INP1+
PTA5
PTA6
PTA7/INP2+
PTB0
PTB1/BLMS
VSSA
VREFL
INP1OUT1TRIOUT1/DADP2
VINP1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
64-LQFP
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
PTD7/RX1
PTD6/TX1
PTD5/SCL/TPM1CH3
PTD4/SDA/TPM1CH2
PTD3/TPM1CH1
PTD2/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2
PTC0/MOSI2
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
OUT2DACO
TRIOUT2/DADP3
VINP2
VINN2/DADM3
DADP0
DADM0
VREFO
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
VINN1/DADM2
INP2-
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
NC
NC
NC
NC
PTF2/TX2/TPM2CH0
PTF1/RX2/TPM2CH1
PTE6/RX2
PTE5/TX2
VDD3
VSS3
PTE4/CMPP3/TPMCLK/IRQ
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
Devices in the MC9S08MM128 series
Figure 3. 64-Pin LQFP for MC9S08MM32A devices
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Devices in the MC9S08MM128 series
1.1.2
80-Pin LQFP
INP1OUT1-
80-LQFP
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
PTE4/CMPP3/TPMCLK/IRQ
PTE3/KBI2P6
PTE2/KBI2P5
PTE1/KBI2P4
PTE0/KBI2P3
PTD7/RX1
PTD6/TX1
PTD5/SCL/TPM1CH3
PTD4/SDA/TPM1CH2
PTD3/TPM1CH1
PTD2/TPM1CH0
PTD1/CMPP2/RESET
PTD0/BKGD/MS
PTC7/KBI2P2/CLKOUT/ADP11
PTC6/KBI2P1/PRACMPO/ADP10
PTC5/KBI2P0/CMPP1/ADP9
PTC4/KBI1P7/CMPP0/ADP8
PTC3/KBI1P6/SS2/ADP7
PTC2/KBI1P5/SPSCK2/ADP6
PTC1/MISO2
DADM0
VREFO
DADP1
DADM1
VREFH
VDDA
VSS2
PTB2/EXTAL1
PTB3/XTAL1
VDD2
PTB4/EXTAL2
PTB5/XTAL2
PTB6/KBI1P3
PTB7/KBI1P4
PTC0/MOSI2
DACO
TRIOUT2/DADP3
VINP2
VINN2/DADM3
DADP0
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
TRIOUT1/DADP2
VINP1
VINN1/DADM2
INP2OUT2-
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Figure 4. 80-Pin LQFP
8
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PTA0/SS1
IRO
PTA1/KBI1P0/TX1
PTA2/KBI1P1/RX1/ADP4
PTA3/KBI1P2/ADP5
PTA4/INP1+
PTA5
PTA6
PTA7/INP2+
PTB0
PTB1/BLMS
VSSA
VREFL
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
PTG0/SPSCK1
PTF7/MISO1
PTF6/MOSI1
VDD1
VSS1
VBUS
USB_DP
USB_DM
VUSB33
PTF5/KBI2P7
PTF4/SDA
PTF3/SCL
PTF2/TX2/TPM2CH0
PTF1/RX2/TPM2CH1
PTF0/TPM2CH2
PTE7/TPM2CH3
PTE6/RX2
PTE5/TX2
VDD3
VSS3
The following figure shows the 80-pin LQFP pinout configuration.
Devices in the MC9S08MM128 series
1.1.3
81-Pin MAPBGA
1
2
3
4
5
6
7
8
9
A
IRO
PTG0
PTF6
USB_DP
VBUS
VUSB33
PTF4
PTF3
PTE4
B
PTF7
PTA0
PTG1
USB_DM
PTF5
PTE7
PTF1
PTF0
PTE3
C
PTA4
PTA5
PTA6
PTA1
PTF2
PTE6
PTE5
PTE2
PTE1
D
INP1-
PTA7
PTB0
PTB1
PTA2
PTA3
PTD5
PTD7
PTE0
E
OUT1
VINN1
OUT2
VDD2
VDD3
VDD1
PTD2
PTD3
PTD6
F
VINP1
TRIOUT1
INP2-
VSS2
VSS3
VSS1
PTB7
PTC7
PTD4
G
DADP0
DACO
TRIOUT2
VINN2
VREFO
PTB6
PTC0
PTC1
PTC2
H
DADM0
DADM1
DADP1
VINP2
PTC3
PTC4
PTD0
PTC5
PTC6
J
VSSA
VREFL
VREFH
VDDA
PTB2
PTB3
PTD1
PTB4
PTB5
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
The following figure shows the 81-pin MAPBGA pinout configuration.
Figure 5. 81-Pin MAPBGA
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Devices in the MC9S08MM128 series
1.2
Pin Assignments by Packages
81 MAPBGA
80 LQFP
64 LQFP
Package
Default
Function
B2
1
1
PTA0
SS1
—
—
PTA0/SS1
A1
2
2
IRO
—
—
—
IRO
C4
3
—
PTA1
KBI1P0
TX1
—
PTA1/KBI1P0/TX1
D5
4
—
PTA2
KBI1P1
RX1
ADP4
PTA2/KBI1P1/RX1/ADP4
D6
5
—
PTA3
KBI1P2
ADP5
—
PTA3/KBI1P2/ADP5
C1
6
3
PTA4
INP1+
—
—
PTA4/INP1+
C2
7
4
PTA5
—
—
—
PTA5
C3
8
5
PTA6
—
—
—
PTA6
D2
9
6
PTA7
INP2+
—
—
PTA7/INP2+
D3
10
7
PTB0
—
—
—
PTB0
D4
11
8
PTB1
BLMS
—
—
PTB1/BLMS
J1
12
9
VSSA
—
—
—
VSSA
J2
13
10
VREFL
—
—
—
VREFL
D1
14
11
INP1-
—
—
—
INP1-
E1
15
12
OUT1
—
—
—
OUT1
F2
16
13
TRIOUT1
DADP2
—
—
DADP2/TRIOUT1
F1
17
14
VINP1
—
—
—
VINP1
E2
18
15
VINN1
DADM2
—
—
DADM2/VINN1
F3
19
16
INP2-
—
—
—
INP2-
E3
20
17
OUT2
—
—
—
OUT2
G2
21
18
DACO
—
—
—
DACO
G3
22
19
TRIOUT2
DADP3
—
—
DADP3/TRIOUT2
H4
23
20
VINP2
—
—
—
VINP2
G4
24
21
VINN2
DADM3
—
—
DADM3/VINN2
G1
25
22
DADP0
—
—
—
DADP0
H1
26
23
DADM0
—
—
—
DADM0
G5
27
24
VREFO
—
—
—
VREFO
H3
28
—
DADP1
—
—
—
DADP1
H2
29
—
DADM1
—
—
—
DADM1
ALT1
ALT2
ALT3
Composite Pin Name
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Table 3. Package Pin Assignments
Devices in the MC9S08MM128 series
Table 3. Package Pin Assignments (Continued)
80 LQFP
64 LQFP
Default
Function
J3
30
25
VREFH
—
—
—
VREFH
J4
31
26
VDDA
—
—
—
VDDA
F4
32
27
VSS2
—
—
—
VSS2
J5
33
28
PTB2
EXTAL1
—
—
PTB2/EXTAL1
J6
34
29
PTB3
XTAL1
—
—
PTB3/XTAL1
E4
35
30
VDD2
—
—
—
VDD2
J8
36
31
PTB4
EXTAL2
—
—
PTB4/EXTAL2
J9
37
32
PTB5
XTAL2
—
—
PTB5/XTAL2
G6
38
—
PTB6
KBI1P3
—
—
PTB6/KBI1P3
F7
39
—
PTB7
KBI1P4
—
—
PTB7/KBI1P4
G7
40
33
PTC0
MOSI2
—
—
PTC0/MOSI2
G8
41
34
PTC1
MISO2
—
—
PTC1/MISO2
G9
42
35
PTC2
KBI1P5
SPSCK2
ADP6
PTC2/KBI1P5/SPSCK2/ADP6
H5
43
36
PTC3
KBI1P6
SS2
ADP7
PTC3/KBI1P6/SS2/ADP7
H6
44
37
PTC4
KBI1P7
CMPP0
ADP8
PTC4/KBI1P7/CMPP0/ADP8
H8
45
38
PTC5
KBI2P0
CMPP1
ADP9
PTC5/KBI2P0/CMPP1/ADP9
H9
46
39
PTC6
KBI2P1
PRACMPO
ADP10
PTC6/KBI2P1/PRACMPO/ADP10
F8
47
40
PTC7
KBI2P2
CLKOUT
ADP11
PTC7/KBI2P2/CLKOUT/ADP11
H7
48
41
PTD0
BKGD
MS
—
PTD0/BKGD/MS
J7
49
42
PTD1
CMPP2
RESET
—
PTD1/CMPP2/RESET
E7
50
43
PTD2
TPM1CH0
—
—
PTD2TPM1CH0
E8
51
44
PTD3
TPM1CH1
—
—
PTD3/TPM1CH1
F9
52
45
PTD4
SDA
TPM1CH2
—
PTD4/SDA/TPM1CH2
D7
53
46
PTD5
SCL
TPM1CH3
—
PTD5/SCL/TPM1CH3
E9
54
47
PTD6
TX1
—
—
PTD6/TX1
D8
55
48
PTD7
RX1
—
—
PTD7/RX1
D9
56
—
PTE0
KBI2P3
—
—
PTE0/KBI2P3
C9
57
—
PTE1
KBI2P4
—
—
PTE1/KBI2P4
C8
58
—
PTE2
KBI2P5
—
—
PTE2/KBI2P5
B9
59
—
PTE3
KBI2P6
—
—
PTE3/KBI2P6
A9
60
49
PTE4
CMPP3
TPMCLK
IRQ
PTE4/CMPP3/TPMCLK/IRQ
ALT1
ALT2
ALT3
Composite Pin Name
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81 MAPBGA
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Devices in the MC9S08MM128 series
Table 3. Package Pin Assignments (Continued)
80 LQFP
64 LQFP
Default
Function
F5
61
50
VSS3
—
—
—
VSS3
E5
62
51
VDD3
—
—
—
VDD3
C7
63
52
PTE5
TX2
—
—
PTE5/TX2
C6
64
53
PTE6
RX2
—
—
PTE6/RX2
B6
65
—
PTE7
TPM2CH3
—
—
PTE7/TPM2CH3
B8
66
—
PTF0
TPM2CH2
—
—
PTF0/TPM2CH2
B7
67
54
PTF1
RX2
TPM2CH1
—
PTF1/RX2/TPM2CH1
C5
68
55
PTF2
TX2
TPM2CH0
—
PTF2/TX2/TPM2CH0
A8
69
—
PTF3
SCL
—
—
PTF3/SCL
A7
70
—
PTF4
SDA
—
—
PTF4/SDA
B5
71
—
PTF5
A6
72
56
ALT1
ALT2
ALT3
Composite Pin Name
KBI2P7
—
—
PTF5/KBI2P7
1
—
—
—
VUSB33
2
VUSB33
B4
73
57
USB_DM
—
—
—
USB_DM
A4
74
58
USB_DP3
—
—
—
USB_DP
A5
75
59
VBUS4
—
—
—
VBUS
F6
76
60
VSS1
—
—
—
VSS1
E6
77
61
VDD1
—
—
—
VDD1
A3
78
62
PTF6
MOSI1
—
—
PTF6/MOSI1
B1
79
63
PTF7
MISO1
—
—
PTF7/MISO1
A2
80
64
PTG0
SPSCK1
—
—
PTG0/SPSCK1
B3
—
—
PTG1
—
—
—
PTG1
1
NC on MC9S08MM32A devices.
NC on MC9S08MM32A devices.
3 NC on MC9S08MM32A devices.
4 NC on MC9S08MM32A devices.
2
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81 MAPBGA
Package
Preliminary Electrical Characteristics
Preliminary Electrical Characteristics
This section contains electrical specification tables and reference timing diagrams for the MC9S08MM128/64/32/32A
microcontroller, including detailed information on power considerations, DC/AC electrical characteristics, and AC timing
specifications.
The electrical specifications are preliminary and are from previous designs or design simulations. These specifications may not
be fully tested or guaranteed at this early stage of the product life cycle. These specifications will, however, be met for
production silicon. Finalized specifications will be published after complete characterization and device qualifications have
been completed.
NOTE
The parameters specified in this data sheet supersede any values found in the module
specifications.
2.1
Parameter Classification
The electrical parameters shown in this supplement are guaranteed by various methods. To give the customer a better
understanding, the following classification is used and the parameters are tagged accordingly in the tables where appropriate:
Table 4. Parameter Classifications
P
Those parameters are guaranteed during production testing on each individual device.
C
Those parameters are achieved by the design characterization by measuring a statistically relevant
sample size across process variations.
T
Those parameters are achieved by design characterization on a small sample size from typical devices
under typical conditions unless otherwise noted. All values shown in the typical column are within this
category.
D
Those parameters are derived mainly from simulations.
NOTE
The classification is shown in the column labeled “C” in the parameter tables where
appropriate.
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2
Preliminary Electrical Characteristics
Absolute Maximum Ratings
Absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. Stress beyond the
limits specified in the following table may affect device reliability or cause permanent damage to the device. For functional
operating conditions, refer to the remaining tables in this section.
Table 5. Absolute Maximum Ratings
#
Rating
Symbol
Value
Unit
1
Supply voltage
VDD
–0.3 to +3.8
V
2
Maximum current into VDD
IDD
120
mA
3
Digital input voltage
VIn
–0.3 to VDD + 0.3
V
4
Instantaneous maximum current
Single pin limit (applies to all port pins)1, 2, 3
ID
± 25
mA
5
Storage temperature range
Tstg
–55 to 150
°C
1
Input must be current limited to the value specified. To determine the value of the required
current-limiting resistor, calculate resistance values for positive (VDD) and negative (VSS) clamp
voltages, then use the larger of the two resistance values.
2 All functional non-supply pins are internally clamped to V
SS and VDD.
3 Power supply must maintain regulation within operating V
DD range during instantaneous and operating
maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection
current may flow out of VDD and could result in external power supply going out of regulation. Ensure
external VDD load will shunt current greater than maximum injection current. This will be the greatest
risk when the MCU is not consuming power. Examples are: if no system clock is present, or if the clock
rate is very low (which would reduce overall power consumption).
This device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised
that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this
high-impedance circuit. Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for
instance, either VSS or VDD).
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2.2
Preliminary Electrical Characteristics
Thermal Characteristics
This section provides information about operating temperature range, power dissipation, and package thermal resistance. Power
dissipation on I/O pins is usually small compared to the power dissipation in on-chip logic and it is user-determined rather than
being controlled by the MCU design. In order to take PI/O into account in power calculations, determine the difference between
actual pin voltage and VSS or VDD and multiply by the pin current for each I/O pin. Except in cases of unusually high pin current
(heavy loads), the difference between pin voltage and VSS or VDD will be very small.
Table 6. Thermal Characteristics
#
Symbol
1
TA
2
TJMAX
3
θJA
4
θJA
Rating
Value
°C
Operating temperature range (packaged):
MC9S08MM128
–40 to 105
MC9S08MM64
–40 to 105
MC9S08MM32
–40 to 105
MC9S08MM32A
–40 to 105
Maximum junction temperature
Thermal
Thermal
resistance1,2,3,4
135
°C
°C/W
Single-layer board — 1s
81-pin MBGA
77
80-pin LQFP
55
64-pin LQFP
68
resistance1, 2, 3, 4
Unit
°C/W
Four-layer board — 2s2p
81-pin MBGA
47
80-pin LQFP
40
64-pin LQFP
49
1
Junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting
site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and
board thermal resistance.
2 Junction to Ambient Natural Convection
3 1s — Single layer board, one signal layer
4
2s2p — Four layer board, 2 signal and 2 power layers
The average chip-junction temperature (TJ) in °C can be obtained from:
TJ = TA + (PD × θJA)
Eqn. 1
where:
TA = Ambient temperature, °C
θJA = Package thermal resistance, junction-to-ambient, °C/W
PD = Pint + PI/O
Pint = IDD × VDD, Watts — chip internal power
PI/O = Power dissipation on input and output pins — user determined
For most applications, PI/O << Pint and can be neglected. An approximate relationship between PD and TJ (if PI/O is neglected)
is:
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2.3
Preliminary Electrical Characteristics
PD = K ÷ (TJ + 273°C)
Eqn. 2
K = PD × (TA + 273°C) + θJA × (PD)2
Eqn. 3
where K is a constant pertaining to the particular part. K can be determined from Equation 3 by measuring PD (at equilibrium)
for a known TA. Using this value of K, the values of PD and TJ can be obtained by solving Equation 1 and Equation 2 iteratively
for any value of TA.
2.4
ESD Protection Characteristics
Although damage from static discharge is much less common on these devices than on early CMOS circuits, normal handling
precautions should be used to avoid exposure to static discharge. Qualification tests are performed to ensure that these devices
can withstand exposure to reasonable levels of static without suffering any permanent damage.
All ESD testing is in conformity with CDF-AEC-Q00 Stress Test Qualification for Automotive Grade Integrated Circuits.
(http://www.aecouncil.com/) This device was qualified to AEC-Q100 Rev E.
A device is considered to have failed if, after exposure to ESD pulses, the device no longer meets the device specification
requirements. Complete dc parametric and functional testing is performed per the applicable device specification at room
temperature followed by hot temperature, unless specified otherwise in the device specification.
Table 7. ESD and Latch-up Test Conditions
Model
Human Body
Machine
Latch-up
Description
Symbol
Value
Unit
Series Resistance
R1
1500
Ω
Storage Capacitance
C
100
pF
Number of Pulse per pin
—
3
—
Series Resistance
R1
0
Ω
Storage Capacitance
C
200
pF
Number of Pulse per pin
—
3
—
Minimum input voltage limit
—
–2.5
V
Maximum input voltage limit
—
7.5
V
Table 8. ESD and Latch-Up Protection Characteristics
#
Rating
Symbol
Min
Max
Unit
C
1
Human Body Model (HBM)
VHBM
±2000
—
V
T
2
Machine Model (MM)
VMM
±200
—
V
T
3
Charge Device Model (CDM)
VCDM
±500
—
V
T
4
Latch-up Current at TA = 125°C
ILAT
±100
—
mA
T
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Solving Equation 1 and Equation 2 for K gives:
Preliminary Electrical Characteristics
DC Characteristics
This section includes information about power supply requirements, I/O pin characteristics, and power supply current in various
operating modes.
Table 9. DC Characteristics
Num Symbol
Characteristic
1
VDD
Operating
Voltage
2
VOH
Output high
voltage
Condition
Min
Typ1
Max
Unit
—
1.82
—
3.6
V
VDD –
0.5
—
—
V
VDD –
0.5
—
—
V
1.8V, ILoad = VDD –
–3 mA
0.5
—
—
V
—
—
100
mA
—
—
0.5
V
2.7 V, ILoad
= 10 mA
—
—
0.5
V
1.8 V, ILoad
= 3 mA
—
—
0.5
V
—
—
—
100
mA
all digital 0.70 x
VDD
inputs,
VDD > 2.7 V
—
—
V
all digital 0.85 x
VDD
inputs,
2.7 V > VDD
≥ 1.8 V
—
C
—
All I/O pins, low-drive strength
1.8 V, ILoad
= –600 μA
C
All I/O pins, high-drive strength
2.7 V, ILoad
= –10 mA
3
IOHT
Output high
current
VOL
Output low
voltage
C
Max total IOH for all ports
—
4
P
D
All I/O pins, low-drive strength
1.8 V, ILoad
= 600 μA
C
All I/O pins, high-drive strength
5
IOLT
Output low
current
Max total IOL
for all ports
6
VIH
Input high voltage all digital inputs
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P
C
D
P
—
V
P
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2.5
Preliminary Electrical Characteristics
Table 9. DC Characteristics (Continued)
Num Symbol
8
VIL
10
Typ1
Max
Unit
all digital
inputs,
VDD > 2.7 V
—
—
0.35 x
VDD
V
all digital
inputs,
2.7 > VDD ≥
1.8 V
—
0.30 x
VDD
V
—
0.06 x
VDD
—
—
mV
all input only VIn = VDD or
pins
VSS
(Per pin)
—
—
0.25
(TBD)
μA
Input hysteresis
|IIn|
Input leakage
current
all digital inputs
P
all input/output VIn = VDD or
(per pin)
VSS
—
—
1(TBD)
μA
|IOZ|
Leakage current
for analog output
pins (DACO,
VREFO, and
OUTx, TRIOUTx)
all input/output VIn = VDD or
(per pin)
VSS
—
—
(TBD)
μA
Total Leakage
Current3
13
RPU
Pull-up resistors
—
RPD
Internal
pull-down
resistors4
—
IIC
For all pins
DC injection
current 5, 6, 7
P
P
|IInT|
14
C
P
Hi-Z (off-state)
leakage current
12
15
—
P
|IOZ|
11
C
Input low voltage all digital inputs
Vhys
9
Min
—
—
2
μA
D
17.5
—
52.5
kΩ
P
17.5
—
52.5
kΩ
P
Single pin limit
VSS > VIN >
VDD
–0.2
—
0.2
mA
D
Total MCU limit, includes sum of all stressed pins
16
CIn
17
VRAM
VSS > VIN >
VDD
–5
—
5
mA
Input Capacitance, all pins
—
—
—
8
pF
C
RAM retention voltage
—
—
0.6
1.0
V
C
—
0.9
1.4
1.79
V
C
—
10
—
—
μs
D
18
VPOR
POR re-arm voltage
19
tPOR
POR re-arm time
8
18
D
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7
Condition
Characteristic
Preliminary Electrical Characteristics
Table 9. DC Characteristics (Continued)
20
Characteristic
VLVDH9 Low-voltage
detection
threshold —
high range
Condition
Min
Typ1
Max
Unit
C
—
2.11
2.16
2.22
V
P
—
2.16
2.23
2.27
V
P
—
1.80
1.84
1.88
V
P
—
1.88
1.93
1.96
V
P
—
2.36
2.46
2.56
V
P
—
2.36
2.46
2.56
V
P
—
2.11
2.16
2.22
V
P
—
2.16
2.23
2.27
V
P
VDD falling
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Num Symbol
VDD rising
VLVDL
21
Low-voltage
detection
threshold —
low range9
VDD falling
VDD rising
22
VLVWH Low-voltage
warning
threshold —
high range9
VDD falling
VDD rising
23
VLVWL Low-voltage
warning
threshold —
low range9
VDD falling
VDD rising
1
2
3
4
5
6
24
Vhys
Low-voltage inhibit reset/recover
hysteresis10
—
—
50
—
mV
C
25
VBG
Bandgap Voltage Reference11
—
1.15
1.17
1.18
V
P
Typical values are measured at 25°C. Characterized, not tested
As the supply voltage rises, the LVD circuit will hold the MCU in reset until the supply has risen above VLVDL.
Total Leakage current is the sum value for all GPIO pins; this leakage current is not distributed evenly across
all pins but characterization data shows that individual pin leakage current maximums are less than 250 nA.
Measured with VIn = VDD.
All functional non-supply pins are internally clamped to VSS and VDD.
Input must be current limited to the value specified. To determine the value of the required current-limiting
resistor, calculate resistance values for positive and negative clamp voltages, then use the larger of the two
values.
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Preliminary Electrical Characteristics
Power supply must maintain regulation within operating VDD range during instantaneous and operating
maximum current conditions. If positive injection current (VIn > VDD) is greater than IDD, the injection current
may flow out of VDD and could result in external power supply going out of regulation. Ensure external VDD
load will shunt current greater than maximum injection current. This will be the greatest risk when the MCU
is not consuming power. Examples are: if no system clock is present, or if clock rate is very low (which would
reduce overall power consumption).
8
Maximum is highest voltage that POR is guaranteed.
9
Run at 1 MHz bus frequency
10
Low voltage detection and warning limits measured at 1 MHz bus frequency.
11
Factory trimmed at VDD = 3.0 V, Temp = 25°C
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Preliminary Electrical Characteristics
2.6
Supply Current Characteristics
#
Symbol
RIDD
1
Parameter
Run
supply
current
Bus
Freq
VDD (V)
24 MHz
20 MHz
8 MHz
1 MHz
RIDD
Run
supply
current
4
RIDD
Run
supply
current
Temp
(°C)
C
3
20
24
mA
–40 to
25
P
3
20
TBD
mA
105
P
3
18
—
mA
–40 to
105
T
3
8
—
mA
–40 to
105
T
3
1.8
—
mA
–40 to
105
T
24 MHz
3
12.3
TBD
mA
–40 to
105
C
20 MHz
3
10.5
—
mA
–40 to
105
T
4.8
—
mA
–40 to
105
T
1.3
—
mA
–40 to
105
T
TBD
—
μA
–40 to
105
T
TBD
—
μA
–40 to
105
T
TBD
—
μA
0 to 70
T
TBD
—
μA
–40 to
105
T
1 MHz
RIDD
Unit
FEI mode; All modules OFF
8 MHz
3
Max
FEI mode
All modules ON
24 MHz
2
Typ1
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Table 10. Supply Current Characteristics
3
3
LPS=0; All modules OFF
16 kHz
FBILP
3
16 kHz
FBELP
3
Run supply LPS=1, all modules OFF
current
16 kHz
FBELP
3
16 kHz
FBELP
3
Freescale Semiconductor
21
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Preliminary — Subject to Change
Preliminary Electrical Characteristics
#
Symbol
5
WIDD
Parameter
Bus
Freq
20 MHz
8 MHz
1 MHz
S2IDD
Temp
(°C)
C
3
TBD
6
mA
–40 to
105
C
3
TBD
—
mA
–40 to
105
T
3
TBD
—
mA
–40 to
105
T
3
TBD
—
mA
–40 to
105
T
3
0.39
0.6
µA
–40 to
25
P
3
TBD
TBD
µA
70
C
N/A
3
7
TBD
µA
85
C
N/A
3
16
TBD
µA
105
P
TBD
TBD
µA
–40 to
25
C
2
N/A
2
TBD
TBD
µA
70
C
N/A
2
TBD
TBD
µA
85
C
N/A
2
TBD
TBD
µA
105
C
0.55
0.9
µA
–40 to
25
P
Stop3 mode No clocks active
supply current
N/A
3
N/A
3
TBD
TBD
µA
70
C
N/A
3
14
TBD
µA
85
C
N/A
3
37
TBD
µA
105
P
2
TBD
TBD
µA
–40 to
25
C
N/A
2
TBD
TBD
µA
70
C
N/A
2
14
TBD
µA
85
C
N/A
2
TBD
TBD
µA
105
C
N/A
1
Unit
N/A
N/A
S3IDD
Max
Stop2 mode
supply current
N/A
7
Typ1
Wait mode FEI mode, all modules OFF
supply current
24 MHz
6
VDD (V)
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
22
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Table 10. Supply Current Characteristics (Continued)
Preliminary Electrical Characteristics
Table 11. Typical Stop Mode Adders
1
2
3
4
5
6
Parameter
LPO
EREFSTEN
1
RANGE = HGO = 0
IREFSTEN1
Units
C
250
nA
D
850
(TBD)
1000
(TBD)
nA
D
77
86
120
µA
T
-40
25
70
85
105
50
75
100
150
600
(TBD)
650
(TBD)
750
(TBD)
68
70
—
—
TOD
Does not include clock source
current
50
75
100
150
250
nA
D
LVD1
LVDSE = 1
114
115
123
135
170
µA
T
ACMP1
Not using the bandgap
(BGBE = 0)
18
20
23
33
65
µA
T
ADC1
ADLPC = ADLSMP = 1
Not using the bandgap
(BGBE = 0)
75
85
100
115
165
µA
T
DAC1
High power mode; no load on
DACO
500
500
500
500
500
µA
T
7
8
Condition
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not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
Temperature (°C)
#
Not available in stop2 mode.
2.7
PRACMP Electricals
Table 12. PRACMP Electrical Specifications
#
Characteristic
Symbol
Min
Typical
Max
Unit
C
VPWR
1.8
—
3.6
V
P
1
Supply voltage
2
Supply current (active) (PRG enabled)
IDDACT1
—
—
60
μA
C
3
Supply current (active) (PRG disabled)
IDDACT2
—
—
40
μA
C
4
Supply current (ACMP and PRG all
disabled)
IDDDIS
—
—
2
nA
D
5
Analog input voltage
VAIN
VSS – 0.3
—
VDD
V
—
6
Analog input offset voltage
VAIO
—
5
40
mV
T
7
Analog comparator hysteresis
VH
3.0
—
20.0
mV
T
8
Analog input leakage current
IALKG
—
—
1
nA
D
9
Analog comparator initialization delay
tAINIT
—
—
1.0
μs
T
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Preliminary — Subject to Change
Preliminary Electrical Characteristics
#
Characteristic
Symbol
Min
Typical
Max
Unit
C
10
Programmable reference generator inputs
VIn2(VDD25)
1.8
—
2.75
V
—
11
Programmable reference generator setup
delay
tPRGST
—
1
—
µs
D
12
Programmable reference generator step
size
Vstep
–0.25
1
0.25
LSB
D
13
Programmable reference generator voltage
range
Vprgout
VIn/32
—
Vin
V
P
2.8
12-bit DAC Electricals
Table 13. DAC 12LV Operating Requirements
#
Characteristic
Symbol
Min
Max
Unit
C
1
Supply voltage
VDDA
1.8
3.6
V
P
2
Reference voltage
VDACR
1.15
3.6
V
C
3
Temperature
TA
–40
105
°C
C
Output load capacitance
CL
—
100
pF
C
—
1
mA
C
4
5
Output load current
IL
24
Notes
A small load capacitance
(47 pF) can improve the
bandwidth performance
of the DAC.
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Table 12. PRACMP Electrical Specifications
Preliminary Electrical Characteristics
Table 14. DAC 12-Bit Operating Behaviors
Characteristic
1
Resolution
2
Symbol
Min
Max
Unit
C
N
12
12
Supply current low-power mode
IDDA_DACLP
50
100
3
Supply current high-power mode
IDDA_DACHP
120
500
(TBD)
µA
C
TsFSLP
4
Full-scale Settling time
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
low-power mode
—
200
(TBD)
µs
C
TsFSHP
5
Full-scale Settling time
(±0.5 LSB)
(0x080 to 0xF7F or 0xF7F to 0x080)
high-power mode
—
30
µs
C
TsC-CLP
6
Code-to-code Settling time
(±0.5 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
low-power mode
—
5
µs
C
TsC-CHP
7
Code-to-code Settling time
(±0.5 LSB)
(0xBF8 to 0xC08 or 0xC08 to
0xBF8)
high-power mode
—
1(TBD)
µs
C
DAC output voltage range low
(high-power mode, no load, DAC
set to 0)
Vdacoutl
8
—
100
(TBD)
mV
C
DAC output voltage range high
(high-power mode, no load, DAC
set to 0x0FFF)
Vdacouth
9
VDACR100
—
mV
C
10
Integral non-linearity error
INL
—
±8
LSB
C
11
Differential non-linearity error
VDACR is > 2.4 V
DNL
—
±1
LSB
C
12
Offset error
EO
—
± 0.5
%FSR
C
13
Gain error
EG
—
± 0.5
(TBD)
%FSR
C
14
Power supply rejection ratio
VDD ≥ 2.4 V
60
—
dB
C
—
2
(TBD)
mV
C
—
TBD
µV/yr
C
PSRR
Temperature drift of offset voltage
(DAC set to 0x0800)
Tco
15
16
Offset aging coefficient
Ac
bit
µA
Notes
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#
C
C
See Typical
Drift figure that
follows.
Figure 6. Offset at Half Scale vs Temperature
Freescale Semiconductor
25
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Preliminary — Subject to Change
Preliminary Electrical Characteristics
2.9
ADC Characteristics
Characteristic
Conditions
Min
Typ1
Max
Unit
C
1.8
—
3.6
V
D
-100
0
+100
mV
D
-100
0
+100
mV
D
VDDAD VDDAD
V
D
VSSAD VSSAD
V
D
VREFH
V
D
8
4
10
5
pF
C
2
5
kΩ
C
#
Symb
1
VDDAD Supply voltage
Absolute
2
ΔVDDAD
Delta to VDD
(VDD-VDDAD)2
3
ΔVSSAD Ground voltage
4
VREFH Ref Voltage High
1.13
5
VREFL Ref Voltage Low
VSSAD
6
VADIN
VREFL
—
7
CADIN Input
Capacitance
—
8
RADIN Input Resistance
—
Delta to VSS
(VSS-VSSAD)2
Input Voltage
16-bit modes
8/10/12-bit modes
26
Comment
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Table 15. 16-bit ADC Operating Conditions
Preliminary Electrical Characteristics
Table 15. 16-bit ADC Operating Conditions (Continued)
Symb
RAS
9
fADCK
10
Characteristic
Conditions
Min
Typ1
Max
Unit
C
Analog Source
Resistance
ADC Conversion
Clock Freq.
Comment
External to
MCU
Assumes
ADLSMP=0
16-bit mode
fADCK > 8 MHz
—
—
0.5
4 MHz < fADCK < 8
MHz
—
—
1
fADCK < 4 MHz
—
—
2
13/12-bit mode
fADCK > 8 MHz
—
—
4 MHz < fADCK < 8
MHz
—
—
2
fADCK < 4 MHz
—
—
5
11/10-bit mode
fADCK > 8 MHz
—
—
2
4 MHz < fADCK < 8
MHz
—
—
5
fADCK < 4 MHz
—
—
10
9/8-bit mode
fADCK > 4 MHz
—
—
5
fADCK < 4 MHz
—
—
10
High Speed
(ADLPC=0,
ADHSC=1)
1.0
—
8.0
High Speed
(ADLPC=0,
ADHSC=0)
1.0
Low Power
(ADLPC=1,
ADHSC=1)
1.0
—
—
kΩ
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#
C
kΩ
C
kΩ
C
kΩ
C
kΩ
C
kΩ
C
kΩ
C
kΩ
C
kΩ
C
kΩ
C
kΩ
C
MHz
D
MHz
D
MHz
D
5.0
2.5
Typical values assume VDDAD = 3.0 V, Temp = 25 °C, fADCK=1.0 MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
2 DC potential difference.
1
Freescale Semiconductor
27
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Preliminary — Subject to Change
Preliminary Electrical Characteristics
Pad
leakage
due to
input
protection
ZAS
RAS
SIMPLIFIED
CHANNEL SELECT
CIRCUIT
RADIN
ADC SAR
ENGINE
+
VADIN
VAS
+
–
CAS
–
RADIN
INPUT PIN
INPUT PIN
RADIN
RADIN
INPUT PIN
CADIN
Figure 7. ADC Input Impedance Equivalency Diagram
28
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SIMPLIFIED
INPUT PIN EQUIVALENT
ZADIN
CIRCUIT
Preliminary Electrical Characteristics
Characterist
ic
Supply
Current
Conditions1
Min
Typ2
Max
—
215
—
—
470
—
—
610
—
—
0.01
—
—
2.4
—
—
5.2
—
—
6.2
—
—
—
±16
±20
+48/-4
0
+56/-2
8
13-bit differential mode
12-bit single-ended mode
—
—
±1.5
±1.75
±3.0
±3.5
T
11-bit differential mode
10-bit single-ended mode
—
—
±0.7
±0.8
±1.5
±1.5
T
9-bit differential mode
8-bit single-ended mode
—
—
±0.5
±0.5
±1.0
±1.0
T
—
—
±2.5
±2.5
+5/-3
+5/-3
13-bit differential mode
12-bit single-ended mode
—
—
±0.7
±0.7
±1
±1
T
11-bit differential mode
10-bit single-ended mode
—
—
±0.5
±0.5
±0.75
±0.75
T
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
T
Symb
ADLPC=1, ADHSC=0
ADLPC=0, ADHSC=0
IDDAD
ADLPC=0, ADHSC=1
Supply
Current
Stop, Reset, Module Off
ADC
Asynchronou
s Clock
Source
ADLPC=1, ADHSC=0
ADLPC=0, ADHSC=0
Sample Time
See Block Guide for sample times
Conversion
Time
See Block Guide for conversion times
Total
Unadjusted
Error
16-bit differential mode
16-bit single-ended mode
Differential
Non-Linearity
IDDAD
fADACK
ADLPC=0, ADHSC=1
16-bit differential mode
16-bit single-ended mode
TUE
DNL
Freescale Semiconductor
Unit
C
Comment
μA
T
ADLSMP=0
ADCO=1
μA
C
MHz
P
tADACK =
1/fADACK
LSB3
T
32x
Hardware
Averaging
(AVGE = %1
AVGS =
%11)
LSB2
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Table 16. 16-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, > 1.8, VREFL = VSSAD ≤ 8 MHz)
T
29
Non-Disclosure Agreement Required
Preliminary — Subject to Change
Preliminary Electrical Characteristics
Characterist
ic
Integral
Non-Linearity
Zero-Scale
Error
Full-Scale
Error
Quantization
Error
Conditions1
Symb
Min
Typ2
Max
Unit
C
INL
—
—
±6.0
±10.0
±16.0
±20.0
LSB2
T
13-bit differential mode
12-bit single-ended mode
—
—
±1.0
±1.0
±2.5
±2.5
T
11-bit differential mode
10-bit single-ended mode
—
—
±0.5
±0.5
±1.0
±1.0
T
9-bit differential mode
8-bit single-ended mode
—
—
±0.3
±0.3
±0.5
±0.5
T
—
—
±4.0
±4.0
+32/-2
4
+24/-1
6
13-bit differential mode
12-bit single-ended mode
—
—
±0.7
±0.7
±2.5
±2.0
T
11-bit differential mode
10-bit single-ended mode
—
—
±0.4
±0.4
±1.0
±1.0
T
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
T
—
—
+10/0
+14/0
+42/-2
+46/-2
13-bit differential mode
12-bit single-ended mode
—
—
±1.0
±1.0
±3.5
±3.5
T
11-bit differential mode
10-bit single-ended mode
—
—
±0.4
±0.4
±1.5
±1.5
T
9-bit differential mode
8-bit single-ended mode
—
—
±0.2
±0.2
±0.5
±0.5
T
—
-1 to 0
—
—
—
±0.5
16-bit differential mode
16-bit single-ended mode
16-bit differential mode
16-bit single-ended mode
16-bit differential mode
16-bit single-ended mode
16-bit modes
<13-bit modes
EZS
EFS
EQ
30
LSB2
LSB2
LSB2
T
T
Comment
VADIN =
VSSAD
VADIN =
VDDAD
D
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Table 16. 16-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, > 1.8, VREFL = VSSAD ≤ 8 MHz) (Continued)
Preliminary Electrical Characteristics
Characterist
ic
Effective
Number of
Bits
Conditions1
Symb
16-bit differential mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
See ENOB
Total
Harmonic
Distortion
16-bit differential mode
Avg=32
Spurious
Free
Dynamic
Range
Input
Leakage
Error
Temp Sensor
Slope
Max
12.8
12.7
12.6
12.5
11.9
14.2
13.8
13.6
13.3
12.5
—
—
—
—
—
—
—
—
—
—
13.2
12.8
12.6
12.3
11.5
—
—
—
—
—
SINAD SINAD = 6.02 ⋅ ENOB + 1.76
Bits
C
Fin =
Fsample/100
dB
C
—
-91.5
-74.3
—
-85.5
—
75.0
92.2
—
—
86.2
—
SFDR
dB
dB
Fin =
Fsample/100
C
Fin =
Fsample/100
D
EIL
m
IIn * RAS
—
1.646
—
—
1.769
—
—
701.2
—
–40°C – 25°C
25°C
Comment
D
16-bit single-ended mode
Avg=32
all modes
C
THD
16-bit single-ended mode
Avg=32
16-bit differential mode
Avg=32
Unit
D
25°C – 125°C
Temp Sensor
Voltage
Typ2
ENOB
16-bit single-ended mode
Avg=32
Avg=16
Avg=8
Avg=4
Avg=1
Signal to
Noise plus
Distortion
Min
Because of an order from the United States International Trade Commission, BGA-packaged product lines and part numbers indicated here currently are
not available from Freescale for import or sale in the United States prior to September 2010: MC9S08MM128 products in 81 MAPBGA packages
Table 16. 16-bit SAR ADC Characteristics full operating range
(VREFH = VDDAD, > 1.8, VREFL = VSSAD ≤ 8 MHz) (Continued)
VTEMP2
mV
D
mV/×
C
C
mV
C
IIn = leakage
current
(refer to DC
characteristi
cs)
5
1
All accuracy numbers assume the ADC is calibrated with VREFH=VDDAD
Typical values assume VDDAD = 3.0V, Temp = 25°C, fADCK=2.0MHz unless otherwise stated. Typical values are for
reference only and are not tested in production.
3
1 LSB = (VREFH - VREFL)/2N
2
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Preliminary — Subject to Change
Preliminary Electrical Characteristics
2.10
MCG and External Oscillator (XOSC) Characteristics
#
Rating
1 Internal reference startup time
factory trimmed at
VDD=3.0 V and
2 Average internal reference frequency temp=25°C
Symbol
Min
Typical
Max
Unit
C
tirefst
—
55
100
μs
D
—
31.25
—
31.25
—
39.0625
16
—
20
32
—
40
40
—
60
—
± 0.1
± 0.2
—
± 0.2
± 0.4
—
±1.0
±2
—
± 0.5
±1
tfll_acquire
—
—
1
tpll_acquire
—
—
1
CJitter
—
0.02
0.2
%fdco
C
fvco
7.0
—
55.0
MHz
D
fpll_ref
1.0
—
2.0
MHz
D
fpll_jitter_625
—
0.5664
—
%fpll
Dlock
± 1.49
—
± 2.98
Dunl
± 4.47
—
± 5.97
tfll_lock
—
—
tfll_acquire+
1075(1/fint_t)
tpll_lock
—
—
C
fint_ft
user trimmed
output frequency range 3 DCO
trimmed
Low range
(DRS=00)
Mid range
(DRS=01)
Resolution of trimmed DCO output fre- with FTRIM
ture
without FTRIM
over voltage and
temperature
Total deviation of trimmed DCO output
5 frequency over voltage and tempera- over fixed voltage
ture
and temp range
of 0 - 70 °C
6 Acquisition time
FLL2
3
PLL
term Jitter of DCO output clock (averaged over 2mS
7 Long
interval) 4
8 VCO operating frequency
9 PLL reference frequency range
of PLL output clock measured
10 Jitter
over 625ns 5
Long term
Exit7
FLL
12 Lock time
MHz
%fdco
C
C
p
%fdco
PLL
C
C
Δfdco_t
ns
Entry6
11 Lock frequency tolerance
Δfdco_res_t
C
C
fdco_t
High range1
(DRS=10)
4 quency at fixed voltage and tempera-
kHz
C
C
ms
tpll_acquire+
1075(1/fpll_re
D
D
D
%
D
D
s
D
f)
13
14
1
2
Loss of external clock minimum frequency - RANGE = 0
Loss of external clock minimum frequency - RANGE = 1
floc_low
(3/5) x
fint_t
—
—
kHz
floc_high
(16/5) x
fint_t
—
—
kHz
D
D
This should not exceed the maximum CPU frequency for this device.
This specification applies to any time the FLL reference source or reference divider is changed, trim value is changed,
DMX32 bit is changed, DRS bit is changed, or changing from FLL disabled (BLPE, BLPI) to FLL enabled (FEI, FEE,
FBE, FBI). If a crystal/resonator is being used as the reference, this specification assumes it is already running.
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Table 17. MCG (Temperature Range = –40 to 105°C Ambient)
Preliminary Electrical Characteristics
3
7
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This specification applies to any time the PLL VCO divider or reference divider is changed, or changing from PLL
disabled (BLPE, BLPI) to PLL enabled (PBE, PEE). If a crystal/resonator is being used as the reference, this
specification assumes it is already running.
4
Jitter is the average deviation from the programmed frequency measured over the specified interval at maximum fBUS.
Measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal.
Noise injected into the FLL circuitry via VDD and VSS and variation in crystal oscillator frequency increase the CJitter
percentage for a given interval.
5
625 ns represents 5 time quanta for CAN applications, under worst-case conditions of 8 MHz CAN bus clock, 1 Mbps
CAN Bus speed, and 8 time quanta per bit for bit time settings. 5 time quanta is the minimum time between a
synchronization edge and the sample point of a bit using 8 time quanta per bit.
6
Below Dlock minimum, the MCG is guaranteed to enter lock. Above Dlock maximum, the MCG will not enter lock. But
if the MCG is already in lock, then the MCG may stay in lock.
Below Dunl minimum, the MCG will not exit lock if already in lock. Above Dunl maximum, the MCG is guaranteed to exit
lock.
Table 18. XOSC (Temperature Range = –40 to 105°C Ambient)
#
Oscillator crystal or resonator
(EREFS = 1, ERCLKEN = 1)
1
2
Symbol
Min
Typ1
Max
Unit
flo
32
—
38.4
kHz
• High range (RANGE = 1),
• FEE or FBE mode 2
fhi
1
—
5
MHz
• High range (RANGE = 1),
• High gain (HGO = 1),
• FBELP mode
fhi
1
—
16
MHz
• High range (RANGE = 1),
• Low power (HGO = 0),
• FBELP mode
fhi
1
—
8
MHz
Characteristic
• Low range (RANGE = 0)
Load capacitors
Feedback resistor
See Note 3
C1
C2
Low range
(32 kHz to 38.4 kHz)
RF
—
—
High range
(1 MHz to 16 MHz)
—
—
1
—
Low Gain (HGO = 0)
RS
—
0
—
—
100
—
—
0
0
4 MHz
—
0
10
1 MHz
—
0
20
10
3
MΩ
Series resistor — Low range
4
High Gain (HGO = 1)
Series resistor — High range
kΩ
• Low Gain (HGO = 0)
• High Gain (HGO = 1)
5
≥ 8 MHz
RS
Freescale Semiconductor
kΩ
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Preliminary Electrical Characteristics
Table 18. XOSC (Temperature Range = –40 to 105°C Ambient)
Characteristic
Crystal start-up time 4, 5
Low range, low gain (RANGE = 0,
HGO = 0)
Symbol
Min
Typ1
—
t
—
—
400
—
—
5
—
—
15
—
6
High range, low gain (RANGE = 1,
HGO = 0)
tCSTH
High range, high gain (RANGE =
1, HGO = 1)
Unit
200
CSTL
Low range, high gain (RANGE =
0, HGO = 1)
Max
ms
1
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
When MCG is configured for FEE or FBE mode, input clock source must be divisible using RDIV to within the range of
31.25 kHz to 39.0625 kHz.
3 See crystal or resonator manufacturer’s recommendation.
4 This parameter is characterized and not tested on each device.
5 Proper PC board layout procedures must be followed to achieve specifications.
2
o
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#
Preliminary Electrical Characteristics
2.11
AC Characteristics
2.11.1
Control Timing
Table 19. Control Timing
#
Symbol
1
fBus
Parameter
Min
Typical1
Max
C
Bus frequency (tcyc = 1/fBus)
Unit
MHz
VDD ≥ 1.8 V
dc
—
10
D
VDD > 2.1 V
dc
—
20
D
VDD > 2.4 V
dc
—
D
24
2
tLPO
Internal low-power oscillator
period
800
990
(TBD)
1500
D
μs
3
textrst
External reset pulse width2
(tcyc = 1/fSelf_reset)
100
—
—
D
ns
4
trstdrv
Reset low drive
66 x tcyc
—
—
D
ns
5
tMSSU
Active background debug
mode latch setup time
500
—
—
D
ns
6
tMSH
Active background debug
mode latch hold time
100
—
—
D
ns
7
tILIH, tIHIL
IRQ pulse width
• Asynchronous path2
• Synchronous path3
100
1.5 x tcyc
—
—
8
tILIH, tIHIL
KBIPx pulse width
• Asynchronous path2
• Synchronous path3
100
1.5 x tcyc
—
—
D
ns
D
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ns
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This section describes ac timing characteristics for each peripheral system.
Preliminary Electrical Characteristics
Table 19. Control Timing
Symbol
9
tRise, tFall
Parameter
Min
Typical1
Max
C
Port rise and fall time (load = 50 pF)4, Low Drive
Unit
ns
Slew rate
control
disabled
(PTxSE = 0)
—
11
—
D
Slew rate
control
enabled
(PTxSE = 1)
—
35
—
D
Slew rate
control
disabled
(PTxSE = 0)
—
40
—
D
Slew rate
control
enabled
(PTxSE = 1)
—
75
—
D
Typical values are based on characterization data at VDD = 5.0 V, 25 °C unless otherwise stated.
This is the shortest pulse that is guaranteed to be recognized as a reset pin request. Shorter pulses are not guaranteed
to override reset requests from internal sources.
3 This is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. Shorter pulses may
or may not be recognized. In stop mode, the synchronizer is bypassed so shorter pulses can be recognized in that case.
4 Timing is shown with respect to 20% V
DD and 80% VDD levels. Temperature range –40 °C to 105 °C.
1
2
textrst
RESET PIN
Figure 8. Reset Timing
tIHIL
IRQ/KBIPx
IRQ/KBIPx
tILIH
Figure 9. IRQ/KBIPx Timing
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#
Preliminary Electrical Characteristics
2.11.2
TPM Timing
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Synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the
optional external source to the timer counter. These synchronizers operate from the current bus rate clock.
Table 20. TPM Input Timing
#
C
Function
Symbol
Min
Max
Unit
1
—
External clock frequency
fTPMext
dc
fBus/4
MHz
2
—
External clock period
tTPMext
4
—
tcyc
3
D
External clock high time
tclkh
1.5
—
tcyc
4
D
External clock low time
tclkl
1.5
—
tcyc
5
D
Input capture pulse width
tICPW
1.5
—
tcyc
tTPMext
tclkh
TPMxCLK
tclkl
Figure 10. Timer External Clock
tICPW
TPMxCHn
TPMxCHn
tICPW
Figure 11. Timer Input Capture Pulse
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Preliminary Electrical Characteristics
2.12
SPI Characteristics
Table 21. SPI Timing
No.1
Characteristic2
Symbol
Operating frequency
Unit
C
fBus/2048
0
fBus/2
fBus/4
Hz
Hz
D
2
4
2048
—
tcyc
tcyc
D
1/2
1
—
—
tSPSCK
tcyc
D
1/2
1
—
—
tSPSCK
tcyc
D
tcyc – 30
tcyc – 30
1024 tcyc
—
ns
ns
D
15
15
—
—
ns
ns
D
0
25
—
—
ns
ns
D
ta
—
1
tcyc
D
tdis
—
1
tcyc
D
—
—
25
25
ns
ns
D
0
0
—
—
ns
ns
D
Master
Slave
SPSCK period
tSPSCK
2
Master
Slave
Enable lead time
tLead
3
Master
Slave
Enable lag time
tLag
4
Master
Slave
Clock (SPSCK) high or low time
5
tWSPSCK
Master
Slave
Data setup time (inputs)
6
Master
Slave
Data hold time (inputs)
7
9
Max
fop
1
8
Min
Master
Slave
Slave access time3
Slave MISO disable time
4
Data valid (after SPSCK edge)
10
tSU
tSU
tHI
tHI
tv
Master
Slave
Data hold time (outputs)
11
tHO
Master
Slave
Rise time
12
Input
Output
tRI
tRO
—
—
tcyc – 25
25
ns
ns
D
Input
Output
tFI
tFO
—
—
tcyc – 25
25
ns
ns
D
Fall time
13
1
Numbers in this column identify elements in Figure 12 through Figure 15.
All timing is shown with respect to 20% VDD and 70% VDD, unless noted; 100 pF load on all SPI pins. All timing
assumes slew rate control disabled and high drive strength enabled for SPI output pins.
3 Time to data active from high-impedance state.
4 Hold time to high-impedance state.
2
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Table 21 and Figure 12 through Figure 15 describe the timing requirements for the SPI system.
Preliminary Electrical Characteristics
SS1
(OUTPUT)
2
3
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2
SCK
(CPOL = 0)
(OUTPUT)
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN2
BIT 6 . . . 1
11
MOSI
(OUTPUT)
LSB IN
11
MSB OUT2
12
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 12. SPI Master Timing (CPHA = 0)
SS(1)
(OUTPUT)
2
2
SCK
(CPOL = 0)
(OUTPUT)
3
5
4
SCK
(CPOL = 1)
(OUTPUT)
5
4
6
MISO
(INPUT)
7
MSB IN(2)
11
MOSI
(OUTPUT)
BIT 6 . . . 1
LSB IN
12
MSB OUT(2)
BIT 6 . . . 1
LSB OUT
NOTES:
1. SS output mode (MODFEN = 1, SSOE = 1).
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
Figure 13. SPI Master Timing (CPHA = 1)
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Preliminary Electrical Characteristics
SS
(INPUT)
5
4
2
SCK
(CPOL = 1)
(INPUT)
5
4
8
MISO
(OUTPUT)
12
11
BIT 6 . . . 1
MSB OUT
SLAVE
SLAVE LSB OUT
SEE
NOTE
7
6
MOSI
(INPUT)
9
BIT 6 . . . 1
MSB IN
LSB IN
NOTE:
1. Not defined, but normally MSB of character just received
Figure 14. SPI Slave Timing (CPHA = 0)
SS
(INPUT)
2
3
2
SCK
(CPOL = 0)
(INPUT)
5
4
SCK
(CPOL = 1)
(INPUT)
5
4
11
MISO
(OUTPUT)
SEE
NOTE
8
MOSI
(INPUT)
SLAVE
12
MSB OUT
6
BIT 6 . . . 1
9
SLAVE LSB OUT
7
MSB IN
BIT 6 . . . 1
LSB IN
NOTE:
1. Not defined, but normally LSB of character just received
Figure 15. SPI Slave Timing (CPHA = 1)
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3
2
SCK
(CPOL = 0)
(INPUT)
Preliminary Electrical Characteristics
2.13
Flash Specifications
Program and erase operations do not require any special power sources other than the normal VDD supply. For more detailed
information about program/erase operations, see the Memory chapter in the Reference Manual for this device
(MC9S08MM128RM).
Table 22. Flash Characteristics
#
Characteristic
Symbol
Min
Typical
Max
Unit
3.6
V
C
1
Supply voltage for program/erase
-40°C to 105°C
Vprog/erase
1.8
2
Supply voltage for read operation
VRead
1.8
—
3.6
V
D
3
Internal FCLK frequency1
fFCLK
150
—
200
kHz
D
4
Internal FCLK period (1/FCLK)
tFcyc
5
—
6.67
μs
D
5
Byte program time (random location)
2
2
—
D
tprog
9
tFcyc
P
tBurst
4
tFcyc
P
6
Byte program time (burst mode)
7
Page erase time2
tPage
4000
tFcyc
P
8
2
tMass
20,000
tFcyc
P
Mass erase time
endurance3
9
Program/erase
TL to TH = –40°C to + 105°C
T = 25°C
10
Data retention4
tD_ret
10,000
—
—
100,000
—
—
cycles
C
15
100
—
years
C
1
The frequency of this clock is controlled by a software setting.
These values are hardware state machine controlled. User code does not need to count cycles. This information supplied for
calculating approximate time to program and erase.
3 Typical endurance for flash was evaluated for this product family on the HC9S12Dx64. For additional information on how
Freescale defines typical endurance, please refer to Engineering Bulletin EB619, Typical Endurance for Nonvolatile Memory.
4
Typical data retention values are based on intrinsic capability of the technology measured at high temperature and de-rated to
25°C using the Arrhenius equation. For additional information on how Freescale defines typical data retention, please refer to
Engineering Bulletin EB618, Typical Data Retention for Nonvolatile Memory.
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This section provides details about program/erase times and program-erase endurance for the Flash memory.
Preliminary Electrical Characteristics
2.14
USB Electricals
If the Freescale USB On-the-Go implementation has electrical characteristics that deviate from the standard or require
additional information, this space would be used to communicate that information.
Table 23. Internal USB 3.3 V Voltage Regulator Characteristics
#
Characteristic
Symbol
Min
Typ
Max
Unit
C
1
Regulator operating voltage
Vregin
3.9
—
5.5
V
C
2
VREG output
Vregout
3
3.3
3.6
V
P
3
VUSB33 input with internal VREG
disabled
Vusb33in
3
3.3
3.6
V
C
4
VREG Quiescent Current
IVRQ
—
0.5
—
mA
C
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The USB electricals for the USB On-the-Go module conform to the standards documented by the Universal Serial Bus
Implementers Forum. For the most up-to-date standards, visit http://www.usb.org.
Preliminary Electrical Characteristics
2.15
VREF Electrical Specifications
Num
Symbol
Min
Max
Unit
C
VDDA
1.80
3.6
V
C
1
Supply voltage
2
Temperature
TA
–40
105
°C
C
3
Output Load Capacitance
CL
—
100
nf
D
4
Maximum Load
—
—
10
mA
—
5
Voltage Reference Output with Factory
Trim. VDD = 3 V.
Vout
1.140
1.160
V
P
6
Temperature Drift (Vmin - Vmax across
the full temperature range)
Tdrift
—
10
(TBD)
mV1
T
7
Aging Coefficient
Ac
—
TBD
ppm/year
C
8
Powered down Current (Off Mode,
VREFEN=0, VRSTEN=0)
I
—
0.10
µA
C
9
Bandgap only (MODE_LV[1:0] = 00)
I
—
75
µA
T
10
Low-Power buffer (MODE_LV[1:0] = 01)
I
—
125
µA
T
11
Tight-Regulation buffer (MODE_LV[1:0]
= 10)
I
—
1.1
mA
T
12
Load Regulation MODE_LV = 10
—
—
100
µV/mA
C
13
Line Regulation (Power Supply
Rejection)
DC
—
TBD
mV
C
AC
TBD
—
dB
14
1
Characteristic
See typical chart below.
Table 25. VREF Limited Range Operating Requirements
#
Characteristic
Symbol
Min
Max
Unit
C
1
Temperature
TA
0
50
°C
C
Notes
Table 26. VREF Limited Range Operating Behaviors
#
Characteristic
Symbol
Min
Max
Unit
C
1
Voltage Reference Output with
Factory Trim
Vout
TBD
TBD
µA
C
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Table 24. VREF Electrical Specifications
Figure 16. Typical Output vs. Temperature
TBD
Figure 17. Typical Output vs. VDD
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Preliminary Electrical Characteristics
Freescale Semiconductor
Preliminary Electrical Characteristics
2.16
TRIAMP Electrical Parameters
Characteristic1
#
1
2
2.17
Symbol
Min
Typ2
Max
Unit
C
VDD
1.8
—
3.6
V
C
1
Operating Voltage
2
Supply Current (IOUT=0mA, CL=0) Low-power
mode
ISUPPLY
—
80
TBD
μA
P
3
Supply Current (IOUT=0mA, CL=0) High-speed
mode
ISUPPLY
—
350
TBD
μA
P
4
Input Offset Voltage
VOS
—
±3
(TBD)
± 10
mV
C
5
Input Offset Voltage Temperature Coefficient
αVOS
—
TBD
—
μV/C
C
6
Input Offset Current
IOS
—
±270
TBD
pA
C
7
Input Bias Current (0 ~ 50°C)
IBIAS
—
±300
(TBD)
±500
(TBD)
pA
C
8
Input Bias Current (-40 ~ 105°C)
IBIAS
—
TBD
TBD
pA
C
9
Input Common Mode Voltage Low
VCML
0
—
—
V
D
10
Input Common Mode Voltage High
VCMH
—
—
VDD–1.4
V
C
11
Input Resistance
RIN
500
—
—
MΩ
Τ
12
Input Capacitances
CIN
—
—
5
pF
T
13
AC Input Impedance (fIN=100kHz)
|XIN|
—
50
—
MΩ
Τ
14
Input Common Mode Rejection Ratio
CMRR
60
70
—
dB
C
15
Power Supply Rejection Ration
PSRR
60
70
—
dB
C
16
Slew Rate (ΔVIN=100mV) Low-power mode
SR
—
0.1
—
V/μs
C
17
Slew Rate (ΔVIN=100mV) High-speed mode
SR
—
1
—
V/μs
C
18
Unity Gain Bandwidth (Low-power mode) 50pF
GBW
0.15
0.5
—
MHz
C
19
Unity Gain Bandwidth (High-speed mode) 50pF
GBW
—
2
—
MHz
C
20
DC Open Loop Voltage Gain (RL = 20 KΩ)
AV
—
80
—
dB
C
21
Load Capacitance Driving Capability
CL(max)
—
—
50
pF
C
22
Output Resistance
ROUT
—
TBD
—
Ω
C
23
Output Voltage Range
triout
0.15
—
VDD –
0.15
V
C
24
Output Drive Capability
IOUT
—
± 1.0
—
mA
C
25
Gain Margin
GM
20
—
—
dB
T
26
Phase Margin
PM
45
55
—
deg
C
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Table 27. TRIAMP Characteristics 1.8-3.6 V, -40°C~105°C
All parameters are measured at 3.3 V, CL= 47 pF across temperature -40 to + 105 °C unless specified.
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
OPAMP Electrical Parameters
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Preliminary Electrical Characteristics
1
2
#
Characteristics1
Symbol
Min
Typ2
Max
Unit
C
1
Operating Voltage
VDD
1.8
—
3.6
V
C
2
Supply Current (IOUT=0mA, CL=0) Low-power
mode
ISUPPLY
—
40
55
(TBD)
μA
P
3
Supply Current (IOUT=0mA, CL=0)
High-speed mode
ISUPPLY
—
420
(TBD)
450
(TBD)
μA
P
4
Input Offset Voltage
VOS
—
±3
±10
mV
C
5
Input Offset Voltage Temperature Coefficient
αVOS
—
1
—
μV/C
C
6
Input Offset Current
IOS
—
± TBD
± TBD
pA
C
7
Input Bias Current
IBIAS
—
± TBD
± TBD
pA
C
8
Input Common Mode Voltage Low
VCML
0.1
—
—
V
C
9
Input Common Mode Voltage High
VCMH
—
—
VDD+0.1
V
T
10
Input Resistance
RIN
500
—
—
MΩ
T
11
Input Capacitances
CIN
—
—
10
pF
T
12
AC Input Impedance (fIN=100kHz)
|XIN|
—
TBD
—
MΩ
T
13
Input Common Mode Rejection Ratio
CMRR
55
65
—
dB
C
14
Power Supply Rejection Ration
PSRR
60
65
—
dB
C
15
Slew Rate (ΔVIN=100mV) Low-power mode
SR
0.1
—
—
V/μs
C
16
Slew Rate (ΔVIN=100mV) High speed mode
SR
1
—
—
V/μs
C
17
Unity Gain Bandwidth Low-power mode
GBW
0.2
—
—
MHz
C
18
Unity Gain Bandwidth High Speed mode
GBW
1
—
—
MHz
C
19
DC Open Loop Voltage Gain
AV
80
90
—
dB
C
20
Load Capacitance Driving Capability
CL(max)
—
—
100
pF
C
21
Output Resistance
ROUT
—
—
1500
Ω
C
22
Output Voltage Range
VOUT
0.15
—
VDD-0.15
V
C
23
Output Drive Capability
IOUT
±0.5
±1.0
—
mA
C
24
Gain Margin
GM
20
—
—
dB
T
25
Phase Margin
PM
45
55
—
deg
C
26
GPAMP settling time (low-power mode)
(To < 0.1%, Vin = 2Vp-p, CL = 25pF, RL = 2k)
Tstartup
—
TBD
—
27
GPAMP settling time (low-power mode)
Tstartup
—
TBD
—
28
GPAMP settling time (high-speed mode)
(To < 0.1%, Vin = 2Vp-p, CL = 25pF, RL = 2k)
Tstartup
—
TBD
—
29
GPAMP settling time (high-speed mode)
Tstartup
—
TBD
—
uS
uS
uS
uS
C
C
C
C
All parameters are measured at 3.3 V, CL =4 7 pF across temperature -40 to + 105°C unless specified.
Data in Typical column was characterized at 3.0 V, 25°C or is typical recommended value.
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Table 28. OPAMP Characteristics 1.8-3.6 V
Ordering Information
3
Ordering Information
3.1
Device Numbering System
Example of the device numbering system:
MC 9 S08 MM 128 V XX
Status
(MC = Fully Qualified)
Package designator (see Table 30)
Temperature range
(V = –40°C to 105°C)
(C = –40°C to 85°C)
Memory
(9 = Flash-based)
Core
Approximate Flash size in Kbytes
Family
Table 29. Device Numbering System
Memory
Device Number1
MC9S08MM128
Available Packages2
Flash
RAM
131,072
12,288
64 LQFP
131,072
12,288
80 LQFP
131,072
12,288
81 MAPBGA
MC9S08MM64
65,536
12,288
64 LQFP
MC9S08MM32
32768
4096
64 LQFP
MC9S08MM32A
32768
2048
64 LQFP
1
See Table 2 for a complete description of modules included on each device.
2
See Table 30 for package information.
3.2
Package Information
Table 30. Package Descriptions
Pin Count
64
3.3
Package Type
Low Quad Flat Package
80
Low Quad Flat Package
81
MAPBGA Package
Abbreviation
Designator
Case No.
Document No.
LQFP
LH
840F-02
98ASS23234W
98ASS23174W
98ASA10670D
LQFP
LK
917-01
Map PBGA
MB
1662-01
Mechanical Drawings
Table 30 provides the available package types and their document numbers. The latest package outline/mechanical drawings
are available on the MC9S08MM128 series Product Summary pages at http://www.freescale.com.
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This appendix contains ordering information for the device numbering system. MC9S08MM128 and MC9S08MM64 devices.
Revision History
4
Revision History
To provide the most up-to-date information, the revision of our documents on the World Wide Web will be the most current.
Your printed copy may be an earlier revision. To verify you have the latest information available, refer to:
http://freescale.com/
The following revision history table summarizes changes contained in this document.
Rev
Date
Description of Changes
0
6/2009
Initial release of the Data Sheet.
1
7/2009
Updated MCG and XOSC Average internal reference frequency.
2
04/2010
Updated electrical characteristic data.
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To view the latest drawing, either:
• Click on the appropriate link in Table 30, or
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Revision History
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