Very Low Power CMOS SRAM 1M X 8 bit BS62LV8001 Pb-Free and Green package materials are compliant to RoHS FEATURES DESCRIPTION y Wide VCC operation voltage : 2.4V ~ 5.5V y Very low power consumption : Operation current : 31mA (Max.) at 55ns VCC = 3.0V 2mA (Max.) at 1MHz O Standby current : 4/8uA (Max.) at 70/85 C Operation current : 76mA (Max.) at 55ns VCC = 5.0V 10mA (Max.) at 1MHz O Standby current : 25/50uA (Max.) at 70/85 C y High speed access time : -55 55ns (Max.) at VCC : 3.0~5.5V -70 70ns (Max.) at VCC : 2.7~5.5V y Automatic power down when chip is deselected y Easy expansion with CE1, CE2 and OE options y Three state outputs and TTL compatible y Fully static operation y Data retention supply voltage as low as 1.5V The BS62LV8001 is a high performance, very low power CMOS Static Random Access Memory organized as 1,048,576 by 8 bits and operates form a wide range of 2.4V to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed and low power features with maximum CMOS standby O current of 8/50uA at Vcc=3/5V at 85 C and maximum access time of 55/70ns. Easy memory expansion is provided by an active LOW chip enable (CE1), an active HIGH chip enable (CE2), and active LOW output enable (OE) and three-state output drivers. The BS62LV8001 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The BS62LV8001 is available in DICE form, JEDEC standard 44-pin TSOP II and 48-ball BGA package. POWER CONSUMPTION POWER DISSIPATION PRODUCT FAMILY OPERATING TEMPERATURE STANDBY Operating (ICCSB1, Max) VCC=5.0V VCC=3.0V PKG TYPE (ICC, Max) VCC=5.0V 10MHz 1MHz fMax. VCC=3.0V 10MHz 1MHz fMax. BS62LV8001DC DICE Commercial O O +0 C to +70 C BS62LV8001EC 25uA 4.0uA 9mA 39mA 75mA 1.5mA 19mA 30mA TSOP II-44 BS62LV8001FC BGA-48-0912 BS62LV8001EI TSOP II-44 Industrial O O -40 C to +85 C BS62LV8001FI 50uA 8.0uA 10mA 40mA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 1 3 A5 A6 A7 OE CE2 A8 NC NC DQ7 DQ6 VSS VCC DQ5 DQ4 NC NC A9 A10 A11 A12 A13 A14 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 BS62LV8001EC BS62LV8001EI 2 2mA 20mA 31mA BGA-48-0912 BLOCK DIAGRAM PIN CONFIGURATIONS A4 A3 A2 A1 A0 CE1 NC NC DQ0 DQ1 VCC VSS DQ2 DQ3 NC NC WE A19 A18 A17 A16 A15 76mA 4 5 A13 A17 A15 A18 A16 A14 A12 A7 A6 A5 A4 NC OE A0 A1 A2 CE2 B NC NC A3 A4 CE1 NC C DQ0 NC A5 A6 NC DQ4 D VSS DQ1 A17 A7 DQ5 VCC E VCC DQ2 NC A16 DQ6 VSS F DQ3 NC A14 A15 NC DQ7 G NC NC A12 A13 WE NC H A18 A8 A9 A10 A11 A19 2048 22 Input Row Buffer Decoder Memory Array 2048 x 4096 4096 DQ0 8 DQ1 DQ2 Data Input Buffer 8 DQ4 8 DQ5 DQ6 8 512 Column Decoder DQ7 CE1 CE2 WE OE VCC VSS Data Output Buffer Column I/O Write Driver Sense Amp DQ3 6 A Address 18 Control Address Input Buffer A11 A9 A8 A3 A2 A1 A0 A10 A19 48-ball BGA top view Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice. R0201-BS62LV8001 1 Revision 2.4 Oct. 2008 BS62LV8001 PIN DESCRIPTIONS Name Function A0-A19 Address Input These 20 address inputs select one of the 1,048,576 x 8-bit in the RAM CE1 Chip Enable 1 Input CE2 Chip Enable 2 Input CE1 is active LOW and CE2 is active HIGH. Both chip enables must be active when data read form or write to the device. If either chip enable is not active, the device is deselected and is in standby power mode. The DQ pins will be in the high impedance state when the device is deselected. The write enable input is active LOW and controls read and write operations. With the WE Write Enable Input chip selected, when WE is HIGH and OE is LOW, output data will be present on the DQ pins; when WE is LOW, the data present on the DQ pins will be written into the selected memory location. The output enable input is active LOW. If the output enable is active while the chip is OE Output Enable Input selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impendence state when OE is inactive. DQ0-DQ7 Data Input/Output Ports There 8 bi-directional ports are used to read data from or write data into the RAM. VCC Power Supply VSS Ground TRUTH TABLE MODE CE1 CE2 WE OE Not selected (Power Down) H X X X X L X X Output Disabled L H H Read L H Write L H I/O OPERATION VCC CURRENT High Z ICCSB, ICCSB1 H High Z ICC H L DOUT ICC L X DIN ICC ABSOLUTE MAXIMUM RATINGS (1) SYMBOL VTERM TBIAS TSTG PARAMETER Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature RATING (2) -0.5 to 7.0 OPERATING RANGE UNITS RANG AMBIENT TEMPERATURE V Commercial 0 C to + 70 C Industrial -40 C to + 85 C -40 to +125 O C -60 to +150 O C PT Power Dissipation 1.0 W IOUT DC Output Current 20 mA O O O 2.4V ~ 5.5V 2.4V ~ 5.5V CAPACITANCE (1) (TA = 25OC, f = 1.0MHz) SYMBOL PAMAMETER CONDITIONS MAX. UNITS 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. –2.0V in case of AC pulse width less than 30 ns. R0201-BS62LV8001 O VCC CIN CIO Input Capacitance Input/Output Capacitance VIN = 0V 6 pF VI/O = 0V 8 pF 1. This parameter is guaranteed and not 100% tested. 2 Revision 2.4 Oct. 2008 BS62LV8001 DC ELECTRICAL CHARACTERISTICS (TA =-40OC to +85OC) PARAMETER NAME PARAMETER TEST CONDITIONS MIN. TYP.(1) MAX. UNITS 2.4 -- 5.5 V 0.8 V VCC Power Supply VIL Input Low Voltage -0.5 -- VIH Input High Voltage 2.2 -- IIL Input Leakage Current -- -- 1 uA ILO Output Leakage Current -- -- 1 uA VOL Output Low Voltage VCC = Max, IOL = 2.0mA -- -- 0.4 V VOH Output High Voltage VCC = Min, IOH = -1.0mA 2.4 -- -- V -- -- -- -- -- -- ICC(5) ICC1 ICCSB ICCSB1(6) (2) VIN = 0V to VCC VI/O = 0V to VCC, CE1= V IH or CE2= V IL, or OE = VIH Operating Power Supply CE1 = VIL and CE2 = VIH, Current IDQ = 0mA, f = FMAX VCC=3.0V (4) VCC=5.0V Operating Power Supply CE1 = VIL and CE2 = VIH, VCC=3.0V Current IDQ = 0mA, f = 1MHz VCC=5.0V Standby Current – TTL Standby Current – CMOS CE1 = VIH, or CE2 = VIL, VCC=3.0V IDQ = 0mA VCC=5.0V CE1≧VCC-0.2V or CE2≦0.2V, VCC=3.0V VIN ≧VCC-0.2V or V IN ≦0.2V VCC=5.0V O -- VCC+0.3 31 (3) V mA 76 2 mA 10 1.0 2.0 0.8 8.0 3.5 50 mA uA 4. FMAX=1/tRC. O 5. ICC (MAX.) is 30mA/75mA at VCC=3.0V/5.0V and TA=70 C. O 6. ICCSB1(MAX.) is 4.0uA/25uA at VCC=3.0V/5.0V and TA=70 C. 1. Typical characteristics are at TA=25 C and not 100% tested. 2. Undershoot: -1.0V in case of pulse width less than 20 ns. 3. Overshoot: VCC+1.0V in case of pulse width less than 20 ns. DATA RETENTION CHARACTERISTICS (TA = -40OC to +85OC) SYMBOL PARAMETER VDR VCC for Data Retention ICCDR(3) Data Retention Current tCDR tR TEST CONDITIONS CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V CE1≧VCC-0.2V or CE2≦0.2V, VIN≧VCC-0.2V or VIN≦0.2V Chip Deselect to Data Retention Time MIN. TYP. (1) MAX. UNITS 1.5 -- -- V -- 0.4 4.0 uA 0 -- -- ns -- -- ns See Retention Waveform Operation Recovery Time tRC (2) O 1. VCC=1.5V, TA=25 C and not 100% tested. 2. tRC = Read Cycle Time. O 3. ICCRD(Max.) is 2.0uA at TA=70 C. LOW VCC DATA RETENTION WAVEFORM (1) (CE1 Controlled) Data Retention Mode VCC CE1 R0201-BS62LV8001 VCC VDR≧1.5V VIH VCC tR tCDR CE1≧VCC - 0.2V 3 VIH Revision 2.4 Oct. 2008 BS62LV8001 LOW VCC DATA RETENTION WAVEFORM (2) (CE2 Controlled) Data Retention Mode VDR≧1.5V VCC VCC VCC tCDR CE2 tR CE2≦0.2V VIL VIL AC TEST CONDITIONS KEY TO SWITCHING WAVEFORMS (Test Load and Input/Output Reference) Input Pulse Levels Vcc / 0V Input Rise and Fall Times 1V/ns Input and Output Timing Reference Level 0.5Vcc Output Load WAVEFORM tCLZ, tOLZ, tCHZ, tOHZ, tWHZ CL = 5pF+1TTL Others CL = 30pF+1TTL ALL INPUT PULSES VCC 1 TTL Output 90% GND (1) CL 90% 10% 10% → ← Rise Time : 1V/ns → ← Fall Time : 1V/ns INPUTS OUTPUTS MUST BE STEADY MUST BE STEADY MAY CHANGE FROM “H” TO “L” WILL BE CHANGE FROM “H” TO “L” MAY CHANGE FROM “L” TO “H” WILL BE CHANGE FROM “L” TO “H” DON’T CARE ANY CHANGE PERMITTED CHANGE : STATE UNKNOW DOES NOT APPLY CENTER LINE IS HIGH INPEDANCE “OFF” STATE 1. Including jig and scope capacitance. AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) READ CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. TYP. MAX. DESCRIPTION CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. MAX. UNITS tAVAX tRC Read Cycle Time 55 -- -- 70 -- -- ns tAVQX tAA Address Access Time -- -- 55 -- -- 70 ns tE1LQV tACS1 Chip Select Access Time (CE1) -- -- 55 -- -- 70 ns tE2HQV tACS2 Chip Select Access Time (CE2) -- -- 55 -- -- 70 ns tGLQV tOE -- -- 25 -- -- 30 ns tE1LQX tCLZ1 Chip Select to Output Low Z (CE1) 10 -- -- 10 -- -- ns tE2HQX tCLZ2 Chip Select to Output Low Z (CE2) 10 -- -- 10 -- -- ns tGLQX tOLZ Output Enable to Output Low Z 10 -- -- 10 -- -- ns tE1HQZ tCHZ1 Chip Select to Output High Z (CE1) -- -- 30 -- -- 35 ns tE2LQZ tCHZ2 Chip Select to Output High Z (CE2) -- -- 30 -- -- 35 ns tGHQZ tOHZ Output Enable to Output High Z -- -- 25 -- -- 30 ns tAVQX tOH Data Hold from Address Change 10 -- -- 10 -- -- ns R0201-BS62LV8001 Output Enable to Output Valid 4 Revision 2.4 Oct. 2008 BS62LV8001 SWITCHING WAVEFORMS (READ CYCLE) READ CYCLE 1 (1,2,4) tRC ADDRESS tAA tOH tOH DOUT READ CYCLE 2 (1,3,4) CE1 tACS1 CE2 DOUT tACS2 tCLZ tCHZ1, tCHZ2(5) (5) READ CYCLE 3 (1, 4) tRC ADDRESS tAA OE tOE tOH tOLZ CE1 tACS1 tCLZ1(5) CE2 tACS2 tCLZ2(5) tOHZ(5) tCHZ1(1,5) tCHZ2(1,5) DOUT NOTES: 1. WE is high in read Cycle. 2. Device is continuously selected when CE1 = VIL and CE2= VIH. 3. Address valid prior to or coincident with CE1 transition low and/or CE2 transition high. 4. OE = VIL. 5. Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. R0201-BS62LV8001 5 Revision 2.4 Oct. 2008 BS62LV8001 AC ELECTRICAL CHARACTERISTICS (TA = -40OC to +85OC) WRITE CYCLE JEDEC PARANETER PARAMETER NAME NAME CYCLE TIME : 55ns (VCC = 3.0~5.5V) MIN. TYP. MAX. DESCRIPTION CYCLE TIME : 70ns (VCC = 2.7~5.5V) MIN. TYP. MAX. UNITS tAVAX tWC Write Cycle Time 55 -- -- 70 -- -- ns tAVWL tAS Chip Select to End of Write 0 -- -- 0 -- -- ns tAVWH tAW Address Set up Time 40 -- -- 50 -- -- ns tE1LWH tCW Address Valid to End of Write 40 -- -- 50 -- -- ns tWLWH tWP Write Pulse Width 30 -- -- 35 -- -- ns tWHAX tWR1 Write Recovery Time (CE1, WE) 0 -- -- 0 -- -- ns tE2LAX tWR2 Write Recovery Time (CE2) 0 -- -- 0 -- -- ns tWLQZ tWHZ Write to Output High Z -- -- 25 -- -- 30 ns tDVWH tDW Data to Write Time Overlap 25 -- -- 30 -- -- ns tWHDX tDH Data Hold from Write Time 0 -- -- 0 -- -- ns tGHQZ tOHZ Output Disable to Output in High Z -- -- 25 -- -- 30 ns tWHQX tOW End of Write to Output Active 5 -- -- 5 -- -- ns SWITCHING WAVEFORMS (WRITE CYCLE) WRITE CYCLE 1 (1) tWC ADDRESS tWR1(3) OE tCW(11) CE1 (5) CE2 (5) tAW WE tCW(11) tWR2(3) tWP(2) tAS tOHZ(4,10) DOUT tDH tDW DIN R0201-BS62LV8001 6 Revision 2.4 Oct. 2008 BS62LV8001 WRITE CYCLE 2 (1,6) tWC ADDRESS CE1 tCW(11) (5) CE2 (5) tAW WE tAS tCW(11) tWR2(3) tWP(2) tWHZ(4,10) tOW (7) (8) DOUT tDW tDH (8,9) DIN NOTES: 1. WE must be high during address transitions. 2. The internal write time of the memory is defined by the overlap of CE1 and CE2 active and WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. tWR is measured from the earlier of CE1 or WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the CE1 low transition or the CE2 high transition occurs simultaneously with the WE low transitions or after the WE transition, output remain in a high impedance state. 6. OE is continuously low (OE = VIL). 7. DOUT is the same phase of write data of this write cycle. 8. DOUT is the read data of next address. 9. If CE1 is low and CE2 is high during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10.Transition is measured ± 500mV from steady state with CL = 5pF. The parameter is guaranteed but not 100% tested. 11.tCW is measured from the later of CE1 going low or CE2 going high to the end of write. R0201-BS62LV8001 7 Revision 2.4 Oct. 2008 BS62LV8001 ORDERING INFORMATION BS62LV8001 X X Z YY SPEED 55: 55ns 70: 70ns PKG MATERIAL G: Green, RoHS Compliant P: Pb free, RoHS Compliant GRADE o o C: +0 C ~ +70 C o o I: -40 C ~ +85 C PACKAGE D: DICE E: TSOP II-44 F: BGA-48-0912 Note: BSI (Brilliance Semiconductor Inc.) assumes no responsibility for the application or use of any product or circuit described herein. BSI does not authorize its products for use as critical components in any application in which the failure of the BSI product may be expected to result in significant injury or death, including life-support systems and critical medical instruments. PACKAGE DIMENSIONS TSOP II-44 R0201-BS62LV8001 8 Revision 2.4 Oct. 2008 BS62LV8001 0.25±0.05 PACKAGE DIMENSIONS (continued) NOTES: 1: CONTROLLING DIMENSIONS ARE IN MILLIMETERS. 2: PIN#1 DOT MARKING BY LASER OR PAD PRINT. 1.2 Max. 3: SYMBOL "N" IS THE NUMBER OF SOLDER BALLS. SIDE VIEW D 3.375 0.1 D1 N D E D1 E1 e 48 12.0 9.0 5.25 3.75 0.75 E±0.1 2.625 E1 e SOLDER BALL 0.35 ±0.05 VIEW A 48 mini-BGA (9mm x 12mm) R0201-BS62LV8001 9 Revision 2.4 Oct. 2008 BS62LV8001 Revision History Revision No. History Draft Date 2.2 Add Icc1 characteristic parameter Improve Iccsb1 spec. I-grade from 110uA to 50uA at 5.0V 10uA to 8.0uA at 3.0V C-grade from 55uA to 25uA at 5.0V 5.0uA to 4.0uA at 3.0V Jan. 13, 2006 2.3 Change I-grade operation temperature range - from –25OC to –40OC Change Iccdr spec. I-grade from 2.5uA to 4.0uA C-grade from 1.3uA to 2.0uA Typical from 0.8 to 0.4uA May. 25, 2006 2.4 Typical value of standby current is replaced by maximum value in Featues and Description section Oct. 31, 2008 Remark Remove “-: Normal” (Leaded) PKG Material in ordering information R0201-BS62LV8001 10 Revision 2.4 Oct. 2008