ON FAN5909UCX Multi-mode buck converter Datasheet

FAN5909
Multi-Mode Buck Converter
with LDO Assist for GSM /
EDGE, 3 G/3.5 G and 4 G PAs
Description
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The FAN5909 is a high−efficiency, low−noise, synchronous,
step−down, DC−DC converter optimized for powering Radio
Frequency (RF) Power Amplifiers (PAs) in handsets and other mobile
applications. Load currents up to 2.5 A are allowed, which enables
GSM / EDGE, 3 G/3.5 G, and 4G platforms under very poor VSWR
conditions.
1
The output voltage may be dynamically adjusted from 0.40 V to
WLCSP
3.60 V, proportional to an analog input voltage VCON ranging from
16 BUMP
0.16 V to 1.44 V, optimizing power−added efficiency. Fast transition
CASE 567SD
times of less than 6 ms are achieved, allowing excellent inter−slot
settling.
An integrated LDO is automatically enabled under heavy load
conditions or when the battery voltage and voltage drop across the
DC−DC PMOS device are within a set range of the desired output
voltage. This LDO−assist feature supports heavy load currents under
the most stringent battery and VSWR conditions while maintaining
high efficiency, low dropout, and superior spectral performance.
The FAN5909 DC−DC operates in PWM Mode with a
• Input Under−Voltage Lockout / Thermal Shutdown
2.9 MHz switching frequency and supports a single, small
• 1.615 mm x 1.615 mm, 16−Bump, 0.4 mm Pitch
form−factor inductor ranging from 1.0 mH to 2.2 mH. In
WLCSP
addition, PFM operation is allowed at low load currents for
• 2.9 MHz PWM Mode
output voltages below 1.5 V to maximize efficiency. PFM
• 6 ms Output Voltage Step Response for early Tx
operation can be disabled by setting MODE pin to LOW.
Power−Loop Settling with 14 mF Load Capacitance
When output regulation is not required, the FAN5909 may
• Sleep Mode for ~50 mA Standby Current Consumption
be placed in Sleep Mode by setting VCON below 100 mV
nominally. This ensures a very low IQ (<50 mA) while
• Forced PWM Mode
enabling a fast return to output regulation.
♦ Up to 95% Efficient Synchronous Operation in High
FAN5909 is available in a low profile, small form factor,
Power Conditions
16 bump, Wafer−Level Chip−Scale Package (WLCSP) that
♦ 2.9 MHz PWM−Only Mode
is 1.615 mm x 1.615 mm. Only three external components
• Auto PFM/PWM Mode
are required: two 0402 capacitors and one 2016 inductor.
♦ 2.9 MHz PWM Operation at High Power and PFM
Operation at Low Power and Low Output Voltage
Features
for Maximum Low Current Efficiency
• Solution Size < 9.52 mm2
• 2.7 V to 5.5 V Input Voltage Range
Applications
• Dynamic Supply Bias for Polar or Linear GSM / EDGE
• VOUT Range from 0.40 V to 3.60 V (or VIN)
PAs and 3 G/3.5 G and 4 G PAs
• Single, Small Form−Factor Inductor
•
Dynamic Supply Bias for GSM / EDGE Quad Band
• 29 mW Integrated LDO
Amplifiers for Mobile Handsets and Data Cards
• 100% Duty Cycle for Low−Dropout Operation
ORDERING INFORMATION
Part Number
Output Voltage
Temperature Range
Package
Packing†
FAN5909UCX
0.4 V to PVIN
−40°C to +85°C
1.615 mm x 1.615 mm, 16−Bump 0.4 mm Pitch,
Wafer−Level Chip−Scale Package (WLCSP)
Tape and Reel
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2013
November, 2017 − Rev. 2
1
Publication Order Number:
FAN5909/D
FAN5909
Block Diagrams
10 mF
220 pF
PVIN
FB
PVIN
VOUT
0.4V to3.6V
up to 2.5A for
VBAT >3.7V
Up to3A in
Bypass Mode
VOUT
1.0 mH
AVIN
VIN
2.7V to
5.5V
SW
FAN5909
VOUT
SW
BPEN
4.7 mF
PGND
PGND
MODE
PGND
6.8pF
4.7μF
EN
From
External
DAC
AGND
VCON
Figure 1. Typical Application
1. The three 4.7 mF capacitors include the FAN5909 output capacitor and PA bypass capacitors.
2. Regulator requires only one 4.7 mF; the VOUT bus should not exceed 14 mF capacitance over DC bias and temperature.
PVIN
VOUT
LDO
Assist
FB
AVIN
Positive
Current Limit
AGND
VCON
PFM/ PWM
Controller
SW
BPEN
MODE
EN
3MHz
Oscillator
to PWM
Controller
Negative
Current Limit
Figure 2. Simplified Block Diagram
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2
PGND
4.7μF
FAN5909
Pin Configuration
PGND
SW
PVIN
VOUT
VOUT
PVIN
SW
PGND
A1
A2
A3
A4
A4
A3
A2
A1
B1
B2
B3
B4
B4
B3
B2
B1
AGND
EN
BPEN
PGND
PGND
BPEN
EN
AGND
C1
C2
C3
C4
C4
C3
C2
C1
FB
FB
MODE
VCON
AVIN
D4
D4
D3
D2
D1
AVIN
VCON MODE
D1
D2
D3
Figure 3. Bumps Face Down – Top−Through View
Figure 4. Bumps Face Up
PIN DEFINITIONS
Pin #
Name
Description
C1
AGND
Analog ground, reference ground for the IC. Follow PCB routing notes for connecting this pin.
A4, B4
VOUT
Output voltage sense pin. Connect to VOUT to establish feedback path for regulation point. Connect
together on PCB.
D4
FB
Feedback pin. Connect to positive (+) pad of COUT on VOUT.
C2
EN
Enables switching when HIGH; Shutdown Mode when LOW. This pin should not be left floating.
D2
VCON
Analog control pin. Shield signal routing against noise.
D1
AVIN
Analog supply voltage input. Connect to PVIN.
C3
BPEN
Force Bypass Mode when HIGH; Auto Bypass Mode when LOW. This pin should not be left floating.
D3
MODE
When MODE is HIGH, the DC−DC permits PFM operation under low load currents and PWM operation
under heavy load currents. When MODE pin is set LOW, the DC−DC operates in forced PWM operation. This pin should not be left floating.
A3, B3
PVIN
A2, B2
SW
A1, B1,C4
PGND
Supply voltage input to the internal MOSFET switches. Connect to input power source.
Switching node of the internal MOSFET switches. Connect to output inductor.
Power ground of the internal MOSFET switches. Follow routing notes for connections between PGND
and AGND.
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3
FAN5909
Table 1. ABSOLUTE MAXIMUM RATINGS
Symbol
Min
Max
Unit
Voltage on AVIN, PVIN
−0.3
6.0
V
Voltage on Any Other Pin
−0.3
AVIN + 0.3
TJ
Junction Temperature
−40
+125
°C
TSTG
Storage Temperature
−65
+150
°C
+260
°C
VIN
TL
ESD
LU
Parameter
Lead Soldering Temperature (10 Seconds)
Electrostatic Discharge Protection Level
Human Body Model, JESD22−A114
2.0
Charged Device Model, JESD22−C101
1.0
Latch Up
kV
JESD 78D
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
Table 2. RECOMMENDED OPERATING CONDITIONS
Symbol
Parameter
Min
Typ
Max
Unit
VIN
Supply Voltage Range
2.7
5.5
V
VOUT
Output Voltage Range
0.35
<VIN
V
4.5
A
IOUT_BYPASS
IOUT
L
CIN
COUT
Output Current in Bypass Mode (100% Duty Cycle)
Output Current
3.0
A
Inductor
1
mH
Input Capacitor (Note 3)
10
mF
Output Capacitor (Note 4)
4.7
mF
TA
Operating Ambient Temperature Range
−40
+85
°C
TJ
Operating Junction Temperature Range
−40
+125
°C
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
3. The input capacitor must be large enough to limit the input voltage drop during GSM bursts, bypass transitions, and large output voltage
transitions.
4. Regulator requires only one 4.7 mF; the VOUT bus should not exceed 14 mF capacitance over DC bias and temperature.
Table 3. DISSIPATION RATINGS
Symbol
qJA
Parameter
Min
Junction−to−Ambient Thermal Resistance (Note 5)
Typ
40
Max
Unit
°C/W
5. Junction−to−ambient thermal resistance is a function of application and board layout. This data is measured with four−layer 2s2p boards
with vias in accordance to JESD51− JEDEC standard. Special attention must be paid not to exceed junction temperature TJ(MAX) at a given
ambient temperature TA.
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FAN5909
Table 4. ELECTRICAL CHARACTERISTICS, ALL MODES Recommended operating conditions, unless otherwise noted, circuit
per Figure 1, VIN = 2.7 V to 5.5 V, TA = −40°C to +85°C. Typical values are given VIN = 3.8 V at TA = 25°C. L = 1 mH, Toko DFE201610C,
CIN = 10 mF 0402 TDK C1005X5R0J106MT, COUT = 3 x 4.7 mF 0402 TDK C1005X5R0J475KT.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
5.5
V
0.5
3.0
mA
2.45
2.60
V
POWER SUPPLIES
VIN
Input Voltage Range
IOUT ≤ 2.5 A
ISD
Shutdown Supply Current
EN = 0 V, MODE = 0
Under Voltage Lockout Threshold
VIN Rising
VUVLO
2.7
2.20
Hysteresis
250
mV
LOGIC CONTROL
VIH
VIL
ICTRL
Logic Threshold Voltage;
EN, BPEN, MODE
Input HIGH Threshold
Logic Control Input Bias Current;
EN, BPEN, MODE
VIN or GND
1.2
V
Input LOW Threshold
0.01
0.4
V
1.00
mA
ANALOG CONTROL
VCON_LDO_EN1
VCON Forced Bypass Enter (Note 6)
VCON Voltage that Forces Bypass;
VIN = 4.0 V – 4.75 V
VCON_LDO_EN2
VCON Forced Bypass Enter (Note 6)
VCON Voltage that Forces Bypass;
VIN ≈ VOUT
VCON_LDO_EX
VCON Forced Bypass Exit
VCON Voltage that Exits Forced Bypass; VIN = 2.70 V – 4.75 V
Vcon_SL_en
Vcon Sleep Enter
VCON Voltage Forcing Low IQ Sleep
Mode
Vcon_SL_ex
Vcon Sleep Exit
VCON Voltage that Exits SLEEP Mode
DC−DC Quiescent Current in Sleep Mode
VCON < 70 mV
IQ
Gain
VOUT_ACC
1.6
VIN/2.5
V
1.4
70
V
mV
50
Gain in Control Range 0.16 V to 1.44 V
VOUT Accuracy
V
125
mV
80
mA
+50
mV
2.5
Ideal = 2.5 x VCON
−50
LDO
RFET
LDO FET Resistance
ΔVOUT_LDO
LDO Dropout (Note 7)
29
mW
IOUT = 2.0 A
100
mV
Rising Temperature
+150
°C
Hysteresis
+20
°C
OVER TEMPERATURE PROTECTION
TOTP
Over−Temperature Protection
OSCILLATOR
fSW
Average Oscillator Frequency
2.6
2.9
3.2
MHz
DC−DC
RDSON
PMOS On Resistance
VIN = VGS = 3.7 V
80
NMOS On Resistance
VIN = VGS = 3.7 V
60
mW
ILIMp
P−Channel Current Limit (Note 8)
1.50
1.90
2.30
A
ILIMn
N−Channel Current Limit (Note 8)
1.50
1.90
2.30
A
3.7
4.5
A
4.5
A
IDischarge
ILIMLDO
Maximum Transient Discharge Current
LDO Current Limit
6.
7.
8.
9.
Input voltages nominally exceeding the lesser of VIN/2.5 or 1.6 V force 100% duty cycle.
Dropout depends on LDO and DC−DC PFET RDSON and inductor DCR.
The current limit is the peak (maximum) current.
Guaranteed by design. Maximum values are based on simulation results with 50% COUT derating; not tested in production. Voltage transient only. Assumes COUT = 3 x 4.7 mF (1x4.7 mF for regulator and 2x4.7 mF for PA decoupling capacitors).
10. Protects part under short−circuit conditions
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FAN5909
Table 4. ELECTRICAL CHARACTERISTICS, ALL MODES Recommended operating conditions, unless otherwise noted, circuit
per Figure 1, VIN = 2.7 V to 5.5 V, TA = −40°C to +85°C. Typical values are given VIN = 3.8 V at TA = 25°C. L = 1 mH, Toko DFE201610C,
CIN = 10 mF 0402 TDK C1005X5R0J106MT, COUT = 3 x 4.7 mF 0402 TDK C1005X5R0J475KT.
Symbol
Parameter
Condition
Min
Typ
Max
Unit
DC−DC
VOUT_MIN
Minimum Output Voltage
VCON = 0.16 V
0.35
0.40
0.45
V
VOUT_MAX
Maximum Output Voltage
VCON = 1.44 V, VIN = 3.9 V
3.55
3.60
3.65
V
DC−DC EFFICIENCY
ηPower
Power Efficiency, Low−Power Auto Mode,
VIN = 3.7 V
VOUT = 3.1 V, ILOAD = 250 mA
95
VOUT = 1.8 V, ILOAD = 250 mA
90
VOUT = 0.5 V, ILOAD = 10 mA
65
%
OUTPUT REGULATION
VOUT_RLine
VOUT Line Regulation
3.1 ≤ VIN ≤ 3.7
±5
mV
VOUT_RLoad
VOUT Load Regulation
20 mA ≤ IOUT ≤ 800 mA
±25
mV
VOUT_Ripple
VOUT Ripple
PFM Mode, VIN = 3.7 V,
IOUT < 100 mA
11
mV
PWM Mode, VIN = 3.7 V
4
Startup Time (Note 9)
VIN = 3.7 V, VOUT from 0 V to 3.1 V,
COUT = 3 x 4.7 mF, 10 V, X5R
50
60
ms
tDC−DC_TR
VCON Step Response Rise Time (Note 9)
From VCON to 95% VOUT, DVOUT ≤
2.7 V (0.7 V – 3.4 V), RLOAD = 5 W,
COUT = 14 mF
6.0
7.3
ms
tDC−DC_TF
VCON Step Response Fall Time (Note 9)
From VCON to 5% VOUT, DVOUT
2.7 V (3.4 V – 0.7 V), RLOAD = 200 W,
COUT = 14 mF
6.8
7.6
ms
tDC−DC_CL
Maximum Allowed Time for Consecutive
Current Limit (Note 10)
VOUT < 1 V
tDCDC_CLR
Consecutive Current Limit Recovery Time
(Note 10)
TIMING
tSS
1500
ms
4800
ms
6.
7.
8.
9.
Input voltages nominally exceeding the lesser of VIN/2.5 or 1.6 V force 100% duty cycle.
Dropout depends on LDO and DC−DC PFET RDSON and inductor DCR.
The current limit is the peak (maximum) current.
Guaranteed by design. Maximum values are based on simulation results with 50% COUT derating; not tested in production. Voltage transient only. Assumes COUT = 3 x 4.7 mF (1x4.7 mF for regulator and 2x4.7 mF for PA decoupling capacitors).
10. Protects part under short−circuit conditions
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
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FAN5909
Typical Characteristics
Unless otherwise noted, VIN = EN = 3.7 V, L = 1.0 mH, CIN = 10 mF, COUT = 3 x 4.7 mF, and TA = +25°C.
100
100
95
95
90
90
85
75
70
VOUT = 0.5V
VOUT = 1.0V
VOUT = 1.5V
VOUT = 2.0V
VOUT = 2.5V
VOUT = 3.0V
65
60
55
50
0
20
40
60
80
100
120
140
85
Efficiency (%)
Efficiency (%)
80
80
VOUT = 1.6V
VOUT = 2.0V
VOUT = 2.5V
VOUT = 3.0V
VOUT = 3.5V
75
70
65
60
160
0 100200300400500600700800
Load Current (mA)
Load Current (mA)
Figure 5. Efficiency vs. Load Current and Output
Voltage, VIN = 3.8 V , IOUT = 10 mA to 150 mA
Figure 6. Efficiency vs. Load Current and Output
Voltage, VIN = 3.8 V
100
100
90
95
80
Efficiency (%)
Efficiency (%)
90
85
VOUT = 1.6V
VOUT = 2.0V
VOUT = 2.5V
VOUT = 3.0V
VOUT = 3.5V
80
75
70
0
200
400
600
800
70
60
50
VOUT = 2.0V
40
VOUT = 2.5V
VOUT = 3.0V
30
VOUT = 3.5V
20
1000
900
1200
1500
Load Current (mA)
Figure 7. Efficiency vs. Load Current and Output
Voltage, VIN = 3.8 V, IOUT = 100 mA to 1 A
2400
2700
4.5
4
3.4
3.5
Output Voltage (V)
Output Voltage (V)
2100
Figure 8. Efficiency vs. Load Current and Output
Voltage, VIN = 3.8 V, IOUT = 1 A to 2.5 A
3.6
3.2
3
2.8
2.6
2.4
1800
Load Current (mA)
3
2.5
2
1.5
1
0.5
0
2.533.544.555.5
Input Voltage (V)
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
VCON (V)
Figure 10. Output Voltage vs. VCON Voltage,
VIN = 4.2 V, RLOAD = 6.8 W, 0.1 V < VCON < 1.6 V
Figure 9. Output Voltage vs. Supply Voltage,
VOUT = 3.4 V, IOUT = 1.5 A, VIN = 4.3 V to Dropout
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FAN5909
Typical Characteristics
850
3.5
3.3
3.1
2.9
2.7
2.5
2.3
2.1
1.9
1.7
1.5
Quiescent Current ( mA)
Switching Frequency (MHz)
Unless otherwise noted, VIN = EN = 3.7 V, L = 1.0 mH, CIN = 10 mF, COUT = 3 x 4.7 mF, and TA = +25°C.
800
750
700
650
600
550
3 3.5 4 4.5 5 5.5
-40 °C
+25°C
+85°C
2.533.544.555.56
Input Voltage (V)
Input Voltage (V)
Quiescent Current (mA)
Figure 11. Center−Switching Frequency vs. Supply
Voltage, VOUT = 2.5 V, IOUT = 700 mA
20
18
16
14
12
10
8
6
4
2
0
Figure 12. Quiescent Current (PFM) vs. Supply
Voltage, VOUT = 1 V, 2.7 V < VIN < 5.5 V (No Load)
VOUT
2V/DIV
VCON
-40 °C
+25°C
2V/DIV
IOUT
+85°C
2.5
3
3.5
4
4.5
5
5.5
500mA/DIV
6
20ms/DIV
Input Voltage (V)
Figure 14. VCON Transient (3 G/4 G), VOUT = 0 V to
3 V, RLOAD = 6.8 W, VIN = 3.8 V, 100 ns Edge
Figure 13. Quiescent Current (PWM) vs. Supply
Voltage, VOUT = 2.5 V, 2.7 V < VIN < 5.5 V (No Load)
VOUT
2V/DIV
VOUT
2V/DIV
VCON
VCON
2V/DIV
1V/DIV
IOUT
IOUT
1A/DIV
500mA/DIV
20ms/DIV
20ms/DIV
Figure 15. VCON Transient (PFM to PWM), VOUT =
1.4 V to 3.4 V, RLOAD = 6.8 W, VIN = 3.8 V, 100 ns Edge
Figure 16. VCON Transient (PWM), VOUT = 1.4 V to
3.4 V, RLOAD = 1.9 W, VIN = 4.2 V, 100 ns Edge
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FAN5909
Typical Characteristics
Unless otherwise noted, VIN = EN = 3.7 V, L = 1.0 mH, CIN = 10 mF, COUT = 3 x 4.7 mF, and TA = +25°C.
VOUT
VOUT
10mV/DIV
20mV/ DIV
IOUT
IOUT
50mA/DIV
200mA/DIV
20ms/DIV
100ms/DIV
Figure 17. Load Transient in PFM Mode, VIN = 3.6 V,
VOUT = 1 V, IOUT = 0 mA to 60 mA, 1 ms Edge
Figure 18. Load Transient in PWM Mode, VIN = 3.8 V,
VOUT = 2.5 V, IOUT = 0 mA to 300 mA, 10 ms Edge
VOUT
VOUT
100mV/DIV
50mV/DIV
IOUT
IOUT
500mA/DIV
500mA/DIV
100ms/DIV
100ms/DIV
Figure 20. Load Transient in PWM Mode, VIN = 4.2 V,
VOUT = 3.0 V, IOUT = 0 mA to 1.2 A, 10 ms Edge
Figure 19. Load Transient in PWM Mode, VIN = 3.8 V,
VOUT = 3.0 V, IOUT = 0 mA to 700 mA, 10 ms Edge
VOUT
VOUT
50mV/DIV
50mV/DIV
VIN
VIN
1V/DIV
1V/DIV
100ms/DIV
100ms/DIV
Figure 21. Line Transient, VIN = 3.6 V to 4.2 V,
VOUT = 1.0 V, 6.8 W Load, 10 ms Edge
Figure 22. Line Transient, VIN = 3.6 V to 4.2 V,
VOUT = 2.5 V, 6.8 W Load, 10 ms Edge
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FAN5909
Typical Characteristics
Unless otherwise noted, VIN = EN = 3.7 V, L = 1.0 mH, CIN = 10 mF, COUT = 3 x 4.7 mF, and TA = +25°C.
SW
SW
2V/DIV
2V/DIV
2V/DIV
VOUT
1V/DIV
VOUT
2V/DIV
2V/DIV EN
EN
20ms/DIV
20ms/DIV
Figure 23. Startup in PFM Mode, VIN = 3.8 V,
VOUT = 1.0 V, No Load, EN = Low to High
Figure 24. Startup in PWM Mode, VIN = 4.2 V,
VOUT = 3.4 V, No Load, EN = Low to High
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FAN5909
Operating Description
The FAN5909 is a high−efficiency, synchronous,
step−down converter (DC−DC) with LDO−assist function.
The DC−DC converter operates with current−mode
control and supports a wide range of load currents.
High−current applications up to a 2.5 A DC output, such as
mandated by GSM/EDGE applications, are allowed.
Performance degradation due to spurs is removed by
spreading the ripple energy through clock dither. A
regulated Bypass Mode continues to regulate the output to
the desired voltage as VIN approaches VOUT. The LDO
offers a dropout voltage of approximately 100 mV under a
2 A load current.
The output voltage VOUT is regulated to 2.5 times the
input control voltage, VCON, set by an external DAC. The
FAN5909 operates in either PWM or PFM Mode, depending
on the output voltage and load current.
In Pulse Width Modulation (PWM) Mode, regulation
begins with on−state. A P−channel transistor is turned on
and the inductor current is ramped up until the off−state
begins. In the off−state, the P−channel is switched off and an
N−channel transistor is turned on. The inductor current
decreases to maintain an average value equal to the DC load
current. The inductor current is continuously monitored. A
current sense flags when the P−channel transistor current
exceeds the current limit and the switcher is turned back to
off−state to decrease the inductor current and prevent
magnetic saturation. The current sense flags when the
N−channel transistor current exceeds the current limit and
redirects discharging current through the inductor back to
the battery.
In Pulse Frequency Modulation (PFM) Mode, the
FAN5909 operates in a constant on−time mode at low load
currents. During on−state, the P−channel is turned on for a
specified time before switching to off−state. In off−state, the
N−channel switch is enabled until inductor current
decreases to 0 A. The switcher enters three−state until a new
regulation cycle starts.
PFM operation is allowed only in Low−Power Mode
(MODE=1) for output voltages nominally less than 1.5 V. At
low load currents, PFM achieves higher efficiency than
PWM. The trade−off for efficiency improvement, however,
is larger output ripple. Some applications, such as audio,
may not tolerate the higher ripple, especially at high output
voltages.
In all cases, it is recommended that sharp VCON
transitions be applied, letting the transition controller
optimize the output voltage slew rate.
DVOUT Positive Step
After a VCON positive step, the FAN5909 enters
Current−Limit Mode, where VOUT ramps with a constant
slew rate dictated by the output capacitor and the current
limit.
DVOUT Negative Step
After a VCON negative step, the FAN5909 enters Current
Limit Mode where VOUT is reduced with a constant slew
rate dictated by the output capacitor and the current limit.
VOUT Transition to or from Forced Bypass
The DC−DC is forced into 100% duty cycle for VCON
nominally greater than 1.6 V. This allows the output to be
connected to the supply through both the low−resistance
DC−DC and the LDO PFETs.
VOUT Transition at Startup
At startup, after the EN rising edge is detected, the system
requires 25 ms for all internal voltage references and
amplifiers to start before enabling the DC−DC converter
function.
MODE Pin
The MODE pin enable Forced PWM Mode or Auto
PFM / PWM Mode. When the MODE pin is toggled HIGH
(logic 1), the FAN5909 operates in PFM for VOUT < 1.5 V
under light−load conditions and PWM for heavy−load
conditions. If the MODE pin is set LOW (logic = 0), it
operates in Forced PWM Mode.
Auto PFM / PWM Mode (MODE = 1)
Auto PFM/PWM Mode is appropriate for 3 G/3.5 G and
4 G applications.
Forced PWM Mode (MODE = 0)
Forced PWM Mode is appropriate for applications that
demand minimal ripple over the entire output voltage range.
DC−DC – LDO−Assist
The LDO−assist function maintains output regulation
when VIN approaches VOUT, enables fast transition times
under heavy loads, and minimizes PCB space by enabling a
smaller inductor to be employed by using the LDO to
provide a portion of the necessary load current.
The LDO−assist function limits the maximum current that
the DC−DC may supply by shunting current away from the
DC−DC under heavy loads and high duty cycles. In addition,
the LDO−assist enables a seamless transition into 100%
duty cycle, ensuring both low output ripple and constant
output regulation. Since the LDO−assist function limits the
maximum current supplied by the DC−DC, PCB area is
minimized by enabling a lower current capable, and thus
smaller form factor, inductor to be used.
Dynamic Output Voltage Transitions
FAN5909 has a complex voltage transition controller that
realizes 6 ms transition times with a large output capacitor
and output voltage ranges.
The transition controller manages five transitions:
• DVOUT positive step
• DVOUT negative step
• DVOUT transition to or from 100% duty cycle
• DVOUT transition at startup
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FAN5909
DC−DC – Sleep Mode
The Sleep Mode minimizing current while enabling rapid
return to regulation. Sleep Mode is entered when VCON is
held below 70 mV for at least 40 ms. In this mode, current
consumption is reduced to under 50 mA. Sleep Mode is
exited after ~12 ms when VCON is set above 125 mV.
Application Information
Figure 26 illustrates the FAN5909 in a GSM / EDGE /
WCDMA transmitter configuration, driving multiple GSM
/ EDGE and 3 G/3.5 G and 4 G PAs. Figure 27 presents a
timing diagram designed to meet GSM specifications.
DC Output Voltage
Figure 25. Output Voltage vs. Control Voltage
The output voltage is determined by VCON provided by an
external DAC or voltage reference:
V OUT + 2.5
V CON
The FAN5909 is designed to support voltage transients of
6 ms when configured for GSM/EDGE applications
(MODE=0) and driving a load capacitance of approximately
14 mF. Figure 28 shows a timing diagram for WCDMA
applications.
(eq. 1)
The FAN5909 provides regulated VOUT only if VCON
falls within the typical range from 0.16 V to 1.44 V. This
allows VOUT to be adjusted between 0.4 V and 3.6 V. If
VCON is less than 0.16 V, VOUT is clamped to 0.40 V. In
Auto PFM/PWM Mode, the FAN5909 automatically
switches between PFM and PWM. In Forced PWM Mode
(MODE = 0), the FAN5909 automatically switches into
PWM Mode.
4.7mF
0402
PA
GSM/ EGSM
850/900MHz
PA
PCS/DCS
1800/1900MHz
LB_IN
FB
PVIN
RFOUT
VRAMP
0.4V to3.5V
up to 2.5A for
VBAT > 3.7V.
Up to 3A in
Bypass Mode
FAN5909
470nF
0201
HB_IN
220pF
0201
VIN
2.7V to 5.5V
10mF
0402
GSM/EDGE
PAM
LDO
Assist
AVIN
VOUT
2.9MHz
Switcher
BPEN
GPIO
GPIO
GPIO
Baseband
Processor
DAC
SW
PFM/ PWM
Controller
1mH
4.7mF
0402
MODE
PGND
EN
VOUT
6.8pF
0201
0.4V to3.4V
Up to
800mA
4.7mF
0402
470nF
0201
PA
UMTS BAND1, …, 9
Reference
AGND
470nF
0201
VCON
Bandgap
PA
UMTS BAND1, …, 9
470nF
0201
*One 4.7μF capacitor can be replaced by a
4.7μF decoupling capacitor at the GSM PAs
.
**220pF and 6.8μF capacitors are optional.
PA
UMTS BAND1, …, 9
470nF
0201
PA
UMTS BAND1, …, 9
Figure 26. Typical Application Diagram with GSM/EDGE/WCDMA Transmitters
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FAN5909
50 μs
DC−DC_ EN
MODE
VCON
DC−DC VOUT
7.3μs
3.4V
DC −DC
2.5 x VCON
0. 7V to 3.4V
0.7V
VRAMP
PA
PA_TX_EN
RF Packet
ANTENNA
Figure 27. Timing Diagram for GSM/EDGE Transmitters
50μs
DC−DC _ EN
MODE
VCON
7.3 μs
DC−DC VOUT
2.5 x VCON
3.4V
DC−DC
0.7V
PA _TX_EN
PA
Continuous RF
ANTENNA
Figure 28. Timing Diagram for WCDMA Transmitters
Inductor Selection
A 6.8 pF capacitor may be added in parallel with COUT to
reduce the capacitor’s parasitic inductance.
The FAN5909 operates at 2.9 MHz switching frequency,
allowing 1.0 mH or 1.5 mH inductors to be used in designs.
For applications requiring the smallest possible PCB area,
use a 1.0 mH 2012 inductor or a 1.0 mH 2016 inductor for
optimum efficiency performance.
Table 6. RECOMMENDED CAPACITOR VALUES
Capacitor
CIN
10 mF, ±20%, X5R, 6.3 V, 0402
(1005 metric) TDK C1005X5R0J106M
COUT
4.7 mF, ±20%, X5R, 6.3 V, 0402
(1005 metric) TDK C1005X5R0J475K
Table 5. RECOMMENDED INDUCTORS
Inductor
L
Description
1.0 mH ±20%, 2.1 A, 2012 Case Size
Cyntec: PSK20121T−1R0MS−63
Description
PCB Layout and Component Placement
• The key point in the placement is the power ground
1.0 mH ±20%, 2.2 A, 2016 Case Size
Toko: DFE201610R−H−1R0M
Capacitor Selection
The minimum required output capacitor COUT should be
one (1) 4.7 mF, 6.3 V, X5R with an ESR of 10 mW or lower
and an ESL of 0.3 nH or lower in parallel after inductor L1.
Larger case sizes result in increased loop parasitic
inductance and higher noise. One 4.7 mF capacitor should be
used as a decoupling capacitor at the GSM/EDGE PA VCC
pin and another 4.7 mF capacitor should be placed at VCC pin
of the 3 G/4 G PA.
•
•
•
(PGND) connection shared between the FAN5909,
CIN, and COUT. This minimizes the parasitic
inductance of the switching loop paths.
Place the inductor away from the feedback pins to
prevent unpredictable loop behavior.
Ensure the traces are wide enough to handle the
maximum current value, especially in Bypass Mode.
Ensure the vias are able to handle the current density.
Use filled vias if available.
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13
FAN5909
PACKAGE DIMENSIONS
WLCSP16 1.615x1.615x0.586
CASE 567SD
ISSUE O
PRODUCT SPECIFIC DIMENSIONS
D
E
X
Y
Unit
1.615 ± 0.030
1.615 ± 0.030
0.2075
0.2075
mm
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14
FAN5909
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FAN5909/D