MITSUBISHI MITSUBISHI 〈DIGITAL 〈DIGITAL ASSP〉 ASSP〉 M66006P/FP M66006P/FP 12-BIT I/O EXPANDER 12-BIT I/O EXPANDER DESCRIPTION The M66006 is a semiconductor integrated circuit which has 12-bit shift register function to execute serial-parallel conversion and parallel-serial conversion. Because a serial-parallel shift register and a parallel-serial shift register are independently built in this IC, it is possible to read serial input data to a shift register while converting parallel data into serial data. Also, parallel data I/O pins can be set to input mode or output mode bit-by-bit. The M66006 can be widely used for I/O port expansion of MCU, serial bus system data communication, etc. PIN CONFIGURATION (TOP VIEW) Serial data output DO ← 1 DO D1 20 ↔ D1 Serial data input DI → 2 DI D2 19 ↔ D2 CLK D3 18 ↔ D3 CS D4 17 ↔ D4 D5 16 ↔ D6 15 ↔ D7 14 ↔ D8 13 ↔ Clock input CLK → 3 Chip select input CS → 4 VCC S→ 6 Set input FEATURES • Bi-directional serial data communication with MCU • Read of serial data during parallel-serial conversion. • Bit resolution of serial data I/O • Low power dissipation (50µW/package max.) (VCC=5V, Ta =25°C, in quiescing) • Schmitt input (DI, CLK, S, CS) • Open drain output (DO, from D1 to D12) • Parallel data I/O (from D1 to D12) • Wide operating supply voltage range (VCC=2 to 6V) • Wide operating temperature range (Ta =–20 to 75°C) 5 S GND 7 Parallel data D12 outputs D11 ↔ 8 D12 ↔ 9 D11 GND 10 D9 12 ↔ D10 11 ↔ D5 Parallel data I/O D6 D7 D8 D9 D10 Outline 20P4 20P2N-A APPLICATION Serial-parallel data conversion, parallel-serial data conversion, serial bus control by MCU. BLOCK DIAGRAM VCC Set input S 6 Chip select input CS 4 Shift register ! D12 D11 D10 Serial 1 DOdata output DO D3 D2 D1 19 18 Q12 Q11 Q10 Q3 Q2 Q1 Parallel output latch D12 D11 D10 D3 D2 D1 Q12 D11 D10 Q3 Q2 Q1 11 9 Shift register @ Serial data input D2 D3 D10 D11 D12 D1 8 DI 2 7 10 GND GND VCC CLK S CS DI 20 D1 Parallel data I/O Clock input CLK 3 Control circuit 5 Input form VCC VCC DO D1~ D12 Output form 1 MITSUBISHI 〈DIGITAL ASSP〉 M66006P/FP 12-BIT I/O EXPANDER FUNCTION The M66006 realizes low power dissipation and high noise immunity by applying silicon CMOS process. Because a 12-bit serial-parallel shift register and a 12-bit parallel-serial shift register are independently built in this IC, it is possible to read serial input data while converting parallel data into serial data. When CS changes from “H” to “L”, serial output of 12-bit parallel data and read of serial data from the MCU start. That is, 12-bit parallel data is latched at the falling edge of CS, synchronized with the falling edge of shift clock, and then output to serial output pin DO as serial data. At the same time, serial data from the MCU is read to the internal shift register at the rising edge of shift clock. The shift clock on and after 13th bit is neglected and pin DO is put in the high impedance state when the reading operation is masked. When CS changes from “L” to “H”, 12-bit serial data read into pin DI is output to parallel output pins from D1 to D12. Because the output form of parallel output pins is N-channel open drain output, “H” must be written to the pin to set to input mode. DESCRIPTION OF OPERATION (1) When power is supplied, pins DO and from D1 to D12 are in undefined state. When S changes to “L”, those pins are in high impedance state. (2) At the falling edge of CS, the status of pins from D1 to D12 is loaded to shift register !. (3) At the falling edge of CLK, data which is loaded as above (2) is output to pin DO as 12-bit serial data in order. (4) At the rising edge of CLK, 12-bit serial data is written from DI to shift register @. (5) CLK on and after the 13th bit is neglected and writing of serial data is not possible. Also, DO is put in the high impedance state. (6) At the rising edge of CS, the data which is written as mentioned in (4) is output to pins from D1 to D12. (7) Shift register ! loads the data applied externally and the AND-tie data latched by the parallel output latch. (8) When CS rises before CLK reaches the 12th bit, the parallel output latch latches the data which has been written to shift register @ and outputs it to pins from D1 to D12. In this case, shift registers ! and @ continues the shift operation and DO outputs serial data until CLK reaches the 12th bit. (9) Switching of I/O mode of pins from D1 to D12 is controlled by the serial data which is input to pin DI. Pins to which “H” is written operates as input pins. OPERATION TIMING DIAGRAM H S CS (1) L (2) (5) CLK 2 1 3 4 5 6 7 8 9 10 11 12 (4) DI DO1 (6) DO2 DO3 DO4 DO5 DO6 DO7 DO8 DO9 DO10 DO11 DO12 DI2 DI3 DI4 DI5 DI6 DI7 DI8 DI9 DI10 High impedance (3) DO DI1 13 DI11 DI12 (6) D1 DI1 DO1 D2 DI2 DO2 DI2 DI12 DO12 1 cycle 2 MITSUBISHI 〈DIGITAL ASSP〉 M66006P/FP 12-BIT I/O EXPANDER ABSOLUTE MAXIMUM RATINGS (Ta = –20 ~ 75°C unless otherwise noted) Symbol Parameter Conditions VCC VI VO Supply voltage Input voltage Output voltage IIK Input protection diode current IOK Output parasitic diode current IGND Tstg GND current Storage temperature Ratings –0.5 ~ +7.0 –0.5 ~ VCC + 0.5 –0.5 ~ VCC + 0.5 –20 20 –20 20 –48 –60 ~ 150 VI<0V VI>VCC VO<0V VO>VCC GND Unit V V V mA mA mA °C RECOMMENDED OPERATIONAL CONDITIONS Symbol VCC VI VO Topr Parameter Min. 2 0 0 –20 Supply voltage Input voltage Output voltage Operating temperature Limits Typ. Max. 6 VCC VCC 75 Unit V V V °C ELECTRICAL CHARACTERISTICS (VCC = 2 ~ 6V unless otherwise noted) Symbol Parameter Positive direction threshold voltage *1 Negative direction threshold voltage *1 VT+ VT– VIH “H” input voltage *2 VIL “L” input voltage *2 VOL “L” output voltage IO Maximum output leak current ICC Static power dissipation Test conditions VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VO=0.1V, VCC–0.1V |IO|=20µA VI=VT+, VT– VCC=4.5V VI=VT+, VT– VCC=6V VI=VCC, GND, VCC=6V Limits Ta=25˚C Min. Typ. Max. 0.35 0.8 × VCC × VCC 0.2 0.65 × VCC × VCC 0.75 × VCC 0.25 × VCC Ta= –20~75˚C Min. Max. 0.35 0.8 × VCC × VCC 0.2 0.65 × VCC × VCC 0.75 × VCC 0.25 × VCC Unit V V V V IOL=3mA 0.4 0.5 V VO=VCC VO=GND 1.0 –1.0 10.0 10.0 –10.0 100.0 µA Ta= –20~75˚C Min. Max. 1.9 400 400 400 400 400 Unit µA *1: DI, CLK, CS, S *2: D1~D12 SWITCHING CHARACTERISTICS (VCC = 5V) Limits Symbol fmax tPLZ tPZL tPLZ tPZL tPLZ Parameter Maximum repeat frequency Output “L-Z”, “Z-L” propagation time CLK-DO Output “L-Z”, “Z-L” propagation time CS-D1 to D12 Output “L-Z” propagation time S-DO, D1 to D12 Test conditions CL=50pF RL=1kΩ (Note 2) Ta=25˚C Min. Typ. Max. 2.5 300 300 300 300 300 MHz ns ns ns ns ns 3 MITSUBISHI 〈DIGITAL ASSP〉 M66006P/FP 12-BIT I/O EXPANDER TIMING CONDITIONS (VCC = 5V) Limits Symbol tw Parameter Test conditions CLK, CS, S pulse width Setup time of DI to CLK Setup time of CS to CLK Setup time of D1 to D12 to CS Hold time of DI to CLK Hold time of CS to CLK Hold time of D1 to D12 to CS Recovery time of CS to S tsu th trec Ta=25˚C Min. Typ. Max. 200 100 100 100 100 100 100 100 Ta= –20~75˚C Min. Max. 260 130 130 130 130 130 130 130 NOTE 2: TEST CIRCUIT Input Output VCC VCC (1)Characteristics of pulse generator (PG) (10% to 90%) tr=6ns, tf=6ns, Zo=50Ω RL (2)Static capacitance CL includes floating capacitance of Tested device PG wiring and input capacitance of probe. CL 50Ω GND 4 Unit ns ns ns ns MITSUBISHI 〈DIGITAL ASSP〉 M66006P/FP 12-BIT I/O EXPANDER TIMING CHARTS tw tw VCC CLK 50% 50% 50% 50% VCC S GND GND tPLZ tPZL trec ≈ VCC DO 50% 10% VCC CS VOL GND tw tw VCC CS 50% 50% 50% 50% GND tPLZ tPZL ≈ VCC D1 ~ D12 50% 10% VOL tw VCC S 50% 50% GND tPLZ ≈ VCC DO D1 ~ D12 10% VOL VCC DI 50% 50% GND tsu th VCC CLK 50% GND VCC D1 ~ D12 50% 50% GND tsu th VCC CS 50% GND VCC CS 50% 50% GND th tsu VCC CLK 50% 50% GND 5