LINER LT1016IS8 Ultrafast precision 10ns comparator Datasheet

LT1016
UltraFast Precision
10ns Comparator
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FEATURES
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DESCRIPTIO
UltraFastTM (10ns typ)
Operates Off Single 5V Supply or ±5V
Complementary Output to TTL
Low Offset Voltage
No Minimum Input Slew Rate Requirement
No Power Supply Current Spiking
Output Latch Capability
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APPLICATIO S
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High Speed A/D Converters
High Speed Sampling Circuits
Line Receivers
Extended Range V-to-F Converters
Fast Pulse Height/Width Discriminators
Zero-Crossing Detectors
Current Sense for Switching Regulators
High Speed Triggers
Crystal Oscillators
, LTC and LT are registered trademarks of Linear Technology Corporation.
UltraFast is a trademark of Linear Technology Corporation.
The LT®1016 is an UltraFast 10ns comparator that interfaces directly to TTL/CMOS logic while operating off either
±5V or single 5V supplies. Tight offset voltage specifications and high gain allow the LT1016 to be used in
precision applications. Matched complementary outputs
further extend the versatility of this comparator.
A unique output stage provides active drive in both directions for maximum speed into TTL/CMOS logic or passive
loads, yet does not exhibit the large current spikes found
in conventional output stages. This allows the LT1016 to
remain stable with the outputs in the active region which,
greatly reduces the problem of output “glitching” when the
input signal is slow moving or is low level.
The LT1016 has a LATCH pin which will retain input data
at the outputs, when held high. Quiescent negative power
supply current is only 3mA. This allows the negative
supply pin to be driven from virtually any supply voltage
with a simple resistive divider. Device performance is not
affected by variations in negative supply voltage.
Linear Technology offers a wide range of comparators in
addition to the LT1016 that address different applications.
See the Related Parts section on the back page of the data
sheet.
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TYPICAL APPLICATION
Response Time
10MHz to 25MHz Crystal Oscillator
5V
22Ω
THRESHOLD
VIN
100mV STEP
5mV OVERDRIVE
10MHz TO 25MHz
(AT CUT)
2k
THRESHOLD
5V
820pF
V+
+
2k
Q
LT1016
–
Q
V–
200pF
OUTPUT
VOUT
1V/DIV
GND
LATCH
0
2k
1016 TA1a
0
20
TIME (ns)
20
1016 TA2b
1
LT1016
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W W
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ABSOLUTE
AXI U RATI GS
(Note 1)
Positive Supply Voltage (Note 5) ............................... 7V
Negative Supply Voltage ............................................ 7V
Differential Input Voltage (Note 7) ........................... ±5V
+IN, –IN and LATCH ENABLE Current (Note 7) .. ±10mA
Output Current (Continuous) (Note 7) ................ ±20mA
Operating Temperature Range
LT1016I ...............................................–40∞C to 85∞C
LT1016C .................................................. 0∞C to 70∞C
Storage Temperature Range ................. – 65∞C to 150∞C
Lead Temperature (Soldering, 10 sec).................. 300∞C
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PACKAGE/ORDER I FOR ATIO
ORDER PART
NUMBER
TOP VIEW
V+ 1
8
Q OUT
+IN 2
+
7
Q OUT
–IN 3
–
6
GND
5
LATCH
ENABLE
V– 4
LT1016CN8
LT1016IN8
N8 PACKAGE
8-LEAD PDIP
TJMAX = 100∞C, qJA = 130∞C/W (N8)
Consult LTC marketing for parts specified with wider operating temperature ranges.
2
ORDER PART
NUMBER
TOP VIEW
V+ 1
8
Q OUT
+IN 2
+
7
Q OUT
– IN 3
–
6
GND
5
LATCH
ENABLE
V–
4
S8 PACKAGE
8-LEAD PLASTIC SO
TJMAX = 110∞C, qJA = 120∞C/W
LT1016CS8
LT1016IS8
S8 PART
MARKING
1016
1016I
LT1016
ELECTRICAL CHARACTERISTICS
The ● denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at TA = 25∞C. V+ = 5V, V– = 5V, VOUT (Q) = 1.4V, VLATCH = 0V, unless otherwise noted.
SYMBOL
PARAMETER
CONDITIONS
VOS
Input Offset Voltage
RS £ 100W (Note 2)
DVOS
DT
Input Offset Voltage Drift
IOS
Input Offset Current
IB
Input Bias Current
MIN
LT1016C/I
TYP
1.0
●
PSRR
Common Mode Rejection
–3.75V £ VCM £ 3.5V
Supply Voltage Rejection
mV/∞C
●
0.3
0.3
1.0
1.3
mA
mA
5
10
13
mA
mA
3.5
3.5
V
V
●
CMRR
mV
mV
4
(Note 3)
(Note 6)
Single 5V Supply
UNITS
±3
3.5
●
(Note 2)
Input Voltage Range
MAX
●
●
–3.75
1.25
●
80
96
dB
V + £ 5.4V
●
60
75
dB
Positive Supply 4.6V £ V + £ 5.4V
LT1016I
●
54
75
dB
Negative Supply 2V £ V – £ 7V
●
80
100
dB
1400
3000
V/V
2.7
2.4
3.4
3.0
Positive Supply 4.6V £
LT1016C
AV
Small-Signal Voltage Gain
1V £ VOUT £ 2V
VOH
Output High Voltage
V+ ≥ 4.6V
VOL
Output Low Voltage
I+
I–
VIH
IOUT =1mA
IOUT = 10mA
●
●
ISINK = 4mA
ISINK = 10mA
●
0.3
0.4
0.5
V
V
Positive Supply Current
●
25
35
mA
Negative Supply Current
●
3
5
mA
LATCH Pin Hi Input Voltage
●
VIL
LATCH Pin Lo Input Voltage
●
IIL
LATCH Pin Current
VLATCH = 0V
tPD
Propagation Delay (Note 4)
DVIN = 100mV, OD = 5mV
DVIN = 100mV, OD = 20mV
DtPD
Differential Propagation
Delay
2.0
V
Note 1: Absolute Maximum Ratings are those values beyond which the life
of a device may be impaired.
Note 2: Input offset voltage is defined as the average of the two voltages
measured by forcing first one output, then the other to 1.4V. Input offset
current is defined in the same way.
Note 3: Input bias current (IB) is defined as the average of the two input
currents.
Note 4: tPD and DtPD cannot be measured in automatic handling
equipment with low values of overdrive. The LT1016 is sample tested with
a 1V step and 500mV overdrive. Correlation tests have shown that tPD and
0.8
V
500
mA
10
14
16
ns
ns
9
12
15
ns
ns
3
ns
●
●
●
(Note 4) DVIN = 100mV,
OD = 5mV
Latch Setup Time
V
V
2
ns
DtPD limits shown can be guaranteed with this test if additional DC tests
are performed to guarantee that all internal bias conditions are correct. For
low overdrive conditions VOS is added to overdrive. Differential
propogation delay is defined as: DtPD = tPDLH – tPDHL
Note 5: Electrical specifications apply only up to 5.4V.
Note 6: Input voltage range is guaranteed in part by CMRR testing and in
part by design and characterization. See text for discussion of input
voltage range for supplies other than ±5V or 5V.
Note 7: This parameter is guaranteed to meet specified performance
through design and characterization. It has not been tested.
3
LT1016
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TYPICAL PERFOR A CE CHARACTERISTICS
Propagation Delay vs Input
Overdrive
Gain Characteristics
5.0
4.5
TJ = 125°C
25
VS = ±5V
TJ = 25°C
VSTEP = 100mV
CLOAD = 10pF
20
VS = ± 5V
TJ = 25°C
=0
I
20 VOUT = 100mV
STEP
OVERDRIVE = 5mV
3.5
TJ = 25°C
2.5
2.0
15
TIME (ns)
3.0
TIME (ns)
OUTPUT VOLTAGE (V)
4.0
25
VS = ± 5V
IOUT = 0
Propagation Delay vs Load
Capacitance
10
15
tPDHL
10
tPDLH
1.5
5
TJ = – 55°C
1.0
5
0.5
0
– 0.5
–1.5
0.5
1.5
DIFFERENTIAL INPUT VOLTAGE (mV)
10
0
2.5
30
20
OVERDRIVE (mV)
40
Propagation Delay vs Source
Resistance
Propagation Delay vs
Temperature
30
25
80
TIME (ns)
V – = – 5V
TJ = 25°C
VSTEP = 100mV
20 OVERDRIVE
= 5mV
CLOAD = 10pF
20
FALLING EDGE tPDHL
RISING EDGE tPDLH
5
5
0
500
2.5k
1k
1.5k
2k
SOURCE RESISTANCE (Ω)
4.8
5.0
5.2
5.4
4.6
POSITIVE SUPPLY VOLTAGE (V)
4.4
3k
Output Low Voltage (VOL) vs
Output Sink Current
0.8
VS = ± 5V
IOUT = 0V
OUTPUT VOLTAGE (V)
TIME (ns)
2
0
–2
–4
Output High Voltage (VOH) vs
Output Source Current
5.0
VS = ± 5V
VIN = 30mV
0.7
0.6
TJ = – 55°C
0.4
TJ = 25°C
0.3
0.2
TJ = 125°C
0.1
–6
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
1016 G07
4.0
TJ = 125°C
3.5
TJ = 25°C
3.0
TJ = – 55°C
2.5
2.0
1.5
0
125
VS = ± 5V
VIN = – 30mV
4.5
0.5
125
1016 G06
1016 G05
Latch Set-Up Time vs
Temperature
4
0
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
5.6
OUTPUT VOLTAGE (V)
0
1016 G04
4
FALLING OUTPUT tPDHL
10
10
6
15
RISING OUTPUT tPDLH
20
0
VS = ± 5V
OVERDRIVE = 5mV
STEP SIZE = 100mV
CLOAD = 10pF
25
15
10
50
1016 G03
Propagation Delay vs Supply
Voltage
VS = ± 5V
T = 25°C
70 J
OVERDRIVE = 20mV
EQUIVALENT INPUT
60
CAPACITANCE IS ≈ 3.5pF
CLOAD = 10pF
50
STEP SIZE = 800mV
400mV
40
200mV
100mV
30
10
30
40
20
OUTPUT LOAD CAPACITANCE (pF)
0
1016 G02
1016 G01
TIME (ns)
0
50
TIME (ns)
0
– 2.5
0
2
4 6 8 10 12 14 16 18 20
OUTPUT SINK CURRENT (mA)
1016 G08
1.0
0
2
4 6 8 10 12 14 16 18 20
OUTPUT SOURCE CURRENT (mA)
1016 G09
LT1016
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TYPICAL PERFOR A CE CHARACTERISTICS
Negative Supply Current vs
Temperature
40
V – = 0V
VIN = 60mV
IOUT = 0
45
40
3
2
30
30
25
20
15
TJ = 125°C
10
1
5
TJ = 25°C
1
2
8
1
10
SWITCHING FREQUENCY (MHz)
6
100
1016 G12
Positive Common Mode Limit vs
Temperature
VS = ± 5V
VIN = 2VP-P
TJ = 25°C
Negative Common Mode Limit vs
Temperature
2
VS = ± 5V*
VS = SINGLE 5V SUPPLY
5
1
90
80
70
INPUT VOLTAGE (V)
INPUT VOLTAGE (V)
100
4
3
2
0
–1
*SEE APPLICATION INFORMATION
FOR COMMON MODE LIMIT WITH
VARYING SUPPLY VOLTAGE.
–2
60
1
50
100k
1M
FREQUENCY (Hz)
10M
*SEE APPLICATION INFORMATION
FOR COMMON MODE LIMIT WITH
VARYING SUPPLY VOLTAGE.
–3
0
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
1016 G13
LATCH Pin Threshold vs
Temperature
2.6
125
VS = ± 5V*
–4
50
100
25
75
–50 –25
0
JUNCTION TEMPERATURE (°C)
1016 G14
125
1016 G15
LATCH Pin Current* vs
Temperature
300
VS = ± 5V
2.2
250
1.8
200
CURRENT (µA)
40
10k
VOLTAGE (V)
REJECTION RATIO (dB)
VS = ± 5V
VIN = ± 50mV
IOUT = 0
1016 G11
Common Mode Rejection vs
Frequency
110
15
0
7
6
4
3
5
SUPPLY VOLTAGE (V)
1016 G10
120
20
5
TJ = – 55°C
0
125
25
10
0
0
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
TJ = 125°C
TJ = 25°C
TJ = – 55°C
35
35
4
CURRENT (mA)
CURRENT (mA)
5
50
VS = ± 5V
IOUT = 0
Positive Supply Current vs
Switching Frequency
CURRENT (mA)
6
Positive Supply Current vs
Positive Supply Voltage
OUTPUT LATCHED
1.4
OUTPUT UNAFFECTED
1.0
0.6
150
100
50
0.2
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
125
1016 G16
VS = ± 5V
VLATCH = 0V
*CURRENT COMES OUT OF
LATCH PIN BELOW THRESHOLD
0
50
100
–50 –25
25
75
0
JUNCTION TEMPERATURE (°C)
125
1016 G17
5
LT1016
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APPLICATIO S I FOR ATIO
Common Mode Considerations
The LT1016 is specified for a common mode range of
–3.75V to 3.5V with supply voltages of ±5V. A more
general consideration is that the common mode range is
1.25V above the negative supply and 1.5V below the
positive supply, independent of the actual supply voltage.
The criteria for common mode limit is that the output still
responds correctly to a small differential input signal.
Either input may be outside the common mode limit (up to
the supply voltage) as long as the remaining input is within
the specified limit, and the output will still respond correctly. There is one consideration, however, for inputs that
exceed the positive common mode limit. Propagation
delay will be increased by up to 10ns if the signal input is
more positive than the upper common mode limit and then
switches back to within the common mode range. This
effect is not seen for signals more negative than the lower
common mode limit.
Input Impedance and Bias Current
Input bias current is measured with the output held at
1.4V. As with any simple NPN differential input stage, the
LT1016 bias current will go to zero on an input that is low
and double on an input that is high. If both inputs are less
than 0.8V above V –, both input bias currents will go to
zero. If either input exceeds the positive common mode
limit, input bias current will increase rapidly, approaching
several milliamperes at VIN = V +.
Differential input resistance at zero differential input
voltage is about 10kW, rapidly increasing as larger DC
differential input signals are applied. Common mode input
resistance is about 4MW with zero differential input
voltage. With large differential input signals, the high input
will have an input resistance of about 2MW and the low
input greater than 20MW.
6
Input capacitance is typically 3.5pF. This is measured by
inserting a 1k resistor in series with the input and measuring the resultant change in propagation delay.
LATCH Pin Dynamics
The LATCH pin is intended to retain input data (output
latched) when the LATCH pin goes high. This pin will float
to a high state when disconnected, so a flowthrough
condition requires that the LATCH pin be grounded. To
guarantee data retention, the input signal must be valid at
least 5ns before the latch goes high (setup time) and must
remain valid at least 3ns after the latch goes high (hold
time). When the latch goes low, new data will appear at the
output in approximately 8ns to 10ns. The LATCH pin is
designed to be driven with TTL or CMOS gates. It has no
built-in hysteresis.
Measuring Response Time
The LT1016 is able to respond quickly to fast low level
signals because it has a very high gain-bandwidth product
(ª50GHz), even at very high frequencies. To properly
measure the response of the LT1016 requires an input
signal source with very fast rise times and exceptionally
clean settling characteristics. This last requirement comes
about because the standard comparator test calls for an
input step size that is large compared to the overdrive
amplitude. Typical test conditions are 100mV step size
with only 5mV overdrive. This requires an input signal that
settles to within 1% (1mV) of final value in only a few
nanoseconds with no ringing or “long tailing.” Ordinary
high speed pulse generators are not capable of generating
such a signal, and in any case, no ordinary oscilloscope is
capable of displaying the waveform to check its fidelity.
Some means must be used to inherently generate a fast,
clean edge with known final value.
LT1016
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The circuit shown in Figure 1 is the best electronic means
of generating a known fast, clean step to test comparators.
It uses a very fast transistor in a common base configuration. The transistor is switched “off” with a fast edge from
the generator and the collector voltage settles to exactly
0V in just a few nanoseconds. The most important feature
of this circuit is the lack of feedthrough from the generator
to the comparator input. This prevents overshoot on the
comparator input that would give a false fast reading on
comparator response time.
To adjust this circuit for exactly 5mV overdrive, V1 is
adjusted so that the LT1016 output under test settles to
1.4V (in the linear region). Then V1 is changed –5V to set
overdrive at 5mV.
The test circuit shown measures low to high transition on
the “+” input. For opposite polarity transitions on the
output, simply reverse the inputs of the LT1016.
High Speed Design Techniques
A substantial amount of design effort has made the LT1016
relatively easy to use. It is much less prone to oscillation
and other vagaries than some slower comparators, even
with slow input signals. In particular, the LT1016 is stable
in its linear region, a feature no other high speed comparator has. Additionally, output stage switching does not
appreciably change power supply current, further enhancing stability. These features make the application of the
50GHz gain-bandwidth LT1016 considerably easier than
other fast comparators. Unfortunately, laws of physics
dictate that the circuit environment the LT1016 works in
must be properly prepared. The performance limits of high
speed circuitry are often determined by parasitics such as
stray capacitance, ground impedance and layout. Some of
these considerations are present in digital systems where
designers are comfortable describing bit patterns and
memory access times in terms of nanoseconds. The
LT1016 can be used in such fast digital systems and
Figure 2 shows just how fast the device is. The simple test
circuit allows us to see that the LT1016’s (Trace B)
response to the pulse generator (Trace A) is as fast as a
TTL inverter (Trace C) even when the LT1016 has only
millivolts of input signal! Linear circuits operating with
this kind of speed make many engineers justifiably wary.
Nanosecond domain linear circuits are widely associated
with oscillations, mysterious shifts in circuit characteristics, unintended modes of operation and outright failure to
function.
5V
0V
–100mV
0.1µF
25Ω
130Ω
25Ω
10k
2N3866
PULSE
IN
V1†
0V
– 3V
50Ω
400Ω
– 5V
750Ω
0.01µF**
+
Q
LT1016
–
L
Q
10 SCOPE PROBE
(CIN ≈ 10pF)
10 SCOPE PROBE
(CIN ≈ 10pF)
10Ω
– 5V
0.01µF
* SEE TEXT FOR CIRCUIT EXPLANATION
** TOTAL LEAD LENGTH INCLUDING DEVICE PIN.
SOCKET AND CAPACITOR LEADS SHOULD BE
LESS THAN 0.5 IN. USE GROUND PLANE
† (VOS + OVERDRIVE) • 1000
1016 F01
Figure 1. Response Time Test Circuit
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LT1016
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Other common problems include different measurement
results using various pieces of test equipment, inability to
make measurement connections to the circuit without
inducing spurious responses and dissimilar operation
between two “identical” circuits. If the components used
in the circuit are good and the design is sound, all of the
above problems can usually be traced to failure to provide
a proper circuit “environment.” To learn how to do this
requires studying the causes of the aforementioned
difficulties.
By far the most common error involves power supply
bypassing. Bypassing is necessary to maintain low supply
impedance. DC resistance and inductance in supply wires
and PC traces can quickly build up to unacceptable levels.
This allows the supply line to move as internal current
levels of the devices connected to it change. This will
almost always cause unruly operation. In addition, several
devices connected to an unbypassed supply can “communicate” through the finite supply impedances, causing
erratic modes. Bypass capacitors furnish a simple way to
eliminate this problem by providing a local reservoir of
energy at the device. The bypass capacitor acts like an
electrical flywheel to keep supply impedance low at high
frequencies. The choice of what type of capacitors to use
for bypassing is a critical issue and should be approached
carefully. An unbypassed LT1016 is shown responding to
a pulse input in Figure 3. The power supply the LT1016
sees at its terminals has high impedance at high frequency. This impedance forms a voltage divider with the
LT1016, allowing the supply to move as internal conditions in the comparator change. This causes local feedback and oscillation occurs. Although the LT1016
responds to the input pulse, its output is a blur of 100MHz
oscillation. Always use bypass capacitors.
TEST CIRCUIT
7404
TRACE A
5V/DIV
PULSE
GENERATOR
1k
OUTPUTS
10Ω
+
TRACE B
5V/DIV
LT1016
–
TRACE C
5V/DIV
VREF
10ns/DIV
Figure 2. LT1016 vs a TTL Gate
2V/DIV
100ns/DIV
1016 F03
Figure 3. Unbypassed LT1016 Response
8
1016 F02
LT1016
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In Figure 4 the LT1016’s supplies are bypassed, but it still
oscillates. In this case, the bypass units are either too far
from the device or are lossy capacitors. Use capacitors
with good high frequency characteristics and mount them
as close as possible to the LT1016. An inch of wire
between the capacitor and the LT1016 can cause problems. If operation in the linear region is desired, the
LT1016 must be over a ground plate with good RF bypass
capacitors (≥0.01mF) having lead lengths less than 0.2
inches. Do not use sockets.
In Figure 5 the device is properly bypassed but a new
problem pops up. This photo shows both outputs of the
comparator. Trace A appears normal, but Trace B shows
an excursion of almost 8V—quite a trick for a device
running from a 5V supply. This is a commonly reported
problem in high speed circuits and can be quite confusing.
It is not due to suspension of natural law, but is traceable
to a grossly miscompensated or improperly selected
oscilloscope probe. Use probes that match your
oscilloscope’s input characteristics and compensate them
properly. Figure 6 shows another probe-induced problem.
Here, the amplitude seems correct but the 10ns response
time LT1016 appears to have 50ns edges! In this case, the
probe used is too heavily compensated or slow for the
oscilloscope. Never use 1¥ or “straight” probes. Their
bandwidth is 20MHz or less and capacitive loading is high.
Check probe bandwidth to ensure it is adequate for
the measurement. Similarly, use an oscilloscope with
adequate bandwidth.
2V/DIV
100ns/DIV
1016 F04
Figure 4. LT1016 Response with Poor Bypassing
TRACE A
2V/DIV
1V/DIV
TRACE B
2V/DIV
10ns/DIV
1016 F05
Figure 5. Improper Probe Compensation Causes
Seemingly Unexplainable Amplitude Error
50ns/DIV
1016 F06
Figure 6. Overcompensated or Slow Probes
Make Edges Look Too Slow
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LT1016
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In Figure 7 the probes are properly selected and applied
but the LT1016’s output rings and distorts badly. In this
case, the probe ground lead is too long. For general
purpose work most probes come with ground leads about
six inches long. At low frequencies this is fine. At high
speed, the long ground lead looks inductive, causing the
ringing shown. High quality probes are always supplied
with some short ground straps to deal with this problem.
Some come with very short spring clips which fix directly
to the probe tip to facilitate a low impedance ground
connection. For fast work, the ground connection to the
probe should not exceed one inch in length. Keep the
probe ground connection as short as possible.
Figure 8 shows the LT1016’s output (Trace B) oscillating
near 40MHz as it responds to an input (Trace A). Note that
the input signal shows artifacts of the oscillation. This
example is caused by improper grounding of the comparator. In this case, the LT1016’s GND pin connection is
one inch long. The ground lead of the LT1016 must be as
short as possible and connected directly to a low impedance ground point. Any substantial impedance in the
LT1016’s ground path will generate effects like this. The
reason for this is related to the necessity of bypassing the
power supplies. The inductance created by a long device
ground lead permits mixing of ground currents, causing
undesired effects in the device. The solution here is
simple. Keep the LT1016’s ground pin connection as short
(typically 1/4 inch) as possible and run it directly to a low
impedance ground. Do not use sockets.
Figure 9 addresses the issue of the “low impedance
ground,” referred to previously. In this example, the
output is clean except for chattering around the edges.
This photograph was generated by running the LT1016
without a “ground plane.” A ground plane is formed by
using a continuous conductive plane over the surface of
the circuit board. The only breaks in this plane are for the
circuit’s necessary current paths. The ground plane serves
two functions. Because it is flat (AC currents travel along
the surface of a conductor) and covers the entire area of
the board, it provides a way to access a low inductance
ground from anywhere on the board. Also, it minimizes the
effects of stray capacitance in the circuit by referring them
to ground. This breaks up potential unintended and harmful feedback paths. Always use a ground plane with the
LT1016 when input signal levels are low or slow moving.
1V/DIV
20ns/DIV
1016 F07
Figure 7. Typical Results Due to Poor Probe Grounding
TRACE A
1V/DIV
TRACE B
2V/DIV
2V/DIV
100ns/DIV
1016 F08
Figure 8. Excessive LT1016 Ground Path
Resistance Causes Oscillation
10
100ns/DIV
1016 F09
Figure 9. Transition Instabilities Due to No Ground Plane
LT1016
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APPLICATIO S I FOR ATIO
“Fuzz” on the edges is the difficulty in Figure 10. This
condition appears similar to Figure 10, but the oscillation
is more stubborn and persists well after the output has
gone low. This condition is due to stray capacitive feedback from the outputs to the inputs. A 3kW input source
impedance and 3pF of stray feedback allowed this oscillation. The solution for this condition is not too difficult.
Keep source impedances as low as possible, preferably 1k
or less. Route output and input pins and components away
from each other.
The opposite of stray-caused oscillations appears in
Figure 11. Here, the output response (Trace B) badly lags
the input (Trace A). This is due to some combination of
high source impedance and stray capacitance to ground at
the input. The resulting RC forces a lagged response at the
input and output delay occurs. An RC combination of 2k
source resistance and 10pF to ground gives a 20ns time
constant—significantly longer than the LT1016’s
response time. Keep source impedances low and minimize stray input capacitance to ground.
Figure 12 shows another capacitance related problem.
Here the output does not oscillate, but the transitions are
discontinuous and relatively slow. The villain of this
situation is a large output load capacitance. This could be
caused by cable driving, excessive output lead length or
the input characteristics of the circuit being driven. In
most situations this is undesirable and may be eliminated
by buffering heavy capacitive loads. In a few circumstances it may not affect overall circuit operation and is
tolerable. Consider the comparator’s output load
characteristics and their potential effect on the circuit. If
necessary, buffer the load.
2V/DIV
50ns/DIV
1016 F10
Figure 10. 3pF Stray Capacitive Feedback
with 3kW Source Can Cause Oscillation
TRACE A
2V/DIV
2V/DIV
TRACE B
2V/DIV
10ns/DIV
Figure 11. Stray 5pF Capacitance from
Input to Ground Causes Delay
1016 F11
100ns/DIV
1016 F12
Figure 12. Excessive Load Capacitance Forces Edge Distortion
11
LT1016
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APPLICATIO S I FOR ATIO
Another output-caused fault is shown in Figure 13. The
output transitions are initially correct but end in a ringing
condition. The key to the solution here is the ringing. What
is happening is caused by an output lead that is too long.
The output lead looks like an unterminated transmission
line at high frequencies and reflections occur. This accounts for the abrupt reversal of direction on the leading
edge and the ringing. If the comparator is driving TTL this
may be acceptable, but other loads may not tolerate it. In
this instance, the direction reversal on the leading edge
might cause trouble in a fast TTL load. Keep output lead
lengths short. If they get much longer than a few inches,
terminate with a resistor (typically 250W to 400W).
200ns-0.01% Sample-and-Hold Circuit
Figure 14’s circuit uses the LT1016’s high speed to
improve upon a standard circuit function. The 200ns
acquisition time is well beyond monolithic sample-andhold capabilities. Other specifications exceed the best
commercial unit’s performance. This circuit also gets
around many of the problems associated with standard
sample-and-hold approaches, including FET switch errors
and amplifier settling time. To achieve this, the LT1016’s
high speed is used in a circuit which completely abandons
traditional sample-and-hold methods.
Important specifications for this circuit include:
Acquisition Time
<200ns
±3V
Common Mode Input Range
Droop
1V/DIV
1mV/ms
Hold Step
2mV
Hold Settling Time
15ns
Feedthrough Rejection
50ns/DIV
>>100dB
When the sample-and-hold line goes low, a linear ramp
starts just below the input level and ramps upward. When
the ramp voltage reaches the input voltage, A1 shuts off
the ramp, latches itself off and sends out a signal indicating sampling is complete.
1016 F13
Figure 13. Lengthy, Unterminated Output Lines
Ring from Reflections
5V
5.1k
1N4148
390Ω
470Ω
100Ω
1k
100Ω
1k
DELAY
COMP
1N4148
Q1
2N5160
Q2
2N2907A
0.1µF
INPUT
±3V
220Ω
5.1k
Q7
2N5486
1.5k
Q3
2N2369
Q5
2N2222
1000pF
(POLYSTYRENE)
NOW
+
SN7402
LATCH
SN7402
SN7402
300Ω
Q4
2N2907A
–15V
– 5V
OUTPUT
Figure 14. 200ns Sample-and-Hold
12
A1
LT1016
1N4148
100Ω
1.5k
–
Q6
2N2222
390Ω
820Ω
1.5k
LT1009
2.5V
8pF
SAMPLE-HOLD
COMMAND (TTL)
1016 F14
LT1016
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APPLICATIO S I FOR ATIO
1.8ms, 12-Bit A/D Converter
To get faster conversion time, the clock is controlled by the
window comparator monitoring the DAC input summing
junction. Additionally, the DMOS FET clamps the DAC
output to ground at the beginning of each clock cycle,
shortening DAC settling time. After the fifth bit is converted, the clock runs at maximum speed.
The LT1016’s high speed is used to implement a very fast
12-bit A/D converter in Figure 15. The circuit is a modified
form of the standard successive approximation approach
and is faster than most commercial SAR 12-bit units. In
this arrangement the 2504 successive approximation register (SAR), A1 and C1 test each bit, beginning with the
MSB, and produce a digital word representing VIN’s value.
5V
2.5k
0.01µF
5V
– 5V
150Ω
VIN
0V TO 10V
1k
1000pF
LT1021 10V
10V
5V
10k
14
SD210
VR+
0.01µF
16
15
VR–
13
19
GND
COMP
IO
15V
20
–15V
17
V+
V–
– 5V
620Ω*
–
2.5k**
10k**
–15V
620Ω*
C1
LT1016
+
Q3
NC
1k
1k
IO
AM6012
18
Q1 Q2
5V
150k
PARALLEL
DIGITAL
DATA
OUTPUT
5V
9
74121
Q
6
IN B
3 4 5 7
5V
24
13
15k
LSB
MSB
27k
Q6
V+
AM2504
CLK
GND
12
E
D
S
1
14
–15V
11
CC
3
Q4
150k
Q5
1/4 74S00
STATUS
5V
5V
1k
–
0.1µF
C3
LT1016
10Ω
NC
+
1/4 74S00
1/4 74S08
– 5V
Q1 TO Q5 RCA CA3127 ARRAY
+
1N4148
–
HP5082-2810
*1% FILM RESISTOR
**PRECISION 0.01%; VISHAY S-102
PRS
C2
LT1016
1k
0.1µF
1/4 74S08
D
– 5V
5V
Q
1/2 74S74
CLK
PRS
1/2 74S74
NC
RST
10Ω
– 5V
1/6 74S04 1/6 74S04
CLOCK
7.4MHz
CONVERT
COMMAND
1016 F15
Figure 15. 12-Bit 1.8ms SAR A-to-D
13
LT1016
U
TYPICAL APPLICATIO S
Voltage Controlled Pulse Width Generator
5V
Single Supply Precision RC 1MHz Oscillator
FULL-SCALE
CALIBRATION
500Ω
LM385
1.23V
2N3906
≈ 6.2k*
1k
5V
25Ω
2N3906
100pF
1000pF
100pF
5V
2.7k
–
+
2k
LT1016
GND
LATCH
5V
CEXT
–5V
1k
Q
1N914
B
74121
A1
Q
V–
10k
1%
2N3906
5pF
5V
0µs TO 2.5µs
(MINIMUM
WIDTH ≈ 0.05µs)
470pF
Q
+
START
–
VIN = 0V TO 2.5V
Q
LT1016
10k
1%
74HC04
10k
1%
OUTPUTS
8.2k
* SELECT OR TRIM FOR f = 1.00MHz
1016 AI02
1016 AI01
–5V
50MHz Fiber Optic Receiver with Adaptive Trigger
5V
3k
10k
–
LT1220
+
22M
500pF
LT1223
–
–
0.005µF
+
LT1097
+
330Ω
1k
22M
0.005µF
0.1µF
+
= HP 5082-4204
50Ω
LT1016
OUTPUT
–
NPN = 2N3904
PNP = 2N3906
3k
–5V
1016 AI03
14
LT1016
U
TYPICAL APPLICATIO S
1MHz to 10MHz Crystal
Oscillator
18ns Fuse with Voltage Programmable Trip Point
Q1
2N3866
28V
5V
2k
1MHz TO 10MHz
CRYSTAL
330Ω
Q2
2N2369
5V
V+
+
2.4k
+
– 5V
A1
LT1193
Q
FB
LT1016
2k
OUTPUT
–
V–
–
900Ω
Q
GND
LATCH
33pF
300Ω
+
1k
2k
A2
LT1016
L
0.068µF
1016 AI04
* = 1% FILM RESISTOR
A1 AND A2 USE ±5V SUPPLIES
–
1k*
9k*
9k*
10Ω
CARBON
1k*
200Ω
CALIBRATE
TRIP SET
0mA TO 250mA = 0V TO 2.5V
RESET (NORMALLY OPEN)
LOAD
1016 AI05
U
APPE DIX A
About Level Shifts
The TTL output of the LT1016 will interface with many
circuits directly. Many applications, however, require some
form of level shifting of the output swing. With LT1016
based circuits this is not trivial because it is desirable to
maintain very low delay in the level shifting stage. When
designing level shifters, keep in mind that the TTL output
of the LT1016 is a sink-source pair (Figure A1) with good
ability to drive capacitance (such as feedforward capacitors).
Figure A2 shows a noninverting voltage gain stage with a
15V output. When the LT1016 switches, the base-emitter
voltages at the 2N2369 reverse, causing it to switch very
quickly. The 2N3866 emitter-follower gives a low impedance output and the Schottky diode aids current sink
capability.
Figure A3 is a very versatile stage. It features a bipolar
swing that may be programmed by varying the output
transistor’s supplies. This 3ns delay stage is ideal for
driving FET switch gates. Q1, a gated current source,
switches the Baker-clamped output transistor, Q2. The
heavy feedforward capacitor from the LT1016 is the key to
low delay, providing Q2’s base with nearly ideal drive. This
capacitor loads the LT1016’s output transition (Trace A,
Figure A4), but Q2’s switching is clean (Trace B, Figure A4)
with 3ns delay on the rise and fall of the pulse.
Figure A5 is similar to Figure A2 except that a sink
transistor has replaced the Schottky diode. The two emitter-followers drive a power MOSFET which switches 1A at
15V. Most of the 7ns to 9ns delay in this stage occurs in
the MOSFET and the 2N2369.
When designing level shifters, remember to use transistors with fast switching times and high fTs. To get the kind
of results shown, switching times in the ns range and fTs
approaching 1GHz are required.
15
LT1016
U
APPE DIX A
15V
+V
1k
2N2369
2N3866
+
OUTPUT = 0V TO
TYPICALLY 3V TO 4V
HP5082-2810
LT1016
OUTPUT
–
1k
1k
LT1016 OUTPUT
NONINVERTING
VOLTAGE GAIN
tRISE = 4ns
tFALL = 5ns
1016 FA01
12pF
1016 fFA02
Figure A1
Figure A2
5V
+
INPUT
LT1016
4.7k
430Ω
1N4148
–
Q1
2N2907
HP5082-2810
1000pF
0.1µF
5V
(TYP)
330Ω
820Ω
Q2
2N2369
5V
OUTPUT
–10V
OUTPUT TRANSISTOR SUPPLIES
(SHOWN IN HEAVY LINES)
CAN BE REFERENCED ANYWHERE
BETWEEN 15V AND –15V
820Ω
INVERTING VOLTAGE GAIN—BIPOLAR SWING
tRISE = 3ns
tFALL = 3ns
–10V
(TYP)
1016 FA03
Figure A3
15V
1k
TRACE A
2V/DIV
RL
2N2369
2N3866
+
TRACE B
10V/DIV
(INVERTED)
–
5ns/DIV
1016 FA04
Figure A4. Figure A3’s Waveforms
16
POWER FET
LT1016
2N5160
1k
1k
12pF
NONINVERTING
VOLTAGE GAIN
tRISE = 7ns
tFALL = 9ns
1016 FA05
Figure A5
V–
LATCH
– INPUT
+ INPUT
D2
D1
Q50
+
Q16
D3
D4
15pF
Q20
1.5k
Q51
150Ω
165Ω
Q10
Q6
375Ω
Q19
1.1k
D5
Q9
Q7 Q8
150Ω
Q18
Q5
1.3k
Q4
830Ω
Q3
Q17
1.3k
75Ω
Q2
65Ω
Q1
15pF
800Ω
50Ω
+
75Ω
800Ω
50Ω
3k
Q49
955Ω
350Ω
1.3k
Q11
165Ω
Q21
15pF
1k
1k
Q14
Q25
Q22
+
210Ω
+
150Ω
565Ω
150Ω
Q13
1.3k
Q12
Q15
2k
300Ω
1.8k
100pF
3.5k
100Ω
1.5k
Q23
1.8k
Q28
3.5k
100Ω
1.5k
Q24
1.2k
90Ω
700Ω
Q33
Q27
210Ω
Q26
300Ω
15pF
+
Q31 D8
670Ω
170Ω
Q32
D6
490Ω
Q35
D7
1.2k
90Ω
170Ω
Q40
Q34
Q36
Q29
Q41
Q30
670Ω
D9
Q42
Q45
700Ω
D10
D10
480Ω
Q
Q46
Q43
Q47
Q44
GND
Q
V+
LT1016
W
W
SI PLIFIED SCHE ATIC
17
LT1016
U
PACKAGE DESCRIPTIO
N8 Package
8-Lead PDIP (Narrow .300 Inch)
(Reference LTC DWG # 05-08-1510)
0.400*
(10.160)
MAX
8
7
6
5
1
2
3
4
0.255 ± 0.015*
(6.477 ± 0.381)
0.300 – 0.325
(7.620 – 8.255)
0.009 – 0.015
(0.229 – 0.381)
(
+0.035
0.325 –0.015
8.255
+0.889
–0.381
)
0.045 – 0.065
(1.143 – 1.651)
0.065
(1.651)
TYP
0.100
(2.54)
BSC
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS.
MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
18
0.130 ± 0.005
(3.302 ± 0.127)
0.125
(3.175) 0.020
MIN
(0.508)
MIN
0.018 ± 0.003
(0.457 ± 0.076)
N8 1098
LT1016
U
PACKAGE DESCRIPTIO
S8 Package
8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference LTC DWG # 05-08-1610)
0.189 – 0.197*
(4.801 – 5.004)
8
7
6
5
0.150 – 0.157**
(3.810 – 3.988)
0.228 – 0.244
(5.791 – 6.197)
SO8 1298
1
0.010 – 0.020
45°
(0.254 – 0.508)
0.008 – 0.010
(0.203 – 0.254)
0.053 – 0.069
(1.346 – 1.752)
0°– 8° TYP
0.016 – 0.050
(0.406 – 1.270)
0.014 – 0.019
(0.355 – 0.483)
TYP
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH
SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE
**DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD
FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
2
3
4
0.004 – 0.010
(0.101 – 0.254)
0.050
(1.270)
BSC
Information furnished by Linear Technology Corporation is believed to be accurate and reliable.
However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
19
LT1016
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APPLICATIO S I FOR ATIO
A1’s 68pF feedback capacitor. The amplifier controls the
circuit’s output pulse generator, closing feedback loop
around the integrating amplifier. To maintain the summing node at zero, the pulse generator runs at a frequency
that permits enough charge pumping to offset the input
signal. Thus, the output frequency is linearly related to the
input voltage.
1Hz to 10MHz V-to-F Converter
The LT1016 and the LT1122 FET input amplifier combine
to form a high speed V-to-F converter in Figure 16. A
variety of techniques is used to achieve a 1Hz to 10MHz
output. Overrange to 12MHz (VIN = 12V) is provided. This
circuit’s dynamic range is 140dB, or seven decades, which
is wider than any commercially available unit. The 10MHz
full-scale frequency is 10 times faster than monolithic
V-to-F’s now available. The theory of operation is based on
the identity Q = CV.
To trim this circuit, apply 6.000V at the input and adjust the
2kW pot for 6.000MHz output. Next, excite the circuit with
a 10.000V input and trim the 20k resistor for 10.000MHz
output. Repeat these adjustments until both points are
fixed. Linearity of the circuit is 0.03%, with full-scale drift
of 50ppm/∞C. The LTC1050 chopper op amp servos the
integrator’s noninverting input and eliminates the need for
a zero trim. Residual zero point error is 0.05Hz/∞C.
Each time the circuit produces an output pulse, it feeds
back a fixed quantity of charge, Q, to a summing node, S.
The circuit’s input furnishes a comparison current at the
summing node. This difference current is integrated in
INPUT
0V TO 10V
OUTPUT
1Hz TO 10MHz
15pF
(POLYSTYRENE)
Q1
5V REF
15V
–15V
+
A4
LT1010
4.7µF
+
Q2
A3
LT1006
470Ω
–
15V
2k
6MHz
TRIM
15V
0.1µF
5V
6.8Ω
68pF
10k*
–
A1
LT1122
+
10k
1.2k
100k*
+
A2
LT1016
100Ω
– 5V
LM134
100k*
5V – 5V
8
LT1034-1.2V
–
LT1034-2.5V
150pF
2.2M*
1k
5V
Q4
0.02µF
–
= 2N2369
36k
LTC1050
= 74HC14
+
* = 1% METAL FILM/10ppm/°C
BYPASS ALL ICs WITH 2.2µF ON
EACH SUPPLY DIRECTLY AT PINS
Q3
5pF
1k
10M
+
10µF
– 5V
10MHz
TRIM
20k
1016 F16
Figure 16. 1Hz to 10MHz V-to-F Converter. Linearity is Better Than 0.03% with 50ppm/∞C Drift
RELATED PARTS
PART NUMBER
DESCRIPTION
COMMENTS
LT1116
12ns Single Supply Ground-Sensing Comparator
Single Supply Version of LT1016, LT1016 Pinout and Functionality
LT1394
7ns, UltraFast, Single Supply Comparator
6mA, 100MHz Data Rate, LT1016 Pinout and Functionality
LT1671
60ns, Low Power, Single Supply Comparator
450mA, Single Supply Comparator, LT1016 Pinout and Functionality
LT1711/LT1712
Single/Dual 4.5ns 3V/5V/±5V Rail-to-Rail Comparators Rail-to-Rail Inputs and Outputs
LT1713/LT1714
Single/Dual 7ns 3V/5V/±5V Rail-to-Rail Comparators
5mA per Comparator, Rail-to-Rail Inputs and Outputs
LT1715
Dual 150MHz 4ns 3V/5V Comparator
150MHz Toggle Rate, Independent Input/Output Supplies
LT1719/LT1720/LT1721 Single/Dual/Quad 4.5ns 3V/5V Comparators
20
Linear Technology Corporation
4mA per Comparator, Ground-Sensing Rail-to-Rail Inputs and Outputs
sn1016 1016fcs LT/TP 0601 1.5K REV C • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417
(408)432-1900 ● FAX: (408) 434-0507 ● www.linear-tech.com
„ LINEAR TECHNOLOGY CORPORATION 1991