Renesas HIP6311ACBZ Microprocessor core voltage regulator multi-phase buck pwm controller Datasheet

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HIP6311A
DATASHEET
FN9035
Rev 1.00
July 2004
Microprocessor CORE Voltage Regulator Multi-Phase Buck PWM Controller
The HIP6311A Multi-Phase Buck PWM control IC together
with HIP6601A, HIP6602A or HIP6603A companion gate
drivers form a precision voltage regulation system for
advanced microprocessors. The HIP6311A controls
microprocessor core voltage regulation by driving 2 to 4
synchronous-rectified buck channels in parallel. The multiphase buck topology takes advantage of interleaving phases
to increase ripple frequency and reduce input and output
ripple currents. Resulting in fewer components, reduced
component ratings, lower power dissipation, and smaller
implementation area.
The HIP6311A control IC features a 5 bit digital-to-analog
converter (DAC) that adjusts the core output voltage from
1.100V to 1.850V with an unsurpassed system accuracy of
±0.5% over temperature. The HIP6311A uses a lossless
current sensing approach in which the voltage developed
across the on-resistance of the lower MOSFETs during
conduction is sampled. Current sensing provides the
required signals for precision droop, channel-current
balancing, load sharing, and over-current protection.
Another feature of this control IC is the PGOOD monitor
which is held low until the core voltage increases to within
8% of the programmed voltage. An over-voltage condition is
detected when the output voltage exceeds 115% of the
programmed VID. This results in the converter shutting down
and PGOOD being pulled low. During an under-voltage
condition (output voltage 10% below the programmed VID),
PGOOD transitions low, but the converter continues to
operate.
TEMP. (oC)
PACKAGE
• Microprocessor Voltage Identification Input
- 5-Bit VID Input
- 1.100V to 1.850V in 25mV Steps
- Programmable Droop Voltage
• RDS(on) Current Sensing
- Accurate Channel Current Balancing
- Loss less Current Sampling
- Low-Cost Implementation
• Fast Transient Response
• Digital Soft Start
• Over Current Protection
• Selection of 2, 3, or 4 Phase Operation
• 50kHz to 1.5MHz Switching Frequency
• Pb-free available
Applications
• Desktop Motherboards
• Voltage Regulator Modules
• Servers and Workstations
Pinout
PKG. NO.
HIP6311ACB
0 to 70
20 Ld SOIC
M20.3
HIP6311ACBZ
(See Note)
0 to 70
20 Ld SOIC
(Pb-free)
M20.3
HIP6311ACBZA
(See Note)
0 to 70
20 Ld SOIC
(Pb-free)
M20.3
*Add “-T” suffix to part number for tape and reel packaging.
NOTE: Intersil Pb-free products employ special Pb-free material
sets; molding compounds/die attach materials and 100% matte tin
plate termination finish, which is compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J Std-020B.
FN9035 Rev 1.00
July 2004
• Precision CORE Voltage Regulation
- ±0.5% System Accuracy Over Temperature
HIP6311A (SOIC)
TOP VIEW
Ordering Information
PART NUMBER
Features
VID4 1
20 VCC
VID3 2
19 PGOOD
VID2 3
18 PWM4
VID1 4
17 ISEN4
VID0 5
16 ISEN1
COMP 6
15 PWM1
FB 7
14 PWM2
FS/DIS 8
13 ISEN2
GND 9
12 ISEN3
VSEN 10
11 PWM3
Page 1 of 16
HIP6311A
Block Diagram
VCC
PGOOD
POWER-ON
RESET (POR)
+
VSEN
THREE
STATE
UV
X 0.9
-
OV
LATCH
CLOCK AND
SAWTOOTH
GENERATOR
S
+
OVP
X1.15

+
-
+
+
PWM1
PWM
-
SOFTSTART
AND FAULT
LOGIC
FS/EN
-

+
PWM2
PWM
-
-
COMP
+

+
PWM
-
VID0
PWM3
-
VID1
VID2
+
D/A
VID3
+
VID4
-

-
E/A
CURRENT
FB
CORRECTION
+
PWM4
PWM
-
PHASE
NUMBER
CHANNEL
DETECTOR
ISEN1
I_TOT
+
+

OC
I_TRIP
+
ISEN2
+
+
ISEN3
ISEN4
GND
FN9035 Rev 1.00
July 2004
Page 2 of 16
HIP6311A
Simplified Power System Diagram
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
VSEN
PWM 1
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
PWM 2
MICROPROCESSOR
HIP6311A
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
PWM 3
PWM 4
VID
SYNCHRONOUS
RECTIFIED BUCK
CHANNEL
Functional Pin Description
converter. Pulling this pin to ground disables the converter and
three states the PWM outputs. See Figure 10.
VID4 1
20 VCC
VID3 2
19 PGOOD
VID2 3
18 PWM4
VID1 4
17 ISEN4
VID0 5
16 ISEN1
VSEN (Pin 10)
COMP 6
15 PWM1
FB 7
14 PWM2
Power good monitor input. Connect to the microprocessorCORE voltage.
FS/DIS 8
13 ISEN2
GND 9
12 ISEN3
VSEN 10
11 PWM3
VID4 (Pin 1), VID3(Pin 2), VID2 (Pin 3), VID1(Pin 4)
and VID0 (Pin 5)
Voltage Identification inputs from microprocessor. These pins
respond to TTL and 3.3V logic signals. The HIP6311A decodes
VID bits to establish the output voltage. See Table 1.
COMP (Pin 6)
Output of the internal error amplifier. Connect this pin to the
external feedback and compensation network.
FB (Pin 7)
Inverting input of the internal error amplifier.
FS/DIS (Pin 8)
Channel frequency, FSW, select and disable. A resistor from
this pin to ground sets the switching frequency of the
FN9035 Rev 1.00
July 2004
GND (Pin 9)
Bias and reference ground. All signals are referenced to this
pin.
PWM1 (Pin 15), PWM2 (Pin 14), PWM3 (Pin 11) and
PWM4 (Pin 18)
PWM outputs for each driven channel in use. Connect these
pins to the PWM input of a HIP6601/2/3 driver. For systems
which use 3 channels, connect PWM4 high. Two channel
systems connect PWM3 and PWM4 high.
ISEN1 (Pin 16), ISEN2 (Pin 13), ISEN3 (Pin 12) and
ISEN4 (Pin 17)
Current sense inputs from the individual converter channel’s
phase nodes. Unused sense lines MUST be left open.
PGOOD (Pin 19)
Power good. This pin provides a logic-high signal when the
microprocessor CORE voltage (VSEN pin) is within specified
limits and Soft-Start has timed out.
VCC (Pin 20)
Bias supply. Connect this pin to a 5V supply.
Page 3 of 16
HIP6311A
Typical Application - 2 Phase Converter Using HIP6601 Gate Drivers
+12V
BOOT
VIN = +5V
PVCC
UGATE
+5V
VCC
PWM
PHASE
DRIVER
HIP6601
COMP
FB
LGATE
GND
VCC
VSEN
+VCORE
PWM4
PGOOD
PWM3
VID4
PWM2
VID3
PWM1
VID2
VID1
+12V
BOOT
VIN = +5V
PVCC
UGATE
MAIN
CONTROL
HIP6311A
PHASE
VCC
VID0
FS/DIS
ISEN4
NC
ISEN3
NC
PWM
DRIVER
HIP6601
LGATE
GND
ISEN2
GND
FN9035 Rev 1.00
July 2004
ISEN1
Page 4 of 16
HIP6311A
Typical Application - 4 Phase Converter Using HIP6602 Gate Drivers
BOOT1
+12V
VIN = +12V
UGATE1
L01
VCC
PHASE1
LGATE1
+5V
DUAL
DRIVER
HIP6602
FB
PVCC
BOOT2
COMP
+5V
VIN +12V
VCC
VSEN
UGATE2
L02
ISEN1
PGOOD
PWM1
VID4
PWM2
VID3
ISEN2
VID2
VID1
PHASE2
PWM1
PWM2
LGATE2
GND
MAIN
CONTROL
HIP6311A
+VCORE
VID0
ISEN3
FS/DIS
PWM3
PWM4
GND
+12V
BOOT3
VIN+12V
ISEN4
UGATE3
L03
VCC
PHASE3
LGATE3
DUAL
DRIVER
HIP6602
PVCC
BOOT4
UGATE4
PWM3
+5V
VIN +12V
L04
PHASE4
PWM4
LGATE4
GND
FN9035 Rev 1.00
July 2004
Page 5 of 16
HIP6311A
Absolute Maximum Ratings
Thermal Information
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+7V
Input, Output, or I/O Voltage . . . . . . . . . . GND -0.3V to VCC + 0.3V
ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5KV
Thermal Resistance (Typical, Note 1)
JA (oC/W)
SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
87
Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . .150oC
Maximum Storage Temperature Range . . . . . . . . . -65oC to 150oC
Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . .300oC
(SOIC - Lead Tips Only)
Recommended Operating Conditions
Supply Voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 5%
Ambient Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 0oC to 70oC
CAUTION: Stress above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational section of this specification is not implied.
NOTE:
1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief 379 for details.
Electrical Specifications
Operating Conditions: VCC = 5V, TA = 0oC to 70oC, Unless Otherwise Specified
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
-
10
15
mA
INPUT SUPPLY POWER
Input Supply Current
RT = 100k, Active and Disabled Maximum Limit
POR (Power-On Reset) Threshold
VCC Rising
4.25
4.38
4.5
V
VCC Falling
3.75
3.88
4.00
V
System Accuracy
Percent system deviation from programmed VID Codes
-0.5
-
0.5
%
DAC (VID0 - VID4) Input Low Voltage
DAC Programming Input Low Threshold Voltage
-
-
0.8
V
DAC (VID0 - VID4) Input High Voltage
DAC Programming Input High Threshold Voltage
2.0
-
-
V
VID Pull-Up
VIDx = 0V or VIDx = 3V
10
20
40
A
Frequency, FSW
RT = 100k, 1%
245
275
305
kHz
Adjustment Range
See Figure 10
0.05
-
1.5
MHz
Disable Voltage
Maximum voltage at FS/DIS to disable controller. IFS/DIS = 1mA.
-
-
1.0
V
DC Gain
RL = 10K to ground
-
72
-
dB
Gain-Bandwidth Product
CL = 100pF, RL = 10K to ground
-
18
-
MHz
Slew Rate
CL = 100pF, Load = 400A
-
5.3
-
V/s
Maximum Output Voltage
Load = 400A
3.6
4.1
-
V
Minimum Output Voltage
Load = -400A
-
0.16
0.5
V
Full Scale Input Current
-
50
-
A
Over-Current Trip Level
-
82.5
-
A
REFERENCE AND DAC
CHANNEL GENERATOR
ERROR AMPLIFIER
ISEN
POWER GOOD MONITOR
Under-Voltage Threshold
VSEN Rising
-
0.92
-
VDAC
Under-Voltage Threshold
VSEN Falling
-
0.90
-
VDAC
PGOOD Low Output Voltage
IPGOOD = 4mA
-
0.18
0.4
V
1.12
1.15
1.2
VDAC
-
2
-
%
PROTECTION
Over-Voltage Threshold
VSEN Rising
Percent Over-Voltage Hysteresis
VSEN Falling after Over-Voltage
FN9035 Rev 1.00
July 2004
Page 6 of 16
HIP6311A
RIN
FB
VIN
HIP6311A
ERROR
AMPLIFIER
+
COMPARATOR
CORRECTION

+
-
Q1
PWM
CIRCUIT
+
L01
PWM1
HIP6601
IL1
-
Q2
PHASE
PROGRAMMABLE
REFERENCE
DAC
+

CURRENT
RISEN1
ISEN1
SENSING
I AVERAGE
CURRENT
AVERAGING
VCORE
+

+
SENSING
CORRECTION
RLOAD
VIN
PHASE
-

COUT
RISEN2
ISEN2
CURRENT
COMPARATOR
+
-
Q3
PWM
CIRCUIT
L02
PWM2
HIP6601
IL2
Q4
FIGURE 1. SIMPLIFIED BLOCK DIAGRAM OF THE HIP6311A VOLTAGE AND CURRENT CONTROL LOOPS FOR A TWO POWER
CHANNEL REGULATOR
Operation
Figure 1 shows a simplified diagram of the voltage regulation
and current control loops. Both voltage and current feedback
are used to precisely regulate voltage and tightly control output
currents, IL1 and IL2, of the two power channels. The voltage
loop comprises the Error Amplifier, Comparators, gate drivers
and output MOSFETS. The Error Amplifier is essentially
connected as a voltage follower that has as an input, the
Programmable Reference DAC and an output that is the
CORE voltage.
Voltage Loop
Feedback from the CORE voltage is applied via resistor RIN to
the inverting input of the Error Amplifier. This signal can drive
the Error Amplifier output either high or low, depending upon
the CORE voltage. Low CORE voltage makes the amplifier
output move towards a higher output voltage level. Amplifier
output voltage is applied to the positive inputs of the
Comparators via the Correction summing networks. Out-ofphase sawtooth signals are applied to the two Comparators
inverting inputs. Increasing Error Amplifier voltage results in
FN9035 Rev 1.00
July 2004
increased Comparator output duty cycle. This increased duty
cycle signal is passed through the PWM CIRCUIT with no
phase reversal and on to the HIP6601, again with no phase
reversal for gate drive to the upper MOSFETs, Q1 and Q3.
Increased duty cycle or ON time for the MOSFET transistors
results in increased output voltage to compensate for the low
output voltage sensed.
Current Loop
The current control loop works in a similar fashion to the
voltage control loop, but with current control information
applied individually to each channel’s Comparator. The
information used for this control is the voltage that is developed
across rDS(ON) of each lower MOSFET, Q2 and Q4, when
they are conducting. A single resistor converts and scales the
voltage across the MOSFETs to a current that is applied to the
Current Sensing circuit within the HIP6311A. Output from
these sensing circuits is applied to the current averaging
circuit. Each PWM channel receives the difference current
signal from the summing circuit that compares the average
sensed current to the individual channel current. When a
power channel’s current is greater than the average current,
Page 7 of 16
HIP6311A
the signal applied via the summing Correction circuit to the
Comparator, reduces the output pulse width of the Comparator
to compensate for the detected “above average” current in that
channel.
Droop Compensation
In addition to control of each power channel’s output current,
the average channel current is also used to provide CORE
voltage “droop” compensation. Average full channel current is
defined as 50A. By selecting an input resistor, RIN, the
amount of voltage droop required at full load current can be
programmed. The average current driven into the FB pin
results in a voltage increase across resistor RIN that is in the
direction to make the Error Amplifier “see” a higher voltage at
the inverting input, resulting in the Error Amplifier adjusting the
output voltage lower. The voltage developed across RIN is
equal to the “droop” voltage. See the “Current Sensing and
Balancing” section for more details.
Applications and Convertor Start-Up
Each PWM power channel’s current is regulated. This enables
the PWM channels to accurately share the load current for
enhanced reliability. The HIP6601, HIP6602 or HIP6603
MOSFET driver interfaces with the HIP6311A. For more
information, see the HIP6601, HIP6602 or HIP6603 data
sheets.
The HIP6311A is capable of controlling up to 4 PWM power
channels. Connecting unused PWM outputs to VCC
automatically sets the number of channels. The phase
relationship between the channels is 360o/number of active
PWM channels. For example, for three channel operation, the
PWM outputs are separated by 120o . Figure 2 shows the
PWM output signals for a four channel system.
PWM 1
PWM 2
PWM 3
PWM 4
FIGURE 2. FOUR PHASE PWM OUTPUT AT 500kHz
Power supply ripple frequency is determined by the channel
frequency, FSW, multiplied by the number of active channels.
FN9035 Rev 1.00
July 2004
For example, if the channel frequency is set to 250kHz and
there are three phases, the ripple frequency is 750kHz.
The IC monitors and precisely regulates the CORE voltage of a
microprocessor. After initial start-up, the controller also
provides protection for the load and the power supply. The
following section discusses these features.
Initialization
The HIP6311A usually operates from an ATX power supply.
Many functions are initiated by the rising supply voltage to the
VCC pin of the HIP6311A. Oscillator, Sawtooth Generator, SoftStart and other functions are initialized during this interval. These
circuits are controlled by POR, Power-On Reset. During this
interval, the PWM outputs are driven to a three state condition that
makes these outputs essentially open. This state results in no
gate drive to the output MOSFETs.
Once the VCC voltage reaches 4.375V (+125mV), a voltage
level to insure proper internal function, the PWM outputs are
enabled and the Soft-Start sequence is initiated. If for any
reason, the VCC voltage drops below 3.875V (+125mV). the
POR circuit shuts the converter down and again three states
the PWM outputs.
Soft-Start
After the POR function is completed with VCC reaching
4.375V, the Soft-Start sequence is initiated. Soft-Start, by its
slow rise in CORE voltage from zero, avoids an over-current
condition by slowly charging the discharged output capacitors.
This voltage rise is initiated by an internal DAC that slowly
raises the reference voltage to the error amplifier input. The
voltage rise is controlled by the oscillator frequency and the
DAC within the HIP6311A, therefore, the output voltage is
effectively regulated as it rises to the final programmed CORE
voltage value.
For the first 32 PWM switching cycles, the DAC output remains
inhibited and the PWM outputs remain three stated. From the
33rd cycle and for another, approximately 150 cycles the PWM
output remains low, clamping the lower output MOSFETs to
ground, see Figure 3. The time variability is due to the Error
Amplifier, Sawtooth Generator and Comparators moving into
their active regions. After this short interval, the PWM outputs
are enabled and increment the PWM pulse width from zero duty
cycle to operational pulse width, thus allowing the output voltage
to slowly reach the CORE voltage. The CORE voltage will reach
its programmed value before the 2048 cycles, but the PGOOD
output will not be initiated until the 2048th PWM switching cycle.
The Soft-Start time or delay time, DT = 2048/FSW. For an
oscillator frequency, FSW, of 200kHz, the first 32 cycles or
160s, the PWM outputs are held in a three state level as
explained above. After this period and a short interval
described above, the PWM outputs are initiated and the
voltage rises in 10.08ms, for a total delay time DT of 10.24ms.
Figure 3 shows the start-up sequence as initiated by a fast
rising 5V supply, VCC, applied to the HIP6311A. Note the short
Page 8 of 16
HIP6311A
rise to the three state level in PWM 1 output during first 32
PWM cycles.
12V ATX
SUPPLY
DELAY TIME
PWM 1
OUTPUT
PGOOD
PGOOD
VCORE
VCORE
5 V ATX
SUPPLY
5V
VCC
VIN = 5V, CORE LOAD CURRENT = 31A
FREQUENCY 200kHz
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
FIGURE 5. SUPPLY POWERED BY ATX SUPPLY
VIN = 12V
FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT
500kHz
Figure 4 shows the waveforms when the regulator is operating
at 200kHz. Note that the Soft-Start duration is a function of the
Channel Frequency as explained previously. Also note the
pulses on the COMP terminal. These pulses are the current
correction signal feeding into the comparator input (see the
Block Diagram on page 2.)
V COMP
Note that Figure 5 shows the 12V gate driver voltage available
before the 5V supply to the HIP6311A has reached its threshold
level. If conditions were reversed and the 5V supply was to rise
first, the start-up sequence would be different. In this case the
HIP6311A will sense an over-current condition due to charging
the output capacitors. The supply will then restart and go
through the normal Soft-Start cycle.
Fault Protection
The HIP6311A protects the microprocessor and the entire
power system from damaging stress levels. Within the
HIP6311A both Over-Voltage and Over-Current circuits are
incorporated to protect the load and regulator.
Over-Voltage
DELAY TIME
PGOOD
VCORE
5V
VCC
VIN = 12V
FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT
200kHz
Figure 5 shows the regulator operating from an ATX supply. In
this figure, note the slight rise in PGOOD as the 5V supply
rises.The PGOOD output stage is made up of NMOS and
PMOS transistors. On the rising VCC, the PMOS device
becomes active slightly before the NMOS transistor pulls
“down”, generating the slight rise in the PGOOD voltage.
FN9035 Rev 1.00
July 2004
The VSEN pin is connected to the microprocessor CORE
voltage. A CORE over-voltage condition is detected when the
VSEN pin goes more than 15% above the programmed VID
level.
The over-voltage condition is latched, disabling normal PWM
operation, and causing PGOOD to go low. The latch can only
be reset by lowering and returning VCC high to initiate a POR
and Soft-Start sequence.
During a latched over-voltage, the PWM outputs will be driven
either low or three state, depending upon the VSEN input.
PWM outputs are driven low when the VSEN pin detects that
the CORE voltage is 15% above the programmed VID level.
This condition drives the PWM outputs low, resulting in the
lower or synchronous rectifier MOSFETS to conduct and shunt
the CORE voltage to ground to protect the load.
If after this event, the CORE voltage falls below the overvoltage limit (plus some hysteresis), the PWM outputs will
three state. The HIP6601 family drivers pass the three state
information along, and shuts off both upper and lower
MOSFETs. This prevents “dumping” of the output capacitors
back through the lower MOSFETs, avoiding a possibly
Page 9 of 16
HIP6311A
destructive ringing of the capacitors and output inductors. If the
conditions that caused the over-voltage still persist, the PWM
outputs will be cycled between three state and VCORE
clamped to ground, as a hysteretic shunt regulator.
Under-Voltage
The VSEN pin also detects when the CORE voltage falls more
than 10% below the VID programmed level. This causes PGOOD
to go low, but has no other effect on operation and is not latched.
There is also hysteresis in this detection point.
CORE Voltage Programming
The voltage identification pins (VID0, VID1, VID3, and VID4)
set the CORE output voltage. Each VID pin is pulled to VCC by
an internal 20A current source and accepts opencollector/open-drain/open-switch-to-ground or standard lowvoltage TTL or CMOS signals.
Table 1 shows the nominal DAC voltage as a function of the
VID codes. The power supply system is 0.5% accurate over
the operating temperature and voltage range.
Over-Current
TABLE 1. VOLTAGE IDENTIFICATION CODES
In the event of an over-current condition, the over-current
protection circuit reduces the average current delivered to less
than 25% of the current limit. When an over-current condition is
detected, the controller forces all PWM outputs into a three
state mode. This condition results in the gate driver removing
drive to the output stages.The HIP6311A goes into a wait delay
timing cycle that is equal to the Soft-Start ramp time. PGOOD
also goes “low” during this time due to VSEN going below its
threshold voltage.To lower the average output dissipation, the
Soft-Start initial wait time is increased from 32 to 2048 cycles,
then the Soft-Start ramp is initiated. At a PWM frequency of
200kHz, for instance, an over-current detection would cause a
dead time of 10.24ms, then a ramp of 10.08ms.
At the end of the delay, PWM outputs are restarted and the
Soft-Start ramp is initiated. If a short is present at that time, the
cycle is repeated. This is the hiccup mode.
Figure 6 shows the supply shorted under operation and the
hiccup operating mode described above. Note that due to the
high short circuit current, over-current is detected before
completion of the start-up sequence so the delay is not quite
as long as the normal Soft-Start cycle.
SHORT APPLIED HERE
PGOOD
SHORT
CURRENT
50A/Div
VID4
VID3
VID2
VID1
VID0
VDAC
1
1
1
1
1
Off
1
1
1
1
0
1.100
1
1
1
0
1
1.125
1
1
1
0
0
1.150
1
1
0
1
1
1.175
1
1
0
1
0
1.200
1
1
0
0
1
1.225
1
1
0
0
0
1.250
1
0
1
1
1
1.275
1
0
1
1
0
1.300
1
0
1
0
1
1.325
1
0
1
0
0
1.350
1
0
0
1
1
1.375
1
0
0
1
0
1.400
1
0
0
0
1
1.425
1
0
0
0
0
1.450
0
1
1
1
1
1.475
0
1
1
1
0
1.500
0
1
1
0
1
1.525
0
1
1
0
0
1.550
0
1
0
1
1
1.575
0
1
0
1
0
1.600
HICCUP MODE. SUPPLY POWERED BY ATX SUPPLY
CORE LOAD CURRENT = 31A, 5V LOAD = 5A
SUPPLY FREQUENCY = 200kHz, V IN = 12V
0
1
0
0
1
1.625
0
1
0
0
0
1.650
ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”
0
0
1
1
1
1.675
FIGURE 6. SHORT APPLIED TO SUPPLY AFTER POWER-UP
0
0
1
1
0
1.700
0
0
1
0
1
1.725
0
0
1
0
0
1.750
0
0
0
1
1
1.775
0
0
0
1
0
1.800
0
0
0
0
1
1.825
0
0
0
0
0
1.850
FN9035 Rev 1.00
July 2004
Page 10 of 16
HIP6311A
RIN
RFB
Cc
COMP
FB
VIN
HIP6311A
-
CORRECTION
+
-
PWM
CIRCUIT
+
L01
Q1
PWM
VCORE
HIP6601
IL
Q2
+
-
PHASE
DIFFERENCE
+
REFERENCE
DAC
RLOAD
COMPARATOR
GENERATOR
COUT
SAWTOOTH
ERROR
AMPLIFIER
CURRENT
ISEN
RISEN
SENSING
CURRENT
SENSING
FROM
OTHER
CHANNELS
TO OTHER
CHANNELS
AVERAGING
TO OVER
CURRENT
TRIP
+
ONLY ONE OUTPUT
STAGE SHOWN
INDUCTOR
CURRENT(S)
FROM
OTHER
CHANNELS
COMPARATOR
REFERENCE
FIGURE 7. SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM SHOWING CURRENT AND VOLTAGE SAMPLING
Current Sensing and Balancing
Overview
The HIP6311A samples the on-state voltage drop across each
synchronous rectifier FET, Q2, as an indication of the inductor
current in that phase, see Figure 7. Neglecting AC effects (to
be discussed later), the voltage drop across Q2 is simply
rDS(ON)(Q2) x inductor current (IL). Note that IL, the inductor
current, is either 1/2, 1/3, or 1/4 of the total current (ILT),
depending on how many phases are in use.
The voltage at Q2’s drain, the PHASE node, is applied to the
RISEN resistor to develop the IISEN current to the HIP6311A
ISEN pin. This pin is held at virtual ground, so the current
through RISEN is IL x rDS(ON)(Q2) / RISEN.
The IISEN current provides information to perform the following
functions:
1. Detection of an over-current condition
2. Reduce the regulator output voltage with increasing load
current (droop)
3. Balance the IL currents in multiple channels
Over-Current, Selecting RISEN
The current detected through the RISEN resistor is averaged with
the current(s) detected in the other 1, 2, or 3 channels. The aver-
FN9035 Rev 1.00
July 2004
aged current is compared with a trimmed, internally generated
current, and used to detect an over-current condition.
The nominal current through the RISEN resistor should be
50A at full output load current, and the nominal trip point for
over-current detection is 165% of that value, or 82.5A.
Therefore, RISEN = IL x rDS(ON) (Q2) / 50A.
For a full load of 25A per phase, and an rDS(ON) (Q2) of 4m,
RISEN = 2k.
The over-current trip point would be 165% of 25A, or ~ 41A per
phase. The RISEN value can be adjusted to change the overcurrent trip point, but it is suggested to stay within 25%of
nominal.
Droop, Selection of RIN
The average of the currents detected through the RISEN
resistors is also steered to the FB pin. There is no DC return
path connected to the FB pin except for RIN, so the average
current creates a voltage drop across RIN. This drop increases
the apparent VCORE voltage with increasing load current,
causing the system to decrease VCORE to maintain balance at
the FB pin. This is the desired “droop” voltage used to maintain
VCORE within limits under transient conditions.
With a high dv/dt load transient, typical of high performance
microprocessors, the largest deviations in output voltage occur
Page 11 of 16
HIP6311A
RIN should be selected to give the desired “droop” voltage at
the normal full load current 50A applied through the RISEN
resistor (or at a different full load current if adjusted as under
“Over-Current, Selecting RISEN” above).
25
20
AMPERES
at the leading and trailing edges of the load transient. In order to
fully utilize the output-voltage tolerance range, the output
voltage is positioned in the upper half of the range when the
output is unloaded and in the lower half of the range when the
controller is under full load. This droop compensation allows
larger transient voltage deviations and thus reduces the size and
cost of the output filter components.
15
10
5
0
RIN = Vdroop/50A
For a Vdroop of 80mV, RIN = 1.6k
The AC feedback components, RFB and Cc, are scaled in
relation to RIN.
FIGURE 8. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING DISABLED
Current Balancing
The detected currents are also used to balance the phase
currents.
The balancing circuit can not make up for a difference in
rDS(ON) between synchronous rectifiers. If a FET has a higher
rDS(ON), the current through that phase will be reduced.
25
20
AMPERES
Each phase’s current is compared to the average of all phase
currents, and the difference is used to create an offset in that
phase’s PWM comparator. The offset is in a direction to reduce
the imbalance.
15
10
5
0
Figures 8 and 9 show the inductor current of a two phase
system without and with current balancing.
Inductor Current
The inductor current in each phase of a multi-phase Buck
converter has two components. There is a current equal to the
load current divided by the number of phases (ILT / n), and a
sawtooth current, (iPK-PK) due to switching. The sawtooth
component is dependent on the size of the inductors, the
switching frequency of each phase, and the values of the input
and output voltage. Ignoring secondary effects, such as series
resistance, the peak to peak value of the sawtooth current can
be described by:
iPK-PK = (VIN x VCORE - VCORE2) / (L x FSW x VIN)
Where: VCORE
VIN
L
FSW
= DC value of the output or VID voltage
= DC value of the input or supply voltage
= value of the inductor
= switching frequency
Example: For VCORE
VIN
L
FSW
Then iPK-PK = 4.3A
FN9035 Rev 1.00
July 2004
= 1.6V,
= 12V,
= 1.3H,
= 250kHz,
FIGURE 9. TWO CHANNEL MULTIPHASE SYSTEM WITH
CURRENT BALANCING ENABLED
The inductor, or load current, flows alternately from VIN
through Q1 and from ground through Q2. The HIP6311A
samples the on-state voltage drop across each Q2 transistor to
indicate the inductor current in that phase. The voltage drop is
sampled 1/3 of a switching period, 1/FSW, after Q1 is turned
OFF and Q2 is turned on. Because of the sawtooth current
component, the sampled current is different from the average
current per phase. Neglecting secondary effects, the sampled
current (ISAMPLE) can be related to the load current (ILT) by:
ISAMPLE = ILT / n + (VINVCORE - 3VCORE2) / (6L x FSW x VIN)
Where: ILT = total load current
n = the number of channels
Example: Using the previously given conditions, and
For ILT = 100A,
n =4
Then ISAMPLE = 25.49A
Page 12 of 16
HIP6311A
As discussed previously, the voltage drop across each Q2
transistor at the point in time when current is sampled is rDSON
(Q2) x ISAMPLE. The voltage at Q2’s drain, the PHASE node,
is applied through the RISEN resistor to the HIP6311A ISEN
pin. This pin is held at virtual ground, so the current into ISEN
is:
ISENSE = ISAMPLE x rDS(ON) (Q2) / RISEN.
RIsen
= ISAMPLE x rDS(ON) (Q2) / 50A
Example: From the previous conditions,
where ILT
= 100A,
ISAMPLE
= 25.49A,
rDS(ON) (Q2)
= 4m
Then: RISEN
= 2.04K and
ICURRENT TRIP
= 165%
Short circuit ILT
= 165A.
Channel Frequency Oscillator
The channel oscillator frequency is set by placing a resistor,
RT, to ground from the FS/DIS pin. Figure 10 is a curve
showing the relationship between frequency, FSW, and resistor
RT. To avoid pickup by the FS/DIS pin, it is important to place
this resistor next to the pin. If this pin is also used to disable the
converter, it is also important to locate the pull-down device
next to this pin.
There are two sets of critical components in a DC-DC
converter using a HIP6311A controller and a HIP6601 gate
driver. The power components are the most critical because
they switch large amounts of energy. Next are small signal
components that connect to sensitive nodes or supply critical
bypassing current and signal coupling.
The power components should be placed first. Locate the input
capacitors close to the power switches. Minimize the length of
the connections between the input capacitors, CIN, and the
power switches. Locate the output inductors and output
capacitors between the MOSFETs and the load. Locate the
gate driver close to the MOSFETs.
The critical small components include the bypass capacitors
for VCC and PVCC on the gate driver ICs. Locate the bypass
capacitor, CBP , for the HIP6311A controller close to the
device. It is especially important to locate the resistors
associated with the input to the amplifiers close to their
respective pins, since they represent the input to feedback
amplifiers. Resistor RT, that sets the oscillator frequency
should also be located next to the associated pin. It is
especially important to place the RSEN resistor(s) at the
respective terminals of the HIP6311A.
1,000
500
200
100
50
RT (k)
causes voltage spikes across the interconnecting impedances
and parasitic circuit elements. These voltage spikes can
degrade efficiency, radiate noise into the circuit and lead to
device over-voltage stress. Careful component layout and
printed circuit design minimizes the voltage spikes in the
converter. Consider, as an example, the turnoff transition of
the upper PWM MOSFET. Prior to turnoff, the upper MOSFET
was carrying channel current. During the turnoff, current stops
flowing in the upper MOSFET and is picked up by the lower
MOSFET. Any inductance in the switched current path
generates a large voltage spike during the switching interval.
Careful component selection, tight layout of the critical
components, and short, wide circuit traces minimize the
magnitude of voltage spikes. Contact Intersil for evaluation
board drawings of the component placement and printed circuit
board.
20
10
5
2
1
10
20
50
100
200
500 1,000 2,000 5,000 10,000
CHANNEL OSCILLATOR FREQUENCY, FSW (kHz)
FIGURE 10. RESISTANCE RT vs FREQUENCY
Layout Considerations
MOSFETs switch very fast and efficiently. The speed with
which the current transitions from one device to another
FN9035 Rev 1.00
July 2004
A multi-layer printed circuit board is recommended. Figure 11
shows the connections of the critical components for one output
channel of the converter. Note that capacitors CIN and COUT
could each represent numerous physical capacitors. Dedicate
one solid layer, usually the middle layer of the PC board, for a
ground plane and make all critical component ground
connections with vias to this layer. Dedicate another solid layer
as a power plane and break this plane into smaller islands of
common voltage levels. Keep the metal runs from the PHASE
terminal to inductor LO1 short. The power plane should support
the input power and output power nodes. Use copper filled
polygons on the top and bottom circuit layers for the phase
nodes. Use the remaining printed circuit layers for small signal
wiring. The wiring traces from the driver IC to the MOSFET gate
and source should be sized to carry at least one ampere of
current.
Page 13 of 16
HIP6311A
+5VIN
USE INDIVIDUAL METAL RUNS
FOR EACH CHANNEL TO HELP
ISOLATE OUTPUT STAGES
+12V
CBP
LOCATE NEXT TO IC PIN(S)
CBP
CT
VCC
CBOOT
CIN
LOCATE NEAR TRANSISTOR
LO1
HIP6601
VCORE
PHASE
COMP FS/DIS
COUT
RT
HIP6311A
RFB
LOCATE NEXT
TO FB PIN
PWM
VCC PVCC
FB
LOCATE NEXT TO IC PIN
RSEN
RIN
VSEN
ISEN
KEY
ISLAND ON POWER PLANE LAYER
ISLAND ON CIRCUIT PLANE LAYER
VIA CONNECTION TO GROUND PLANE
FIGURE 11. PRINTED CIRCUIT BOARD POWER PLANES AND ISLANDS
Component Selection Guidelines
Output Capacitor Selection
The output capacitor is selected to meet both the dynamic
load requirements and the voltage ripple requirements. The
load transient for the microprocessor CORE is characterized
by high slew rate (di/dt) current demands. In general,
multiple high quality capacitors of different size and dielectric
are paralleled to meet the design constraints.
Modern microprocessors produce severe transient load
rates. High frequency capacitors supply the initially transient
current and slow the load rate-of-change seen by the bulk
capacitors. The bulk filter capacitor values are generally
determined by the ESR (effective series resistance) and
voltage rating requirements rather than actual capacitance
requirements.
High frequency decoupling capacitors should be placed as
close to the power pins of the load as physically possible. Be
careful not to add inductance in the circuit board wiring that
could cancel the usefulness of these low inductance
components. Consult with the manufacturer of the load on
specific decoupling requirements.
Use only specialized low-ESR capacitors intended for
switching-regulator applications for the bulk capacitors. The
bulk capacitor’s ESR determines the output ripple voltage
and the initial voltage drop following a high slew-rate
transient’s edge. In most cases, multiple capacitors of small
case size perform better than a single large case capacitor.
Bulk capacitor choices include aluminum electrolytic, OSCon, Tantalum and even ceramic dielectrics. An aluminum
electrolytic capacitor’s ESR value is related to the case size
FN9035 Rev 1.00
July 2004
with lower ESR available in larger case sizes. However, the
equivalent series inductance (ESL) of these capacitors
increases with case size and can reduce the usefulness of
the capacitor to high slew-rate transient loading.
Unfortunately, ESL is not a specified parameter. Consult the
capacitor manufacturer and measure the capacitor’s
impedance with frequency to select a suitable component.
Output Inductor Selection
One of the parameters limiting the converter’s response to a
load transient is the time required to change the inductor
current. Small inductors in a multi-phase converter reduces
the response time without significant increases in total ripple
current.
The output inductor of each power channel controls the
ripple current. The control IC is stable for channel ripple
current (peak-to-peak) up to twice the average current. A
single channel’s ripple current is approximately:
V IN – V OUT V OUT
I = --------------------------------  ---------------V IN
F SW  L
The current from multiple channels tend to cancel each other
and reduce the total ripple current. Figure 12 gives the total
ripple current as a function of duty cycle, normalized to the
parameter  Vo    LxF SW  at zero duty cycle. To determine
the total ripple current from the number of channels and the
duty cycle, multiply the y-axis value by  Vo    LxF SW  .
Small values of output inductance can cause excessive
power dissipation. The HIP6311A is designed for stable
operation for ripple currents up to twice the load current.
However, for this condition, the RMS current is 115% above
the value shown in the following MOSFET Selection and
Page 14 of 16
HIP6311A
the high frequency decoupling and bulk capacitors to supply the
RMS current. Small ceramic capacitors should be placed very
close to the drain of the upper MOSFET to suppress the voltage
induced in the parasitic circuit impedances.
Considerations section. With all else fixed, decreasing the
inductance could increase the power dissipated in the
MOSFETs by 30%.
For bulk capacitance, several electrolytic capacitors
(Panasonic HFQ series or Nichicon PL series or Sanyo MV-GX
or equivalent) may be needed. For surface mount designs,
solid tantalum capacitors can be used, but caution must be
exercised with regard to the capacitor surge current rating.
These capacitors must be capable of handling the surgecurrent at power-up. The TPS series available from AVX, and
the 593D series from Sprague are both surge current tested.
SINGLE
CHANNEL
0.8
VO / (LX FSW)
RIPPLE CURRENT (APEAK-PEAK)
1.0
0.6
2 CHANNEL
0.4
3 CHANNEL
0.2
MOSFET Selection and Considerations
4 CHANNEL
0
0
0.1
0.2
0.3
0.4
0.5
DUTY CYCLE (VO/VIN)
FIGURE 12. RIPPLE CURRENT vs DUTY CYCLE
Input Capacitor Selection
The important parameters for the bulk input capacitors are the
voltage rating and the RMS current rating. For reliable operation,
select bulk input capacitors with voltage and current ratings above
the maximum input voltage and largest RMS current required by
the circuit. The capacitor voltage rating should be at least 1.25
times greater than the maximum input voltage and a voltage
rating of 1.5 times is a conservative guideline. The RMS current
required for a multi-phase converter can be approximated with the
aid of Figure 13.
CURRENT MULTIPLIER
0.5
SINGLE
CHANNEL
0.4
0.3
2 CHANNEL
The equations assume linear voltage-current transitions and
do not model power loss due to the reverse-recovery of the
lower MOSFETs body diode. The gate-charge losses are
dissipated by the Driver IC and don't heat the MOSFETs.
However, large gate-charge increases the switching time, tSW
which increases the upper MOSFET switching losses. Ensure
that both MOSFETs are within their maximum junction
temperature at high ambient temperature by calculating the
temperature rise according to package thermal-resistance
specifications. A separate heatsink may be necessary
depending upon MOSFET power, package type, ambient
temperature and air flow.
2
0.2
I O  r DS  ON   V OUT I O  V IN  t SW  F SW
P UPPER = ------------------------------------------------------------ + ---------------------------------------------------------V IN
2
3 CHANNEL
0.1
0
In high-current PWM applications, the MOSFET power
dissipation, package selection and heatsink are the dominant
design factors. The power dissipation includes two loss
components; conduction loss and switching loss. These losses
are distributed between the upper and lower MOSFETs
according to duty factor (see the following equations). The
conduction losses are the main component of power
dissipation for the lower MOSFETs, Q2 and Q4 of Figure 1.
Only the upper MOSFETs, Q1 and Q3 have significant
switching losses, since the lower device turns on and off into
near zero voltage.
4 CHANNEL
0
0.1
2
I O  r DS  ON    V IN – V OUT 
P LOWER = --------------------------------------------------------------------------------V IN
0.2
0.3
0.4
0.5
DUTY CYCLE (VO/VIN)
FIGURE 13. CURRENT MULTIPLIER vs DUTY CYCLE
First determine the operating duty ratio as the ratio of the
output voltage divided by the input voltage. Find the Current
Multiplier from the curve with the appropriate power channels.
Multiply the current multiplier by the full load output current.
The resulting value is the RMS current rating required by the
input capacitor.
Use a mix of input bypass capacitors to control the voltage
overshoot across the MOSFETs. Use ceramic capacitance for
FN9035 Rev 1.00
July 2004
A diode, anode to ground, may be placed across Q2 and Q4.
These diodes function as a clamp that catches the negative
inductor swing during the dead time between the turn off of the
lower MOSFETs and the turn on of the upper MOSFETs. The
diodes must be a Schottky type to prevent the lossy parasitic
MOSFET body diode from conducting. It is usually acceptable
to omit the diodes and let the body diodes of the lower
MOSFETs clamp the negative inductor swing, but efficiency
could drop one or two percent as a result. The diode's rated
reverse breakdown voltage must be greater than the maximum
input voltage.
Page 15 of 16
HIP6311A
Small Outline Plastic Packages (SOIC)
N
INDEX
AREA
0.25(0.010) M
H
M20.3 (JEDEC MS-013-AC ISSUE C)
B M
20 LEAD WIDE BODY SMALL OUTLINE PLASTIC PACKAGE
E
INCHES
-B-
1
2
SYMBOL
3
L
SEATING PLANE
-A-
h x 45o
A
D
-C-
e
C
0.10(0.004)
C A M
B S
1. Symbols are defined in the “MO Series Symbol List” in Section 2.2 of
Publication Number 95.
MILLIMETERS
MIN
MAX
NOTES
A
0.0926
0.1043
2.35
2.65
-
0.0040
0.0118
0.10
0.30
-
B
0.013
0.0200
0.33
0.51
9
C
0.0091
0.0125
0.23
0.32
-
D
0.4961
0.5118
12.60
13.00
3
E
0.2914
0.2992
7.40
7.60
4
0.050 BSC
1.27 BSC
-
H
0.394
0.419
10.00
10.65
-
h
0.010
0.029
0.25
0.75
5
L
0.016
0.050
0.40
1.27
6
N
NOTES:
MAX
A1
e
A1
B
0.25(0.010) M
µ
MIN

20
0o
20
8o
0o
7
8o
Rev. 0 12/93
2. Dimensioning and tolerancing per ANSI Y14.5M-1982.
3. Dimension “D” does not include mold flash, protrusions or gate burrs.
Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006
inch) per side.
4. Dimension “E” does not include interlead flash or protrusions. Interlead
flash and protrusions shall not exceed 0.25mm (0.010 inch) per side.
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. “L” is the length of terminal for soldering to a substrate.
7. “N” is the number of terminal positions.
8. Terminal numbers are shown for reference only.
9. The lead width “B”, as measured 0.36mm (0.014 inch) or greater
above the seating plane, shall not exceed a maximum value of
0.61mm (0.024 inch)
10. Controlling dimension: MILLIMETER. Converted inch dimensions
are not necessarily exact.
© Copyright Intersil Americas LLC 2001-2004. All Rights Reserved.
All trademarks and registered trademarks are the property of their respective owners.
For additional products, see www.intersil.com/en/products.html
Intersil products are manufactured, assembled and tested utilizing ISO9001 quality systems as noted
in the quality certifications found at www.intersil.com/en/support/qualandreliability.html
Intersil products are sold by description only. Intersil may modify the circuit design and/or specifications of products at any time without notice, provided that such
modification does not, in Intersil's sole judgment, affect the form, fit or function of the product. Accordingly, the reader is cautioned to verify that datasheets are
current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its
subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN9035 Rev 1.00
July 2004
Page 16 of 16
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