AVAGO HCPL-7710-000E 40 ns propagation delay, cmos optocoupler Datasheet

HCPL-7710/0710
40 ns Propagation Delay, CMOS Optocoupler
Data Sheet
Lead (Pb) Free
RoHS 6 fully
compliant
RoHS 6 fully compliant options available;
-xxxE denotes a lead-free product
Description
Available in either an 8-pin DIP or SO-8 package style
respectively, the HCPL-7710 or HCPL-0710 optocouplers
utilize the latest CMOS IC technology to achieve outstanding performance with very low power consumption. The
HCPL-x710 require only two bypass capacitors for complete
CMOS compatibility.
Basic building blocks of the HCPL-x710 are a CMOS LED
driver IC, a high speed LED and a CMOS detector IC. A
CMOS logic input signal controls the LED driver IC which
supplies current to the LED. The detector IC incorporates
an integrated photodiode, a high-speed transimpedance amplifier, and a voltage comparator with an output
driver.
Functional Diagram
**VDD1
VI
NC*
1
8
2
7
IO
3
VDD2**
NC*
6
VO
5
GND2
VI, INPUT
H
L
LED1
GND1
4
SHIELD
Features
• +5 V CMOS compatibility
• 8 ns maximum pulse width distortion
• 20 ns maximum prop. delay skew
• High speed: 12 Mbd
• 40 ns maximum prop. delay
• 10 kV/µs minimum common mode rejection
• -40°C to 100°C temperature range
• Safety and regulatory approvals
UL Recognized 3750 V rms for 1 min. per UL 1577
5000 V rms for 1 min. per UL 1577 (for HCPL-7710
option 020)
CSA Component Acceptance Notice #5
IEC/EN/DIN EN 60747-5-2
–V
IORM = 630 Vpeak for HCPL-7710 Option 060
TRUTH
TABLE
(POSITIVE
LOGIC)
– VIORM
= 560 Vpeak for HCPL-0710 Option 060
LED1
VO, OUTPUT
OFF
Applications
ON
•
•
•
•
•
H
L
Digital fieldbus isolation: DeviceNet, SDS, Profibus
AC plasma display panel level shifting
Multiplexed data transmission
Computer peripheral interface
Microprocessor system interface
* Pin 3 is the anode of the internal LED and must be left
unconnected for guaranteed data sheet performance.
Pin 7 is not connected internally.
** A 0.1 µF bypass capacitor must be connected
between pins 1 and 4, and 5 and 8.
8
IO
VDD2**
7
NC*
6
VO
5
GND2
TRUTH TABLE
(POSITIVE LOGIC)
VI, INPUT
LED1
VO, OUTPUT
H
L
OFF
ON
H
L
CAUTION: It is advised that normal static precautions be taken in handling and assembly
of this component to prevent damage and/or degradation which may be induced by ESD.
Selection Guide
8-Pin DIP
(300 Mil)
HCPL-7710
Small Outline
SO-8
HCPL-0710
Ordering Information
HCPL-0710 and HCPL-7710 are UL Recognized with 3750 Vrms for 1 minute per UL1577.
Option
Part
number
HCPL-7710
HCPL-0710
RoHS
Compliant
Non RoHS
Compliant
-000E
No option
-300E
#300
X
X
-500E
#500
X
X
-020E
-020
-320E
-320
-520E
-520
-060E
#060
-360E
#360
X
X
-560E
#560
X
X
-000E
No option
X
-500E
#500
-060E
#060
-560E
#560
Package
Surface
Mount
Gull
Wing
Tape
& Reel
UL 5000
Vrms/ 1
IEC/EN/DIN
Minute rating EN 60747-5-2 Quantity
50 per tube
300mil
DIP-8
SO-8
X
X
X
X
X
50 per tube
X
X
X
X
50 per tube
X
50 per tube
X
1000 per reel
X
50 per tube
X
50 per tube
X
1000 per reel
100 per tube
X
X
X
1000 per reel
X
1500 per reel
X
100 per tube
X
1500 per reel
To order, choose a part number from the part number column and combine with the desired option from the option
column to form an order entry.
Example 1:
HCPL-7710-560E to order product of Gull Wing Surface Mount package in Tape and Reel packaging with IEC/EN/
DIN EN 60747-5-2 Safety Approval in RoHS compliant.
Example 2:
HCPL-0710 to order product of Small Outline SO-8 package in tube packaging and non RoHS compliant.
Option datasheets are available. Contact your Avago sales representative or authorized distributor for information.
Remarks: The notation ‘#XXX’ is used for existing products, while (new) products launched since 15th July 2001 and
RoHS compliant option will use ‘-XXXE‘.
Package Outline Drawing
HCPL-7710 8-Pin DIP Package
7.62 ± 0.25
(0.300 ± 0.010)
9.65 ± 0.25
(0.380 ± 0.010)
8
TYPE NUMBER
7
6
5
6.35 ± 0.25
(0.250 ± 0.010)
DATE CODE
A XXXX
YYWW
1
2
3
4
1.78 (0.070) MAX.
1.19 (0.047) MAX.
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
5° TYP.
4.70 (0.185) MAX.
0.51 (0.020) MIN.
2.92 (0.115) MIN.
1.080 ± 0.320
(0.043 ± 0.013)
DIMENSIONS IN MILLIMETERS AND (INCHES).
*MARKING CODE LETTER FOR OPTION NUMBERS
"L" = OPTION 020
"V" = OPTION 060
OPTION NUMBERS 300 AND 500 NOT MARKED.
0.65 (0.025) MAX.
2.54 ± 0.25
(0.100 ± 0.010)
Package Outline Drawing
HCPL-7710 Package with Gull Wing Surface Mount Option 300
PAD LOCATION (FOR REFERENCE ONLY)
9.65 ± 0.25
(0.380 ± 0.010)
8
7
6
1.016 (0.040)
1.194 (0.047)
5
4.826 TYP.
(0.190)
6.350 ± 0.25
(0.250 ± 0.010)
1
2
3
9.398 (0.370)
9.906 (0.390)
4
1.194 (0.047)
1.778 (0.070)
1.19
(0.047)
MAX.
1.780
(0.070)
MAX.
9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
4.19 MAX.
(0.165)
1.080 ± 0.320
(0.043 ± 0.013)
0.635 ± 0.25
(0.025 ± 0.010)
0.635 ± 0.130
2.54
(0.025 ± 0.005)
(0.100)
BSC
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES).
Outline (8-pin DIP - Option 300)
0.381 (0.015)
0.635 (0.025)
+ 0.076
0.254 - 0.051
+ 0.003)
(0.010 - 0.002)
12° NOM.
Package Outline Drawing
HCPL-0710 Outline Drawing (Small Outline SO-8 Package)
LAND PATTERN RECOMMENDATION
8
7
6
5
5.994 ± 0.203
(0.236 ± 0.008)
XXXV
YWW
3.937 ± 0.127
(0.155 ± 0.005)
TYPE NUMBER
(LAST 3 DIGITS)
7.49 (0.295)
DATE CODE
PIN ONE 1
2
3
4
1.9 (0.075)
0.406 ± 0.076
(0.016 ± 0.003)
1.270 BSC
(0.050)
0.64 (0.025)
* 5.080 ± 0.127
(0.200 ± 0.005)
7°
3.175 ± 0.127
(0.125 ± 0.005)
1.524
(0.060)
45° X
0.432
(0.017)
0 ~ 7°
0.228 ± 0.025
(0.009 ± 0.001)
0.203 ± 0.102
(0.008 ± 0.004)
* TOTAL PACKAGE LENGTH (INCLUSIVE OF MOLD FLASH)
0.305 MIN.
(0.012)
5.207 ± 0.254 (0.205 ± 0.010)
DIMENSIONS IN MILLIMETERS (INCHES).
LEAD COPLANARITY = 0.10 mm (0.004 INCHES) MAX.
OPTION NUMBER 500 NOT MARKED.
NOTE: FLOATING LEAD PROTRUSION IS 0.15 mm (6 mils) MAX.
Solder Reflow Thermal Profile
TEMPERATURE ( °C)
300
PREHEATING RATE 3°C + 1°C/- 0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC.
200
PEAK
TEMP.
245°C
PEAK
TEMP.
240°C
2.5°C ± 0.5°C/SEC.
30
SEC.
160°C
150°C
140°C
SOLDERING
TIME
200°C
30
SEC.
3°C + 1°C/- 0.5°C
100
PREHEATING TIME
150°C, 90 + 30 SEC.
50 SEC.
TIGHT
TYPICAL
LOOSE
ROOM
TEMPERATURE
0
0
50
100
TIME (SECONDS)
Note: Non-halide flux should be used.
PEAK
TEMP.
230°C
150
200
250
Recommended Pb-Free IR Profile
tp
Tp
TEMPERATURE
TL
Tsmax
260 +0/-5 °C
TIME WITHIN 5 °C of ACTUAL
PEAK TEMPERATURE
20-40 SEC.
217 °C
RAMP-UP
3 °C/SEC. MAX.
150 - 200 °C
RAMP-DOWN
6 °C/SEC. MAX.
Tsmin
ts
PREHEAT
60 to 180 SEC.
25
tL
60 to 150 SEC.
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C
Note: Non-halide flux should be used.
Regulatory Information
The HCPL-x710 have been approved by the following organizations:
UL
Recognized under UL 1577, component recognition
program, File E55361.
CSA
Approved under CSA Component Acceptance Notice
#5, File CA 88324.
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01.
(Option 060 only)
Insulation and Safety Related Specifications
Value
Parameter
Symbol
7710
0710
Units
Minimum External Air
L(I01)
7.1
4.9
mm
Gap (Clearance)
Minimum External
L(I02)
7.4
4.8
mm
Tracking (Creepage)
Minimum Internal Plastic
0.08
0.08
mm
Gap (Internal Clearance)
Tracking Resistance
CTI
≥175
≥175 Volts
(Comparative Tracking Index)
Isolation Group
IIIa
IIIa
All Avago data sheets report the creepage and clearance
inherent to the optocoupler component itself. These
dimen­sions are needed as a starting point for the equipment designer when determining the circuit insulation
requirements. However, once mounted on a printed circuit
board, minimum creepage and clearance require­ments
must be met as specified for individual equipment standards. For creepage, the shortest distance path along the
Conditions
Measured from input terminals to output
terminals, shortest distance through air.
Measured from input terminals to output
terminals, shortest distance path along body.
Insulation thickness between emitter and
detector; also known as distance through
insulation.
DIN IEC 112/VDE 0303 Part 1
Material Group (DIN VDE 0110, 1/89, Table 1)
surface of a printed circuit board between the solder fillets
of the input and output leads must be considered. There
are recommended techniques such as grooves and ribs
which may be used on a printed circuit board to achieve
desired creepage and clearances. Creepage and clearance
distances will also change depending on factors such as
pollution degree and insulation level.
IEC/EN/DIN EN 60747-5-2 Insulation Related Characteristics (Option 060)
Description
Symbol
Installation classification per DIN VDE 0110/1.89, Table 1
for rated mains voltage ≤150 V rms
for rated mains voltage ≤300 V rms
for rated mains voltage ≤450 V rms
Climatic Classification
Pollution Degree (DIN VDE 0110/1.89)
Maximum Working Insulation Voltage
VIORM
Input to Output Test Voltage, Method b†
VPR
VIORM x 1.875 = VPR, 100% Production
Test with tm = 1 sec, Partial Discharge < 5 pC
Input to Output Test Voltage, Method a†
VPR
VIORM x 1.5 = VPR, Type and Sample Test,
tm = 60 sec, Partial Discharge < 5 pC
Highest Allowable Overvoltage†
VIOTM
(Transient Overvoltage, tini = 10 sec)
Safety Limiting Values
(Maximum values allowed in the event of a failure,
also see Thermal Derating curve, Figure 11.)
Case Temperature
TS
Input Current
IS,INPUT
Output Power
PS,OUTPUT
Insulation Resistance at TS, V10 = 500 V
RIO
HCPL-7710
Option 060
HCPL-0710
Option 060
Units
I-IV
I-IV
I-IV
I-III
I-III
55/100/21
55/100/21
2
2
630
560
V peak
1181
1050
V peak
945
840
V peak
6000
4000
V peak
175
230
600
≥109
150
150
600
≥109
°C
mA
mW
Ω
†Refer to the front of the optocoupler section of the Isolation and Control Component Designer’s Catalog, under Product Safety Regulations section IEC/EN/DIN EN 60747-5-2, for a detailed description.
Note: These optocouplers are suitable for “safe electrical isolation” only within the safety limit data. Maintenance of the safety data shall be
ensured by means of protective circuits.
Note: The surface mount classification is Class A in accordance with CECC 00802.
Absolute Maximum Ratings
Parameter
Storage Temperature
Ambient Operating Temperature
Supply Voltages
Input Voltage
Output Voltage
Input Current
Average Output Current
Lead Solder Temperature
Solder Reflow Temperature Profile
Symbol
Min.
Max.
Units
TS
–55
125
°C
TA
–40
+100
°C
VDD1, VDD2
0
6.0
Volts
VI
–0.5
VDD1 +0.5
Volts
VO
–0.5
VDD2 +0.5
Volts
II
–10
+10
mA
IO
10
mA
260°C for 10 sec., 1.6 mm below seating plane
See Solder Reflow Temperature Profile Section
Recommended Operating Conditions
Parameter
Ambient Operating Temperature
Supply Voltages
Logic High Input Voltage
Logic Low Input Voltage
Input Signal Rise and Fall Times
Symbol
Min.
TA
–40
VDD1, VDD2
4.5
VIH
2.0
VIL
0.0
tr, tf
Max.
+100
5.5
VDD1
0.8
1.0
Units
°C
V
V
V
ms
Electrical Specifications
Test conditions that are not specified can be anywhere within the recommended operating range.
All typical specifications are at TA = +25°C, VDD1 = VDD2 = +5 V.
DC Specifications
Parameter
Symbol
Logic Low Input
Supply Current [1]
Typ.
Max.
Units
Test Conditions
IDD1L
6.0
10.0
mA
VI = 0 V
Logic High Input
Supply Current
IDD1H
1.5
3.0
mA
VI = VDDI
Input Supply Current
IDD1
13.0
mA
Output Supply Current
IDD2
11.0
mA
Input Current
II
10
µA
Logic High Output
VOH
Voltage
Min.
5.5
-10
4.4
4.0
Logic Low Output
VOL
Voltage
5.0
V
4.8
IO = -20 µA, VI = VIH
IO = -4 mA, VI = VIH
0
0.5
0.1
V
1.0
IO = -20 µA, VI = VIL
IO = -4 mA, VI = VIL
Typ.
Max.
Test Conditions
Switching Specifications
Parameter
Symbol
Min.
Units
Propagation Delay Time
tPHL
20
40
ns
to Logic Low Output [2]
CL = 15 pF
CMOS Signal Levels
Propagation Delay Time
tPHL
20
40
ns
to Logic Low Output [2]
CL = 15 pF
CMOS Signal Levels
Propagation Delay Time
tPLH
23
40
ns
to Logic High Output
CL = 15 pF
CMOS Signal Levels
Pulse Width [3]
PW
80
ns
CL = 15 pF
CMOS Signal Levels
Data Rate [3]
12.5
MBd
CL = 15 pF
CMOS Signal Levels
Pulse Width Distortion [4]
PWD
3
8
ns
|tPHL - tPLH|
CL = 15 pF
CMOS Signal Levels
Propagation Delay Skew [5]
CL = 15 pF
tPSK
20
ns
Output Rise Time
tR
9
ns
(10 - 90%)
CL = 15 pF
CMOS Signal Levels
Output Fall Time
tF
8
ns
(90 - 10%)
CL = 15 pF
CMOS Signal Levels
Common Mode
|CMH|
10
20
kV/µs
Transient Immunity at
Logic High Output [6]
VI = VDD1, VO >
0.8 VDD1,
VCM = 1000 V
Common Mode
|CML|
10
20
kV/µs
Transient Immunity at
Logic Low Output [6]
VI = 0 V, VO > 0.8 V,
VCM = 1000 V
Input Dynamic Power
Dissipation Capacitance [7]
CPD1
60
pF
Output Dynamic Power
Dissipation Capacitance [7]
CPD2
10
pF
Package Characteristics
Parameter
Symbol Min.
Input-Output Momentary
Withstand Voltage [8, 9, 10]
0710
VISO
Typ.
Max.
3750
7710
3750
Option 020
5000
Units
Test Conditions
Vrms
RH = 50%,
t = 1 min.,
TA = 25°C
Resistance
(Input-Output) [8]
RI-O
1012
W
VI-O = 500 Vdc
Capacitance
(Input-Output) [8]
CI-O
0.6
pF
f = 1 MHz
Input Capacitance [11]
CI
3.0
qjci
145
°C/W
Thermocouple
located at center
underside of package
Input IC Junction-to-Case
Thermal Resistance
-7710
Output IC Junction-to-Case
Thermal Resistance
-7710
-0710
160
qjco
140
-0710
135
Package Power Dissipation
PPD
150
mW
Notes:
1. The LED is ON when VI is low and OFF when VI is high.
2. tPHL propagation delay is measured from the 50% level on the falling edge of the VI signal to the 50% level of the falling edge of the VO signal.
tPLH propagation delay is measured from the 50% level on the rising edge of the VI signal to the 50% level of the rising edge of the VO signal.
3. Mimimum Pulse Width is the shortest pulse width at which 10% maximum, Pulse Width Distortion can be guaran­teed. Maximum Data Rate is
the inverse of Minimum Pulse Width. Operating the HCPL-x710 at data rates above 12.5 MBd is possible provided PWD and data dependent
jitter increases and relaxed noise margins are tolerable within the application. For instance, if the maximum allowable variation of bit width is
30%, the maximum data rate becomes 37.5 MBd. Please note that HCPL-x710 performances above 12.5 MBd are not guaranteed by HewlettPackard.
4. PWD is defined as |tPHL - tPLH|. %PWD (percent pulse width distortion) is equal to the PWD divided by pulse width.
5. tPSK is equal to the magnitude of the worst case difference in tPHL and/or tPLH that will be seen between units at any given temperature within
the recommended operating conditions.
6. CMH is the maximum common mode voltage slew rate that can be sustained while maintaining VO > 0.8 VDD2. CML is the maximum common
mode voltage slew rate that can be sustained while maintaining VO < 0.8 V. The common mode voltage slew rates apply to both rising and
falling common mode voltage edges.
7. Unloaded dynamic power dissipation is calculated as follows: CPD * VDD2 * f + IDD * VDD, where f is switching frequency in MHz.
8. Device considered a two-terminal device: pins 1, 2, 3, and 4 shorted together and pins 5, 6, 7, and 8 shorted together.
9. In accordance with UL1577, each HCPL-0710 is proof tested by applying an insulation test voltage ≥4500 VRMS for 1 second (leakage detection current limit, II-O ≤5 µA). Each HCPL-7710 is proof tested by applying an insulation test voltage ≥ 4500 V rms for 1 second (leakage detection current limit, II-O ≤ 5 µA).
10. The Input-Output Momentary With­stand Voltage is a dielectric voltage rating that should not be interpreted as an input-output continuous
voltage rating. For the continuous voltage rating refer to your equipment level safety specification or Avago Application Note 1074 entitled
“Optocoupler Input-Output Endurance Voltage.”
11. CI is the capacitance measured at pin 2 (VI).
2.2
5
0 °C
25 °C
85 °C
2
1.9
1.8
1
1.7
0
1
2
3
4
VI (V)
Figure 1. Typical output voltage vs. input voltage.
HCPL-0710 fig 1
27
TPLH, TPHL (ns)
3
0
29
0 °C
25 °C
85 °C
2.0
VITH (V)
4
VO (V)
2.1
5
1.6
4.5
25
TPLH
23
TPHL
21
19
17
4.75
5
5.25
5.5
VDD1 (V)
Figure 2. Typical input voltage switching threshold vs.
input supply voltage.
HCPL-0710 fig 2
15
0
10
20 30
40
50
60 70
80
TA (C)
Figure 3. Typical propagation delays vs. temperature.
HCPL-0710 fig 3
4
7
15
6
3
2
TF (ns)
TR (ns)
PWD (ns)
14
4
13
1
0
3
0
20
40
60
12
80
0
20
40
TA (C)
60
2
80
6
27
5
25
TPLH
23
21
19
3
2
15
15
20
25
30
35
40
45
0
50
17
15
13
11
9
1
17
7
15
20
25
30
35
40
45
5
50
0
5
10
C I (pF)
CI (pF)
Figure 7. Typical propagation delays vs. output load
capacitance.
80
25
TR (ns)
PWD (ns)
TPHL
60
HCPL-0710 fig 6
4
19
40
Figure 6. Typical fall time vs. temperature.
HCPL-0710 fig 5
29
21
20
TA (C)
Figure 5. Typical rise time vs. temperature.
HCPL-0710 fig 4
23
0
TA (C)
Figure 4. Typical pulse width distortion vs. temperature.
TPLH, TPHL (ns)
5
Figure 8. Typical pulse width distortion vs. output load
capacitance.
15
20
25
30
35
CI (pF)
Figure 9. Typical rise time vs. load capacitance.
HCPL-0710 fig 9
FALL TIME (ns)
8
7
6
5
4
3
2
1
0
0
5
10
15
20
25
30
CI (pF)
Figure 10. Typical fall time vs. load capacitance.
HCPL-0710 fig 10
35
STANDARD 8 PIN DIP PRODUCT
800
P S (mW)
I S (mA)
700
600
500
400
300
(230)
200
100
0
0
25
50
75
100 125 150 175 200
T A - CASE TEMPERATURE - o C
OUTPUT POWER - P S , INPUT CURRENT - I S
9
OUTPUT POWER - P S , INPUT CURRENT - I S
10
SURFACE MOUNT SO8 PRODUCT
800
P S (mW)
I S (mA)
700
600
500
400
300
200
(150)
100
0
0
25
50
75
100 125 150 175 200
T A - CASE TEMPERATURE - o C
Figure 11. Thermal derating curve, dependence of Safety Limiting Value with case temperature per IEC/EN/DIN EN
60747-5-2.
Application Information
Bypassing and PC Board Layout
The HCPL-x710 optocouplers are extremely easy to
use. No external interface circuitry is required because
the HCPL-x710 use high-speed CMOS IC technology
allowing CMOS logic to be connected directly to the
inputs and outputs.
As shown in Figure 12, the only external components
VDD1
VDD2
8
1
required for proper operation are two bypass capacitors.
Capacitor values should be between 0.01 µF and 0.1 µF.
For each capacitor, the total lead length between both
ends of the capacitor and the power-supply pins should
not exceed 20 mm. Figure 13 illustrates the recommended printed circuit board layout for the HPCL-x710.
C1
C2
VI
NC 3
GND1
7 NC
710
YYWW
2
6
VO
5
4
GND2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 12. Recommended Printed Circuit Board layout.
VDD1
VDD2
710
YYWW
VI
C1
C2
VO
HCPL-0710 fig 11
GND1
GND2
C1, C2 = 0.01 µF TO 0.1 µF
Figure 13. Recommended Printed Circuit Board layout.
Propagation Delay, Pulse-Width Distortion and Propagation Delay
Skew
Propagation Delay is a figure of merit which
describes
HCPL-0710
fig 12
how quickly a logic signal propagates through a
system. The propaga­tion delay from low to high (tPLH)
is the amount of time required for an input signal to
propagate to the output, causing the output to change
INPUT
VI
5 V CMOS
50%
tPLH
OUTPUT
VO
from low to high. Similarly, the propagation delay from
high to low (tPHL) is the amount of time required for the
input signal to propagate to the output, causing the
output to change from high to low. See Figure 14.
0V
tPHL
90%
90%
10%
10%
Figure 14.
10
HCPL-0710 fig 13
VOH
2.5 V CMOS
VOL
Pulse-width distortion (PWD) is the difference between
tPHL and tPLH and often determines the maxi­mum data
rate capability of a transmission system. PWD can be
expressed in percent by dividing the PWD (in ns) by
the minimum pulse width (in ns) being trans­mitted.
Typically, PWD on the order of 20 - 30% of the minimum
pulse width is tolerable. The PWD specification for the
HCPL-x710 is 8 ns (10%) maximum across recommended operating condi­tions. 10% maximum is dictated
by the most stringent of the three fieldbus standards,
PROFIBUS.
Propagation delay skew is defined as the difference between the minimum and maximum propa­
gation delays, either tPLH or tPHL, for any given group
of optocoup­lers which are operating under the same
conditions (i.e., the same drive current, supply volt­age,
output load, and operating temperature). As illustrated
in Figure 15,­ if the inputs of a group of optocouplers
are switched either ON or OFF at the same time, tPSK is
the difference between the shortest propagation delay,
either tPLH or tPHL, and the longest propagation delay,
either tPLH or tPHL.
Propagation delay skew, tPSK, is an important parameter
to con­sider in parallel data applications where synchronization of signals on parallel data lines is a concern. If
the parallel data is being sent through a group of optocouplers, differences in propagation delays will cause
the data to arrive at the outputs of the optocouplers at
different times. If this difference in propagation delay
is large enough it will determine the maximum rate at
which parallel data can be sent through the optocouplers.
As mentioned earlier, tPSK can determine the maximum
parallel data transmission rate. Figure 16 is the timing
diagram of a typical parallel data application with both
the clock and data lines being sent through the optocouplers. The figure shows data and clock signals at the
inputs and outputs of the optocouplers. In this case the
data is assumed to be clocked off of the rising edge of
the clock.
VI
DATA
50%
INPUTS
VO
CLOCK
2.5 V,
CMOS
tPSK
VI
DATA
50%
OUTPUTS
tPSK
CLOCK
2.5 V,
CMOS
VO
Figure 15. Propagation delay skew waveform.
HCPL-0710 fig 14
Propagation delay skew repre­sents the uncertainty of
where an edge might be after being sent through an
optocoupler. Figure 16 shows that there will be uncertainty in both the data and clock lines. It is important
that these two areas of uncertainty not overlap,
otherwise the clock signal might arrive before all of
the data outputs have settled, or some of the data
outputs may start to change before the clock signal
has arrived. From these considerations, the absolute
minimum pulse width that can be sent through op-
11
tPSK
Figure 16. Parallel data transmission example.
HCPL-0710 fig 15
tocouplers in a parallel application is twice tPSK.
A cautious design should use a slightly longer pulse
width to ensure that any additional uncertainty in the
rest of the circuit does not cause a problem.
The HCPL-x710 optocouplers offer the advantage of
guaranteed specifications for propagation delays, pulsewidth distortion, and propagation delay skew over the
recommended temperature and power supply ranges.
Digital Field Bus Communication Networks
To date, despite its many draw­backs, the 4 - 20 mA
analog current loop has been the most widely accepted
standard for implementing process control systems.
In today’s manufacturing environment, however,
automated systems are expected to help manage
the process, not merely monitor it. With the advent
of digital field bus communication networks such as
DeviceNet, PROFIBUS, and Smart Distributed Systems
(SDS), gone are the days of constrained information.
Controllers can now receive multiple readings from field
devices (sensors, actuators, etc.) in addition to diagnostic information.
The physical model for each of these digital field bus
communica­tion networks is very similar as shown in
Figure 17. Each includes one or more buses, an interface
unit, optical isolation, transceiver, and sensing and/or
actuating devices.
CONTROLLER
BUS
INTERFACE
OPTICAL
ISOLATION
TRANSCEIVER
FIELD BUS
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
TRANSCEIVER
OPTICAL
ISOLATION
OPTICAL
ISOLATION
OPTICAL
ISOLATION
OPTICAL
ISOLATION
BUS
INTERFACE
BUS
INTERFACE
BUS
INTERFACE
BUS
INTERFACE
XXXXXX
SENSOR
YYY
DEVICE
CONFIGURATION
MOTOR
CONTROLLER
MOTOR
STARTER
Figure 17. Typical field bus communication physical model.
HCPL-0710 fig 16
Optical Isolation for Field Bus Networks
To recognize the full benefits of these networks, each
recom­mends providing galvanic isolation using Avago
optocouplers. Since network communication is bi-directional (involving receiving data from and transmitting
data onto the network), two Avago optocouplers are
needed. By providing galvanic isolation, data integrity is
retained via noise reduction and the elimination of false
signals. In addition, the network receives maximum protection from power system faults and ground loops.
Within an isolated node, such as the DeviceNet Node
shown in Figure 18, some of the node’s components are
referenced to a ground other than V- of the network.
12
These components could include such things as devices
with serial ports, parallel ports, RS232 and RS485 type
ports. As shown in Figure 18, power from the network is
used only for the transceiver and input (network) side of
the optocouplers.
Isolation of nodes connected to any of the three types of
digital field bus networks is best achieved by using the
HCPL-x710 optocouplers. For each network, the HCPLx710 satisify the critical propagation delay and pulse
width distortion require­ments over the temperature
range of 0°C to +85°C, and power supply voltage range
of 4.5 V to 5.5 V.
AC LINE
NODE/APP SPECIFIC
uP/CAN
HCPL
x710
LOCAL
NODE
SUPPLY
GALVANIC
ISOLATION
BOUNDARY
HCPL
x710
5 V REG.
TRANSCEIVER
DRAIN/SHIELD
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
SIGNAL
POWER
NETWORK
POWER
SUPPLY
Figure 18. Typical DeviceNet node.
Implementing DeviceNet and SDS withHCPL-0710
the HCPL‑x710
fig 17
Isolated Node Powered by the Network
With transmission rates up to 1 Mbit/s, both DeviceNet
and SDS are based upon the same broadcast-oriented,
communica­tions protocol — the Controller Area
Network (CAN). Three types of isolated nodes are recommended for use on these networks: Isolated Node
Powered by the Network (Figure 19), Isolated Node
with Transceiver Powered by the Network (Figure 20),
and Isolated Node Providing Power to the Network
(Figure 21).
This type of node is very flexible and as can be seen in
Figure 19, is regarded as “isolated” because not all of its
components have the same ground reference. Yet, all
compo­nents are still powered by the network. This node
contains two regulators: one is isolated and powers the
CAN controller, node-specific application and isolated
(node) side of the two optocoup­lers while the other is
non-isolated. The non-isolated regulator supplies the
transceiver and the non-isolated (network) half of the
two optocouplers.
NODE/APP SPECIFIC
uP/CAN
HCPL
x710
ISOLATED
SWITCHING
POWER
SUPPLY
HCPL
x710
GALVANIC
ISOLATION
BOUNDARY
REG.
TRANSCEIVER
DRAIN/SHIELD
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
SIGNAL
POWER
NETWORK
POWER
SUPPLY
Figure 19. Isolated node powered by the network.
13
HCPL-0710 fig 18
Isolated Node with Transceiver Powered by the Network
Figure 20 shows a node powered by both the network
and another source. In this case, the trans­ceiver and
isolated (network) side of the two optocouplers are
powered by the network. The rest of the node is
powered by the AC line which is very beneficial when
an application requires a significant amount of power.
This method is also desirable as it does not heavily load
the network.
More importantly, the unique “dual-inverting” design
of the HCPL-x710 ensure the network will not “lock-up”
if either AC line power to the node is lost or the node
powered-off. Specifically, when input power (VDD1) to
the HCPL-x710 located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL‑x710
output voltage (VO) go HIGH.
*Bus V+ Sensing
It is suggested that the Bus V+ sense block shown in
Figure 20 be implemented. A locally powered node with
an un-powered isolated Physical Layer will accumulate
errors and become bus-off if it attempts to transmit. The
Bus V+ sense signal would be used to change the BOI
attribute of the DeviceNet Object to the “auto-reset”
(01) value. Refer to Volume 1, Section 5.5.3. This would
cause the node to continually reset until bus power was
detected. Once power was detected, the BOI attribute
would be returned to the “hold in bus-off” (00) value.
The BOI attribute should not be left in the “auto-reset”
(01) value since this defeats the jabber protection capability of the CAN error confinement. Any inexpensive
low frequency optical isolator can be used to implement
this feature.
AC LINE
NODE/APP SPECIFIC
NON ISO
5V
uP/CAN
HCPL
0710
HCPL
0710
HCPL
0710
GALVANIC
ISOLATION
BOUNDARY
REG.
TRANSCEIVER
DRAIN/SHIELD
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
SIGNAL
POWER
NETWORK
POWER
SUPPLY
* OPTIONAL FOR BUS V + SENSE
Figure 20. Isolated node with transceiver powered by the network.
HCPL-0710 fig 19
14
Isolated Node Providing Power to the Network
Figure 21 shows a node providing power to the
network. The AC line powers a regulator which provides
five (5) volts locally. The AC line also powers a 24 volt
isolated supply, which powers the network, and another
five-volt regulator, which, in turn, powers the transceiver and isolated (network) side of the two optocouplers.
This method is recommended when there are a limited
number of devices on the network that don’t require
much power, thus eliminating the need for separate
power supplies.
More importantly, the unique “dual-inverting” design
of the HCPL-x710 ensure the network will not “lock-up”
if either AC line power to the node is lost or the node
powered-off. Specifically, when input power (VDD1) to
the HCPL-x710 located in the transmit path is eliminated, a RECESSIVE bus state is ensured as the HCPL‑x710
output voltage (VO) go HIGH.
AC LINE
DEVICENET NODE
NODE/APP SPECIFIC
5 V REG.
uP/CAN
HCPL
0710
ISOLATED
SWITCHING
POWER
SUPPLY
HCPL
0710
GALVANIC
ISOLATION
BOUNDARY
5 V REG.
TRANSCEIVER
DRAIN/SHIELD
V+ (SIGNAL)
V– (SIGNAL)
V+ (POWER)
V– (POWER)
SIGNAL
POWER
Figure 21. Isolated node providing power to the network.
HCPL-0710 fig 20
15
Power Supplies and Bypassing
The recommended DeviceNet application circuit is
shown in Figure 22. Since the HCPL-x710 are fully compatible with CMOS logic level signals, the optocoup­ler is
connected directly to the CAN transceiver. Two bypass
capacitors (with values between 0.01 and 0.1 µF) are
required and should be located as close as possible to
GALVANIC
ISOLATION
BOUNDARY
ISO 5 V
1 VDD1
TX0
2 VIN
0.01 µF
3
5V
VDD2 8
+
0.01
µF
7
HCPL-0710
TxD
VO 6
4 GND1
GND2 5
5 V+
+
C4
0.01 µF
3 SHIELD
2 CAN–
CANL
REF
GND
0.01
µF
3
4 CAN+
82C250
GND1 4
6 VO
7
8 VDD2
RXD
D1
30 V
VIN 2
VDD1 1
ISO 5 V
5V
Figure 22. Recommended DeviceNet application circuit.
HCPL-0710 fig 21
Implementing PROFIBUS with the HCPL-x710
An acronym for Process Fieldbus, PROFIBUS is essentially a twisted-pair serial link very similar to RS-485
capable of achieving high-speed communi­cation up to
12 MBd. As shown in Figure 23, a PROFIBUS Control­ler
(PBC) establishes the connec­tion of a field automation
unit (control or central processing station) or a field
device to the transmission medium. The PBC consists
of the line transceiver, optical isolation, frame character
transmitter/receiver (UART), and the FDL/APP processor
with the interface to the PROFIBUS user.
1 V–
VREF
HCPL-0710
0.01 µF
+
VCC
Rs
5 GND2
LINEAR OR
SWITCHING
REGULATOR
CANH
GND
RX0
the input and output power-supply pins of the HCPLx710. For each capacitor, the total lead length between
both ends of the capacitor and the power supply pins
should not exceed 20 mm. The bypass capac­itors are
required because of the high-speed digital nature of the
signals inside the optocoupler.
PROFIBUS USER:
CONTROL STATION
(CENTRAL PROCESSING)
OR FIELD DEVICE
USER INTERFACE
FDL/APP
PROCESSOR
UART
PBC
OPTICAL ISOLATION
TRANSCEIVER
MEDIUM
Figure 23. PROFIBUS Controller (PBC).
16
HCPL-0710 fig 22
C1
0.01 µF
500 V
R1
1M
Power Supplies and Bypassing
The recommended PROFIBUS application circuit is
shown in Figure 24. Since the HCPL-x710 are fully compatible with CMOS logic level signals, the optocoup ­
ler is connected directly to the transceiver. Two bypass
capacitors (with values between 0.01 and 0.1 µF) are
required and should be located as close as possible to
the input and output power-supply pins of the HCPLx710. For each capacitor, the total lead length between
both ends of the capacitor and the power supply pins
should not exceed 20 mm. The bypass capac­itors are
required because of the high-speed digital nature of the
signals inside the optocoupler.
Being very similar to multi-station RS485 systems, the
HCPL-061N optocoupler provides a transmit disable
function which is necessary to make the bus free after
each master/slave transmission cycle. Specifically, the
HCPL-061N disables the transmitter of the line driver
by putting it into a high state mode. In addition, the
HCPL-061N switches the RX/TX driver IC into the listen
mode. The HCPL-061N offers HCMOS compatibility and
the high CMR performance (1 kV/µs at VCM = 1000 V)
essential in industrial communication interfaces.
GALVANIC
ISOLATION
BOUNDARY
5V
ISO 5 V
8 VDD2
VDD1 1
VIN 2
7
0.01 µF
ISO 5 V
HCPL-x710
6 VO
Rx
3
5 GND2
1
0.01
µF
A
0.01
µF
GND1 4
4
ISO 5 V
1 VDD1
2 VIN
Tx
0.01
µF
7
VO 6
4 GND1
GND2 5
ISO 5 V
VCC 8
1
5V
Tx ENABLE
1, 0 kΩ
2 ANODE
VE 7
3 CATHODE
VO 6
4
0.01
µF
680 Ω
GND 5
HCPL-061N
HCPL-0710 fig 23
Figure 24. Recommended PROFIBUS application circuit.
17
+
RT
B
7
SHIELD
–
DE
GND
5
0.01 µF
HCPL-x710
3
0.01 µF
D
2 RE
VDD2 8
6
SN75176B
3
5V
R
8
VCC
1M
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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies Limited in the United States and other countries.
Data subject to change. Copyright © 2007 Avago Technologies Limited. All rights reserved. Obsoletes AV01-0564EN
AV02-0641EN - January 4, 2008