LT1009 www.ti.com................................................................................................................................................................. SLVS013N – MAY 1987 – REVISED MAY 2009 2.5-V INTEGRATED REFERENCE CIRCUIT FEATURES 1 • • • • • • Excellent Temperature Stability Initial Tolerance: 0.2% Max Dynamic Impedance: 0.6 Ω Max D OR PW PACKAGE (TOP VIEW) NC NC NC ANODE 1 8 2 7 3 6 4 5 Wide Operating Current Range Directly Interchangeable With LM136 Needs No Adjustment for Minimum Temperature Coefficient LP PACKAGE (TOP VIEW) CATHODE NC CATHODE ADJ ANODE CATHODE ADJ NC − No internal connection DESCRIPTION/ORDERING INFORMATION The LT1009 reference circuit is a precision-trimmed 2.5-V shunt regulator featuring low dynamic impedance and a wide operating current range. The maximum initial tolerance is ±5 mV in the LP package and ±10 mV in the D and PW packages. The reference tolerance is achieved by on-chip trimming, which minimizes the initial voltage tolerance and the temperature coefficient, αVZ. Although the LT1009 needs no adjustments, a third terminal (ADJ) allows the reference voltage to be adjusted ±5% to eliminate system errors. In many applications, the LT1009 can be used as a terminal-for-terminal replacement for the LM136-2.5, which eliminates the external trim network. The LT1009 uses include 5-V system references, 8-bit analog-to-digital converter (ADC) and digital-to-analog converter (DAC) references, and power-supply monitors. The device also can be used in applications such as digital voltmeters and current-loop measurement and control systems. The LT1009C is characterized for operation from 0°C to 70°C. The LT1009I is characterized for operation from –40°C to 85°C. SYMBOL ANODE CATHODE ADJ 1 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 1987–2009, Texas Instruments Incorporated LT1009 SLVS013N – MAY 1987 – REVISED MAY 2009................................................................................................................................................................. www.ti.com ORDERING INFORMATION (1) PACKAGE (2) TA SOIC – D 0°C to 70°C TO-226/TO-92 – LP TSSOP – PW SOIC – D –40°C to 85°C TO-226/TO-92 – LP TSSOP – PW (1) (2) ORDERABLE PART NUMBER Tube of 75 LT1009CD Reel of 2500 LT1009CDR Bulk of 1000 LT1009CLP Ammo of 2000 LT1009CLPM Reel of 2000 LT1009CLPR Tube of 150 LT1009CPW Reel of 2000 LT1009CPWR Tube of 75 LT1009ID Reel of 2500 LT1009IDR Bulk of 1000 LT1009ILP Ammo of 2000 LT1009ILPM Reel of 2000 LT1009ILPR Tube of 150 LT1009IPW Reel of 2000 LT1009IPWR TOP-SIDE MARKING 1009C LT1009C 1009C 1009I LT1009I 1009I For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com. Package drawings, thermal data, and symbolization are available at www.ti.com/packaging. SCHEMATIC CATHODE Q14 Q11 24 kΩ 24 kΩ 6.6 kΩ Q8 20 pF Q7 30 pF Q10 10 kΩ 500 Ω Q2 Q9 Q4 30 kΩ ADJ Q1 6.6 kΩ Q6 Q3 Q12 Q5 720 Ω Q13 ANODE NOTE: All component values shown are nominal. 2 Submit Documentation Feedback Copyright © 1987–2009, Texas Instruments Incorporated Product Folder Link(s): LT1009 LT1009 www.ti.com................................................................................................................................................................. SLVS013N – MAY 1987 – REVISED MAY 2009 ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT IR Reverse current 20 mA IF Forward current 10 mA θJA Package thermal impedance (2) (3) TJ Operating virtual junction temperature Tstg Storage temperature range (1) (2) (3) D package 97 LP package 140 PW package 149 –65 °C/W 150 °C 150 °C Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. Maximum power dissipation is a function of TJ(max), θJA, and TA. The maximum allowable power dissipation at any allowable ambient temperature is PD = (TJ(max) – TA)/θJA. Operating at the absolute maximum TJ of 150°C can affect reliability. The package thermal impedance is calculated in accordance with JESD 51-7. RECOMMENDED OPERATING CONDITIONS TA Operating free-air temperature range LT1009C LT1009I MIN MAX 0 70 –40 85 Submit Documentation Feedback Copyright © 1987–2009, Texas Instruments Incorporated Product Folder Link(s): LT1009 UNIT °C 3 LT1009 SLVS013N – MAY 1987 – REVISED MAY 2009................................................................................................................................................................. www.ti.com ELECTRICAL CHARACTERISTICS at specified free-air temperature PARAMETER TA (1) TEST CONDITIONS D/PW package VZ Reference voltage IZ = 1 mA LP package D/PW package LP package VF Forward voltage Full range IF = 2 mA MAX MIN TYP MAX 2.49 2.5 2.51 2.49 2.5 2.51 2.495 2.5 2.5 2.505 2.505 2.495 2.485 2.515 2.475 2.525 2.491 2.509 2.48 2.52 0.4 1 0.4 1 Change in reference voltage with temperature αVZ Average temperature coefficient of reference voltage (2) IZ = 1 mA, VADJ = open ΔVZ Change in reference voltage with current IZ = 400 µA to 10 mA ΔVZ/Δt Long-term change in reference voltage IZ = 1 mA ZZ Reference impedance IZ = 1 mA 125 125 45 45 25°C IZ = 1 mA, VADJ = 0.6 V to VZ – 0.6 V ΔVZ(temp) UNIT V V mV D/PW package Full range LP package LT1009I TYP 25°C IZ = 1 mA, VADJ = GND to VZ Adjustment range (1) (2) 25°C LT1009C MIN 0°C to 70°C 15 5 15 4 15 25 –40°C to 85°C 25°C 2.6 Full range 10 15 25 20 35 2.6 12 25°C 20 25°C 0.3 Full range 6 10 1 0.3 ppm/ °C mV ppm/ khr 20 1.4 mV 1 1.4 Ω Full range is 0°C to 70°C for the LT1009C and –40°C to 85°C for the LT1009I. The deviation parameter VZ(dev) is defined as the difference between the maximum and minimum values obtained over the recommended operating temperature range, measured at IZ = 1 mA. The average full-range temperature coefficient of the reference voltage (αVZ) is defined as: Maximum VZ VZ(dev) ppm = |aVZ| °C VZ at 25°C × 10 VZ(dev) at IZ = 1 mA 6 Minimum VZ DTA DTA αVZ can be positive or negative, depending upon whether the minimum VZ or maximum VZ, respectively, occurs at the lower temperature. For example, at IZ = 1 mA, maximum VZ = 2501 mV at 30°C, minimum VZ = 2497 mV at 0°C, VZ = 2500 mV at 25°C, ΔTA = 70°C for LT1009C: 4 mV |aVZ| = 2500 mV 70°C 6 × 10 » 23 ppm °C Because minimum VZ occurs at the lower temperature, the coefficient in this example is positive. 4 Submit Documentation Feedback Copyright © 1987–2009, Texas Instruments Incorporated Product Folder Link(s): LT1009 LT1009 www.ti.com................................................................................................................................................................. SLVS013N – MAY 1987 – REVISED MAY 2009 TYPICAL CHARACTERISTICS Data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various devices. REFERENCE VOLTAGE vs FREE-AIR TEMPERATURE CHANGE IN REFERENCE VOLTAGE vs REFERENCE CURRENT 2.53 5 ∆V Z − Change in Reference Voltage − mV Iz = 1 mA V Z − Reference Voltage − V 2.52 2.51 2.5 2.49 2.48 2.47 −50 4 3 2 1 0 −25 0 25 50 75 100 TA − Free-Air Temperature − °C 125 0 4 8 12 16 IZ − Reference Current − mA Figure 1. Figure 2. REVERSE CURRENT vs REVERSE VOLTAGE FORWARD VOLTAGE vs FORWARD CURRENT 20 1.2 10−1 TJ = 25°C 1 V F − Forward Voltage − V I R − Reverse Current − A 10−2 10−3 TJ = 125°C 10−4 TJ = −55°C 0.6 1 1.4 1.8 2.2 VR − Reverse Voltage − V 0.6 0.4 0.2 TJ = 25°C 10−5 0.8 2.6 0 0.001 Figure 3. 0.01 0.1 1 IF − Forward Current − mA 10 Figure 4. Submit Documentation Feedback Copyright © 1987–2009, Texas Instruments Incorporated Product Folder Link(s): LT1009 5 LT1009 SLVS013N – MAY 1987 – REVISED MAY 2009................................................................................................................................................................. www.ti.com TYPICAL CHARACTERISTICS (continued) REFERENCE IMPEDANCE vs FREQUENCY NOISE VOLTAGE vs FREQUENCY 100 250 Iz = 1 mA TJ = 25°C 200 V n − Noise Voltage − nV/ Hz ZZ − Reference Impedance − Ω Iz = 1 mA TJ = −55°C to 125°C 10 1 0.1 10 100 1k 10k f − Frequency − Hz 150 100 50 10 100k 100 Figure 5. 1k f − Frequency − Hz Figure 6. 10k 100k TRANSIENT RESPONSE 3.5 3 Output Input and Output Voltages − V 2.5 2 1.5 1 0.5 5 kΩ Input 0 Output 8 Input 4 0 0 1 20 t − Time − µs Figure 7. 6 Submit Documentation Feedback Copyright © 1987–2009, Texas Instruments Incorporated Product Folder Link(s): LT1009 LT1009 www.ti.com................................................................................................................................................................. SLVS013N – MAY 1987 – REVISED MAY 2009 APPLICATION INFORMATION 5 V to 35 V 3.6 kΩ Output 10-kΩ Trim (see Note A) LT1009 A. This does not affect temperature coefficient. It provides ±5% trim range. Figure 8. 2.5-V Reference 3.6 V to 40 V V+ LM334 R V− 62 Ω Output LT1009 10 kΩ Figure 9. Adjustable Reference With Wide Supply Range LT1084 VI IN 10 µF ADJ OUT VO 10 µF 1.2 kΩ 374 Ω LT1009 2 kΩ Figure 10. Power Regulator With Low Temperature Coefficient Submit Documentation Feedback Copyright © 1987–2009, Texas Instruments Incorporated Product Folder Link(s): LT1009 7 LT1009 SLVS013N – MAY 1987 – REVISED MAY 2009................................................................................................................................................................. www.ti.com 5V 5.1 kΩ 5V 5.1 kΩ LT1009 10 kΩ 1% −5 V Output 9.76 kΩ 1% 500 Ω 5 kΩ −5 V Figure 11. Switchable ±1.25-V Bipolar Reference 1 µF 10 kΩ VI ≥ 6 V 1 kΩ − 10 kΩ 2.5 V 1 kΩ + + 100 kΩ LT1009 + LT1001C 20 µF 20 µF Figure 12. Low-Noise 2.5-V Buffered Reference 8 Submit Documentation Feedback Copyright © 1987–2009, Texas Instruments Incorporated Product Folder Link(s): LT1009 PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LT1009CD ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 1009C LT1009CDE4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 1009C LT1009CDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 1009C LT1009CDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 1009C LT1009CLP ACTIVE TO-92 LP 3 1000 Pb-Free (RoHS) CU SN N / A for Pkg Type 0 to 70 LT1009C LT1009CLPE3 ACTIVE TO-92 LP 3 1000 Pb-Free (RoHS) CU SN N / A for Pkg Type 0 to 70 LT1009C LT1009CLPM ACTIVE TO-92 LP 3 2000 Pb-Free (RoHS) CU SN N / A for Pkg Type 0 to 70 LT1009C LT1009CLPR ACTIVE TO-92 LP 3 2000 Pb-Free (RoHS) CU SN N / A for Pkg Type 0 to 70 LT1009C LT1009CLPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free (RoHS) CU SN N / A for Pkg Type 0 to 70 LT1009C LT1009CPK OBSOLETE SOT-89 PK 3 TBD Call TI Call TI 0 to 70 LT1009CPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM 0 to 70 1009C LT1009ID ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 1009I LT1009IDG4 ACTIVE SOIC D 8 75 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 1009I LT1009IDR ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 1009I LT1009IDRG4 ACTIVE SOIC D 8 2500 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 1009I LT1009ILP ACTIVE TO-92 LP 3 1000 Pb-Free (RoHS) CU SN N / A for Pkg Type -40 to 85 LT1009I LT1009ILPE3 ACTIVE TO-92 LP 3 1000 Pb-Free (RoHS) CU SN N / A for Pkg Type -40 to 85 LT1009I Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (°C) Device Marking (4/5) LT1009ILPR ACTIVE TO-92 LP 3 2000 Pb-Free (RoHS) CU SN N / A for Pkg Type -40 to 85 LT1009I LT1009ILPRE3 ACTIVE TO-92 LP 3 2000 Pb-Free (RoHS) CU SN N / A for Pkg Type -40 to 85 LT1009I LT1009IPWR ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 1009I LT1009IPWRG4 ACTIVE TSSOP PW 8 2000 Green (RoHS & no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -40 to 85 1009I LT1009QDR OBSOLETE SOIC D 8 TBD Call TI Call TI -40 to 125 LT1009Y OBSOLETE DIESALE Y 0 TBD Call TI Call TI (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Addendum-Page 2 Samples PACKAGE OPTION ADDENDUM www.ti.com 10-Jun-2014 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. 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OTHER QUALIFIED VERSIONS OF LT1009 : • Military: LT1009M NOTE: Qualified Version Definitions: • Military - QML certified for Military and Defense Applications Addendum-Page 3 PACKAGE MATERIALS INFORMATION www.ti.com 15-Feb-2016 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant LT1009CDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 LT1009CPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 LT1009IDR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 LT1009IPWR TSSOP PW 8 2000 330.0 12.4 7.0 3.6 1.6 8.0 12.0 Q1 Pack Materials-Page 1 PACKAGE MATERIALS INFORMATION www.ti.com 15-Feb-2016 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LT1009CDR SOIC D 8 2500 340.5 338.1 20.6 LT1009CPWR TSSOP PW 8 2000 367.0 367.0 35.0 LT1009IDR SOIC D 8 2500 340.5 338.1 20.6 LT1009IPWR TSSOP PW 8 2000 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE PW0008A TSSOP - 1.2 mm max height SCALE 2.800 SMALL OUTLINE PACKAGE C 6.6 TYP 6.2 SEATING PLANE PIN 1 ID AREA A 0.1 C 6X 0.65 8 1 3.1 2.9 NOTE 3 2X 1.95 4 5 B 4.5 4.3 NOTE 4 SEE DETAIL A 8X 0.30 0.19 0.1 C A 1.2 MAX B (0.15) TYP 0.25 GAGE PLANE 0 -8 0.15 0.05 0.75 0.50 DETAIL A TYPICAL 4221848/A 02/2015 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153, variation AA. www.ti.com EXAMPLE BOARD LAYOUT PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM 1 8 (R0.05) TYP SYMM 6X (0.65) 5 4 (5.8) LAND PATTERN EXAMPLE SCALE:10X SOLDER MASK OPENING METAL SOLDER MASK OPENING METAL UNDER SOLDER MASK 0.05 MAX ALL AROUND 0.05 MIN ALL AROUND SOLDER MASK DEFINED NON SOLDER MASK DEFINED SOLDER MASK DETAILS NOT TO SCALE 4221848/A 02/2015 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0008A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 8X (1.5) 8X (0.45) SYMM (R0.05) TYP 1 8 SYMM 6X (0.65) 5 4 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE:10X 4221848/A 02/2015 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. Board assembly site may have different recommendations for stencil design. www.ti.com IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. 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