HANBit HMS3224M3/Z3 HAN SRAM MODULE 768KBit (32K x 24-Bit) BIT Part No. HMS3224M3, HMS3224Z3 GENERAL DESCRIPTION The HMS3224M3/Z3 is a high-speed static random access memory (SRAM) module containing 32,768 words organized in a x24-bit configuration. The module consists of three 32K x 8 SRAMs mounted on a 56-pin, singlesided, FR4-printed circuit board. Writing to the device is accomplished when the chip enable (/CE) and write enable(/WE) inputs are both LOW. Data on the input/output pins (DQ0 through DQ23) of the device is written into the memory location specified on the address pins (A0 through A14). Reading the device is accomplished by taking the chip enable (/CE) and output enable(/OE) LOW while write enable(/WE) remains HIGH. Under these conditions, the contents of the memory location specified on the address pins will appear on the input/output pins. The input/output pins remains in a high-impedance state unless the module is selected, outputs are enabled, and write enable is HIGH. PIN ASSIGNMENT FEATURES Access times : 12, 15 and 20ns High-density 768Kbit design High-reliability, high-speed design Single + 5V ±0.5V power supply 56-pin, low-active power design All inputs and outputs are TTL-compatible Industry-standard pinout FR4-PCB design Part identification Vcc DQ1 DQ3 DQ5 DQ7 Vss A1 A3 A5 A7 NC Vss DQ9 DQ11 DQ13 DQ15 NC /OE A9 A11 A13 NC Vss DQ17 DQ19 DQ21 DQ23 Vcc HMS3224M3 : 56Pin SIMM Design HMS3224Z3 : 56Pin ZIP Design →Pin-compatible with the HMS3224M3 OPTIONS MARKING Timing 12ns access -12 15ns access -15 20ns access -20 Packages 56-pin SIMM M 56-pin ZIP Z 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 Vcc DQ0 DQ2 DQ4 DQ6 Vss A0 A2 A4 A6 /CE NC DQ8 DQ10 DQ12 DQ14 Vss /WE A8 A10 A12 A14 Vss DQ16 DQ18 DQ20 DQ22 Vcc ZIP TOP VIEW 1 HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 FUNCTIONAL BLOCK DIAGRAM DQ0 - DQ23 A0 - A14 24 15 A0-14 DQ 0-7 /WE U1 /OE /CE /CE1 A0-14 DQ 8-15 /WE U2 /OE /CE /CE2 A0-14 DQ16-23 /WE /OE /WE /OE U3 /CE /CE3 TRUTH TABLE MODE /OE /CE /WE OUTPUT POWER STANDBY X H X HIGH-Z STANDBY NOT SELECTED H L H HIGH-Z ACTIVE READ L L H Dout ACTIVE WRITE X L L Din ACTIVE 2 HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 ABSOLUTE MAXIMUM RATINGS PARAMETER SYMBOL RATING VIN,OUT -0.5V to +7.0V Voltage on Vcc Supply Relative to Vss VCC -0.5V to +7.0V Power Dissipation PD 3W TSTG -65oC to +150oC Voltage on Any Pin Relative to Vss Storage Temperature Operating Temperature TA 0oC to +70oC Stresses greater than those listed under " Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operating section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. RECOMMENDED DC OPERATING CONDITIONS PARAMETER * ( TA=0 to 70 o C ) SYMBOL MIN TYP. MAX Supply Voltage VCC 4.5V 5.0V 5.5V Ground VSS 0 0 0 Input High Voltage VIH 2.2 - Vcc+0.5V** Input Low Voltage VIL -0.5* - 0.8V VIL(Min.) = -2.0V (Pulse Width ≤ 10ns) for I ≤ 20 mA ** VIH(Min.) = Vcc+2.0V (Pulse Width ≤ 10ns) for I ≤ 20 mA DC AND OPERATING CHARACTERISTICS (1)(0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V ) PARAMETER Input Leakage Current Output Leakage Current TEST CONDITIONS VIN = Vss to Vcc CE=VIH or OE =VIH or WE=VIL VOUT=Vss to VCC SYMBO L MIN MAX UNITS ILI -6 6 µA IL0 -6 6 µA 2.4 Output High Voltage IOH = -4.0mA VOH Output Low Voltage IOL = 8.0mA VOL V 0.4 V * Vcc=5.0V, Temp=25 oC 3 HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 DC AND OPERATING CHARACTERISTICS (2) MAX DESCRIPTION TEST CONDITIONS Min. Cycle, 100% Duty /CE=VIL, VIN=VIH or VIL, IOUT=0mA Power Supply Current: Operating Power Supply Current :Standby SYMBOL -12 -15 -20 UNIT lCC 495 450 420 mA Min. Cycle, /CE=VIH lSB 120 120 120 mA f=0MHZ, /CE≥VCC-0.2V, VIN≥ VCC-0.2V or VIN≤0.2V lSB1 6 6 6 mA CAPACITANCE DESCRIPTION TEST CONDITIONS SYMBOL MAX UNIT Input /Output Capacitance VI/O=0V CI/O 24 pF Input Capacitance VIN=0V CIN 21 pF * NOTE : Capacitance is sampled and not 100% tested AC CHARACTERISTICS (0oC ≤ TA ≤ 70 oC ; Vcc = 5V ± 0.5V, unless otherwise specified) TEST CONDITIONS PARAMETER VALUE Input Pulse Level 0 to 3V Input Rise and Fall Time 3ns Input and Output Timing Reference Levels 1.5V Output Load See below Output Load Output Load (B) for tHZ, tLZ, tWHZ, tOW, tOLZ & tOHZ +5V +5V 480Ω DOUT 255Ω 30pF* 480Ω DOUT 255Ω 4 5pF* HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 READ CYCLE -12 PARAMETER -15 -20 SYMBOL UNIT MIN MAX 12 MIN MAX 15 MIN MAX Read Cycle Time tRC ns Address Access Time tAA 12 15 20 ns Chip Select to Output tCO 12 15 20 ns Output Enable to Output tOE 6 7 9 ns Output Enable to Low-Z Output tOLZ 0 0 0 ns Chip Enable to Low-Z Output tLZ 3 3 3 ns Output Disable to High-Z Output tOHZ 0 6 0 7 0 10 ns Chip Disable to High-Z Output tHZ 0 6 0 7 0 10 ns Output Hold from Address Change tOH 3 3 3 ns Chip Select to Power Up Time tPU 0 0 0 ns Chip Select to Power Down Time tPD 20 12 15 20 ns WRITE CYCLE -12 PARAMETER -15 -20 SYMBOL UNIT MIN MAX MIN MAX MIN MAX Write Cycle Time tWC 12 15 20 ns Chip Select to End of Write tCW 9 11 13 ns Address Set-up Time tAS 0 0 0 ns Address Valid to End of Write tAW 9 12 13 ns Write Pulse Width tWP 9 12 13 ns Write Recovery Time tWR 12 0 0 ns Write to Output High-Z tWHZ 0 Data to Write Time Overlap tDW 7 8 10 ns Data Hold from Write Time tDH 0 0 0 ns End of Write to Output Low-Z tOW 0 0 0 ns 5 6 0 8 0 8 ns HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 TIMING DIAGRAMS TIMING WAVEFORM OF READ CYCLE( Address Controlled) ( /CE =/OE = VIL , /WE = VIH) tRC Address tAA tOH Data out Previous Data Valid Data Valid TIMING WAVEFORM OF READ CYCLE ( /WE=VIH ) tRC Address tHZ(3,4,5) tAA tCO /CE tLZ(4,5) tOHZ tOE /OE tOH tOLZ Data Out Vcc Supply Current High-Z Valid Data lCC lSB tPD tPU 50% 50% Notes (Read Cycle) 1. /WE is high for read cycle. 2. All read cycle timing is referenced from the last valid address to the first transition address. 3. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition are not referenced to VOH or VOL levels. 4. At any given temperature and voltage condition, tHZ (max.) is less than tLZ (min.) both for a given device and from device to device. 5. Transition is measured ± 200mV from steady state voltage with Load (B). This parameter is sampled and not 100% tested. 6. Device is continuously selected with /CE = VIL. 7. Address valid prior to coincident with /CE transition low. 6 HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 TIMING WAVEFORM OF WRITE CYCLE (/OE = Clock ) tWC Address tAW tWR(5) /OE tCW(3) /CE tAS(4) tWP(2) /WE tDW tDH High-Z Data In tOHZ(6) tOW Data Out High-Z TIMING WAVEFORM OF WRITE CYCLE (/OE Low Fixed ) tWC Address tAW tWR(5) tCW(3) /CE tAS(4) tOH tWP(2) / WE tDW tDH High-Z Data In tWHZ(6,7) tOW (10) (9) High-Z(8) Data Out Notes(Write Cycle) 1. All write cycle timing is referenced from the last valid address to the first transition address. 2. A write occurs during the overlap of a low /CE and a low /WE. A write begins at the latest transition among /CE going low and /WE going low: A write ends at the earliest transition among /CE going high and /WE going high. tWP is measured from the beginning of write to the end of write. 7 HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 3. tCW is measured from the later of /CE going low to the end of write. 4. tAS is measured from the address valid to the beginning of write. 5. tWR is measured from the end of write to the address change. tWR applied in case a write ends as /CE, or /WE going high. 6. If /OE,/CE and /WE are in the read mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase of the output must not be applied because bus contention can occur. 7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle. 8. If /CE goes low simultaneously with /WE going low or after /WE going low, the outputs remain high impedance state. 9. DOUT is the read data of the new address. 10. When /CE is low: I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be applied. FUNCTIONAL DESCRIPTION /CE /WE /OE MODE I/O PIN SUPPLY CURRENT H X* X Not Select High-Z l SB, l SB1 L H H Output Disable High-Z lCC L H L Read DOUT lCC L L X Write DIN lCC Note: X means Don't Care 8 HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 PACKAGING INFORMATION ZIP Design 73.50mm CUT 1.5 mm 12.5 mm 56 1 6 mm 1.27 mm 69.85 mm 1.29±0.08mm 2.5 mm 9 HANBit Electronics Co.,Ltd. HANBit HMS3224M3/Z3 ODERING INFORMATION 1 2 3 HMS 4 5 6 7 8 32 24 M 3 - 15 15ns Access Time HANBit Component Memory Modules SIMM X24bit SRAM 32K 1. - Product Line Identifier HANBit Technology --------------------------------------- H 2. - Memory Modules 3. - SRAM 4. - Depth : 32K 5. - Width : x 24bit 6. - Package Code SIMM ------------------------------------------------------- M ZIP ------------------------------------------------------- Z 7. – Number of Memory Components 8. - Access time 10 ----------------------------------------------------------- 10ns 12 ----------------------------------------------------------- 12ns 15 ----------------------------------------------------------- 15ns 17 ----------------------------------------------------------- 17ns 20 ----------------------------------------------------------- 20ns 10 HANBit Electronics Co.,Ltd.