HUFA76504DK8
Data Sheet
2.3A, 80V, 0.222 Ohm, Dual N-Channel,
Logic Level UltraFET Power MOSFET
[ /Title
(HUF7 Packaging
JEDEC MS-012AA
6400S
BRANDING DASH
K8)
/Subject
(60V,
0.072
1
2
Ohm,
3
4
4A, NChannel,
Symbol
Logic
Level
SOURCE1 (1)
UltraFE
GATE1 (2)
Power
MOSFET)
/Author
June 2001
Features
• Ultra Low On-Resistance
- rDS(ON) = 0.200Ω, VGS = 10V
- rDS(ON) = 0.222Ω, VGS = 5V
• Simulation Models
- Temperature Compensated PSPICE™ and SABER
Electrical Models
- Spice and SABER Thermal Impedance Models
- www.Fairchildsemi.com
5
• Internal RG = 50Ω
• Peak Current vs Pulse Width Curve
• UIS Rating Curve
DRAIN 1 (8)
• Transient Thermal Impedance Curve vs Board Mounting
Area
DRAIN 1 (7)
Ordering Information
DRAIN 2 (6)
SOURCE2 (3)
GATE2 (4)
DRAIN 2 (5)
PART NUMBER
HUFA76504DK8
BRAND
76504DK8
NOTE: When ordering, use the entire part number. Add the suffix T
to obtain the variant in tape and reel, e.g., HUFA76504DK8T.
/KeyAbsolute Maximum Ratings TA = 25oC, Unless Otherwise Specified
words
(Harris
Drain to Source Voltage (Note 1). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDSS
SemiDrain to Gate Voltage (RGS = 20kΩ) (Note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDGR
conduc- Gate to Source Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VGS
Current
tor, N- Drain
Continuous (TA= 25oC, VGS = 5V) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
ChanContinuous (TA= 25oC, VGS = 10V) (Figure 2) (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . ID
Continuous (TA= 100oC, VGS = 5V) (Note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ID
nel,
Continuous (TA= 100oC, VGS = 4.5V) (Figure 2) (Note 3). . . . . . . . . . . . . . . . . . . . . . . . ID
Logic
Pulsed Drain Current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .IDM
Pulsed Avalanche Rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .UIS
Level
Dissipation (Note 2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PD
UltraFE Power
Derate Above 25oC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Power
MOS-
PACKAGE
MS-012AA
Operating and Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TJ, TSTG
Maximum Temperature for Soldering
Leads at 0.063in (1.6mm) from Case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .TL
Package Body for 10s, See Techbrief TB334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Tpkg
NOTES:
1. TJ = 25oC to 125oC.
2. 50oC/W measured using FR-4 board with 0.76 in2 (490.3 mm2) copper pad at 1 second.
3. 228oC/W measured using FR-4 board with 0.006 in2 (3.87 mm2) copper pad at 1000 seconds.
HUFA76504DK8
80
80
±16
UNITS
V
V
V
2.3
2.5
1.1
1.1
Figure 4
Figures 6, 17, 18
2.5
20
-55 to 150
A
A
A
A
W
mW/oC
oC
300
260
oC
oC
CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the
device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
This product has been designed to meet the extreme test conditions and environment demanded by the automotive industry. For a copy
of the requirements, see AEC Q101 at: http://www.aecouncil.com/
Reliability data can be found at: http://www.mtp.intersil.com/automotive.html.
All Fairchild semiconductor products are manufactured, assembled and tested under ISO9000 and QS9000 quality systems certification.
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
CAUTION: These devices are sensitive to electrostatic discharge; follow proper ESD Handling Procedures.
UltraFET® is a registered trademark of Fairchild Corporation. PSPICE® is a registered trademark of Cadence Corporation.
SABER© is a registered trademark of Avanti corporation.
HUFA76504DK8
Electrical Specifications
TA = 25oC, Unless Otherwise Specified
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNITS
V
OFF STATE SPECIFICATIONS
Drain to Source Breakdown Voltage
Zero Gate Voltage Drain Current
Gate to Source Leakage Current
BVDSS
IDSS
IGSS
ID = 250µA, VGS = 0V (Figure 12)
80
-
-
ID = 250µA, VGS = 0V , TA = -40oC (Figure 12)
70
-
-
V
-
-
1
µA
VDS = 75V, VGS = 0V
VDS = 70V, VGS = 0V, TA = 150oC
-
-
250
µA
VGS = ±16V
-
-
±100
nA
VGS = VDS, ID = 250µA (Figure 11)
1
-
3
V
ON STATE SPECIFICATIONS
Gate to Source Threshold Voltage
VGS(TH)
Drain to Source On Resistance
rDS(ON)
ID = 2.5A, VGS = 10V (Figures 9, 10)
-
0.173
0.200
Ω
ID = 1.1A, VGS = 5V (Figure 9)
-
0.193
0.222
Ω
ID = 1.1A, VGS = 4.5V (Figure 9)
-
0.200
0.230
Ω
THERMAL SPECIFICATIONS
Thermal Resistance Junction to Lead
Thermal Resistance Junction to Ambient
-
-
25
oC/W
Pad Area = 0.50 in2 (323 mm2) (Note 2)
Pad Area = 0.027 in2 (17.4 mm2) (Figure 23)
Pad Area = 0.006 in2 (3.87 mm2) (Figure 23)
-
-
50
oC/W
-
-
191
oC/W
-
-
228
oC/W
VDD = 40V, ID = 1.1A
VGS = 4.5V, RGS = 43Ω
(Figures 15, 21, 22)
-
-
100
ns
-
27
-
ns
tr
-
40
-
ns
td(OFF)
-
73
-
ns
tf
-
31
-
ns
tOFF
-
-
160
ns
-
-
41
ns
-
10
-
ns
-
18
-
ns
td(OFF)
-
115
-
ns
tf
-
36
-
ns
tOFF
-
-
230
ns
-
6.6
10
nC
-
3.4
5.4
nC
RθJL
RθJA
SWITCHING SPECIFICATIONS (VGS = 4.5V)
Turn-On Time
Turn-On Delay Time
tON
td(ON)
Rise Time
Turn-Off Delay Time
Fall Time
Turn-Off Time
SWITCHING SPECIFICATIONS (VGS = 10V)
Turn-On Time
Turn-On Delay Time
Rise Time
tON
td(ON)
tr
Turn-Off Delay Time
Fall Time
Turn-Off Time
VDD = 40V, ID = 2.5A
VGS = 10V,
RGS = 47Ω
(Figures 16, 21, 22)
GATE CHARGE SPECIFICATIONS
Total Gate Charge
Qg(TOT)
VGS = 0V to 10V
Gate Charge at 5V
Qg(5)
VGS = 0V to 5V
Qg(TH)
VGS = 0V to 1V
Threshold Gate Charge
VDD = 40V,
ID = 1.1A,
Ig(REF) = 1.0mA
-
0.3
0.5
nC
Gate to Source Gate Charge
Qgs
-
0.8
-
nC
Gate to Drain “Miller” Charge
Qgd
-
1.4
-
nC
-
270
-
pF
-
62
-
pF
-
11
-
pF
MIN
TYP
MAX
UNITS
ISD =1.1A
-
-
1.25
V
ISD = 0.7A
-
-
1.00
V
trr
ISD = 5.0A, dISD/dt = 100A/µs
-
-
62
ns
QRR
ISD = 5.0A, dISD/dt = 100A/µs
-
-
115
nC
(Figures 14, 19, 20)
CAPACITANCE SPECIFICATIONS
Input Capacitance
CISS
Output Capacitance
COSS
Reverse Transfer Capacitance
CRSS
VDS = 25V, VGS = 0V,
f = 1MHz
(Figure 13)
Source to Drain Diode Specifications
PARAMETER
Source to Drain Diode Voltage
Reverse Recovery Time
Reverse Recovered Charge
©2001 Fairchild Semiconductor Corporation
SYMBOL
VSD
TEST CONDITIONS
Rev. A, June 4, 2001
HUFA76504DK8
1.2
3.0
1.0
2.5
ID, DRAIN CURRENT (A)
POWER DISSIPATION MULTIPLIER
Typical Performance Curves
0.8
0.6
0.4
0.2
VGS = 10V, RθJA = 50oC/W
2.0
1.5
1.0
0.5
0
0
25
50
75
100
0
150
125
VGS = 4.5V, RθJA = 228oC/W
25
50
75
100
125
TA, AMBIENT TEMPERATURE (oC)
TA , AMBIENT TEMPERATURE (oC)
FIGURE 1. NORMALIZED POWER DISSIPATION vs AMBIENT
TEMPERATURE
150
FIGURE 2. MAXIMUM CONTINUOUS DRAIN CURRENT vs
AMBIENT TEMPERATURE
2
ZθJA, NORMALIZED
THERMAL IMPEDANCE
1
0.1
DUTY CYCLE - DESCENDING ORDER
0.5
0.2
0.1
0.05
0.02
0.01
RθJA = 228oC/W
PDM
t1
0.01
t2
NOTES:
DUTY FACTOR: D = t1/t2
PEAK TJ = PDM x ZθJA x RθJA + TA
SINGLE PULSE
0.001
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 3. NORMALIZED MAXIMUM TRANSIENT THERMAL IMPEDANCE
200
100
IDM, PEAK CURRENT (A)
RθJA = 228oC/W
TRANSCONDUCTANCE
MAY LIMIT CURRENT
IN THIS REGION
TC = 25oC
FOR TEMPERATURES
ABOVE 25oC DERATE PEAK
CURRENT AS FOLLOWS:
VGS = 10V
I = I25
150 - TA
125
10
1
VGS = 4.5V
10-5
10-4
10-3
10-2
10-1
100
101
102
103
t, PULSE WIDTH (s)
FIGURE 4. PEAK CURRENT CAPABILITY
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8
Typical Performance Curves
20
200
IAS, AVALANCHE CURRENT (A)
SINGLE PULSE
TJ = MAX RATED
TA = 25oC
100
ID, DRAIN CURRENT (A)
(Continued)
10
100µs
OPERATION IN THIS
AREA MAY BE
LIMITED BY rDS(ON)
1
1ms
0.1
1
STARTING TJ = 25oC
STARTING TJ = 150oC
10
100
VDS, DRAIN TO SOURCE VOLTAGE (V)
1
0.01
1
tAV, TIME IN AVALANCHE (ms)
NOTE: Refer to Application Notes AN9321 and AN9322.
FIGURE 6. UNCLAMPED INDUCTIVE SWITCHING
CAPABILITY
10
10
ID, DRAIN CURRENT (A)
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VDD = 15V
8
6
4
TJ = 25oC
2
TJ = 150oC
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
TA = 25oC
8
VGS = 4.5V
6
VGS = 10V
VGS = 3.5V
4
VGS = 3V
2
TJ = -55oC
0
0
2.5
3.0
3.5
4.0
VGS, GATE TO SOURCE VOLTAGE (V)
2.0
0
4.5
FIGURE 7. TRANSFER CHARACTERISTICS
300
ID = 2.5A
250
ID = 1.1A
200
150
4
6
8
VGS, GATE TO SOURCE VOLTAGE (V)
10
FIGURE 9. DRAIN TO SOURCE ON RESISTANCE vs GATE
VOLTAGE AND DRAIN CURRENT
©2001 Fairchild Semiconductor Corporation
NORMALIZED DRAIN TO SOURCE
ON RESISTANCE
2.5
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
2
1
2
VDS, DRAIN TO SOURCE VOLTAGE (V)
3
FIGURE 8. SATURATION CHARACTERISTICS
350
rDS(ON), DRAIN TO SOURCE
ON RESISTANCE (mΩ)
0.1
200
FIGURE 5. FORWARD BIAS SAFE OPERATING AREA
ID, DRAIN CURRENT (A)
10
10ms
RθJA = 228oC/W
IfSTARTING
R=0
TJ = 150oC
tAV = (L)(IAS)/(1.3*RATED BVDSS - VDD)
If R ≠ 0
tAV = (L/R)ln[(IAS*R)/(1.3*RATED BVDSS - VDD) +1]
PULSE DURATION = 80µs
DUTY CYCLE = 0.5% MAX
VGS = 10V, ID = 2.5A
2.0
1.5
1.0
0.5
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
160
FIGURE 10. NORMALIZED DRAIN TO SOURCE ON
RESISTANCE vs JUNCTION TEMPERATURE
Rev. A, June 4, 2001
HUFA76504DK8
Typical Performance Curves
(Continued)
1.2
1.2
NORMALIZED DRAIN TO SOURCE
BREAKDOWN VOLTAGE
NORMALIZED GATE
THRESHOLD VOLTAGE
VGS = VDS, ID = 250µA
1.0
0.8
0.6
-80
-40
0
40
80
120
TJ, JUNCTION TEMPERATURE (oC)
1.0
-40
0
40
80
120
TJ , JUNCTION TEMPERATURE (oC)
FIGURE 12. NORMALIZED DRAIN TO SOURCE BREAKDOWN
VOLTAGE vs JUNCTION TEMPERATURE
VGS , GATE TO SOURCE VOLTAGE (V)
CISS = CGS + CGD
100
COSS ≅ CDS + CGD
CRSS = CGD
10
VGS = 0V, f = 1MHz
0.1
VDD = 40V
8
6
4
WAVEFORMS IN
DESCENDING ORDER:
ID = 2.5A
ID = 1.1A
2
0
3
0
80
1
10
VDS , DRAIN TO SOURCE VOLTAGE (V)
2
4
Qg, GATE CHARGE (nC)
6
8
NOTE: Refer to Application Notes AN7254 and AN7260.
FIGURE 13. CAPACITANCE vs DRAIN TO SOURCE VOLTAGE
FIGURE 14. GATE CHARGE WAVEFORMS FOR CONSTANT
GATE CURRENT
120
80
VGS = 10V, VDD = 40V, ID = 2.5A
VGS = 4.5V, VDD = 40V, ID = 1.1A
td(OFF)
60
tr
40
tf
td(ON)
20
SWITCHING TIME (ns)
td(OFF)
SWITCHING TIME (ns)
160
10
1000
C, CAPACITANCE (pF)
1.1
0.9
-80
160
FIGURE 11. NORMALIZED GATE THRESHOLD VOLTAGE vs
JUNCTION TEMPERATURE
ID = 250µA
80
40
tf
tr
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
FIGURE 15. SWITCHING TIME vs GATE RESISTANCE
©2001 Fairchild Semiconductor Corporation
50
td(ON)
0
0
10
20
30
40
RGS, GATE TO SOURCE RESISTANCE (Ω)
50
FIGURE 16. SWITCHING TIME vs GATE RESISTANCE
Rev. A, June 4, 2001
HUFA76504DK8
Test Circuits and Waveforms
VDS
BVDSS
L
tP
VARY tP TO OBTAIN
REQUIRED PEAK IAS
+
RG
VDS
IAS
VDD
VDD
-
VGS
DUT
tP
0V
IAS
0
0.01Ω
tAV
FIGURE 17. UNCLAMPED ENERGY TEST CIRCUIT
FIGURE 18. UNCLAMPED ENERGY WAVEFORMS
VDS
VDD
RL
Qg(TOT)
VDS
VGS = 10V
VGS
Qg(5)
+
VDD
VGS = 5V
VGS
DUT
VGS = 1V
Ig(REF)
0
Qg(TH)
Qgs
Qgd
Ig(REF)
0
FIGURE 19. GATE CHARGE TEST CIRCUIT
FIGURE 20. GATE CHARGE WAVEFORMS
VDS
tON
tOFF
td(ON)
td(OFF)
tr
RL
VDS
tf
90%
90%
+
VGS
VDD
-
10%
0
10%
DUT
90%
RGS
VGS
VGS
0
FIGURE 21. SWITCHING TIME TEST CIRCUIT
©2001 Fairchild Semiconductor Corporation
10%
50%
50%
PULSE WIDTH
FIGURE 22. SWITCHING TIME WAVEFORM
Rev. A, June 4, 2001
HUFA76504DK8
Thermal Resistance vs. Mounting Pad Area
The maximum rated junction temperature, TJM, and the
thermal resistance of the heat dissipating path determines
the maximum allowable device power dissipation, PDM, in
an application. Therefore the application’s ambient
temperature, TA (oC), and thermal resistance RθJA (oC/W)
must be reviewed to ensure that TJM is never exceeded.
Equation 1 mathematically represents the relationship and
serves as the basis for establishing the rating of the part.
P
RθJA = 103.2 - 24.3
250
Rθβ, RθJA (oC/W)
(T
–T )
JM
A
= ------------------------------DM
R θJA
300
228 oC/W - 0.006in2
200
191 oC/W - 0.027in2
150
100
(EQ. 1)
50
Rθβ = 46.4 - 21.7 * ln(AREA)
In using surface mount devices such as the SOP-8 package,
the environment in which it is applied will have a significant
influence on the part’s current and maximum power
dissipation ratings. Precise determination of P DM is complex
and influenced by many factors:
1. Mounting pad area onto which the device is attached and
whether there is copper on one side or both sides of the
board.
2. The number of copper layers and the thickness of the
board.
0
0.001
4. The use of thermal vias.
5. Air flow and board orientation.
6. For non steady state applications, the pulse width, the
duty cycle and the transient thermal response of the part,
the board and the environment they are in.
Fairchild provides thermal information to assist the
designer’s preliminary application evaluation. Figure 23
defines the RθJA for the device as a function of the top
copper (component side) area. This is for a horizontally
positioned FR-4 board with 1oz copper after 1000 seconds
of steady state power with no air flow. This graph provides
the necessary information for calculation of the steady state
junction temperature or power dissipation. Pulse
applications can be evaluated using the Fairchild device
Spice thermal model or manually utilizing the normalized
maximum transient thermal impedance curve.
Displayed on the curve are RθJA values listed in the
Electrical Specifications table. The points were chosen to
depict the compromise between the copper board area, the
thermal resistance and ultimately the power dissipation,
PDM.
Thermal resistances corresponding to other copper areas
can be obtained from Figure 23 or by calculation using
Equation 2. RθJA is defined as the natural log of the area
times a cofficient added to a constant. The area, in square
inches is the top copper area including the gate and source
pads.
ln ( Area )
©2001 Fairchild Semiconductor Corporation
(EQ. 2)
0.01
0.1
1
AREA, TOP COPPER AREA (in2) PER DIE
FIGURE 23. THERMAL RESISTANCE vs MOUNTING PAD AREA
While Equation 2 describes the thermal resistance of a
single die, several of the new UltraFET™s are offered with
two die in the SOP-8 package. The dual die SOP-8 package
introduces an additional thermal component, thermal
coupling resistance, Rθβ. Equation 3 describes Rθβ as a
function of the top copper mounting pad area.
R θβ
3. The use of external heat sinks.
R θJA = 103.2 – 24.3 ×
* ln(AREA)
= 46.4 – 21.7 ×
ln ( Area )
(EQ. 3)
The thermal coupling resistance vs. copper area is also
graphically depicted in Figure 23. It is important to note the
thermal resistance (RθJA) and thermal coupling resistance
(Rθβ) are equivalent for both die. For example at 0.1 square
inches of copper:
RθJA1 = RθJA2 = 159°C/W
Rθβ1 = Rθβ2 = 97°C/W
TJ1 and TJ2 define the junction temerature of the respective
die. Similarly, P1 and P2 define the power dissipated in each
die. The steady state junction temperature can be calculated
using Equation 4 for die 1and Equation 5 for die 2.
Example: To calculate the junction temperature of each die
when die 2 is dissipating 0.5 Watts and die 1 is dissipating 0
Watts. The ambient temperature is 70°C and the package is
mounted to a top copper area of 0.1 square inches per die.
Use Equation 4 to calulate TJ1 and and Equation 5 to
calulate TJ2.
.
T J1 = P 1 R θJA + P 2 R θβ + T A
(EQ. 4)
TJ1 = (0 Watts)(159°C/W) + (0.5 Watts)(97°C/W) + 70°C
TJ1 = 119°C
T J2 = P 2 R θJA + P 1 R θβ + T A
(EQ. 5)
TJ2 = (0.5 Watts)(159°C/W) + (0 Watts)(97°C/W) + 70°C
TJ2 = 150°C
Rev. A, June 4, 2001
HUFA76504DK8
The transient thermal impedance (ZθJA) is also effected by
varied top copper board area. Figure 24 shows the effect of
copper pad area on single pulse transient thermal
impedance. Each trace represents a copper pad area in
square inches corresponding to the descending list in the
graph. Spice and SABER thermal models are provided for
each of the listed pad areas.
ZθJA, THERMAL
IMPEDANCE (oC/W)
160
120
Copper pad area has no perceivable effect on transient
thermal impedance for pulse widths less than 100ms. For
pulse widths less than 100ms the transient thermal
impedance is determined by the die and package. Therefore,
CTHERM1 through CTHERM5 and RTHERM1 through
RTHERM5 remain constant for each of the thermal models. A
listing of the model component values is available in Table 1.
COPPER BOARD AREA - DESCENDING ORDER
0.020 in2
0.140 in2
0.257 in2
0.380 in2
0.493 in2
80
40
0
10-1
100
101
102
103
t, RECTANGULAR PULSE DURATION (s)
FIGURE 24. THERMAL RESISTANCE vs MOUNTING PAD AREA
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8
PSPICE Electrical Model
.SUBCKT HUFA76504DK8 2 1 3 ;
REV 18 January 2001
CA 12 8 2.5e-10
CB 15 14 3e-10
CIN 6 8 2.6e-10
DBODY 7 5 DBODYMOD
DBREAK 5 11 DBREAKMOD
DPLCAP 10 5 DPLCAPMOD
LDRAIN
DPLCAP
DRAIN
2
5
10
5
51
ESLC
11
-
RDRAIN
6
8
EVTHRES
+ 19 8
+
LGATE
GATE
1
MMED 16 6 8 8 MMEDMOD
MSTRO 16 6 8 8 MSTROMOD
MWEAK 16 21 8 8 MWEAKMOD
+
50
ESG
EVTEMP
RGATE +
18 22
9
20
21
EBREAK
17
18
DBODY
-
16
MWEAK
6
MMED
MSTRO
RLGATE
LSOURCE
CIN
8
SOURCE
3
7
RSOURCE
RBREAK 17 18 RBREAKMOD 1
RDRAIN 50 16 RDRAINMOD 1.1e-1
RGATE 9 20 5.74e1
RLDRAIN 2 5 10
RLGATE 1 9 42.1
RLSOURCE 3 7 12.8
RSLC1 5 51 RSLCMOD 1e-6
RSLC2 5 50 1e3
RSOURCE 8 7 RSOURCEMOD 5.72e-2
RVTHRES 22 8 RVTHRESMOD 1
RVTEMP 18 19 RVTEMPMOD 1
S1A
S1B
S2A
S2B
DBREAK
+
RSLC2
IT 8 17 1
LDRAIN 2 5 1.0e-9
LGATE 1 9 4.21e-10
LSOURCE 3 7 1.28e-10
RLDRAIN
RSLC1
51
EBREAK 11 7 17 18 100.6
EDS 14 8 5 8 1
EGS 13 8 6 8 1
ESG 6 10 6 8 1
EVTHRES 6 21 19 8 1
EVTEMP 20 6 18 22 1
RLSOURCE
S1A
12
S2A
14
13
13
8
S1B
CA
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
6 12 13 8 S1AMOD
13 12 13 8 S1BMOD
6 15 14 13 S2AMOD
13 15 14 13 S2BMOD
RBREAK
15
VBAT
5
8
EDS
-
+
8
22
RVTHRES
VBAT 22 19 DC 1
ESLC 51 50 VALUE={(V(5,51)/ABS(V(5,51)))*(PWR(V(5,51)/(1e-6*12),3.7))}
.MODEL DBODYMOD D (IS = 3.1e-13 N = 1.03 RS = 4.2e-2 TRS1 = 3e-4 TRS2 = 1.3e-6 CJO = 6.82e-10 TT = 3.3e-8 M = 0.8 XTI = 4)
.MODEL DBREAKMOD D (RS = 1.65 TRS1 = 1e-3 TRS2 = -9e-6)
.MODEL DPLCAPMOD D (CJO = 1.7e-10 IS = 1e-30 M = 0.85)
.MODEL MMEDMOD NMOS (VTO = 2.2 KP = 1.1 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.74e1)
.MODEL MSTROMOD NMOS (VTO = 2.56 KP = 18 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u)
.MODEL MWEAKMOD NMOS (VTO = 1.94 KP = 0.04 IS = 1e-30 N = 10 TOX = 1 L = 1u W = 1u RG = 5.74e2 RS = 0.1)
.MODEL RBREAKMOD RES (TC1 = 1.12e-3 TC2 = -3e-7)
.MODEL RDRAINMOD RES (TC1 = 9e-3 TC2 = 2e-5)
.MODEL RSLCMOD RES (TC1 = 2.8e-3 TC2 = 1.9e-5)
.MODEL RSOURCEMOD RES (TC1 = 1e-3 TC2 = 1e-6)
.MODEL RVTHRESMOD RES (TC1 = -2e-3 TC2 = -3e-6)
.MODEL RVTEMPMOD RES (TC1 = -1.5e-3 TC2 = 1e-6)
.MODEL S1AMOD VSWITCH (RON = 1e-5
.MODEL S1BMOD VSWITCH (RON = 1e-5
.MODEL S2AMOD VSWITCH (RON = 1e-5
.MODEL S2BMOD VSWITCH (RON = 1e-5
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
ROFF = 0.1
VON = -4 VOFF= -1)
VON = -1 VOFF= -4)
VON = -0.5 VOFF= 0.5)
VON = 0.5 VOFF= -0.5)
.ENDS
NOTE: For further discussion of the PSPICE model, consult A New PSPICE Sub-Circuit for the Power MOSFET Featuring Global
Temperature Options; IEEE Power Electronics Specialist Conference Records, 1991, written by William J. Hepp and C. Frank Wheatley.
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8
SABER Electrical Model
REV 18 January 2001
template HUFA76504dk8 n2,n1,n3
electrical n2,n1,n3
{
var i iscl
dp..model dbodymod = (is = 3.1e-13, n1 = 1.03, rs = 4.2e-2, trs1 = 3e-4, trs2 = 1.3e-6, cjo = 6.82e-10, tt = 3.38e-8, m = 0.8, xti = 4)
dp..model dbreakmod = (rs = 1.65, trs1 = 1e-3, trs2 = -9e-6)
dp..model dplcapmod = (cjo = 1.7e-10, isl = 10e-30, n1 = 10, m = 0.85)
m..model mmedmod = (type=_n, vto = 2.2, kp = 1.1, is = 1e-30, tox = 1)
m..model mstrongmod = (type=_n, vto = 2.56, kp = 18, is = 1e-30, tox = 1)
LDRAIN
m..model mweakmod = (type=_n, vto = 1.94, kp = 0.04, is = 1e-30, tox = 1, rs = .1)
DPLCAP 5
sw_vcsp..model s1amod = (ron = 1e-5, roff = 0.1, von = -4, voff = -1)
sw_vcsp..model s1bmod = (ron =1e-5, roff = 0.1, von = -1, voff = -4)
10
sw_vcsp..model s2amod = (ron = 1e-5, roff = 0.1, von = -0.5, voff = 0.5)
RLDRAIN
RSLC1
sw_vcsp..model s2bmod = (ron = 1e-5, roff = 0.1, von = 0.5, voff = -0.5)
RDBREAK
51
RSLC2
c.ca n12 n8 = 2.5e-10
c.cb n15 n14 = 3e-10
c.cin n6 n8 = 2.6e-10
RDRAIN
6
8
ESG
EVTHRES
+ 19 8
+
LGATE
GATE
1
EVTEMP
RGATE +
18 22
9
20
21
DBODY
EBREAK
+
17
18
MSTRO
-
8
m.mmed n16 n6 n8 n8 = model=mmedmod, l=1u, w=1u
m.mstrong n16 n6 n8 n8 = model=mstrongmod, l=1u, w=1u
m.mweak n16 n21 n8 n8 = model=mweakmod, l=1u, w=1u
LSOURCE
7
SOURCE
3
RSOURCE
RLSOURCE
S1A
res.rbreak n17 n18 = 1, tc1 = 1.12e-3, tc2 = -3e-7
res.rdrain n50 n16 = 1.1e-1, tc1 = 9e-3, tc2 = 2e-5
res.rgate n9 n20 = 5.74e1
res.rldrain n2 n5 = 10
res.rlgate n1 n9 = 42.1
res.rlsource n3 n7 = 12.8
res.rslc1 n5 n51 = 1e-6, tc1 = 2.8e-3, tc2 = 1.9e-5
res.rslc2 n5 n50 = 1e3
res.rsource n8 n7 = 5.72e-2, tc1 = 1e-3, tc2 = 1e-6
res.rvtemp n18 n19 = 1, tc1 = -1.5e-3, tc2 = 1e-6
res.rvthres n22 n8 = 1, tc1 = -2e-3, tc2 = -3e-6
MWEAK
MMED
CIN
71
11
16
6
RLGATE
RDBODY
DBREAK
50
-
i.it n8 n17 = 1
l.ldrain n2 n5 = 1e-9
l.lgate n1 n9 = 4.21e-10
l.lsource n3 n7 = 1.28e-10
72
ISCL
dp.dbody n7 n71 = model=dbodymod
dp.dbreak n72 n11 = model=dbreakmod
dp.dplcap n10 n5 = model=dplcapmod
DRAIN
2
12
S2A
14
13
13
8
S1B
CA
RBREAK
15
17
18
RVTEMP
S2B
13
CB
6
8
EGS
19
-
-
IT
14
+
+
VBAT
5
8
EDS
-
+
8
22
RVTHRES
spe.ebreak n11 n7 n17 n18 = 100.6
spe.eds n14 n8 n5 n8 = 1
spe.egs n13 n8 n6 n8 = 1
spe.esg n6 n10 n6 n8 = 1
spe.evtemp n20 n6 n18 n22 = 1
spe.evthres n6 n21 n19 n8 = 1
sw_vcsp.s1a n6 n12 n13 n8 = model=s1amod
sw_vcsp.s1b n13 n12 n13 n8 = model=s1bmod
sw_vcsp.s2a n6 n15 n14 n13 = model=s2amod
sw_vcsp.s2b n13 n15 n14 n13 = model=s2bmod
v.vbat n22 n19 = dc=1
equations {
i (n51->n50) +=iscl
iscl: v(n51,n50) = ((v(n5,n51)/(1e-9+abs(v(n5,n51))))*((abs(v(n5,n51)*1e6/12))** 3.7))
}
}
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8
SPICE Thermal Model
REV 18 January 2001
HUFA76504DK8
Copper Area = 0.38 in 2
th
CTHERM1 th 8 8.5e-4
CTHERM2 8 7 1.8e-3
CTHERM3 7 6 5.0e-3
CTHERM4 6 5 1.3e-2
CTHERM5 5 4 4.0e-2
CTHERM6 4 3 1.5e-1
CTHERM7 3 2 6.5e-1
CTHERM8 2 tl 3.0
JUNCTION
RTHERM1
CTHERM1
8
RTHERM2
RTHERM1 th 8 3.5e-2
RTHERM2 8 7 6.0e-1
RTHERM3 7 6 2
RTHERM4 6 5 8
RTHERM5 5 4 18
RTHERM6 4 3 20
RTHERM7 3 2 29
RTHERM8 2 tl 31
CTHERM2
7
RTHERM3
CTHERM3
6
CTHERM4
RTHERM4
SABER Thermal Model
5
Copper Area = 0.38 in 2
template thermal_model th tl
thermal_c th, tl
{
ctherm.ctherm1 th 8 = 8.5e-4
ctherm.ctherm2 8 7 = 1.8e-3
ctherm.ctherm3 7 6 = 5.0e-3
ctherm.ctherm4 6 5 = 1.3e-2
ctherm.ctherm5 5 4 = 4.0e-2
ctherm.ctherm6 4 3 = 1.5e-1
ctherm.ctherm7 3 2 = 6.5e-1
ctherm.ctherm8 2 tl = 3.0
RTHERM5
CTHERM5
4
RTHERM6
CTHERM6
3
RTHERM7
rtherm.rtherm1 th 8 = 3.5e-2
rtherm.rtherm2 8 7 = 6.0e-1
rtherm.rtherm3 7 6 = 2
rtherm.rtherm4 6 5 = 8
rtherm.rtherm5 5 4 = 18
rtherm.rtherm6 4 3 = 20
rtherm.rtherm7 3 2 = 29
rtherm.rtherm8 2 tl = 31
}
CTHERM7
2
RTHERM8
CTHERM8
tl
AMBIENT
TABLE 1. Thermal Models
0.02 in2
0.14 in2
0.257 in2
0.38 in2
0.493 in2
CTHERM6
9.0e-2
1.3e-1
1.5e-1
1.5e-1
1.5e-1
CTHERM7
4.0e-1
6.0e-1
4.5e-1
6.5e-1
7.5e-1
CTHERM8
1.4
2.5
2.2
3
3
RTHERM6
39
26
20
20
20
RTHERM7
42
32
31
29
23
RTHERM8
48
35
38
31
25
COMPONANT
©2001 Fairchild Semiconductor Corporation
Rev. A, June 4, 2001
HUFA76504DK8
MS-012AA
8 LEAD JEDEC MS-012AA SMALL OUTLINE PLASTIC PACKAGE
E
E1
INCHES
A
A1
1
e
2
6
D
5
b
SYMBOL
MIN
c
MIN
MAX
NOTES
A
0.0532
0.0688
1.35
1.75
-
A1
0.004
0.0098
0.10
0.25
-
b
0.013
0.020
0.33
0.51
-
c
0.0075
0.0098
0.19
0.25
-
D
0.189
0.1968
4.80
5.00
2
E
0.2284
0.244
5.80
6.20
-
E1
0.1497
0.1574
3.80
4.00
3
e
h x 45o
MILLIMETERS
MAX
0.050 BSC
1.27 BSC
-
H
0.0099
0.0196
0.25
0.50
-
L
0.016
0.050
0.40
1.27
4
NOTES:
0.004 IN
0.10 mm
L
0o-8o
0.060
1.52
1. All dimensions are within allowable dimensions of Rev. C of
JEDEC MS-012AA outline dated 5-90.
2. Dimension “D” does not include mold flash, protrusions or gate
burrs. Mold flash, protrusions or gate burrs shall not exceed
0.006 inches (0.15mm) per side.
3. Dimension “E1” does not include inter-lead flash or protrusions.
Inter-lead flash and protrusions shall not exceed 0.010 inches
(0.25mm) per side.
4. “L” is the length of terminal for soldering.
0.050
1.27
0.155
4.0
0.275
7.0
MINIMUM RECOMMENDED FOOTPRINT FOR
SURFACE-MOUNTED APPLICATIONS
5. The chamfer on the body is optional. If it is not present, a visual index
feature must be located within the crosshatched area.
6. Controlling dimension: Millimeter.
0.024
0.6
7. Revision 8 dated 5-99.
1.5mm
DIA. HOLE
4.0mm
2.0mm
USER DIRECTION OF FEED
CL
MS-012AA
12mm TAPE AND REEL
1.75mm
12mm
8.0mm
40mm MIN.
ACCESS HOLE
18.4mm
COVER TAPE
13mm
330mm
GENERAL INFORMATION
1. 2500 PIECES PER REEL.
2. ORDER IN MULTIPLES OF FULL REELS ONLY.
3. MEETS EIA-481 REVISION “A” SPECIFICATIONS.
©2001 Fairchild Semiconductor Corporation
50mm
12.4mm
Rev. A, June 4, 2001
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PRODUCT STATUS DEFINITIONS
Definition of Terms
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Definition
Advance Information
Formative or
In Design
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
Preliminary
First Production
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
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changes at any time without notice in order to improve
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Rev. H3