ON ADP3208C 7-bit,programmable,dual- phase,mobile,cpu,synchronous buck controller Datasheet

Preliminary
7-Bit,Programmable,DualPhase,Mobile,CPU,Synchronous
Buck Controller
ADP3208C
FEATURES
GENERAL DESCRIPTION
Single-chip solution
Fully compatible with the Intel® IMVP-6+™ specifications
Integrated MOSFET drivers
Input Voltage Range of 3.3 V to 22 V
Selectable 1- or 2-phase operation with up to 1 MHz per
phase switching frequency
Guaranteed ±8 mV worst-case differentially sensed core
voltage error over temperature
Automatic power-saving mode maximizes efficiency with
light load during deeper sleep operation
Soft transient control reduces inrush current and audio noise
Active current balancing between output phases
Independent current limit and load line setting inputs for
additional design flexibility
Built-in power-good blanking supports
voltage identification (VID) on-the-fly transients
7-bit, digitally programmable DAC with 0.3 V to 1.5 V output
Short-circuit protection with latch-off delay
Clock enable output delays the CPU clock until the core
voltage is stable
Output load current monitor
48-lead LFCSP
The ADP3208C is a highly efficient, multiphase, synchronous
buck switching regulator controller. With its integrated drivers,
the ADP3208C is optimized for converting the notebook
battery voltage into the core supply voltage required by high
performance Intel processors. An internal 7-bit DAC is used to
read a VID code directly from the processor and to set the CPU
core voltage to a value within the range of 0.3 V to 1.5 V. The
phase relationship of the output signals ensures interleaved 2phase operation.
APPLICATIONS
Notebook power supplies for next-generation Intel processors
The ADP3208C uses a multimode architecture run at a
programmable switching frequency and optimized for efficiency
depending on the output current requirement. The ADP3208C
switches between single- and dual-phase operation to maximize
efficiency with all load conditions. The chip includes a
programmable load line slope function to adjust the output voltage
as a function of the load current so that the core voltage is always
optimally positioned for a load transient. The ADP3208C also
provides accurate and reliable short-circuit protection,
adjustable current limiting, and a delayed power-good output.
The IC supports on-the-fly output voltage changes requested by
the CPU.
The ADP3208C is specified over the extended commercial
temperature range of -10°C to 100°C and is available in a 48-lead
LFCSP.
May 2008– Rev. 1
ADP3208C
FUNCTIONAL BLOCK DIAGRAM
GND VCC EN
VEA
+
CSREF
Σ
+
+
Σ
Oscillator
_
1.7V
DRVH1
Driver
Logic
Current
Balancing
Circuit
+
+
REF
LLINE
BST1
UVLO
Shutdown
and Bias
COMP
FB
RPM RT RAMP VARFREQ SP
SW1
PVCC1
DRVL1
PGND1
OVP
BST2
DRVH2
PSI
SW2
Thermal
Throttle
Control
TTSNS
VRTT
PVCC2
DRVL2
PGND2
DAC - 200mV
CSREF
DAC - 300mV
DPRSTP
DPRSLP
Logic
VID0
CSREF
CSSUM
ILIMN
ILIMP
DAC
VID2
VID1
IMON
CSCOMP
Delay
Disable
CLKEN
Start Up
Delay
VID
DAC
DPRSLP
+
-
REF
Soft Start
Soft Transient
IREF
Precision
Reference
DPRSTP
Current
Monitor
Soft
Transient
Delay
VID3
FBRTN
Current
Limit
Circuit
PWRGD
Start Up
Delay
CLKEN
Open
Drain
VID4
CLKEN
+
PWRGD
Open
Drain
VID6
VID5
PWRGD
OCP
Shutdown
Delay
+
Figure 1.
Rev. 1 | Page 2 of 41 | www.onsemi.com
ADP3208C
TABLE OF CONTENTS
Features...............................................................................................1
OUTPUT CROWBAR ...............................................................26
Applications .......................................................................................1
Reverse Voltage Protection ........................................................27
General Description..........................................................................1
Output Enable and UVLO.........................................................27
Functional Block Diagram ...............................................................2
Thermal Throttling Control ......................................................27
Revision History................................................................................3
CURRENT MONITOR FUNCTION ......................................27
Specifications .....................................................................................4
Application Information ................................................................31
Timing Diagram................................................................................9
Setting the Clock Frequency for PWM....................................31
Absolute Maximum Ratings ..........................................................10
Setting the Switching Frequency for RPM Operation of Phase
1 .....................................................................................................31
ESD Caution ................................................................................10
Pin Configuration and Function Descriptions ...........................11
Test Circuits .....................................................................................13
Typical Performance Characteristics............................................15
Theory of Operation .......................................................................19
Number of Phases .......................................................................19
Operation Modes ........................................................................19
Differential Sensing of Output Voltage ....................................22
Output Current Sensing .............................................................22
Active Impedance Control Mode..............................................22
CURRENT Control Mode AND THERMAL BALANCE ....23
Voltage Control Mode ................................................................23
Power-Good Monitoring............................................................23
Power-Up Sequence and Soft Start ...........................................23
Soft Transient...............................................................................24
Inductor Selection.......................................................................31
COUT Selection..............................................................................33
Power MOSFETs .........................................................................34
Ramp Resistor Selection.............................................................35
COMP Pin Ramp ........................................................................35
Current Limit Setpoint...............................................................36
Output Current monitor ............................................................36
Feedback Loop Compensation Design ....................................36
CIN Selection and Input Current di/dt Reduction ..................37
Selecting Thermal Monitor Components................................38
Tuning Procedure for ADP3208C ............................................38
Layout and Component Placement ..........................................39
Outline Dimension .........................................................................41
Ordering Guide ...........................................................................41
Current Limit...............................................................................24
Changing VID on the Fly...........................................................25
REVISION HISTORY
5/08- Rev 1: Initial Preliminary Version
Rev. 1 | Page 3 of 41 | www.onsemi.com
ADP3208C
SPECIFICATIONS
VCC = PVCC1 = PVCC2 = BST1 = BST2 = high = 5 V, FBRTN = GND = SW1 = SW2 = PGND1 = PGND2 = low = 0 V, EN = VARFREQ =
high, DPRSLP = 0 V, PSI = 1.05 V, VVID = 1.2000 V, TA = -10°C to 100°C, unless otherwise noted.1 Current entering a pin (sunk by the
device) has a positive sign. RREF = 80 kΩ.
Table 1.
Parameter
Symbol
Conditions
Min
VFB, VLLINE
VOSVEA
IFB
VFB − VVID
Relative to CSREF = VDAC
Relative to CSREF = VDAC
−200
-0.5
−100
−78
Typ
Max
Units
−80
+200
+0.5
100
−82
mV
mV
nA
mV
4.0
V
VOLTAGE CONTROL
VOLTAGE ERROR AMPLIFIER
(VEAMP)
FB, LLINE Voltage Range2
FB, LLINE Offset Voltage2
FB, LLINE Bias Current2
LLINE Positioning Accuracy
COMP Voltage Range2
COMP Current
VCOMP
ICOMP
COMP Slew Rate
Gain Bandwidth2
VID DAC VOLTAGE REFERENCE
VDAC Voltage Range3
VDAC Accuracy
SRCOMP
GBW
VFB − VVID
VDAC Differential
Nonlinearity2
VDAC Line Regulation
VDAC Boot Voltage2
Soft-start Delay2
Soft-start Time
ΔVFB
VBOOTFB
tDSS
tSS
Boot Delay
tBOOT
VDAC Slew Rate
FBRTN Current
Measured on FB relative to VVID, LLINE forced 80 mV
below CSREF
Operating Range
COMP = 2 V, CSREF = VDAC
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
CCOMP = 10 pF, CSREF = VDAC, Open loop
configuration
FB forced 200 mV below CSREF
FB forced 200 mV above CSREF
0.85
Non-inverting unit gain configuration, RFB = 1 kΩ
See VID table
Measured on FB (includes offset), relative to VVID,
for VID table see Table 6
VVID = 1.2125V to 1.5000V
VVID = 0.3000V to 1.2000V
−0.75
6
mA
mA
15
−20
V/μs
V/μs
MHz
20
0
1.5
V
−9
−7.5
−1
+9
+7.5
+1
mV
mV
LSB
VCC = 4.75 V to 5.25 V
Measured during boot delay period
Measured from EN pos edge to FB = 50 mV
Measured from EN pos edge to FB settles to Vboot =
1.2 V within -5 %
Measured from FB settling to Vboot = 1.2 V within -5
% to CLKEN# neg edge
Soft-start
Non-LSB VID step, DPRSLP = H, Slow C4 Entry/Exit
Non-LSB VID step, DPRSLP = L, Fast C4 Exit
IFBRTN
0.05
1.200
200
1.7
%
V
μs
ms
150
μs
0.0625
0.25
1
90
200
LSB/μs
LSB/μs
LSB/μs
μA
−300
−200
200
−240
−160
250
mV
mV
mV
VOLTAGE MONITORING
and PROTECTION
POWER GOOD
CSREF Under-voltage
Threshold
CSREF Over-voltage
Threshold
VUVCSREF
VOVCSREF
Relative to DAC voltage = 0.5 V to 1.5 V
Relative to DAC voltage = 0.3 V to 0.4875 V
Relative to nominal DAC voltage
Rev. 1 | Page 4 of 41 | www.onsemi.com
−360
−360
150
ADP3208C
Parameter
CSREF Crowbar Voltage
Threshold
CSREF Reverse Voltage
Threshold
Symbol
VCBCSREF
Conditions
Relative to FBRTN
VRVCSREF
Relative to FBRTN, Latch-off mode
CSREF falling
CSREF rising
IPWRGD(SINK) = 4 mA
VPWRDG = 5 V
PWRGD Low Voltage
PWRGD High, Leakage
Current
PWRGD Start-up Delay
VPWRGD
IPWRGD
PWRGD Latch-off Delay
TLOFFPWRGD
PWRGD Propagation Delay3
TPDPWRGD
Crowbar Latch-off Delay2
TLOFFCB
TSSPWRGD
PWRGD Masking Time
CSREF Soft-stop Resistance
Min
1.57
Typ
1.7
−350
−300
−70
50
Measured from CLKEN neg edge to PWRGD pos
edge
Measured from Out-off-Good-Window event to
Latch-off (switching stops)
Measured from Out-off-Good-Window event to
PWRGD neg edge
Measured from Crowbar event to Latch-off
(switching stops)
Triggered by any VID change or OCP event
EN = L or Latch-off condition
Max
1.78
Units
V
−5
150
0.1
mV
mV
mV
μA
8
ms
8
ms
200
ns
200
ns
100
70
μs
Ω
CURRENT CONTROL
CURRENT-SENSE AMPLIFIER
(CSAMP)
CSSUM, CSREF CommonMode Range2
CSSUM, CSREF Offset Voltage
CSSUM Bias Current
CSREF Bias Current
CSCOMP Voltage Range2
CSCOMP Current
VOSCSA
0
2
V
CSREF – CSSUM TA = –10 C to 85 C
TA = 25 C
−1.7
−0.5
−50
−120
0.05
+1.7
+0.5
+50
+120
2
mV
mV
nA
nA
V
IBCSSUM
IBCSRE
ICSCOMPsource
ICSCOMPsink
CSCOMP Slew Rate
Gain Bandwidth2
Voltage range of interest
Operating Range
CSCOMP = 2 V
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
CCSCOMP = 10 pF, Open Loop Configuration
CSSUM forced 200 mV below CSREF
CSSUM forced 200 mV above CSREF
GBWCSA
Non-inverting unit gain configuration
RFB = 1 kOhm
CURRENT REFERENCE
IREF Voltage
VREF
RREF = 80 kΩ to set IREF = 20 uA
CURRENT LIMITER (OCP)
Current Limit (OCP) Threshold
VLIMTH
Measured from CSCOMP to CSREF, RLIM = 4.5 kΩ,
2-ph configuration, PSI = H
2-ph configuration, PSI = L
1-ph configuration
Measured from OCP event to PWRGD de-assertion
−750
1
μA
mA
10
−10
V/μs
V/μs
MHz
20
CURRENT MONITORING
and PROTECTION
Current Limit Latch-off Delay
CURRENT MONITOR
Current Gain Accuracy
IMON Clamp Voltage
IMON/ILIM
VMAXMON
Measured from ILIMP to IMON
ILIM = −20 μA
ILIM = −10 μA
ILIM = −5 μA
Relative to FBRTN, ILIMP = -30 uA
Rev. 1 | Page 5 of 41 | www.onsemi.com
1.55
1.6
1.65
V
−70
−32
−95
−47.5
−115
−65
mV
mV
−70
−95
8
−115
mV
ms
9.5
9.4
9
10
10
10
10.5
10.7
11
-
1.15
V
1.0
ADP3208C
Parameter
Symbol
Conditions
Min
Typ
Max
Units
VRT
VARFREQ = high, RT = 125 kΩ, VVID = 1.5000 V
VARFREQ = low
See also VRT(VVID) formula
Operating Range
1.22
0.98
1.25
1
1.27
1.02
V
V
3
MHz
PULSE WIDTH
MODULATOR
CLOCK OSCILLATOR
RT Voltage
PWM Clock Frequency
Range2
PWM Clock Frequency
RAMP GENERATOR
RAMP Voltage
RAMP Current Range2
fCLK
fCLK
VRAMP
IRAMP
TA = +25°C, VVID = 1.2000 V
RT = 73 kΩ
RT = 125 kΩ
RT = 180 kΩ
1570
955
700
kHz
kHz
kHz
0.9
1
VIN
1.1
1
−0.5
100
+0.5
−3
3
mV
VRAMP − VCOMP
RPM COMPARATOR
RPM Current
IRPM
VVID = 1.2 V, RT = 125 kΩ, VARFREQ = High
See also IRPM(RT) formula
VCOMP − (1 +VRPM)
EPWM CLOCK SYNC
Trigger Threshold2
1270
830
600
V
V
μA
μA
VOSRPM
VOSRPM
970
705
500
EN = high, IRAMP = 30 μA
EN = low
EN = high
EN = low, RAMP = 19 V
PWM COMPARATOR
PWM Comparator Offset2
RPM Comparator Offset2
0.3
−3
Relative to COMP sampled TCLK earlier
2-phase configuration
1-phase configuration
SWITCH AMPLIFIER
SW Common Mode Range2
SW Resistance
VSW(X)CM
RSW_PGND(X)
Operating Range for current sensing
Measured from SW to PGND
ZERO CURRENT SWITCHING
COMPARATOR
SW ZCS Threshold
Masked Off-Time
VDCM(SW1)
tOFFMSKD
DCM mode, DPRSLP = 3.3 V
Measured from DRVH neg edge to DRVH pos edge
at max frequency of operation
μA
−8.8
3
400
450
−600
mV
mV
mV
3
+200
mV
kΩ
−6
700
mV
ns
SYSTEM I/O BUFFERS
VID[6:0], PSI# INPUTS
Input Voltage
Input Current
VID Delay Time2
DPRSLP
Input Voltage
Input Current
Refers to driving signal level
Logic low, Isink ≥ 1 μA
Logic high, Isource ≤ −5 μA
V = 0.2 V
VID[6:0], DPRSLP (active pull down to GND)
PSI# (active pull-up to VCC)
Any VID edge to FB change 10%
Refers to driving signal level
Logic low, Isink > 1 μA
Logic high, Isource < -5 μA
DPRSLP = low
DPRSLP = high
Rev. 1 | Page 6 of 41 | www.onsemi.com
0.3
0.7
μA
μA
ns
−1
+1
200
1.0
2.3
−1
+2
V
V
V
V
μA
μA
ADP3208C
Parameter
Symbol
Conditions
Min
Refers to driving signal level
Logic low, Isink ≥ 1 μA
Logic high, Isource ≤ -5 μA
0.7
Typ
Max
Units
0.3
V
V
DPRSTP
Input Voltage
Input Current
μA
1
VARFREQ, SP
Input Voltage
Refers to driving signal level
Logic low, Isink ≥ 1 μA
Logic high, Isource ≤ -5 μA
0.7
4
Input Current
μA
1
EN INPUT
Input Voltage
Refers to driving signal level
Logic low, Isink ≥ 1 μA
Logic high, Isource ≤ -5 μA
EN = L or EN = H (static)
0.8 V < EN < 1.6 V (during transition)
Input Current
V
V
1
2.3
10
70
V
V
nA
μA
CLKEN OUTPUT
Output Low Voltage
Output High, Leakage
Current
Logic low, Isink = 4 mA
Logic high, VCLKEN = VCC
50
100
1
mV
μA
5
2.55
V
V
mV
μA
mV
V
THERMAL MONITORING
and PROTECTION
TTSNS Voltage Range2
TTSNS Threshold
TTSNS Hysteresis
TTSNS Bias Current
VRTT Output Voltage
VCC = 5 V, TTSNS is falling
VVRTT
TTSNS = 2.6 V
Logic low, IVRTT(SINK) = 400 μA
Logic high, IVRTT(SOURCE) = -400 μA
0
2.45
50
−2
4
2.5
110
10
5
2
100
SUPPLY
Supply Voltage Range
Supply Current
VCC
VCC OK Threshold
VCC UVLO Threshold
VCC Hysteresis2
VCCOK
VCCUVLO
HIGH-SIDE MOSFET DRIVER
Pull-up Resistance, Sourcing
Current
Pull-down Resistance, Sinking
Current
Transition Times
Dead Delay Times
BST Quiescent Current
trDRVH,
tfDRVH
tpdhDRVH
4.5
EN = H
EN = 0 V
VCC is rising
VCC is falling
4.0
6.2
15
4.3
4.1
210
5.5
10
50
4.5
V
mA
μA
V
V
mV
BST = PVCC
1.8
3.3
Ω
BST = PVCC
1.0
3
Ω
BST = PVCC, CL = 3 nF, Figure 2
BST = PVCC, CL = 3 nF, Figure 2
BST = PVCC, Figure 2
EN = L (Shutdown)
EN = H, no switching
15
13
39
0.6
15
35
31
60
5
ns
ns
ns
μA
μA
1.6
3.3
Ω
0.8
2.5
Ω
LOW-SIDE MOSFET DRIVER
Pull-up Resistance, Sourcing
Current
Pull-down Resistance, Sinking
Current
Rev. 1 | Page 7 of 41 | www.onsemi.com
ADP3208C
Parameter
Transition Times
Propagation Delay Times
SW Transition Timeout
SW Off Threshold
PVCC Quiescent Current
BOOTSTRAP RECTIFIER
SWITCH
On Resistance
1
2
Symbol
trDRVL
tfDRVL
tpdhDRVL
tTOSW
VOFFSW
Conditions
CL = 3 nF, Figure 2
CL = 3 nF, Figure 2
CL = 3 nF, Figure 2
DRVH = L, SW = 2.5 V
Min
2150
EN = L (Shutdown)
EN = H, no switching
EN = L or EN = H and DRVL = H
All limits at temperature extremes are guaranteed via correlation using standard statistical quality control (SQC).
Guaranteed by design or bench characterization, not production tested.
Rev. 1 | Page 8 of 41 | www.onsemi.com
3
Typ
15
14
10
250
1.6
1
240
Max
35
35
30
450
6
10
15
Units
ns
ns
ns
ns
V
μA
μA
Ω
ADP3208C
TIMING DIAGRAM
Timing is referenced to the 90% and 10% points, unless otherwise noted.
IN
tpdlDRVL
tfDRVL
tpdlDRVH
trDRVL
DRVL
tfDRVH
tpdhDRVH
DRVH
(WITH RESPECT
TO SW)
trDRVH
VTH
VTH
1V
SW
Figure 2. Timing Diagram
Rev. 1 | Page 9 of 41 | www.onsemi.com
06374-006
tpdhDRVL
ADP3208C
ABSOLUTE MAXIMUM RATINGS
Table 2.
Parameter
VCC, PVCC1, PVCC2
FBRTN, PGND1, PGND2
BST1, BST2
DC
t < 200 ns
BST1 to SW1, BST2 to SW2
SW1, SW2
DC
t < 200 ns
DRVH1 to SW1, DRVH2 to SW2,
DRVL1 to PGND1, DRVL2 to PGND2
DC
t < 200 ns
RAMP (in Shutdown)
DC
All Other Inputs and Outputs
Storage Temperature
Operating Ambient Temperature Range
Operating Junction Temperature
Thermal Impedance (θJA) 2-Layer Board
Lead Temperature
Soldering (10 sec)
Infrared (15 sec)
Rating
−0.3 V to +6 V
−0.3 V to +0.3 V
−0.3 V to +28 V
−0.3 V to +33 V
−0.3 V to +6 V
−5 V to +22 V
−10 V to +28 V
−0.3 V to +6 V
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
ESD CAUTION
−0.3 V to +6 V
−5 V to +6 V
−0.3 V to +22 V
−0.3 V to +6 V
−65°C to +150°C
−10°C to 100°C
125°C
40°C/W
300°C
260°C
Rev. 1 | Page 10 of 41 | www.onsemi.com
ADP3208C
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN
PWRGD
NC
CLKEN
FBRTN
FB
COMP
NC
IRPM
VARFREQ
VRTT
TTSNS
1
ADP3208C
(top view)
BST1
DRVH1
SW1
PVCC1
DRVL1
PGND1
PGND2
DRVL2
PVCC2
SW2
DRVH2
BST2
Figure 3. LFCSP Pin Configuration
Table 3. Pin Function Descriptions
Pin No.
1
Mnemonic
EN
Description
Enable Input. Driving this pin low shuts down the chip, disables the driver outputs, pulls PWRGD
and VRTT low, and pulls CLKEN high.
2
PWRGD
3
4
NC
CLKEN
5
FBRTN
6
7
8
9
FB
COMP
NC
IRPM
10
VARFREQ
11
VRTT
12
TTSNS
13
IMON
14
RPM
15
IREF
Power-Good Output. Open-drain output. A low logic state means that the output voltage is outside
of the VID DAC defined range.
Not Connected.
Clock Enable Output. Open-drain output. A low logic state enables the CPU internal PLL clock to
lock to the external clock.
Feedback Return Input/Output. This pin remotely senses the CPU core voltage. It is also used as the
ground return for the VID DAC and the voltage error amplifier blocks.
Voltage Error Amplifier Feedback Input. The inverting input of the voltage error amplifier.
Voltage Error Amplifier Output and Frequency Compensation Point.
Not Connected.
RPM Mode Timing Control Input. A resistor between this pin or RPM pin to ground sets the RPM mode
turn-on threshold voltage. If a resistor is connected between this pin to ground, RPM pin must remain
floating.
Variable Frequency Enable Input. A high logic state enables the PWM clock frequency to vary with
VID code.
Voltage Regulator Thermal Throttling Output. Logic high state indicates that the voltage regulator
temperature at the remote sensing point exceeded a set alarm threshold level.
Thermal Throttling Sense and Crowbar Disable Input. A resistor divider where the upper resistor is
connected to VCC, the lower resistor (NTC thermistor) is connected to GND, and the center point is
connected to this pin and acts as a temperature sensor half bridge. Connecting TTSNS to GND disables
the thermal throttling function and disables the crowbar, or overvoltage protection (OVP), feature
of the chip.
Current Monitor Output. This pin sources a current proportional to the output load current. A
resistor to FBRTN sets the current monitor gain.
RPM Mode Timing Control Input. A resistor between this pin or IRPM pin to ground sets the RPM mode
turn-on threshold voltage. If a resistor is connected between this pin to ground, IRPM pin must remain
floating.
This pin sets the internal bias currents. A 80kOhm resistor is connected from this pin to ground.
Rev. 1 | Page 11 of 41 | www.onsemi.com
ADP3208C
Pin No.
16
Mnemonic
LLINE
17
18
CSCOMP
CSREF
19
CSSUM
20
RAMP
21
ILIMN
22
ILIMP
23
RT
24
25
GND
BST2
26
27
28
29
30
31
32
33
34
35
36
DRVH2
SW2
PVCC2
DRVL2
PGND2
PGND1
DRVL1
PVCC1
SW1
DRVH1
BST1
37
38
39 to 45
VCC
SP
VID6 to VID0
46
PSI
47
DPRSTP
48
DPRSLP
Description
Load Line Programming Input. The center point of a resistor divider connected between CSREF and
CSCOMP can be tied to this pin to set the load line slope.
Current Sense Amplifier Output and Frequency Compensation Point.
Current Sense Reference Input. This pin must be connected to the common point of the output
inductors. The node is shorted to GND through an internal switch when the chip is disabled to
provide soft stop transient control of the converter output voltage.
Current Sense Summing Input. External resistors from each switch node to this pin sum the
inductor currents to provide total current information.
PWM Ramp Slope Setting Input. An external resistor from the converter input voltage node to this
pin sets the slope of the internal PWM stabilizing ramp used for phase-current balancing.
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current-limit threshold of the
converter.
Current Limit Set. An external resistor from ILIMN to ILIMP sets the current-limit threshold of the
converter.
PWM Oscillator Frequency Setting Input. An external resistor from this pin to GND sets the PWM
oscillator frequency.
Analog and Digital Signal Ground.
High-Side Bootstrap Supply for Phase 2. A capacitor from this pin to SW2 holds the bootstrapped
voltage while the high-side MOSFET is on.
High-Side Gate Drive Output for Phase 2.
Current Balance Input for Phase 2 and Current Return for High-Side Gate Drive.
Power Supply Input/Output of Low-Side Gate Driver for Phase 2.
Low-Side Gate Drive Output for Phase 2.
Low-Side Driver Power Ground for Phase 2.
Low-Side Driver Power Ground for Phase 1.
Low-Side Gate Drive Output for Phase 1.
Power Supply Input/Output of Low-Side Gate Driver for Phase 1.
Current Balance Input for Phase 1 and Current Return For High-Side Gate Drive.
High-Side Gate Drive Output for Phase 1.
High-Side Bootstrap Supply for Phase 1. A capacitor from this pin to SW1 holds the bootstrapped
voltage while the high-side MOSFET is on.
Power Supply Input/Output of the Controller.
Single-Phase Select Input. Logic high state sets single-phase configuration.
Voltage Identification DAC Inputs. A 7-bit word (the VID code) programs the DAC output voltage,
the reference voltage of the voltage error amplifier without a load (see the VID code table, Table 6).
Power State Indicator Input. Driving this pin low forces the controller to operate in single-phase mode.
Deeper Stop Control Input. The logic state of this pin is usually complementary to the state of the
DPRSLP pin; however, during slow deeper sleep exit, both pins are logic low.
Deeper Sleep Control Input.
Rev. 1 | Page 12 of 41 | www.onsemi.com
ADP3208C
TEST CIRCUITS
5V
SP
VCC
VID6
VID5
VID3
VID4
VID2
VID1
PSI#
VID0
DPRSLP
DPRSTP#
37
7
10kΩ
6
VCC
ADP3208C
COMP
FB
+
GND
RT
ILIMP
ILIMN
ΔV
RAMP
CSSUM
CSREF
CSCOMP
LLINE
IREF
RPM
IMON
16
LLINE
CSREF
18
1.0V
24
VID DAC
GND
ΔV FB = FBΔV= ΔV - FB ΔV=0mV
Figure 4. Closed-Loop Output Voltage Accuracy
Figure 6. Positioning Accuracy
Figure 5. Current Sense Amplifier, VOS
Rev. 1 | Page 13 of 41 | www.onsemi.com
ADP3208C
Rev. 1 | Page 14 of 41 | www.onsemi.com
ADP3208C
TYPICAL PERFORMANCE CHARACTERISTICS
VVID = 1.5 V, TA = 20°C to 100°C, unless otherwise noted.
95
VIN = 9 V
90
SW2
EFFICIENCY (%
85
80
V IN = 19 V
75
SW1
70
65
60
OUTPUT VOLTAGE
VOUT = 1.2 V
55
f SW = 305 kHz
50
0
5
10
15
20
25
30
35
40
Input = 12V, Output = 1V
9A to 44A Load Step
45
LOAD CURRENT (A)
Figure 7. PWM Mode Efficiency vs. Load Current
Figure 9. . Load Transient with 2 Phases
OUTPUT RIPPLE
SW2
SW1
CSREF to CSCOMP
SW1
OUTPUT VOLTAGE
SW2
Input = 12V, Output = 1V
44A to 9A Load Step
Input = 12V, Output = 1.1V
No Load
Figure 10. Switching Waveforms in 2 Phase
Figure 8. Load Transient with 2 Phases
OUTPUT RIPPLE
COMP
SW1
SW2
Input = 12V, Output = 1.1V
No Load
Figure 11. Switching Waveforms in 2 Phase
Rev. 1 | Page 15 of 41 | www.onsemi.com
1000
400
350
Switching Frequency (kHz)
PER PHASE SWITCHING FREQUENCY (kHz)
ADP3208C
VARFREQ = 0V
300
250
VARFREQ = 5V
200
150
100
50
0
0.25
RT = 187kΩ
2 Phase Mode
0.5
0.75
1
VID OUTPUT VOLTAGE (V)
1.25
VID = 1.4125V
VID = 1.2125V
VID = 1.1V
VID = 0.8125
VID = 0.6125
2 Phase Configuration
100
10
1.5
100
Figure 12. Switching Frequency vs. VID Output Voltage in PWM Mode
Figure 15. Per Phase Switching Frequency vs. RT Resistance
350
1.05
1 Phase
PSI = Low
1
250
2 Phase
PSI = High
Output (V)
+2%
200
150
100
0.95
-2%
0.9
50
06374-013
SWITCHING FREQUENCY (kHz)
300
0
1000
Rt RESISTANCE (kΩ)
RT = 237kΩ
RPM = 80.5kΩ
0.5
0
1.0
0.85
0
1.5
10
20
30
40
50
Load (A)
OUTPUT VOLTAGE (V)
Figure 13. Switching Frequency vs. Output Voltage in RPM Mode
Figure 16. Load Line Accuracy
1200
0.8
VCC CURRENT (mA)
800
600
400
0.6
0.4
0.2
VDC = 12V
EN = LOW
200
0
06374-014
PMON VOLTAGE (mV)
1000
0
20
40
60
0
0
1
2
3
4
5
VCC VOLTAGE (V)
80
OUTPUT POWER (W)
Figure 14. IMON Voltage vs. Output Current
Figure 17. VCC Current vs. VCC Voltage with Enable Low
Rev. 1 | Page 16 of 41 | www.onsemi.com
6
ADP3208C
OUTPUT VOLTAGE
PWRGD
SWITCH
NODE 1
SWITCH
NODE 2
CLKEN
EN
OUTPUT VOLTAGE
Figure 18. Start-Up Waveforms
Figure 21. PSI Transition
OUTPUT VOLTAGE
4
OUTPUT VOLTAGE
L1 CURRENT
L2 CURRENT
SWITCH
NODE 1
2
DPRSLP
R1
SWITCH NODE 1
SWITCH NODE 2
CH1 10.0V
CH2 5.00A
CH3 5.00A
CH4 20.0mV
REF1 10.0V 1.00µs
M1.00µs
SWITCH
NODE 2
06374-019
1
A CH3
PSI = HI GH
LOA D = 2 A
8.00A
T 20.00%
Figure 26. DPRSLP Transition
Figure 19. Dual-Phase, Interleaved PWM Waveform, 20 A Load
OUTPUT VOLTAGE
SWITCH
NODE 2
SWITCH
NODE 1
DPRSLP
PSI
SWITCH
NODE 1
SWITCH
NODE 2
OUTPUT VOLTAGE
PSI = HIG H
LO A D = 2 A
Figure 27. DPRSLP Transition
Figure 20. PSI Transition
Rev. 1 | Page 17 of 41 | www.onsemi.com
ADP3208C
OUTPUT VOLTAGE
DPRSLP
SWITCH
NODE 2
SWITCH
NODE 1
PSI = LOW
LOA D = 2 A
Figure28. DPRSLP Transition
OUTPUT VOLTAGE
DPRSLP
SWITCH
NODE 2
SWITCH
NODE 1
PSI = LOW
LOA D = 2 A
Figure29. DPRSLP Transition
Rev. 1 | Page 18 of 41 | www.onsemi.com
ADP3208C
THEORY OF OPERATION
The ADP3208C combines multimode pulse-width-modulated
(PWM) control and ramp-pulse-modulated (RPM) control with
multiphase logic outputs for use in single- and dual-phase
synchronous buck CPU core supply power converters. The
internal 7-bit VID DAC conforms to the Intel IMVP-6+
specifications.
Multiphase operation is important for producing the high
currents and low voltages demanded by today’s microprocessors.
Handling high currents in a single-phase converter would put
too high of a thermal stress on system components such as the
inductors and MOSFETs.
The multimode control of the ADP3208C is a stable, high
performance architecture that includes
•
•
•
•
•
•
•
•
•
•
Current and thermal balance between phases
High speed response at the lowest possible switching
frequency and minimal count of output decoupling capacitors
Minimized thermal switching losses due to lower frequency
operation
High accuracy load line regulation
High current output by supporting 2-phase operation
Reduced output ripple due to multiphase ripple cancellation
High power conversion efficiency with heavy and light loads
Increased immunity from noise introduced by PC board
layout constraints
Ease of use due to independent component selection
Flexibility in design by allowing optimization for either low
cost or high performance
NUMBER OF PHASES
The number of operational phases can be set by the user. Tying
the SP pin to the VCC pin forces the chip into single-phase
operation. Otherwise, dual-phase operation is automatically
selected, and the chip switches between single- and dual-phase
modes as the load changes to optimize power conversion efficiency.
In dual-phase configuration, SP is low and the timing
relationship between the two phases is determined by internal
circuitry that monitors the PWM outputs. Because each phase
is monitored independently, operation approaching 100% duty
cycle is possible. In addition, more than one output can be
active at a time, permitting overlapping phases.
OPERATION MODES
The number of phases can be static (see the Number of Phases
section) or dynamically controlled by system signals to
optimize the power conversion efficiency with heavy and light
loads.
If SP is set low (user-selected dual-phase mode) during a VID
transient or with a heavy load condition (indicated by DPRSLP
being low and PSI being high), the ADP3208C runs in 2-phase,
interleaved PWM mode to achieve minimal VCORE output voltage
ripple and the best transient performance possible. If the load
becomes light (indicated by PSI being low or DPRSLP being
high), ADP3208C switches to single-phase mode to maximize
the power conversion efficiency.
In addition to changing the number of phases, the ADP3208C is
also capable of dynamically changing the control method. In
dual-phase operation, the ADP3208C runs in PWM mode,
where the switching frequency is controlled by the master clock.
In single-phase operation (commanded by the PSI low state),
the ADP3208C runs in RPM mode, where the switching
frequency is controlled by the ripple voltage appearing on the
COMP pin. In RPM mode, the DRVH1 pin is driven high each
time the COMP pin voltage rises to a voltage limit set by the
VID voltage and an external resistor connected from the RPM
to GND. If the device is in single-phase mode and the system
signal DPRSLP is asserted high during the deeper sleep mode of
CPU operation, the ADP3208C continues running in RPM
mode but offers the option of turning off the low-side
(synchronous rectifier) MOSFET when the inductor current
drops to 0. Turning off the low-side MOSFETs at the zero
current crossing prevents reversed inductor current build up
and breaks synchronous operation of high- and low-side
switches. Due to the asynchronous operation, the switching
frequency becomes slower as the load current decreases,
resulting in good power conversion efficiency with very light
loads.
Table 4 summarizes how the ADP3208C dynamically changes
the number of active phases and transitions the operation mode
based on system signals and operating conditions.
Rev. 1 | Page 19 of 41 | www.onsemi.com
ADP3208C
Table 4. Phase Number and Operation Modes1
PSI No.
*
1
0
0
*
*
DPRSLP
*
0
0
0
1
1
VID Transition2
Yes
No
No
No
No
No
Current Limit
*
*
No
Yes
No
Yes
No. of Phases
Selected by
the User
N [2 or 1]
N [2 or 1]
*
*
*
*
No. of Phases
in Operation
N
N
1
1
1
1
Operation Modes3
PWM, CCM only
PWM, CCM only
RPM, CCM only
PWM, CCM only
RPM, automatic CCM/DCM
PWM, CCM only
1
* = don’t care.
VID transient period is the time following any VID change, including entry into and exit from deeper sleep mode. The duration of VID transient period is the same as
that of PWRGD masking time.
3
CCM stands for continuous current mode, and DCM stands for discontinuous current mode.
2
VRMP
5V
FLIP-FLOP
IR = AR × IRAMP
S
Q
BST1
GATE DRIVER
BST
DRVH
RD
CR
FLIP-FLOP
400ns
1V
IN
SW
DCM
DRVL
Q
S
Q
Q
VCC
RI
DRVH1
L
SW1
LOAD
DRVL1
5V
RD
R2
BST2
R1
VCC
DRVH2
R2
30mV
R1
RI
L
SW2
1V
DRVL2
VDC
+–
+
CSREF
–
VCS
+
COMP
CA
RA
CFB
+
FBRTN
FB
CB
LLINE
CSCOMP
CSSUM
RCS
RPH
CCS
RPH
RB
-2
4
7
3
6
0
Figure 22. Single-Phase RPM Mode Operation
Rev. 1 | Page 20 of 41 | www.onsemi.com
ADP3208C
5V
BST1
VCC
GATE DRIVER
IR = A R × I RAMP
BST
DRVH
FLIP-FLOP
CLOCK
OSCILLATOR
S
Q
IN
SW
DRVL
RD
CR
RI
L
SW1
DRVL1
LOAD
5V
AD
BST2
VCC
GATE DRIVER
0.2V
IR = A R × IRAMP
BST
DRVH
FLIP-FLOP
CLOCK
OSCILLATOR
S
SW
Q
DRVL
DRVH2
RI
L
SW2
DRVL2
RD
CR
VCC
DRVH1
AD
VDC
+–
0.2V
CSREF
–
+ V
CS
RAMP
+
COMP
RA
CA
CFB
+
FBRTN
FB
CB
LLINE
CSCOMP
CSSUM
RCS
RPH
CCS
RPH
RB
5
-2
4
7
3
6
0
Figure 23. Dual-Phase PWM Mode Operation
Rev. 1 | Page 21 of 41 | www.onsemi.com
ADP3208C
Setting Switch Frequency
OUTPUT CURRENT SENSING
Master Clock Frequency in PWM Mode
The ADP3208C includes a dedicated current sense amplifier (CSA)
to monitor the total output current of the converter for proper
voltage positioning vs. load current and for over current
detection. Sensing the current delivered to the load is an
inherently more accurate method than detecting peak current
or sampling the current across a sense element, such as the lowside MOSFET. The current sense amplifier can be configured
several ways, depending on system optimization objectives, and
the current information can be obtained by
When the ADP3208C runs in PWM, the clock frequency is set
by an external resistor connected from the RT pin to GND. The
frequency is constant at a given VID code but varies with the
VID voltage: the lower the VID voltage, the lower the clock
frequency. The variation of clock frequency with VID voltage
maintains constant VCORE ripple and improves power conversion
efficiency at lower VID voltages. Figure 15 shows the
relationship between clock frequency and VID voltage,
parameterized by RT resistance.
•
To determine the switching frequency per phase, divide the
clock by the number of phases in use.
•
Switching Frequency in RPM Mode—
Single-Phase Operation
•
In single-phase RPM mode, the switching frequency is
controlled by the ripple voltage on the COMP pin, rather than
by the master clock. Each time the COMP pin voltage exceeds
the RPM pin voltage threshold level determined by the VID
voltage and the external resistor connected from RPM to GND,
an internal ramp signal is started and DRVH1 is driven high.
The slew rate of the internal ramp is programmed by the
current entering the RAMP pin. One-third of the RAMP
current charges an internal ramp capacitor (5 pF typical) and
creates a ramp. When the internal ramp signal intercepts the
COMP voltage, the DRVH1 pin is reset low.
In continuous current mode, the switching frequency of RPM
operation is almost constant. While in discontinuous current
conduction mode, the switching frequency is reduced as a
function of the load current.
DIFFERENTIAL SENSING OF OUTPUT VOLTAGE
The ADP3208C combines differential sensing with a high accuracy
VID DAC, referenced by a precision band gap source and a low
offset error amplifier, to meet the rigorous accuracy requirement
of the Intel IMVP-6+ specification. In steady-state mode, the
combination of the VID DAC and error amplifier maintain the
output voltage for a worst-case scenario within ±8 mV of the
full operating output voltage and temperature range.
The CPU core output voltage is sensed between the FB and
FBRTN pins. FB should be connected through a resistor to the
positive regulation point—the VCC remote sensing pin of the
microprocessor. FBRTN should be connected directly to the
negative remote sensing point—the VSS sensing point of the
CPU. The internal VID DAC and precision voltage reference
are referenced to FBRTN and have a maximum current of
200 μA for guaranteed accurate remote sensing.
Output inductor ESR sensing without the use of a
thermistor for the lowest cost
Output inductor ESR sensing with the use of a thermistor
that tracks inductor temperature to improve accuracy
Discrete resistor sensing for the highest accuracy
At the positive input of the CSA, the CSREF pin is connected to
the output voltage. At the negative input (that is, the CSSUM pin
of the CSA), signals from the sensing element (in the case of
inductor DCR sensing, signals from the switch node side of the
output inductors) are summed together by series summing
resistors. The feedback resistor between the CSCOMP and
CSSUM pins sets the gain of the current sense amplifier, and a
filter capacitor is placed in parallel with this resistor. The
current information is then given as the voltage difference
between the CSCOMP and CSREF pins. This signal is used
internally as a differential input for the current limit
comparator.
An additional resistor divider connected between the CSCOMP
and CSREF pins with the midpoint connected to the LLINE pin
can be used to set the load line required by the microprocessor
specification. The current information to set the load line is
then given as the voltage difference between the LLINE and
CSREF pins. This configuration allows the load line slope to be
set independent from the current limit threshold. If the current
limit threshold and load line do not have to be set independently,
the resistor divider between the CSCOMP and CSREF pins can
be omitted and the CSCOMP pin can be connected directly to
LLINE. To disable voltage positioning entirely (that is, to set no
load line), LLINE should be tied to CSREF.
To provide the best accuracy for current sensing, the CSA has a
low offset input voltage and the sensing gain is set by an external
resistor ratio.
ACTIVE IMPEDANCE CONTROL MODE
To control the dynamic output voltage droop as a function of
the output current, the signal that is proportional to the total
output current, converted from the voltage difference between
LLINE and CSREF, can be scaled to be equal to the required
droop voltage. This droop voltage is calculated by multiplying
Rev. 1 | Page 22 of 41 | www.onsemi.com
ADP3208C
the droop impedance of the regulator by the output current.
This value is used as the control voltage of the PWM regulator.
The droop voltage is subtracted from the DAC reference output
voltage, and the resulting voltage is used as the voltage
positioning setpoint. The arrangement results in an enhanced
feedforward response.
CURRENT CONTROL MODE AND
THERMAL BALANCE
The ADP3208C has individual inputs for monitoring the
current of each phase. The phase current information is
combined with an internal ramp to create a current-balancing
feedback system that is optimized for initial current accuracy and
dynamic thermal balance. The current balance information is
independent from the total inductor current information used for
voltage positioning described in the Active Impedance Control
Mode section.
The magnitude of the internal ramp can be set so that the transient
response of the system is optimal. The ADP3208C monitors the
supply voltage to achieve feedforward control whenever the
supply voltage changes. A resistor connected from the power
input voltage rail to the RAMP pin determines the slope of the
internal PWM ramp. More detail about programming the ramp
is provided in the Application Information section.
The ADP3208C should not require external thermal balance
circuitry if a good layout is used. However, if mismatch is desired
due to uneven cooling in phase, external resistors can be added
to individually control phase currents as long as the phase currents
are mismatched by less than 30%. If unwanted mismatch exceeds
30%, a new layout that improves phase symmetry should be
considered.
Figure 24. Optional Current Balance Resistors
In 2-phase operation, alternate cycles of the internal ramp control
the duty cycle of the separate phases. Figure 24 shows the
addition of two resistors from each switch node to the RAMP
pin; this modifies the ramp-charging current individually for
each phase. During Phase 1, SW Node 1 is high (practically at
the input voltage potential) and SW Node 2 is low (practically at
the ground potential). As a consequence, the RAMP pin, through
the R2 resistor, sees the tap point of a divider connected to the
input voltage, where RSW1 is the upper element and RSW2 is the
lower element of the divider. During Phase 2, the voltages on
SW Node 1 and SW Node 2 switch and the resistors swap
functions. Tuning RSW1 and RSW2 allows the current to be
optimally set for each phase. To increase the current for a
given phase, decrease RSW for that phase.
VOLTAGE CONTROL MODE
A high-gain bandwidth error amplifier is used for the voltage
mode control loop. The noninverting input voltage is set via the
7-bit VID DAC. The VID codes are listed in Table 6. The
noninverting input voltage is offset by the droop voltage as a
function of current, commonly known as active voltage
positioning. The output of the error amplifier is the COMP pin,
which sets the termination voltage of the internal PWM ramps.
At the negative input, the FB pin is tied to the output sense
location using RB, a resistor for sensing and controlling the
output voltage at the remote sensing point. The main loop
compensation is incorporated in the feedback network
connected between the FB and COMP pins.
POWER-GOOD MONITORING
The power-good comparator monitors the output voltage via
the CSREF pin. The PWRGD pin is an open-drain output that
can be pulled up through an external resistor to a voltage rail—
not necessarily the same VCC voltage rail that is running the
controller. A logic high level indicates that the output voltage is
within the voltage limits defined by a range around the VID
voltage setting. PWRGD goes low when the output voltage is
outside of this range.
Following the IMVP-6+ specification, the PWRGD range is
defined to be 300 mV less than and 200 mV greater than the
actual VID DAC output voltage. For any DAC voltage less than
300 mV, only the upper limit of the PWRGD range is
monitored. To prevent a false alarm, the power-good circuit is
masked during various system transitions, including a VID
change and entrance into or exit out of deeper sleep. The
duration of the PWRGD mask is set to approximately 130 μs by
an internal timer. If the voltage drop is greater than 200 mV
during deeper sleep entry or slow deeper sleep exit, the
duration of PWRGD masking is extended by the internal logic
circuit.
POWER-UP SEQUENCE AND SOFT START
The power-on ramp-up time of the output voltage is set
internally. The power-up sequence, including the soft start is
illustrated in Figure 25.
After EN is asserted high, the soft start sequence starts. The
core voltage ramps up linearly to the boot voltage. The
ADP3208C regulates at the boot voltage for 100 μs. After the
boot time is completed, CLKEN# is asserted low. After
CLKEN# is asserted low for 9ms, PWRGD is asserted high.
Rev. 1 | Page 23 of 41 | www.onsemi.com
ADP3208C
In VCC UVLO or in shutdown, a small MOSFET turns on
connecting the CSREF to GND. The MOSFET on the CSREF
pin has a resistance of approximately 100Ω. When VCC ramps
above the upper UVLO threshold and EN is asserted high, the
ADP3208C enables internal bias and starts a reset cycle that
lasts about 50 μs to 60 μs. Next, when initial reset is over, the
chip detects the number of phases set by the user, and gives a go
signal to start soft start. The ADP3208C reads the VID codes
provided by the CPU on VID0 to VID6 input pins after
CLKEN# is asserted low.The PWRGD signal is asserted after a
tCPU_PWRGD delay of about 9 ms, as specified by IMVP-6+. The
power-good delay is programmed internally.
Table 5. Soft Transient Slew Rate
VID Transient
Entrance to Deeper Sleep
Fast Exit from Deeper Sleep
Slow Exit from Deeper Sleep
Transient from VBOOT to VID
DPRSLP
HIGH
LOW
HIGH
DNC1
Slew Rate
−3.125mV/μs
+12.5mV/μs
+3.125mV/μs
±3.125mV/μs
CURRENT LIMIT
The ADP3208C compares the differential output of a currentsense amplifier to a programmable current-limit setpoint to
provide current-limiting function. The current limit set point is
set with a resistor connected from ILIM pin to CSCOMP pin.
This is the Rlim resistor. During normal operation, the voltage
on the ILIM pin is equal to the CSREF pin. The voltage across
Rlim is equal to the voltage across the current sense amplifier
(from CSREF pin to CSCOMP pin). This voltage is
proportional to output current. The current through Rlim is
proportional to the output inductor current. The current
through Rlim is compared with an internal reference current.
When the Rlim current goes above the internal reference current,
the ADP3208C goes into current limit. The current limit circuit
is shown in figure 28.
Figure 25. Power-Up Sequence of ADP3208C
If EN is taken low or VCC drops below the VCC UVLO
threshold, both the SS capacitor and the PGDELAY capacitor
are reset to ground to prepare the chip for a subsequent soft
start cycle.
SOFT TRANSIENT
When a VID input changes, the ADP3208C detects the change but
ignores new code for a minimum of 400 ns. This delay is required to
prevent the device from reacting to digital signal skew while the 7bit VID input code is in transition. Additionally, the VID change
triggers a PWRGD masking timer to prevent a PWRGD failure.
Each VID change resets and retriggers the internal PWRGD
masking timer.
The ADP3208C provides a soft transient function to reduce inrush
current during VID transitions. Reducing the inrush current helps
decrease the acoustic noise generated by the MLCC input capacitors
and inductors.
The soft transient feature is implemented internally. When a new
VID code is detected, the ADP3208C steps sequentially through
each VID voltage to the final VID voltage. There is a PWRGD
masking time of 100μs after the last VID code is changed internally.
Table 5 lists the soft transient slew rate.
Figure28. Current Limit Circuit
During start-up when the output voltage is below 200 mV, a
secondary current limit is activated. This is necessary because
the voltage swing on CSCOMP cannot extend below ground.
The secondary current-limit circuit clamps the internal COMP
voltage and sets the internal compensation ramp termination
voltage at 1.5 V level. The clamp actually limits voltage drop
across the low side MOSFETs through the current balance
circuitry.
An inherent per phase current limit protects individual phases
in case one or more phases stop functioning because of a faulty
component. This limit is based on the maximum normal-mode
COMP voltage.
Rev. 1 | Page 24 of 41 | www.onsemi.com
ADP3208C
After 9ms in current limit, the ADP3207C will latch off . The
latch-off can be reset by removing and reapplying VCC, or by
recycling the EN pin low and high for a short time.
The latch-off can be reset by removing and reapplying VCC,
or by recycling the EN pin low and high for a short time.
over the entire load range. The upper and lower MOSFETs run
synchronously and in complementary phase. See Figure 27 for
the typical waveforms of the ADP3208C running in CCM with
a 7 A load current.
OUTPUT VOLTAGE 20mV/DIV
4
PWRGD 2V/DIV
INDUCTOR CURRENT 5A/DIV
2
OUTPUT 0.5V/DIV
3
SWITCH NODE 5V/DIV
LOW-SIDE GATE DRIVE 5V/DIV
2ms/DIV
06374-030
1
400ns/DIV
Figure 27. Single-Phase Waveforms in CCM
LATCHED
CURRENT LIMIT
OFF
APPLIED
Figure 26. Current Overload
CHANGING VID ON THE FLY
The ADP3208C is designed to track dynamically changing VID
code. As a consequence, the CPU VCC voltage can change without
the need to reset the controller or the CPU. This concept is commonly referred to as VID on-the-fly (VID OTF) transient. A
VID OTF can occur with either light or heavy load conditions. The
processor alerts the controller that a VID change is occurring
by changing the VID inputs in LSB incremental steps from the
start code to the finish code. The change can be either upwards
or downwards steps.
When a VID input changes, the ADP3208C detects the change
but ignores new code for a minimum of 400 ns. This delay is
required to prevent the device from reacting to digital signal
skew while the 7-bit VID input code is in transition. Additionally,
the VID change triggers a PWRGD masking timer to prevent
a PWRGD failure. Each VID change resets and retriggers the
internal PWRGD masking timer.
As listed in Table 6, during a VID transient, the ADP3208C
forces PWM mode regardless of the state of the system input
signals. For example, this means that if the chip is configured as
a dual-phase controller but is running in single-phase mode due
to a light load condition, a current overload event causes the
chip to switch to dual-phase mode to share the excessive load
until the delayed current limit latch-off cycle terminates.
In user-set single-phase mode, the ADP3208C usually runs in
RPM mode. When a VID transition occurs, however, the
ADP3208C switches to dual-phase PWM mode.
Light Load RPM DCM Operation
In single-phase normal mode, DPRSLP is pulled low and the
APD3208 operates in continuous conduction mode (CCM)
If DPRSLP is pulled high, the ADP3208C operates in RPM
mode. If the load condition is light, the chip enters
discontinuous conduction mode (DCM). Figure 28 shows a
typical single-phase buck with one upper FET, one lower FET,
an output inductor, an output capacitor, and a load resistor.
Figure 29 shows the path of the inductor current with the upper
FET on and the lower FET off. In Figure 30 the high-side FET is
off and the low-side FET is on. In CCM, if one FET is on, its
complementary FET must be off; however, in DCM, both highand low-side FETs are off and no current flows into the inductor
(see Figure 31). Figure 32 shows the inductor current and switch
node voltage in DCM.
In DCM with a light load, the ADP3208C monitors the switch
node voltage to determine when to turn off the low-side FET.
Figure 33 shows a typical waveform in DCM with a 1 A load
current. Between t1 and t2, the inductor current ramps down. The
current flows through the source drain of the low-side FET and
creates a voltage drop across the FET with a slightly negative
switch node. As the inductor current ramps down to 0 A, the
switch voltage approaches 0 V, as seen just before t2. When the
switch voltage is approximately −6 mV, the low-side FET is
turned off.
Figure 32 shows a small, dampened ringing at t2. This is caused by
the LC created from capacitance on the switch node, including
the CDS of the FETs and the output inductor. This ringing is normal.
The ADP3208C automatically goes into DCM with a light load.
Figure 33 shows the typical DCM waveform of the ADP3208C.
As the load increases, the ADP3208C enters into CCM. In
DCM, frequency decreases with load current. Figure 34 shows
switching frequency vs. load current for a typical design. In DCM,
switching frequency is a function of the inductor, load current,
input voltage, and output voltage.
Rev. 1 | Page 25 of 41 | www.onsemi.com
ADP3208C
Q1
4
DRVH
INPUT
VOLTAGE
OUTPUT VOLTAGE
20mV/DIV
OUTPUT
VOLTAGE
SWITCH L
NODE
Q2
LOAD
SWITCH NODE 5V/DIV
06374-031
C
DRVL
2
Figure 28. Buck Topology
INDUCTOR CURRENT
5A/DIV
3
ON
L
06374-036
1
LOW-SIDE GATE DRIVE 5V/DIV
LOAD
2µs/DIV
06374-032
C
OFF
Figure 33. Single-Phase Waveforms in DCM with 1 A Load Current
Figure 29. Buck Topology Inductor Current During t0 and t1
400
350
OFF
300
LOAD
06374-033
C
ON
FREQUENCY (kHz)
L
Figure 30. Buck Topology Inductor Current During t1 and t2
9V INPUT
250
19V INPUT
200
150
100
OFF
LOAD
06374-034
0
C
OFF
06374-037
50
L
0
2
4
6
8
10
12
14
LOAD CURRENT (A)
Figure 34. Single-Phase CCM/DCM Frequency vs. Load Current
Figure 31. Buck Topology Inductor Current During t2 and t3
OUTPUT CROWBAR
To prevent the CPU and other external components from
damage due to overvoltage, the ADP3208C turns off the
DRVH1 and DRVH2 outputs and turns on the DRVL1 and
DRVL2 outputs when the output voltage exceeds the OVP
threshold (1.7 V typical).
INDUCTOR
CURRENT
t0
t1
t2
t3
06374-035
SWITCH
NODE
VOLTAGE
t4
Figure 32. Inductor Current and Switch Node in DCM
Turning on the low-side MOSFETs forces the output capacitor
to discharge and the current to reverse due to current build up
in the inductors. If the output overvoltage is due to a drainsource short of the high-side MOSFET, turning on the low-side
MOSFET results in a crowbar across the input voltage rail. The
crowbar action blows the fuse of the input rail, breaking the
circuit and thus protecting the microprocessor from
destruction.
When the OVP feature is triggered, the ADP3208C is latched
off. The latch-off function can be reset by removing and
reapplying VCC to the ADP3208C or by briefly pulling the EN
pin low.
Rev. 1 | Page 26 of 41 | www.onsemi.com
ADP3208C
Pulling TTSNS to less than 1 V disables the overvoltage
protection function. In this configuration, VRTT should be tied
to ground.
OUTPUT VOLTAGE
REVERSE VOLTAGE PROTECTION
Very large reverse current in inductors can cause negative VCORE
voltage, which is harmful to the CPU and other output
components. The ADP3208C provides a reverse voltage
protection (RVP) function without additional system cost. The
VCORE voltage is monitored through the CSREF pin. When the
CSREF pin voltage drops to less than −300 mV, the ADP3208C
triggers the RVP function by disabling all PWM outputs and
driving DRVL1 and DRVL2 low, thus turning off all MOSFETs.
The reverse inductor currents can be quickly reset to 0 by
discharging the built-up energy in the inductor into the input
dc voltage source via the forward-biased body diode of the
high-side MOSFETs. The RVP function is terminated when the
CSREF pin voltage returns to greater than −100 mV.
Sometimes the crowbar feature inadvertently causes output
reverse voltage because turning on the low-side MOSFETs
results in a very large reverse inductor current. To prevent
damage to the CPU caused from negative voltage, the
ADP3208C maintains its RVP monitoring function even after
OVP latch-off. During OVP latch-off, if the CSREF pin voltage
drops to less than −300 mV, the low-side MOSFETs is turned
off. DRVL outputs are allowed to turn back on when the CSREF
voltage recovers to greater than −100 mV.
Figure 37 shows a typical Over Voltage Protection test. FB pin is
shorted to ground causing the control to command a large duty
cycle. The output voltage climbs up. When the output voltage
is climbs 200 mV above the DAC voltage, the PWRGD signal
de-asserts. When the output voltage climbs to 1.7V, Over
Voltage Protection is enabled. In Over Voltage Protection, the
phase 1 and phase 2 low side drive turns on the low side power
MOSFETs. The low side MOSFETs pull the output voltage low
through the power inductor. When the output voltage falls
below -300 mV, Reverse Voltage Protection is enabled. In
Reverse Voltage Protection, all power MOSFETs are turned off.
This protects the CPU from seeing a large negative voltage.
PWRGD
PHASE 2
LOW SIDE GATE
PHASE 1
LOW SIDE GATE
Figure 37. Over Voltage Protection and Reverse Voltage Protection
OUTPUT ENABLE AND UVLO
For the ADP3208C to begin switching, the VCC supply voltage
to the controller must be greater than the VCCOK threshold and
the EN pin must be driven high. If the VCC voltage is less than
the VCCUVLO threshold or the EN pin is a logic low, the
ADP3208C shuts off. In shutdown mode, the controller holds
the PWM outputs low, shorts the capacitors of the SS and
PGDELAY pins to ground, and drives the DRVH and DRVL
outputs low.
The user must adhere to proper power-supply sequencing during
startup and shutdown of the ADP3208C. All input pins must be
at ground prior to removing or applying VCC, and all output
pins should be left in high impedance state while VCC is off.
THERMAL THROTTLING CONTROL
The ADP3208C includes a thermal monitoring circuit to detect
whether the temperature of the VR has exceeded a user-defined
thermal throttling threshold. The thermal monitoring circuit
requires an external resistor divider connected between the
VCC pin and GND. The divider consists of an NTC thermistor
and a resistor. To generate a voltage that is proportional to
temperature, the midpoint of the divider is connected to the
TTSNS pin. An internal comparator circuit compares the
TTSNS voltage to half the VCC threshold and outputs a logic
level signal at the VRTT output when the temperature trips the
user-set alarm threshold. The VRTT output is designed to drive
an external transistor that in turn provides the high current,
open-drain VRTT signal required by the IMVP-6+ specification.
The internal VRTT comparator has a hysteresis of approximately
100 mV to prevent high frequency oscillation of VRTT when
the temperature approaches the set alarm point.
CURRENT MONITOR FUNCTION
The ADP3208C has an output current monitor. The IMON pin
sources a current proportional to the inductor current. A
resistor from IMON pin to FBRTN sets the gain. A 0.1 μF is
Rev. 1 | Page 27 of 41 | www.onsemi.com
ADP3208C
added in parallel with RMON to filter the inductor ripple. The
IMON pin is clamped to prevent it from going above 1.15V
Rev. 1 | Page 28 of 41 | www.onsemi.com
ADP3208C
Table 6. VID Codes
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Output
VID6
VID5
VID4
VID3
VID2
VID1
VID0
Output
0
0
0
0
0
0
0
1.5000 V
1
0
0
0
0
0
0
0.7000 V
0
0
0
0
0
0
1
1.4875 V
1
0
0
0
0
0
1
0.6875 V
0
0
0
0
0
1
0
1.4750 V
1
0
0
0
0
1
0
0.6750 V
0
0
0
0
0
1
1
1.4625 V
1
0
0
0
0
1
1
0.6625 V
0
0
0
0
1
0
0
1.4500 V
1
0
0
0
1
0
0
0.6500 V
0
0
0
0
1
0
1
1.4375 V
1
0
0
0
1
0
1
0.6375 V
0
0
0
0
1
1
0
1.4250 V
1
0
0
0
1
1
0
0.6250 V
0
0
0
0
1
1
1
1.4125 V
1
0
0
0
1
1
1
0.6125 V
0
0
0
1
0
0
0
1.4000 V
1
0
0
1
0
0
0
0.6000 V
0
0
0
1
0
0
1
1.3875 V
1
0
0
1
0
0
1
0.5875 V
0
0
0
1
0
1
0
1.3750 V
1
0
0
1
0
1
0
0.5750 V
0
0
0
1
0
1
1
1.3625 V
1
0
0
1
0
1
1
0.5625 V
0
0
0
1
1
0
0
1.3500 V
1
0
0
1
1
0
0
0.5500 V
0
0
0
1
1
0
1
1.3375 V
1
0
0
1
1
0
1
0.5375 V
0
0
0
1
1
1
0
1.3250 V
1
0
0
1
1
1
0
0.5250 V
0
0
0
1
1
1
1
1.3125 V
1
0
0
1
1
1
1
0.5125 V
0
0
1
0
0
0
0
1.3000 V
1
0
1
0
0
0
0
0.5000 V
0
0
1
0
0
0
1
1.2875 V
1
0
1
0
0
0
1
0.4875 V
0
0
1
0
0
1
0
1.2750 V
1
0
1
0
0
1
0
0.4750 V
0
0
1
0
0
1
1
1.2625 V
1
0
1
0
0
1
1
0.4625 V
0
0
1
0
1
0
0
1.2500 V
1
0
1
0
1
0
0
0.4500 V
0
0
1
0
1
0
1
1.2375 V
1
0
1
0
1
0
1
0.4375 V
0
0
1
0
1
1
0
1.2250 V
1
0
1
0
1
1
0
0.4250 V
0
0
1
0
1
1
1
1.2125 V
1
0
1
0
1
1
1
0.4125 V
0
0
1
1
0
0
0
1.2000 V
1
0
1
1
0
0
0
0.4000 V
0
0
1
1
0
0
1
1.1875 V
1
0
1
1
0
0
1
0.3875 V
0
0
1
1
0
1
0
1.1750 V
1
0
1
1
0
1
0
0.3750 V
0
0
1
1
0
1
1
1.1625 V
1
0
1
1
0
1
1
0.3625 V
0
0
1
1
1
0
0
1.1500 V
1
0
1
1
1
0
0
0.3500 V
0
0
1
1
1
0
1
1.1375 V
1
0
1
1
1
0
1
0.3375 V
0
0
1
1
1
1
0
1.1250 V
1
0
1
1
1
1
0
0.3250 V
0
0
1
1
1
1
1
1.1125 V
1
0
1
1
1
1
1
0.3125 V
0
1
0
0
0
0
0
1.1000 V
1
1
0
0
0
0
0
0.3000 V
0
1
0
0
0
0
1
1.0875 V
1
1
0
0
0
0
1
0.2875 V
0
1
0
0
0
1
0
1.0750 V
1
1
0
0
0
1
0
0.2750 V
0
1
0
0
0
1
1
1.0625 V
1
1
0
0
0
1
1
0.2625 V
0
1
0
0
1
0
0
1.0500 V
1
1
0
0
1
0
0
0.2500 V
0
1
0
0
1
0
1
1.0375 V
1
1
0
0
1
0
1
0.2375 V
0
1
0
0
1
1
0
1.0250 V
1
1
0
0
1
1
0
0.2250 V
0
1
0
0
1
1
1
1.0125 V
1
1
0
0
1
1
1
0.2125 V
0
1
0
1
0
0
0
1.0000 V
1
1
0
1
0
0
0
0.2000 V
0
1
0
1
0
0
1
0.9875 V
1
1
0
1
0
0
1
0.1875 V
0
1
0
1
0
1
0
0.9750 V
1
1
0
1
0
1
0
0.1750 V
0
1
0
1
0
1
1
0.9625 V
1
1
0
1
0
1
1
0.1625 V
0
1
0
1
1
0
0
0.9500 V
1
1
0
1
1
0
0
0.1500 V
0
1
0
1
1
0
1
0.9375 V
1
1
0
1
1
0
1
0.1375 V
0
1
0
1
1
1
0
0.9250 V
1
1
0
1
1
1
0
0.1250 V
0
1
0
1
1
1
1
0.9125 V
1
1
0
1
1
1
1
0.1125 V
0
1
1
0
0
0
0
0.9000 V
1
1
1
0
0
0
0
0.1000 V
0
1
1
0
0
0
1
0.8875 V
1
1
1
0
0
0
1
0.0875 V
0
1
1
0
0
1
0
0.8750 V
1
1
1
0
0
1
0
0.0750 V
0
1
1
0
0
1
1
0.8625 V
1
1
1
0
0
1
1
0.0625 V
0
1
1
0
1
0
0
0.8500 V
1
1
1
0
1
0
0
0.0500 V
0
1
1
0
1
0
1
0.8375 V
1
1
1
0
1
0
1
0.0375 V
0
1
1
0
1
1
0
0.8250 V
1
1
1
0
1
1
0
0.0250 V
0
1
1
0
1
1
1
0.8125 V
1
1
1
0
1
1
1
0.0125 V
0
1
1
1
0
0
0
0.8000 V
1
1
1
1
0
0
0
0.0000 V
0
1
1
1
0
0
1
0.7875 V
1
1
1
1
0
0
1
0.0000 V
0
1
1
1
0
1
0
0.7750 V
1
1
1
1
0
1
0
0.0000 V
0
1
1
1
0
1
1
0.7625 V
1
1
1
1
0
1
1
0.0000 V
0
1
1
1
1
0
0
0.7500 V
1
1
1
1
1
0
0
0.0000 V
0
1
1
1
1
0
1
0.7375 V
1
1
1
1
1
0
1
0.0000 V
0
1
1
1
1
1
0
0.7250 V
1
1
1
1
1
1
0
0.0000 V
0
1
1
1
1
1
1
0.7125 V
1
1
1
1
1
1
1
0.0000 V
Rev. 1 | Page 29 of 41 | www.onsemi.com
ADP3208C
Figure 35. Typical Dual-Phase Application Circuit
Rev. 1 | Page 30 of 41 | www.onsemi.com
ADP3208C
APPLICATION INFORMATION
The design parameters for a typical IMVP-6+-compliant CPU
core VR application are as follows:
For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.
•
•
•
•
•
•
•
SETTING THE SWITCHING FREQUENCY FOR
RPM OPERATION OF PHASE 1
•
•
•
•
•
Maximum input voltage (VINMAX) = 19 V
Minimum input voltage (VINMIN) = 8 V
Output voltage by VID setting (VVID) = 1.4375 V
Maximum output current (IO) = 40 A
Droop resistance (RO) = 2.1 mΩ
Nominal output voltage at 40 A load (VOFL) = 1.3535 V
Static output voltage drop from no load to full load
(ΔV) = VONL − VOFL = 1.4375 V − 1.3535 V = 84 mV
Maximum output current step (ΔIO) = 27.9 A
Number of phases (n) = 2
Switching frequency per phase (fSW) = 300 kHz
Duty cycle at maximum input voltage (DMAX) = 0.18 V
Duty cycle at minimum input voltage (DMIN) = 0.076 V
During the RPM mode operation of Phase 1, the ADP3208C
runs in pseudo constant frequency, given that the load current
is high enough for continuous current mode. While in
discontinuous current mode, the switching frequency is
reduced with the load current in a linear manner. When
considering power conversion efficiency in light load, lower
switching frequency is usually preferred for RPM mode.
However, the VCORE ripple specification in the IMVP-6 sets the
limitation for lowest switching frequency. Therefore, depending
on the inductor and output capacitors, the switching frequency
in RPM mode can be equal, larger, or smaller than its
counterpart in PWM mode.
SETTING THE CLOCK FREQUENCY FOR PWM
In PWM operation, the ADP3208C uses a fixed-frequency control
architecture. The frequency is set by an external timing resistor
(RT). The clock frequency and the number of phases determine
the switching frequency per phase, which relates directly to the
switching losses and the sizes of the inductors and input and
output capacitors. For a dual-phase design, a clock frequency
of 600 kHz sets the switching frequency to 300 kHz per phase.
This selection represents the trade-off between the switching
losses and the minimum sizes of the output filter components.
To achieve a 600 kHz oscillator frequency at a VID voltage of
1.2 V, RT must be 187 kΩ. Alternatively, the value for RT can
be calculated by using the following equation:
RT =
VVID + 1V
− 16kΩ
2 × n × f SW × 9 pF
(1)
where:
9 pF and 16 kΩ are internal IC component values.
VVID is the VID voltage in volts.
n is the number of phases.
fSW is the switching frequency in hertz for each phase.
When VARFREQ pin is connected to ground, the switching
frequency does not change with VID. The value for RT can be
calculated by using the following equation.
1V
− 16kΩ
n × f SW × 9 pF
RRPM =
A × (1 − D ) × VVID
2 × RT
− 0.5 kΩ (24)
× R
VVID + 1.0 V
RR × C R × f SW
where:
AR is the internal ramp amplifier gain.
CR is the internal ramp capacitor value.
RR is an external resistor on the RAMPADJ pin to set the
internal ramp magnitude.
Because RR = 280 kΩ, the following resistance sets up 300 kHz
switching frequency in RPM operation.
RRPM =
2 × 280 kΩ
0.5 × (1 − 0.061) × 1.150
×
− 500 Ω = 202 kΩ
1.150 V + 1.0 V 462 k Ω × 5 pF × 300 kHz
INDUCTOR SELECTION
For good initial accuracy and frequency stability, it is
recommended to use a 1% resistor.
RT =
A resistor from RPM to GND sets the pseudo constant
frequency as following:
(2)
The choice of inductance determines the ripple current of the
inductor. Less inductance results in more ripple current, which
increases the output ripple voltage and the conduction losses in the
MOSFETs. However, this allows the use of smaller-size inductors,
and for a specified peak-to-peak transient deviation, it allows
less total output capacitance. Conversely, a higher inductance
results in lower ripple current and reduced conduction losses,
but it requires larger-size inductors and more output capacitance
for the same peak-to-peak transient deviation. For a multiphase
converter, the practical value for peak-to-peak inductor ripple
current is less than 50% of the maximum dc current of that
inductor. Equation 3 shows the relationship between the
inductance, oscillator frequency, and peak-to-peak ripple
Rev. 1 | Page 31 of 41 | www.onsemi.com
ADP3208C
current. Equation 4 can be used to determine the minimum
inductance based on a given output ripple voltage.
V × (1 − D MIN )
I R = VID
f SW × L
L≥
Output Droop Resistance
(3)
VVID × RO × (1 − (n × DMIN ))
f SW × VRIPPLE
(4)
Solving Equation 4 for a 16 mV peak-to-peak output ripple
voltage yields
L≥
1.4375 V × 2.1 mΩ × (1 − 2 × 0.076)
= 533 nH
300 kHz × 16 mV
If the resultant ripple voltage is less than the initially selected
value, the inductor can be changed to a smaller value until the
ripple value is met. This iteration allows optimal transient
response and minimum output decoupling.
The design requires that the regulator output voltage measured
at the CPU pins decreases when the output current increases. The
specified voltage drop corresponds to the droop resistance (RO).
The output current is measured by summing the currents of the
resistors monitoring the voltage across each inductor and by
passing the signal through a low-pass filter. The summing is
implemented by the CS amplifier that is configured with resistor
RPH(x) (summer) and resistors RCS and CCS (filters). The output
resistance of the regulator is set by the following equations:
RO =
C CS =
RCS
R PH ( x )
× R SENSE
(5)
L
RSENSE × RCS
(6)
where RSENSE is the DCR of the output inductors.
The smallest possible inductor should be used to minimize the
number of output capacitors. Choosing a 490 nH inductor is a
good choice for a starting point, and it provides a calculated
ripple current of 9.0 A. The inductor should not saturate at the
peak current of 24.5 A, and it should be able to handle the sum
of the power dissipation caused by the winding’s average current
(20 A) plus the ac core loss. In this example, 330 nH is used.
Either RCS or RPH(x) can be chosen for added flexibility. Due to
the current drive ability of the CSCOMP pin, the RCS resistance
should be greater than 100 kΩ. For example, initially select RCS
to be equal to 200 kΩ, and then use Equation 6 to solve for CCS:
Another important factor in the inductor design is the DCR,
which is used for measuring the phase currents. Too large of a
DCR causes excessive power losses, whereas too small of a value
leads to increased measurement error. For this example, an
inductor with a DCR of 0.8 mΩ is used.
If CCS is not a standard capacitance, RCS can be tuned. For
example, if the optimal CCS capacitance is 1.5 nF, adjust RCS to
280 kΩ. For best accuracy, CCS should be a 5% NPO capacitor.
In this example, a 220 kΩ is used for RCS to achieve optimal results.
Selecting a Standard Inductor
After the inductance and DCR are known, select a standard
inductor that best meets the overall design goals. It is also
important to specify the inductance and DCR tolerance to
maintain the accuracy of the system. Using 20% tolerance for
the inductance and 15% for the DCR at room temperature are
reasonable values that most manufacturers can meet.
Power Inductor Manufacturers
The following companies provide surface-mount power inductors
optimized for high power applications upon request:
•
•
•
•
Vishay Dale Electronics, Inc.
(605) 665-9301
Panasonic
(714) 373-7334
Sumida Electric Company
(847) 545-6700
NEC Tokin Corporation
(510) 324-4110
CCS =
330 nH
0.8 mΩ × 200 kΩ
= 2.1 nF
Next, solve for RPH(x) by rearranging Equation 5 as follows:
R PH ( x ) ≥
0.8 mΩ
2.1 mΩ
× 220 kΩ = 83.8 kΩ
The standard 1% resistor for RPH(x) is 86.6 kΩ.
Inductor DCR Temperature Correction
If the DCR of the inductor is used as a sense element and
copper wire is the source of the DCR, the temperature changes
associated with the inductor’s winding must be compensated
for. Fortunately, copper has a well-known temperature
coefficient (TC) of 0.39%/°C.
If RCS is designed to have an opposite but equal percentage of
change in resistance, it cancels the temperature variation of the
inductor’s DCR. Due to the nonlinear nature of NTC thermistors,
series resistors RCS1 and RCS2 (see Figure 36) are needed to linearize
the NTC and produce the desired temperature coefficient tracking.
Rev. 1 | Page 32 of 41 | www.onsemi.com
ADP3208C
6.
Calculate values for RCS1 and RCS2 by using the following
equations:
R CS1 = RCS × k × rCS1
(9)
RCS2 = RCS × ((1 − k ) + (k × rCS2 ))
Figure 36. Temperature-Compensation Circuit Values
The following procedure and expressions yield values for
RCS1, RCS2, and RTH (the thermistor value at 25°C) for a given
RCS value.
1.
2.
3.
4.
Select an NTC to be used based on its type and value.
Because the value needed is not yet determined, start with
a thermistor with a value close to RCS and an NTC with an
initial tolerance of better than 5%.
Find the relative resistance value of the NTC at two
temperatures. The appropriate temperatures will depend
on the type of NTC, but 50°C and 90°C have been shown
to work well for most types of NTCs. The resistance values
are called A (A is RTH(50°C)/RTH(25°C)) and B (B is
RTH(90°C)/RTH(25°C)). Note that the relative value of the
NTC is always 1 at 25°C.
Find the relative value of RCS required for each of the two
temperatures. The relative value of RCS is based on the
percentage of change needed, which is initially assumed to
be 0.39%/°C in this example.
The relative values are called r1 (r1 is 1/(1+ TC × (T1 − 25)))
and r2 (r2 is 1/(1 + TC × (T2 − 25))), where TC is 0.0039,
T1 is 50°C, and T2 is 90°C.
Compute the relative values for rCS1, rCS2, and rTH by using
the following equations:
rCS2 =
rCS1 =
rTH =
5.
( A − B) × r1 × r2 − A × (1 − B) × r2 + B × (1 − A) × r1
(7)
A × (1 − B) × r1 − B × (1 − A) × r2 − ( A − B)
(1 − A)
1
A
−
1 − rCS2 r1 − rCS2
1
1
1
−
1 − rCS2 rCS1
RTH ( ACTUAL )
RTH (CALCULATED )
COUT Selection
The required output decoupling for processors and platforms is
typically recommended by Intel. For systems containing both
bulk and ceramic capacitors, however, the following guidelines
can be a helpful supplement.
Select the number of ceramics and determine the total ceramic
capacitance (CZ). This is based on the number and type of
capacitors used. Keep in mind that the best location to place
ceramic capacitors is inside the socket; however, the physical
limit is twenty 0805-size pieces inside the socket. Additional
ceramic capacitors can be placed along the outer edge of the
socket. A combined ceramic capacitor value of 200 μF to 300 μF
is recommended and is usually composed of multiple 10 μF or
22 μF capacitors.
Ensure that the total amount of bulk capacitance (CX) is within
its limits. The upper limit is dependent on the VID on-the-fly
output voltage stepping (voltage step, VV, in time, tV, with error
of VERR); the lower limit is based on meeting the critical capacitance
for load release at a given maximum load step, ΔIO. The current
version of the IMVP-6+ specification allows a maximum VCORE
overshoot (VOSMAX) of 10 mV more than the VID voltage for a
step-off load current.
C X ( MIN )
Calculate RTH = rTH × RCS, and then select a thermistor of
the closest value available. In addition, compute a scaling
factor k based on the ratio of the actual thermistor value
used relative to the computed one:
k=
For example, if a thermistor value of 100 kΩ is selected in Step 1,
an available 0603-size thermistor with a value close to RCS is the
Vishay NTHS0603N04 NTC thermistor, which has resistance
values of A = 0.3359 and B = 0.0771. Using the equations in
Step 4, rCS1 is 0.359, rCS2 is 0.729, and rTH is 1.094. Solving for rTH
yields 241 kΩ, so a thermistor of 220 kΩ would be a reasonable
selection, making k equal to 0.913. Finally, RCS1 and RCS2 are found
to be 72.1 kΩ and 166 kΩ. Choosing the closest 1% resistor for
RCS2 yields 165 kΩ. To correct for this approximation, 73.3 kΩ
is used for RCS1.
(8)
⎛
⎜
⎜
L × ΔI O
≥⎜
⎛
VOSMAX
⎜
⎜ n × ⎜⎜ RO + ΔI
O
⎝
⎝
C X ( MAX ) ≤
⎞
⎟ × VVID
⎟
⎠
⎞
⎟
⎟
−CZ ⎟
⎟
⎟
⎠
⎛
⎛ V
n × k × RO
VV
L
⎜
×
×
1 + ⎜⎜ t v VID ×
⎜
2
2
n × k × RO VVID ⎜
L
⎝ VV
⎝
⎛V
where k = −ln ⎜⎜ ERR
⎝ VV
Rev. 1 | Page 33 of 41 | www.onsemi.com
⎞
⎟
⎟
⎠
(10)
2
⎞
⎞
⎟
⎟ − 1⎟ − C Z
⎟
⎟
⎠
⎠
(11)
ADP3208C
To meet the conditions of these expressions and the transient
response, the ESR of the bulk capacitor bank (RX) should be less
than two times the droop resistance, RO. If the CX(MIN) is greater
than CX(MAX), the system does not meet the VID on-the-fly
and/or the deeper sleep exit specifications and may require less
inductance or more phases. In addition, the switching frequency
may have to be increased to maintain the output ripple.
For example, if 30 pieces of 10 μF, 0805-size MLC capacitors
(CZ = 300 μF) are used, the fastest VID voltage change is when
the device exits deeper sleep, during which the VCORE change is
220 mV in 22 μs with a setting error of 10 mV. If k = 3.1, solving
for the bulk capacitance yields
C X ( MIN )
⎛
⎞
⎜
⎟
⎜
⎟
330 nH × 27.9 A
≥⎜
− 300 μF ⎟ = 1.0 mF
⎛
⎜
⎟
10 mV ⎞
⎟ × 1.4375 V
⎜ 2 × ⎜⎜ 2.1 mΩ+
⎟
⎟
⎜
⎟
27.9 A ⎠
⎝
⎝
⎠
C X ( MAX ) ≤
330 nH × 220 mV
2 × 3.1 × (2.1 mΩ) 2 × 1.4375 V
2
×
2
⎛
⎞
⎛ 22 μs × 1.4375 V × 2 × 3.1 × 2.1 mΩ ⎞
⎜
⎟
⎜
⎟
+
1
−
1
⎜
⎟ − 300 μF
⎜
⎟
220 mV × 490 nH
⎜
⎟
⎝
⎠
⎝
⎠
= 21 mF
Using six 330 μF Panasonic SP capacitors with a typical ESR of
7 mΩ each yields CX = 1.98 mF and RX = 1.2 mΩ.
Ensure that the ESL of the bulk capacitors (LX) is low enough to
limit the high frequency ringing during a load change. This is
tested using
LX ≤ CZ × RO2 × Q2
(12)
L X ≤ 300 μF × (2.1 mΩ )2 × 2 = 2 nH
where:
Q is limited to the square root of 2 to ensure a critically damped
system.
LX is about 150 pH for the six SP capacitors, which is low
enough to avoid ringing during a load change. If the LX of the
chosen bulk capacitor bank is too large, the number of ceramic
capacitors may need to be increased to prevent excessive
ringing.
For this multimode control technique, an all ceramic capacitor
design can be used if the conditions of Equations 10, 11, and 12
are satisfied.
Power MOSFETs
For typical 20 A per phase applications, the N-channel power
MOSFETs are selected for two high-side switches and two or
three low-side switches per phase. The main selection
parameters for the power MOSFETs are VGS(TH), QG, CISS, CRSS,
and RDS(ON). Because the voltage of the gate driver is 5 V, logiclevel threshold MOSFETs must be used.
The maximum output current, IO, determines the RDS(ON)
requirement for the low-side (synchronous) MOSFETs. In the
ADP3208C, currents are balanced between phases; the current
in each low-side MOSFET is the output current divided by the
total number of MOSFETs (nSF). With conduction losses being
dominant, the following expression shows the total power that
is dissipated in each synchronous MOSFET in terms of the
ripple current per phase (IR) and the average total output
current (IO):
PSF
⎡⎛ I
= (1 − D) × ⎢⎜⎜ O
⎢⎣⎝ nSF
2
⎞
1 ⎛ n× I R
⎟ + ×⎜
⎟ 12 ⎜ n
⎠
⎝ SF
⎞
⎟
⎟
⎠
2
⎤
⎥ × R DS( SF )
⎥⎦
(13)
where:
D is the duty cycle and is approximately the output voltage
divided by the input voltage.
IR is the inductor peak-to-peak ripple current and is
approximately
(1 − D ) × VOUT
IR =
L × f SW
Knowing the maximum output current and the maximum
allowed power dissipation, the user can calculate the required
RDS(ON) for the MOSFET. For 8-lead SOIC or 8-lead SOICcompatible MOSFETs, the junction-to-ambient (PCB) thermal
impedance is 50°C/W. In the worst case, the PCB temperature is
70°C to 80°C during heavy load operation of the notebook, and
a safe limit for PSF is about 0.8 W to 1.0 W at 120°C junction temperature. Therefore, for this example (40 A maximum), the RDS(SF)
per MOSFET is less than 8.5 mΩ for two pieces of low-side
MOSFETs. This RDS(SF) is also at a junction temperature of about
120°C; therefore, the RDS(SF) per MOSFET should be less than
6 mΩ at room temperature, or 8.5 mΩ at high temperature.
Another important factor for the synchronous MOSFET is the
input capacitance and feedback capacitance. The ratio of the
feedback to input must be small (less than 10% is recommended)
to prevent accidentally turning on the synchronous MOSFETs
when the switch node goes high.
The high-side (main) MOSFET must be able to handle two
main power dissipation components: conduction losses and
switching losses. Switching loss is related to the time for the
main MOSFET to turn on and off and to the current and
voltage that are being switched. Basing the switching speed
on the rise and fall times of the gate driver impedance and
MOSFET input capacitance, the following expression provides
an approximate value for the switching loss per main MOSFET:
Rev. 1 | Page 34 of 41 | www.onsemi.com
ADP3208C
PS( MF ) = 2 × f SW ×
VDC × I O
n
× RG × MF × C ISS
n MF
n
where:
nMF is the total number of main MOSFETs.
RG is the total gate resistance.
CISS is the input capacitance of the main MOSFET.
The most effective way to reduce switching loss is to use lower
gate capacitance devices.
The conduction loss of the main MOSFET is given by the
following equation:
⎡⎛ I
PC ( MF ) = D × ⎢⎜⎜ O
⎢⎣⎝ n MF
2
⎞
1 ⎛ n× I R
⎟ + ×⎜
⎟ 12 ⎜ n
⎠
⎝ MF
⎞
⎟
⎟
⎠
2
⎤
⎥ × R DS( MF )
⎥⎦
(15)
where RDS(MF) is the on resistance of the MOSFET.
Typically, a user wants the highest speed (low CISS) device
for a main MOSFET, but such a device usually has higher on
resistance. Therefore, the user must select a device that meets
the total power dissipation (about 0.8 W to 1.0 W for an 8-lead
SOIC) when combining the switching and conduction losses.
For example, an IRF7821 device can be selected as the main
MOSFET (four in total; that is, nMF = 4), with approximately
CISS = 1010 pF (maximum) and RDS(MF) = 18 mΩ (maximum at
TJ = 120°C), and an IR7832 device can be selected as the
synchronous MOSFET (four in total; that is, nSF = 4), with
RDS(SF) = 6.7 mΩ (maximum at TJ = 120°C). Solving for the
power dissipation per MOSFET at IO = 40 A and IR = 9.0 A
yields 630 mW for each synchronous MOSFET and 590 mW
for each main MOSFET. A third synchronous MOSFET is an
option to further increase the conversion efficiency and reduce
thermal stress.
Finally, consider the power dissipation in the driver for each
phase. This is best described in terms of the QG for the
MOSFETs and is given by the following equation:
PDRV
(17)
(14)
⎡f
⎤
= ⎢ SW × (n MF × Q GMF + n SF × Q GSF ) + I CC ⎥ × VCC
2
×
n
⎣
⎦
RR =
AR × L
3 × AD × RDS × C R
RR =
0.5 × 360 nH
= 462 kΩ
3 × 5 × 5.2 mΩ × 5 pF
where:
AR is the internal ramp amplifier gain.
AD is the current balancing amplifier gain.
RDS is the total low-side MOSFET ON-resistance,
CR is the internal ramp capacitor value.
Another consideration in the selection of RR is the size of the
internal ramp voltage (see Equation 18). For stability and noise
immunity, keep the ramp size larger than 0.5 V. Taking this into
consideration, the value of RR in this example is selected as 280 kΩ.
The internal ramp voltage magnitude can be calculated as follows:
VR =
AR × (1 − D ) × VVID
RR × C R × f SW
(18)
VR =
0.5 × (1 − 0.061) × 1.150 V
= 0.83 V
462 kΩ × 5 pF × 280 kHz
The size of the internal ramp can be increased or decreased. If it
is increased, stability and transient response improves but
thermal balance degrades. Conversely, if the ramp size is
decreased, thermal balance improves but stability and transient
response degrade. In the denominator of Equation 17, the factor
of 3 sets the minimum ramp size that produces an optimal
combination of good stability, transient response, and thermal
balance.
COMP Pin Ramp
(16)
where QGMF is the total gate charge for each main MOSFET, and
QGSF is the total gate charge for each synchronous MOSFET.
The previous equation also shows the standby dissipation
(ICC times the VCC) of the driver.
Ramp Resistor Selection
The ramp resistor (RR) is used to set the size of the internal PWM
ramp. The value of this resistor is chosen to provide the best
combination of thermal balance, stability, and transient response.
Use the following expression to determine a starting value:
In addition to the internal ramp, there is a ramp signal on the
COMP pin due to the droop voltage and output voltage ramps.
This ramp amplitude adds to the internal ramp to produce the
following overall ramp signal at the PWM input:
VRT =
VR
⎛
2 × (1 − n × D )
⎜1 −
⎜ n× f ×C × R
X
SW
O
⎝
⎞
⎟
⎟
⎠
where CX is the total bulk capacitance, and RO is the droop
resistance of the regulator.
For this example, the overall ramp signal is 1.85 V.
Rev. 1 | Page 35 of 41 | www.onsemi.com
(19)
ADP3208C
Current Limit Setpoint
To select the current-limit setpoint, we need to find the resistor
value for RLIM. The current-limit threshold for the ADP3208C is
set when the current in RLIM is equal to the internal reference
current of 20 μA. The current in RLIM is equal to the inductor
current times RO. RLIM can be found using the following
equation:
RLIM =
I LIM × RO
20μA
RMON =
1.15V × RLIM
10 × RO × I FS
(28)
where:
RMON is the current monitor resistor. RMON is connected from
IMON pin to FBRTN.
RLIM is the current limit resistor.
RO is the output load line resistance.
IFS is the output current when the voltage on IMON is at full
scale.
In this example, if choosing 55 A for ILIM, RLIM is 5.775 kΩ,
which is close to a standard 1% resistance of 5.76 kΩ.
Feedback Loop Compensation Design
The per-phase current limit described earlier has its limit
determined by the following:
VCOMP ( MAX ) − VR − VBIAS
AD × RDS( MAX )
+
IR
2
(26)
For the ADP3208C, the maximum COMP voltage (VCOMP(MAX))
is 3.3 V, the COMP pin bias voltage (VBIAS) is 1.0 V, and the
current balancing amplifier gain (AD) is 5. Using a VR of 0.55 V,
and a RDS(MAX) of 3.8 mΩ (low-side on-resistance at 150°C)
results in a per-phase limit of 85 A. Although this number
seems high, this current level can only be reached with a
absolute short at the output and the current-limit latch-off
function shutting down the regulator before overheating occurs.
This limit can be adjusted by changing the ramp voltage VR.
However, users should not set the per-phase limit lower than
the average per-phase current (ILIM/n).
There is also a per-phase initial duty-cycle limit at maximum
input voltage:
D LIM = D MIN ×
The IMON pin current is equal to the RLIMtimes a fixed gain of
10. RMON can be found using the following equation:
(25)
where:
RLIM is the current limit resistor. RLIM is connected from the
ILIM pin to ground.
RO is the output load line resistance.
ILIM is the current limit set point. This is the peak inductor
current that will trip current limit.
I PHLIM ≅
to filter the inductor current ripple and high frequency load
transients. Since the IMON pin is connected directly to the
CPU, it is clamped to prevent it from going above 1.15V.
VCOMP ( MAX ) − V BIAS
Optimized compensation of the ADP3208C allows the best
possible response of the regulator’s output to a load change. The
basis for determining the optimum compensation is to make
the regulator and output decoupling appear as an output
impedance that is entirely resistive over the widest possible
frequency range, including dc, and that is equal to the droop
resistance (RO). With the resistive output impedance, the output
voltage droops in proportion with the load current at any load
current slew rate, ensuring the optimal position and allowing
the minimization of the output decoupling.
With the multimode feedback structure of the ADP3208C, it is
necessary to set the feedback compensation so that the
converter’s output impedance works in parallel with the output
decoupling. In addition, it is necessary to compensate for the
several poles and zeros created by the output inductor and
decoupling capacitors (output filter).
A Type III compensator on the voltage feedback is adequate
for proper compensation of the output filter. Figure 37 shows the
Type III amplifier used in the ADP3208C. Figure 38 shows the
locations of the two poles and two zeros created by this amplifier.
(27)
VR
For this example, the duty-cycle limit at maximum input
voltage is found to be 0.25 when D is 0.061.
Output Current monitor
The ADP3208C has output current monitor. The IMON pin
sources a current proportional to the total inductor current. A
resistor, RMON, from IMON to FBRTN sets the gain of the
output current monitor. A 0.1 μF is placed in parallel with RMON
Rev. 1 | Page 36 of 41 | www.onsemi.com
ADP3208C
VOLTAGE ERROR
AMPLIFIER
COMP
ADP3208C
FB
CB
TD =
C X × C Z × RO2
C X × (R O − R ' ) + C Z × R O
(27)
(28)
where:
R' is the PCB resistance from the bulk capacitors to the ceramics
and is approximately 0.4 mΩ (assuming an 8-layer motherboard).
RDS is the total low-side MOSFET for on resistance per phase.
AD is 5.
VRT is 1.25 V.
LX is 150 pH for the six Panasonic SP capacitors.
OUTPUT
VOLTAGE
CFB
CA
RA
⎛
A × RDS ⎞
⎟
VRT × ⎜⎜ L − D
2 × f SW ⎟⎠
⎝
TC =
VVID × RE
REFERENCE
VOLTAGE
RFB
Figure 37. Voltage Error Amplifier
GAIN
The compensation values can be calculated as follows:
–20dB/DEC
CA =
n × RO × TA
RE × RB
(29)
RA =
TC
CA
(30)
CB =
TB
RB
(31)
C FB =
TD
RA
(32)
0dB
fP1
fZ2
fZ1
fP2
FREQUENCY
06374-043
–20dB/DEC
Figure 38. Poles and Zeros of Voltage Error Amplifier
The following equations give the locations of the poles and
zeros shown in Figure 38:
f Z1 =
1
2π × C A × R A
(20)
f Z2 =
1
2π × C FB × R FB
(21)
f P1
1
=
2π(C A + C B ) × R FB
(22)
CA + CB
2π × R A × C B × C A
(23)
f P2 =
The expressions that follow compute the time constants for
the poles and zeros in the system and are intended to yield an
optimal starting point for the design; some adjustments may be
necessary to account for PCB and component parasitic effects
(see the Tuning Procedure for ADP3208C section):
R E = n × R O + A D × R DS +
R L × V RT
VVID
+
TB = (R X + R'− RO )× C X
In continuous inductor-current mode, the source current of the
high-side MOSFET is approximately a square wave with a duty
ratio equal to n × VOUT/VIN and an amplitude that is one-nth of
the maximum output current. To prevent large voltage
transients, use a low ESR input capacitor sized for the
maximum rms current. The maximum rms capacitor current
occurs at the lowest input voltage and is given by
I CRMS = D × I O ×
1
−1
n× D
I CRMS = 0.18 × 40 A ×
n × C X × R O × VVID
L X RO − R'
×
RO
RX
CIN Selection and Input Current
DI/DT Reduction
(24)
2 × L × (1 − (n × D)) × V RT
TA = C X × (RO − R' ) +
The standard values for these components are subject to the
tuning procedure described in the Tuning Procedure for
ADP3208C section.
1
− 1 = 9.6 A
2 × 0.18
where IO is the output current.
(25)
(26)
In a typical notebook system, the battery rail decoupling is
achieved by using MLC capacitors or a mixture of MLC
capacitors and bulk capacitors. In this example, the input
Rev. 1 | Page 37 of 41 | www.onsemi.com
(33)
ADP3208C
capacitor bank is formed by eight pieces of 10 μF, 25 V MLC
capacitors, with a ripple current rating of about 1.5 A each.
Selecting Thermal Monitor Components
To monitor the temperature of a single-point hot spot, set
RTTSET1 equal to the NTC thermistor’s resistance at the alarm
temperature. For example, if the alarm temperature for VRTT is
100°C and a Vishey thermistor (NTHS-0603N011003J) with a
resistance of 100 kΩ at 25°C, or 6.8 kΩ at 100°C, is used, the
user can set RTTSET1 equal to 6.8 kΩ (the RTH1 at 100°C).
The number of hot spots monitored is not limited. The alarm
temperature of each hot spot can be individually set by using
different values for RTTSET1, RTTSET2, … RTTSETn.
TUNING PROCEDURE FOR ADP3208C
Set Up and Test the Circuit
1.
2.
3.
4.
Build a circuit based on the compensation values
computed from the design spreadsheet.
Connect a dc load to the circuit.
Turn on the ADP3208C and verify that it operates
properly.
Check for jitter with no load and full load conditions.
Set the DC Load Line
1.
2.
Figure 39. Single-Point Thermal Monitoring
R CS2(NEW) = RCS2(OLD) ×
To monitor the temperature of multiple-point hot spots, use the
configuration shown in Figure 40. If any of the monitored hot
spots reaches the alarm temperature, the VRTT signal is
asserted. The following calculation sets the alarm temperature:
VFD
VREF
=
× RTH1AlarmTemperature
V
1 / 2 − FD
VREF
3.
4.
1/ 2 +
RTTSET1
(34)
5.
Because the forward current is very small, the forward drop
voltage is very low, that is, less than 100 mV. Assuming the same
conditions used for the single-point thermal monitoring
example—that is, an alarm temperature of 100°C and use of an
NTHS-0603N011003J Vishay thermistor—solving Equation 42
gives a RTTSET of 7.37 kΩ, and the closest standard resistor is
7.32 kΩ (1%).
6.
7.
V NL − V FLCOLD
V NL − V FLHOT
(35)
Repeat Step 2 until no adjustment of RCS2 is needed.
Compare the output voltage with no load to that with a full
load using 5 A steps. Compute the load line slope for each
change and then find the average to determine the overall
load line slope (ROMEAS).
If the difference between ROMEAS and RO is more than 0.05 mΩ,
use the following equation to adjust the RPH values:
R PH ( NEW ) = R PH (OLD ) ×
where VFD is the forward drop voltage of the parallel diode.
R OMEAS
RO
(36)
Repeat Steps 4 and 5 until no adjustment of RPH is needed.
Once this is achieved, do not change RPH, RCS1, RCS2, or RTH
for the rest of the procedure.
Measure the output ripple with no load and with a full load
with scope, making sure both are within the specifications.
Set the AC Load Line
1.
2.
3.
4.
Figure 40. Multiple-Point Thermal Monitoring
Measure the output voltage with no load (VNL) and verify
that this voltage is within the specified tolerance range.
Measure the output voltage with a full load when the
device is cold (VFLCOLD). Allow the board to run for ~10
minutes with a full load and then measure the output when
the device is hot (VFLHOT). If the difference between the two
measured voltages is more than a few millivolts, adjust RCS2
using Equation 35.
Remove the dc load from the circuit and connect a
dynamic load.
Connect the scope to the output voltage and set it to dc
coupling mode with a time scale of 100 μs/div.
Set the dynamic load for a transient step of about 40 A at
1 kHz with 50% duty cycle.
Measure the output waveform (note that use of a dc offset
on the scope may be necessary to see the waveform). Try to
use a vertical scale of 100 mV/div or finer.
Rev. 1 | Page 38 of 41 | www.onsemi.com
ADP3208C
5.
The resulting waveform will be similar to that shown in
Figure 41. Use the horizontal cursors to measure VACDRP and
VDCDRP, as shown in Figure 41. Do not measure the undershoot or overshoot that occurs immediately after the step.
VDROOP
VTRAN1
VTRAN2
06374-047
VACDRP
VDCDRP
Figure 42. Transient Setting Waveform, Load Step
06374-046
2.
Figure 41. AC Load Line Waveform
6.
If the difference between VACDRP and VDCDRP is more than a
couple of millivolts, use Equation 46 to adjust CCS. It may
be necessary to try several parallel values to obtain an
adequate one because there are limited standard capacitor
values available (it is a good idea to have locations for two
capacitors in the layout for this reason).
C CS ( NEW ) = C CS (OLD ) ×
7.
8.
9.
V ACDRP
VDCDRP
(37)
Repeat Steps 5 and 6 until no adjustment of CCS is needed.
Once this is achieved, do not change CCS for the rest of the
procedure.
Set the dynamic load step to its maximum step size (but do
not use a step size that is larger than needed) and verify
that the output waveform is square, meaning VACDRP and
VDCDRP are equal.
Ensure that the load step slew rate and the power-up slew
rate are set to ~150 A/μs to 250 A/μs (for example, a load
step of 50 A should take 200 ns to 300 ns) with no
overshoot. Some dynamic loads have an excessive
overshoot at power-up if a minimum current is incorrectly
set (this is an issue if a VTT tool is in use).
3.
If both overshoots are larger than desired, try the following
adjustments in the order shown.
a. Increase the resistance of the ramp resistor
(RRAMP) by 25%.
b. For VTRAN1, increase CB or increase the switching
frequency.
c. For VTRAN2, increase RA by 25% and decrease CA by 25%.
If these adjustments do not change the response, it is
because the system is limited by the output decoupling.
Check the output response and the switching nodes each
time a change is made to ensure that the output decoupling
is stable.
For load release (see Figure 43), if VTRANREL is larger than
the value specified by IMVP-6+, a greater percentage of
output capacitance is needed. Either increase the
capacitance directly or decrease the inductor values. (If
inductors are changed, however, it will be necessary to
redesign the circuit using the information from the
spreadsheet and to repeat all tuning guide procedures).
VTRANREL
VDROOP
1.
With the dynamic load set at its maximum step size,
expand the scope time scale to 2 μs/div to 5 μs/div. This
results in a waveform that may have two overshoots and
one minor undershoot before achieving the final desired
value after VDROOP (see Figure 42).
06374-048
Set the Initial Transient
Figure 43. Transient Setting Waveform, Load Release
LAYOUT AND COMPONENT PLACEMENT
The following guidelines are recommended for optimal
performance of a switching regulator in a PC system.
Rev. 1 | Page 39 of 41 | www.onsemi.com
ADP3208C
General Recommendations
1.
2.
3.
4.
5.
6.
7.
For best results, use a PCB of four or more layers. This
should provide the needed versatility for control circuitry
interconnections with optimal placement; power planes for
ground, input, and output; and wide interconnection traces
in the rest of the power delivery current paths. Keep in
mind that each square unit of 1 oz copper trace has a
resistance of ~0.53 mΩ at room temperature.
When high currents must be routed between PCB layers,
vias should be used liberally to create several parallel
current paths so that the resistance and inductance
introduced by these current paths is minimized and the via
current rating is not exceeded.
If critical signal lines (including the output voltage sense
lines of the ADP3208C) must cross through power
circuitry, it is best if a signal ground plane can be
interposed between those signal lines and the traces of the
power circuitry. This serves as a shield to minimize noise
injection into the signals at the expense of increasing signal
ground noise.
An analog ground plane should be used around and under
the ADP3208C for referencing the components associated
with the controller. This plane should be tied to the nearest
ground of the output decoupling capacitor, but should not
be tied to any other power circuitry to prevent power
currents from flowing into the plane.
The components around the ADP3208C should be located
close to the controller with short traces. The most important
traces to keep short and away from other traces are those
to the FB and CSSUM pins. Refer to Figure 36 for more
details on the layout for the CSSUM node.
The output capacitors should be connected as close as
possible to the load (or connector) that receives the power
(for example, a microprocessor core). If the load is distributed,
the capacitors should also be distributed and generally placed
in greater proportion where the load is more dynamic.
Avoid crossing signal lines over the switching power path
loop, as described in the Power Circuitry section.
2.
3.
4.
Signal Circuitry
1.
2.
Power Circuitry
1.
The switching power path on the PCB should be routed to
encompass the shortest possible length to minimize
radiated switching noise energy (that is, EMI) and
conduction losses in the board. Failure to take proper
precautions often results in EMI problems for the entire PC
system as well as noise-related operational problems in the
power-converter control circuitry. The switching power
path is the loop formed by the current path through the
input capacitors and the power MOSFETs, including all
interconnecting PCB traces and planes. The use of short,
wide interconnection traces is especially critical in this
path for two reasons: it minimizes the inductance in the
switching loop, which can cause high energy ringing, and it
accommodates the high current demand with minimal
voltage loss.
When a power-dissipating component (for example, a
power MOSFET) is soldered to a PCB, the liberal use of
vias, both directly on the mounting pad and immediately
surrounding it, is recommended. Two important reasons
for this are improved current rating through the vias and
improved thermal performance from vias extended to the
opposite side of the PCB, where a plane can more readily
transfer heat to the surrounding air. To achieve optimal
thermal dissipation, mirror the pad configurations used to
heat sink the MOSFETs on the opposite side of the PCB. In
addition, improvements in thermal performance can be
obtained using the largest possible pad area.
The output power path should also be routed to encompass
a short distance. The output power path is formed by the
current path through the inductor, the output capacitors,
and the load.
For best EMI containment, a solid power ground plane
should be used as one of the inner layers and extended
under all power components.
3.
The output voltage is sensed and regulated between the FB
and FBRTN pins, and the traces of these pins should be
connected to the signal ground of the load. To avoid
differential mode noise pickup in the sensed signal, the
loop area should be as small as possible. Therefore, the FB
and FBRTN traces should be routed adjacent to each other,
atop the power ground plane, and back to the controller.
The feedback traces from the switch nodes should be
connected as close as possible to the inductor. The CSREF
signal should be Kelvin connected to the center point of
the copper bar, which is the VCORE common node for the
inductors of all the phases.
On the back of the ADP3208C package, there is a metal
pad that can be used to heat sink the device. Therefore,
running vias under the ADP3208C is not recommended
because the metal pad may cause shorting between vias.
Rev. 1 | Page 40 of 41 | www.onsemi.com
ADP3208C
OUTLINE DIMENSION
7.00
BSC SQ
0.60 MAX
37
36
PIN 1
INDICATOR
TOP
VIEW
48
1
5.25
5.10 SQ
4.95
(BOTTOM VIEW)
25
24
12
13
0.25 MIN
5.50
REF
0.80 MAX
0.65 TYP
12° MAX
PIN 1
INDICATOR
EXPOSED
PAD
6.75
BSC SQ
0.50
0.40
0.30
1.00
0.85
0.80
0.30
0.23
0.18
0.60 MAX
0.05 MAX
0.02 NOM
0.50 BSC
SEATING
PLANE
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2
Figure 44. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
7 mm × 7 mm Body, Very Thin Quad
(CP-48-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADP3208CJCPZ-RL1
1
Temperature
Range
-10°C to 100°C
Package Description
48-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
Package
Option
CP-48-1
Package Marking
Line 1: ADP3208C
Line 2: AWLYYWG
Ordering
Quantity
2,500
Z = RoHS Compliant Part.
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any
products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising
out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical”
parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating
parameters, including “Typicals” must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the
rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to
support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or
use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors
harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such
unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action
Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
Literature Distribution Center for ON Semiconductor
P.O. Box 5163, Denver, Colorado 80217 USA
Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada
Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada
Email: [email protected]
N. American Technical Support: 800-282-9855
Toll Free USA/Canada
Europe, Middle East and Africa Technical Support:
Phone: 421 33 790 2910
Japan Customer Focus Center
Phone: 81-3-5773-3850
Rev. 1 | Page 41 of 41 | www.onsemi.com
ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
Similar pages