Qimonda HYS72T256040HP-3S-A 240-pin registered ddr2 sdram module Datasheet

July 2007
HYS72T64000HP–[3S/3.7]–A
HYS72T1280x0HP–[3S/3.7]–A
HYS72T256220HP–[3S/3.7]–A
HYS72T256040HP–[3S/3.7]–A
240-Pin Registered DDR2 SDRAM Modules
DDR2 SDRAM
RDIMM SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.02
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
HYS72T64000HP–[3S/3.7]–A, HYS72T1280x0HP–[3S/3.7]–A, HYS72T256220HP–[3S/3.7]–A, HYS72T256040HP–
[3S/3.7]–A
Revision History: 2007-07, Rev. 1.02
Page
Subjects (major changes since last revision)
All
Adapted internet edition
All
Editorial changes
Previous Revision: 2006-09, Rev. 1.01
All
Qimonda update
Previous Revision: 2006-02, Rev. 1.0
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-08VU-L8WK
2
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 1.8 V 240-Pin Registered DDR2 SDRAM Modules with parity bit product family and
describes its main characteristics.
1.1
Features
• 240-Pin PC2–5300 and PC2–4200 DDR2 SDRAM
memory modules.
• One rank 64M ×72, 128M ×72, and two ranks 128M ×72,
256M ×72, and four rank 256M ×72 module organization
and 64M ×8, 128M ×4 chip organization
• Registered DIMM Parity bit for address and control bus
• 512 MB, 1 GB, and 2 GB module built with 512 Mbit DDR2
SDRAMs in P-TFBGA-60 chipsize packages.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• All speed grades faster than DDR2–400 comply with
DDR2–400 timing specifications.
• Programmable CAS Latencies (3, 4, 5, 6), Burst Length (4
& 8)
•
•
•
•
•
•
•
•
•
•
Auto Refresh (CBR) and Self Refresh
Programmable self refresh rate via EMRS2 setting
Programmable partial array refresh via EMRS2 settings
DCC enabling via EMRS2 setting
All inputs and outputs SSTL_18 compatible
Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
Serial Presence Detect with E2PROM
RDIMM Dimensions (nominal): 30 mm high, 133.35 mm
wide
Based on standard reference card layouts Raw Card “G”,
“H“, “J“, ”N” and “F“
RoHS compliant products1)
TABLE 1
Performance Table
Product Type Speed Code
–3S
–3.7
DRAM Speed Grade
DDR2–667D
DDR2–533C
Module Speed Grade
PC2–5300
PC2–4200
CAS-RCD-RP latencies
5-5-5
4-4-4
tCK
333
266
MHz
266
266
MHz
200
200
MHz
15
15
ns
15
15
ns
45
45
ns
60
60
ns
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
Unit
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.02, 2007-07
03292006-08VU-L8WK
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS72T[64/128/256]xx0HP–[3S/3.7]–A module
family are Registered DIMM (with parity) modules with 30 mm
height based on DDR2 technology.
DIMMs are available as ECC modules in 64M × 72 (512 MB),
128M × 72 (1 GB), 256M x72 (2GB) organization and density,
intended for mounting into 240-Pin connector sockets.
The memory array is designed with 512-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. All control and
address signals are re-driven on the DIMM using register
devices and a PLL for the clock distribution. This reduces
capacitive loading to the system bus, but adds one cycle to
the SDRAM timing. Decoupling capacitors are mounted on
the PCB board. The DIMMs feature serial presence detect
based on a serial E2PROM device using the 2-pin I2C
protocol. The first 128 bytes are programmed with
configuration data and the second 128 bytes are available to
the customer.
TABLE 2
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
HYS72T64000HP–3S–A
512 MB 1Rx8 PC2-5300P-555-12-F0
1 Rank ECC
512 Mbit (×8)
HYS72T128000HP–3S–A
1 GB 1Rx4 PC2-5300P-555-12-H0
1 Rank ECC
512 Mbit (×4)
HYS72T128020HP–3S–A
1 GB 2Rx8 PC2-5300P-555-12-G0
2 Ranks, ECC
512 Mbit (×8)
HYS72T256220HP–3S–A
2 GB 2Rx4 PC2-5300P-555-12-J2
2 Ranks, ECC
512 Mbit (×4)
HYS72T256040HP–3S–A
2 GB 4Rx8 PC2-5300P-555-12-N0
4 Ranks, ECC
512 Mbit (×8)
HYS72T64000HP–3.7–A
512 MB 1Rx8 PC2-4200P-444-12-F0
1 Rank ECC
512 Mbit (×8)
HYS72T128000HP–3.7–A
1 GB 1Rx4 PC2-4200P-444-12-H0
1 Rank ECC
512 Mbit (×4)
HYS72T128020HP–3.7–A
1 GB 2Rx8 PC2-4200P-444-12-G0
2 Ranks, ECC
512 Mbit (×8)
PC2–5300-555
PC2–4200-444
HYS72T256220HP–3.7–A
2 GB 2Rx4 PC2-4200P-444-12-J2
2 Ranks, ECC
512 Mbit (×4)
HYS72T256040HP–3.7–A
2 GB 4Rx8 PC2-5300P-555-12-N0
4 Ranks, ECC
512 Mbit (×8)
1) All Product Type number end with a place code, designating the silicon die revision. Example: HYS72T64000HP–3.7–A, indicating Rev.
“B” dies are used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data
sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–4200R–444–12–R0”, where
4200P means Registered DIMM modules (with Parity Bit) with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address
Strobe (CAS) latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD
Revision 1.2 and produced on the Raw Card “R”
TABLE 3
Address Format Table
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
512 MB
64M ×72
1
ECC
9
14/2/10
F
1 GB
128M ×72
1
ECC
18
14/2/11
H
1 GB
128M ×72
2
ECC
18
14/2/10
G
Rev. 1.02, 2007-07
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
DIMM
Density
Module
Organization
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
2 GB
256M ×72
2
ECC
36
14/2/11
J
2 GB
256M ×72
4
ECC
36
14/2/10
N
TABLE 4
Components on Modules
Product Type1)
DRAM Components1)2)
DRAM Density
DRAM Organisation
HYS72T64000HP
HYB18T512800AF
512 Mbit
64M × 8
HYS72T128000HP
HYB18T512400AF
512 Mbit
128M × 4
HYS72T128020HP
HYB18T512800AF
512 Mbit
64M × 8
HYS72T256220HP
HYB18T512400AF
512 Mbit
128M × 4
HYS72T256040HP
HYB18T512800AF
512 Mbit
64M × 8
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.02, 2007-07
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
2
Pin Configuration
This chapter contains the pin configuration and block diagrams.
2.1
Pin Configuration
The pin configuration of the Registered DDR2 SDRAM DIMM
is listed by function in Table 5 (240 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 6
and Table 7 respectively. The pin numbering is depicted in
Figure 1.
TABLE 5
Pin Configuration of RDIMM
Pin No.
Name
Pin
Type
Buffer
Type
Function
185
CK0
I
SSTL
186
CK0
I
SSTL
Clock Signal CK0, Complementary Clock Signal CK0
The system clock inputs. All address and command lines are sampled
on the cross point of the rising edge of CK and the falling edge of CK.
A Delay Locked Loop (DLL) circuit is driven from the clock inputs and
output timing for read operations is synchronized to the input clock.
52
CKE0
I
SSTL
171
CKE1
I
SSTL
NC
NC
—
Not Connected
Note: 1-Rank module
193
S0
I
SSTL
76
S1
I
SSTL
Chip Select
Enables the associated DDR2 SDRAM command decoder when LOW
and disables the command decoder when HIGH. When the command
decoder is disabled, new commands are ignored but previous
operations continue.
Rank 0 is selected by S0
Rank 1 is selected by S1
The input signals also disable all outputs (except CKE and ODT) of the
register(s) on the DIMM when both inputs are high. When S is HIGH,
all register outputs (except CK, ODT and Chip select) remain in the
previous state.
Note: 2-Ranks module
NC
NC
—
Clock Signals
Clock Enables 1:0
Activates the DDR2 SDRAM CK signal when HIGH and deactivates
the CK signal when LOW. By deactivating the clocks, CKE0 initiates
the Power Down Mode or the Self Refresh Mode.
Note: 2-Ranks module
Control Signals
Rev. 1.02, 2007-07
03292006-08VU-L8WK
Not Connected
Note: 1-Rank module
6
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Type
Buffer
Type
220
S2
I
SSTL
Function
Rank 2 is selected by S2
221
NC
NC
—
S3
I
SSTL
Not Connected
Note: 1-Rank, 2-Ranks module
Rank 3 is selected by S3
192
NC
NC
—
Not Connected
Note: 1-Rank, 2-Ranks module
RAS
I
SSTL
Row Address Strobe (RAS), Column Address Strobe (CAS), Write
Enable (WE)
When sampled at the cross point of the rising edge of CK, and falling
edge of CK, RAS, CAS and WE define the operation to be executed by
the SDRAM.
74
CAS
I
SSTL
73
WE
I
SSTL
18
RESET
I
CMOS
Register Reset
The RESET pin is connected to the RST pin on the register and to the
OE pin on the PLL. When LOW, all register outputs will be driven LOW
and the PLL clocks to the DRAMs and the register(s) will be set to lowlevel. The PLL will remain synchronized with the input clock.
Bank Address Bus 1:0
Selects internal SDRAM memory bank
Address Signals
71
BA0
I
SSTL
190
BA1
I
SSTL
54
BA2
I
SSTL
Bank Address Bus 2
Greater than 512Mb DDR2 SDRAMS
NC
I
SSTL
Not Connected
Less than 1Gb DDR2 SDRAMS
188
A0
I
SSTL
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
70
A10
I
SSTL
Address Bus 12:0, Address Signal 10/AutoPrecharge
During a Bank Activate command cycle, defines the row address when
sampled at the crosspoint of the rising edge of CK and falling edge of
CK. During a Read or Write command cycle, defines the column
address when sampled at the cross point of the rising edge of CK and
falling edge of CK. In addition to the column address, AP is used to
invoke autoprecharge operation at the end of the burst read or write
cycle. If AP is HIGH, autoprecharge is selected and BA[1:0] defines the
bank to be precharged. If AP is LOW, autoprecharge is disabled.
During a Precharge command cycle, AP is used in conjunction with
BA[1:0] to control which bank(s) to precharge. If AP is HIGH, all banks
will be precharged regardless of the state of BA[1:0] inputs. If AP is
LOW, then BA[1:0] are used to define which bank to precharge.
AP
I
SSTL
57
A11
I
SSTL
176
A12
I
SSTL
196
A13
I
SSTL
Address Signal 13
NC
NC
—
Not Connected
Note: Non CA parity modules based on 256 Mbit component
Rev. 1.02, 2007-07
03292006-08VU-L8WK
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Type
Buffer
Type
Function
174
A14
I
SSTL
Address Signal 14
Note: CA Parity module
NC
NC
—
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
A15
I
SSTL
Address Signal 14
Note: CA Parity module
NC
NC
—
Not Connected
Note: Non CA parity module. Less than 1 GBit per DRAM die.
3
DQ0
I/O
SSTL
4
DQ1
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
9
DQ2
I/O
SSTL
10
DQ3
I/O
SSTL
122
DQ4
I/O
SSTL
123
DQ5
I/O
SSTL
128
DQ6
I/O
SSTL
129
DQ7
I/O
SSTL
12
DQ8
I/O
SSTL
13
DQ9
I/O
SSTL
21
DQ10
I/O
SSTL
22
DQ11
I/O
SSTL
131
DQ12
I/O
SSTL
132
DQ13
I/O
SSTL
140
DQ14
I/O
SSTL
141
DQ15
I/O
SSTL
24
DQ16
I/O
SSTL
25
DQ17
I/O
SSTL
30
DQ18
I/O
SSTL
31
DQ19
I/O
SSTL
143
DQ20
I/O
SSTL
144
DQ21
I/O
SSTL
149
DQ22
I/O
SSTL
150
DQ23
I/O
SSTL
33
DQ24
I/O
SSTL
34
DQ25
I/O
SSTL
39
DQ26
I/O
SSTL
40
DQ27
I/O
SSTL
152
DQ28
I/O
SSTL
153
DQ29
I/O
SSTL
158
DQ30
I/O
SSTL
173
Data Signals
Rev. 1.02, 2007-07
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Type
Buffer
Type
Function
159
DQ31
I/O
SSTL
80
DQ32
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
81
DQ33
I/O
SSTL
86
DQ34
I/O
SSTL
87
DQ35
I/O
SSTL
199
DQ36
I/O
SSTL
200
DQ37
I/O
SSTL
205
DQ38
I/O
SSTL
206
DQ39
I/O
SSTL
89
DQ40
I/O
SSTL
90
DQ41
I/O
SSTL
95
DQ42
I/O
SSTL
96
DQ43
I/O
SSTL
208
DQ44
I/O
SSTL
209
DQ45
I/O
SSTL
214
DQ46
I/O
SSTL
215
DQ47
I/O
SSTL
98
DQ48
I/O
SSTL
99
DQ49
I/O
SSTL
107
DQ50
I/O
SSTL
108
DQ51
I/O
SSTL
217
DQ52
I/O
SSTL
218
DQ53
I/O
SSTL
226
DQ54
I/O
SSTL
227
DQ55
I/O
SSTL
110
DQ56
I/O
SSTL
111
DQ57
I/O
SSTL
116
DQ58
I/O
SSTL
117
DQ59
I/O
SSTL
229
DQ60
I/O
SSTL
230
DQ61
I/O
SSTL
235
DQ62
I/O
SSTL
236
DQ63
I/O
SSTL
42
CB0
I/O
SSTL
43
CB1
I/O
SSTL
48
CB2
I/O
SSTL
49
CB3
I/O
SSTL
Check Bits
Rev. 1.02, 2007-07
03292006-08VU-L8WK
Check Bits 7:0
Check Bit Input / Output pins
Note: NC on Non-ECC module
9
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Type
Buffer
Type
Function
161
CB4
I/O
SSTL
162
CB5
I/O
SSTL
167
CB6
I/O
SSTL
Check Bits 7:0
Check Bit Input / Output pins
Note: NC on Non-ECC module
168
CB7
I/O
SSTL
7
DQS0
I/O
SSTL
6
DQS0
I/O
SSTL
16
DQS1
I/O
SSTL
15
DQS1
I/O
SSTL
28
DQS2
I/O
SSTL
27
DQS2
I/O
SSTL
37
DQS3
I/O
SSTL
36
DQS3
I/O
SSTL
84
DQS4
I/O
SSTL
83
DQS4
I/O
SSTL
93
DQS5
I/O
SSTL
92
DQS5
I/O
SSTL
105
DQS6
I/O
SSTL
104
DQS6
I/O
SSTL
114
DQS7
I/O
SSTL
113
DQS7
I/O
SSTL
46
DQS8
I/O
SSTL
45
DQS8
I/O
SSTL
125
DQS9
I/O
SSTL
126
DQS9
I/O
SSTL
134
DQS10
I/O
SSTL
135
DQS10
I/O
SSTL
146
DQS11
I/O
SSTL
147
DQS11
I/O
SSTL
155
DQS12
I/O
SSTL
156
DQS12
I/O
SSTL
202
DQS13
I/O
SSTL
203
DQS13
I/O
SSTL
211
DQS14
I/O
SSTL
212
DQS14
I/O
SSTL
223
DQS15
I/O
SSTL
224
DQS15
I/O
SSTL
232
DQS16
I/O
SSTL
Data Strobe Bus
Rev. 1.02, 2007-07
03292006-08VU-L8WK
Data Strobes 17:0
The data strobes, associated with one data byte, sourced with data
transfers. In Write mode, the data strobe is sourced by the controller
and is centered in the data window. In Read mode the data strobe is
sourced by the DDR2 SDRAM and is sent at the leading edge of the
data window. DQS signals are complements, and timing is relative to
the crosspoint of respective DQS and DQS. If the module is to be
operated in single ended strobe mode, all DQS signals must be tied on
the system board to VSS through a 20 Ω to 10 kΩ resistor and DDR2
SDRAM mode registers programmed appropriately.
Note: See block diagram for corresponding DQ signals
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Pin No.
Name
Pin
Type
Buffer
Type
Function
233
DQS16
I/O
SSTL
Data Strobes 17:0
164
DQS17
I/O
SSTL
165
DQS17
I/O
SSTL
125
DM0
I
SSTL
134
DM1
I
SSTL
146
DM2
I
SSTL
155
DM3
I
SSTL
202
DM4
I
SSTL
211
DM5
I
SSTL
223
DM6
I
SSTL
232
DM7
I
SSTL
164
DM8
I
SSTL
120
SCL
I
CMOS
Serial Bus Clock
This signal is used to clock data into and out of the SPD EEPROM.
119
SDA
I/O
OD
Serial Bus Data
This is a bidirectional pin used to transfer data into or out of the SPD
EEPROM. A resistor must be connected from SDA to VDDSPD on the
motherboard to act as a pull-up.
239
SA0
I
CMOS
240
SA1
I
CMOS
101
SA2
I
CMOS
Serial Address Select Bus 2:0
These signals are tied at the system planar to either VSS or VDDSPD to
configure the serial SPD EEPROM address range
55
ERR_OUT
O
CMOS
68
PAR_IN
I
CMOS
1
VREF
AI
—
I/O Reference Voltage
Reference voltage for the SSTL-18 inputs.
238
VDDSPD
PWR
—
EEPROM Power Supply
Serial EEPROM positive power supply, wired to a separated power pin
at the connector which supports from 1.7 Volt to 3.6 Volt.
51, 56, 62, 72, 75,
78, 170, 175, 181,
191, 194
VDDQ
PWR
—
I/O Driver Power Supply
Power and ground for the DDR SDRAM
PWR
—
Power Supply
Power and ground for the DDR SDRAM
Data Mask
Data Masks 8:0
The data write masks, associated with one data byte. In Write mode,
DM operates as a byte mask by allowing input data to be written if it is
LOW but blocks the write operation if it is HIGH. In Read mode, DM
lines have no effect.
Note: ×8 based module
EEPROM
Parity
Parity bits
Note: Only for modules with parity bit for address and control bus. Not
connected on non-parity registered modules.
Power Supplies
53, 59, 64, 67, 69, VDD
172, 178, 184, 187,
189, 197
Rev. 1.02, 2007-07
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Pin No.
Name
2, 5, 8, 11, 14, 17, VSS
20, 23, 26, 29, 32,
35, 38, 41, 44, 47,
50, 65, 66, 79, 82,
85, 88, 91, 94, 97,
100, 103, 106, 109,
112, 115, 118, 121,
124, 127, 130, 133,
136, 139, 142, 145,
148, 151, 154, 157,
160, 163, 166, 169,
198, 201, 204, 207,
210, 213, 216, 219,
222, 225, 228, 231,
234, 237
Pin
Type
Buffer
Type
Function
GND
—
Ground Plane
Power and ground for the DDR SDRAM
Other Pins
19, 102, 137, 138,
NC
NC
—
Not connected
Pins not connected on Qimonda RDIMM’s
195
ODT0
I
SSTL
77
ODT1
I
SSTL
On-Die Termination Control 1:0
Asserts on-die termination for DQ, DM, DQS, and DQS signals if
enabled via the DDR2 SDRAM mode register.
Note: 2-Ranks module
NC
NC
—
Note: 1-Rank modules
TABLE 6
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tristate,
and allows multiple devices to share as a wire-OR.
Rev. 1.02, 2007-07
03292006-08VU-L8WK
12
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 7
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NU
Not Usable
NC
Not Connected
Rev. 1.02, 2007-07
03292006-08VU-L8WK
13
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
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0337
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3
Electrical Characteristics
This chapter lists the electrical characteristics.
3.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 8 at any time.
TABLE 8
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Parameter
Rating
Unit
Note
Min.
Max.
Voltage on VDD pin relative to VSS
–1.0
+2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on VDDL pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on any pin relative to VSS
–0.5
+2.3
V
1)
°C
1)2)
Storage Temperature
–55
+100
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 9
DRAM Component Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Operating Temperature
Min.
Max.
0
95
Unit
Note
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
Rev. 1.02, 2007-07
03292006-08VU-L8WK
15
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HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.2
DC Operating Conditions
This chapter contains the DC operating condition tables.
TABLE 10
Operating Conditions
Parameter
Symbol
Values
Unit
Min.
Max.
0
+65
°C
0
+95
°C
Storage Temperature
TOPR
TCASE
TSTG
– 50
+100
°C
Barometric Pressure (operating & storage)
PBar
+69
+105
kPa
Operating Humidity (relative)
HOPR
HSTG
10
90
%
5
95
%
Operating temperature (ambient)
DRAM Case Temperature
Storage Humidity (without condensation)
Note
1)2)3)4)
5)
1)
2)
3)
4)
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%.
5) Up to 3000 m.
TABLE 11
Supply Voltage Levels and DC Operating Conditions
Parameter
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
DC Input Logic High
DC Input Logic Low
Symbol
VDD
VDDQ
VREF
VDDSPD
VIH(DC)
VIL (DC)
IL
Values
Unit
Min.
Typ.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
1)
0.49 × VDDQ
0.5 × VDDQ
0.51 × VDDQ
V
2)
1.7
—
3.6
V
VREF + 0.125
—
– 0.30
—
VDDQ + 0.3
VREF – 0.125
V
V
–5
—
5
µA
In / Output Leakage Current
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ.
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Rev. 1.02, 2007-07
03292006-08VU-L8WK
Note
16
3)
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.3
Timing Characteristics
This chapter describes the AC characteristics tables.
3.3.1
Speed Grades Definitions
Speed Grade Definitions for: DDR2–667D (Table 12), DDR2–533C (Table 13)
TABLE 12
Speed Grade Definition Speed Bins for DDR2–667D
Speed Grade
DDR2–667D
QAG Sort Name
–3S
CAS-RCD-RP latencies
5–5–5
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Notes
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
ns
1)2)3)4)
3.75
8
ns
1)2)3)4)
3
8
ns
1)2)3)4)
45
70000
ns
1)2)3)4)5)
60
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 13
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533C
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
Rev. 1.02, 2007-07
03292006-08VU-L8WK
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
5
8
ns
1)2)3)4)
3.75
8
ns
1)2)3)4)
3.75
8
ns
1)2)3)4)
45
70000
ns
1)2)3)4)5)
60
—
ns
1)2)3)4)
17
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Speed Grade
DDR2–533C
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
Unit
Note
tCK
Parameter
Symbol
Min.
Max.
—
RAS-CAS-Delay
tRCD
tRP
15
—
ns
1)2)3)4)
15
—
ns
1)2)3)4)
Row Precharge Time
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.02, 2007-07
03292006-08VU-L8WK
18
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.3.2
Component AC Timing Parameters
Speed Grade Definitions for: DDR2–667 (Table 14), DDR2–533C (Table 15)
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Notes1)2)3)4)5)6)
7)8)
Min.
Max.
tAC
tCCD
tCH.AVG
tCK.AVG
tCKE
–450
+450
ps
2
—
nCK
0.48
0.52
tCK.AVG
3000
8000
ps
3
—
nCK
12)
tCL.AVG
Auto-Precharge write recovery + precharge time tDAL
Minimum time clocks remain ON after CKE
tDELAY
0.48
0.52
tCK.AVG
10)11)
WR + tnRP
—
nCK
13)14)
tIS + tCK .AVG +
tIH
––
ns
tDH.BASE
DQ and DM input pulse width for each input
tDIPW
DQS output access time from CK / CK
tDQSCK
DQS input high pulse width
tDQSH
DQS input low pulse width
tDQSL
DQS-DQ skew for DQS & associated DQ signals tDQSQ
DQS latching rising transition to associated clock tDQSS
175
––
ps
0.35
—
tCK.AVG
–400
+400
ps
0.35
—
0.35
—
tCK.AVG
tCK.AVG
—
240
ps
16)
– 0.25
+ 0.25
tCK.AVG
17)
tDS.BASE
tDSH
tDSS
tHP
100
––
ps
18)19)20)
17)
DQ output access time from CK / CK
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and low pulse
width)
Average clock low pulse width
asynchronously drops LOW
DQ and DM input hold time
edges
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
tHZ
Address and control input hold time
tIH.BASE
Control & address input pulse width for each input tIPW
Address and control input setup time
tIS.BASE
DQ low impedance time from CK/CK
tLZ.DQ
DQS/DQS low-impedance time from CK / CK
tLZ.DQS
MRS command to ODT update delay
tMOD
Mode register set command cycle time
tMRD
OCD drive mode output delay
tOIT
DQ/DQS output hold time from DQS
tQH
DQ hold skew factor
tQHS
Data-out high-impedance time from CK / CK
Rev. 1.02, 2007-07
03292006-08VU-L8WK
19
9)
10)11)
19)20)15)
9)
0.2
—
0.2
—
tCK.AVG
tCK.AVG
Min(tCH.ABS,
tCL.ABS)
__
ps
21)
—
tAC.MAX
ps
9)22)
275
—
ps
25)23)
0.6
—
tCK.AVG
200
—
ps
24)25)
2 x tAC.MIN
ps
9)22)
tAC.MIN
tAC.MAX
tAC.MAX
ps
9)22)
0
12
ns
35)
2
—
nCK
0
12
ns
35)
tHP – tQHS
—
ps
26)
—
340
ps
27)
17)
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Unit
Notes1)2)3)4)5)6)
7)8)
Average periodic refresh Interval
tREFI
Min.
Max.
—
7.8
µs
28)29)
—
3.9
µs
29)30)
31)
Auto-Refresh to Active/Auto-Refresh command
period
tRFC
105
—
ns
Precharge-All (4 banks) command period
tRP
tRPRE
tRPST
tRTP
tWPRE
tWPST
tWR
tWTR
tXARD
tXARDS
tRP
—
ns
0.9
1.1
32)33)
0.4
0.6
tCK.AVG
tCK.AVG
7.5
—
ns
35)
0.35
—
0.4
0.6
tCK.AVG
tCK.AVG
15
—
ns
35)
7.5
—
ns
35)36)
2
—
nCK
7 – AL
—
nCK
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
nCK
Exit self-refresh to a non-read command
tRFC +10
—
ns
Exit self-refresh to read command
tXSNR
tXSRD
200
—
nCK
Write command to DQS associated clock edges
WL
RL–1
Read preamble
Read postamble
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time
Internal write to read command delay
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
32)34)
35)
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
Rev. 1.02, 2007-07
03292006-08VU-L8WK
20
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
13) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
14) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 3.
16) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
17) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
18) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 3.
19) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
20) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
21) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
22) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
23) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 4.
24) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 4.
25) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
26) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
27) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
28) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
29) 0 °C≤ TCASE ≤ 85 °C
30) 85 °C < TCASE ≤ 95 °C
31) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
32) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 2 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
33) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
34) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
35) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
36) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
FIGURE 2
Method for calculating transitions and endpoint
92+[P9
977[P9
92+[P9
977[P9
W/=
W+=
W535(EHJLQSRLQW
W5367
H
QGSRLQW
92/[P9
977[P9
92/[P9
977[P9
7 7
7 7
W+=W5367
HQGSRLQW 77
W/=W535(
E HJLQSRLQW 7
7
FIGURE 3
Differential input waveform timing - tDS and tDS
'46
'46
W'6
W'+
W'6
W'+
9''4
9,+ DF PL
Q
9,+ GF PL
Q
62%&DC
9,/ GF PD
[
9,/ DF PD
[
966
FIGURE 4
Differential input waveform timing - tlS and tlH
&.
&.
W,6
W,+
W,6
W,+
9''4
9,+DF PLQ
9,+GF PLQ
95() GF 9,/ GF PD[
9,/ DF PD[
966
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Notes1)2)3)4)5)
6)7)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–500
+500
ps
2
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
––
ns
9)
DQ and DM input hold time (differential data
strobe)
tDH(base)
225
––
ps
10)
–25
—
ps
11)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
0.35
—
tCK
–450
+450
ps
0.35
—
tCK
—
300
ps
tDQSS
tDS(base)
– 0.25
+ 0.25
tCK
100
—
ps
11)
–25
—
ps
11)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data tDS1(base)
strobe)
DQS falling edge hold time from CK (write
cycle)
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Data hold skew factor
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tHP
tHZ
tIH(base)
tIPW
23
11)
12)
MIN. (tCL, tCH)
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMOD
tMRD
tOIT
tQH
tQHS
8)18)
—
tAC.MAX
ps
13)
375
—
ps
11)
0.6
—
tCK
250
—
ps
11)
2 × tAC.MIN
ps
14)
tAC.MIN
tAC.MAX
tAC.MAX
ps
14)
0
12
ns
2
—
tCK
0
12
ns
tHP –tQHS
—
—
400
ps
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Unit
Notes1)2)3)4)5)
6)7)
Min.
Max.
tREFI
tREFI
tRFC
—
7.8
µs
14)15)
—
3.9
µs
16)18)
105
—
ns
17)
tRP
tRPRE
tRPST
tRRD
tRP
—
ns
0.9
1.1
14)
0.40
0.60
tCK
tCK
7.5
—
ns
14)18)
Active bank A to Active bank B command
period
tRRD
10
—
ns
16)22)
Internal Read to Precharge command delay
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
0.25
—
0.40
0.60
tCK
tCK
15
—
ns
tWTR
tXARD
7.5
—
ns
20)
2
—
tCK
21)
Exit active power-down mode to Read
command (slow exit, lower power)
tXARDS
6 – AL
—
tCK
21)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
200
—
WR
tWR/tCK
tCK
tCK
Average periodic refresh Interval
Average periodic refresh Interval
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
Write recovery time for write with AutoPrecharge
14)
19)
22)
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
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HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
This chapter contains the ODT AC characteristic tables.
TABLE 16
ODT AC Character. and Operating Conditions for DDR2-667
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Note
Min.
Max.
ODT turn-on delay
2
2
nCK
1)
ODT turn-on
tAC.MAX + 0.7 ns
2 tCK + tAC.MAX + 1 ns
ns
1)2)
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT turn-off delay
2.5
2.5
nCK
1)
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
1)3)
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ns
1)
ODT to Power Down Mode Entry Latency
3
—
nCK
1)
1)
ODT Power Down Exit Latency
8
—
nCK
1) New units, 'tCK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 'tCK.AVG' represents the actual tCK.AVG of the input clock
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, 'tCK' is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 × tCK.AVG+ tEPR.2PER(MIN).
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-667/800, tAOND is 2 clock
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-667/800,if tCK.AVG =
3 ns is assumed, tAOFD= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT
LOW and by counting the actual input clock edge.
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HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 17
ODT AC Character. and Operating Conditions for DDR2-533
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Min.
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MAX + 1 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
tCK
tCK
Note
1)
ns
2)
ns
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from tAOND, which is interpreted differently per speed bin. For DDR2-400/533, tAOND is 10 ns
(= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD. Both are measured from tAOFD, which is interpreted differently per speed bin. For DDR2-400/533, tAOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if tCK = 5 ns.
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
3.4
IDD Specifications and Conditions
This chapter describes the IDD Specifications and Conditions.
• Table 18 “IDD Measurement Conditions” on Page 27
• Table 19 “Definitions for IDD” on Page 28
• Table 20 “IDD Specification for HYS72T[64/128/256]xx0HP-3S-A” on Page 29
• Table 21 “IDD Specification for HYS72T[64/128/256]xx0HP-3.7-A” on Page 30
TABLE 18
IDD Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
IDD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
IDD4R
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;
tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
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6)
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Parameter
Symbol Note
1)2)3)4)5)
Distributed Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5D
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
6)
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 19
4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down
Mode
5) For details and notes see the relevant Qimonda component data sheet
6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 19
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
Inputs are stable at a HIGH or LOW level
FLOATING
Inputs are VREF = VDDQ /2
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
Rev. 1.02, 2007-07
03292006-08VU-L8WK
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 20
HYS72T128020HP–3S–A
HYS72T256220HP–3S–A
HYS72T256040HP–3S–A
1 GB
1 GB
2 GB
2 GB
×72
×72
×72
×72
×72
1 Ranks
1 Ranks
2 Ranks
2 Ranks
4 Ranks
–3S
–3S
–3S
–3S
–3S
1020
1870
1280
1960
1370
mA
2)
1150
2130
1410
2220
1500
mA
2)
430
690
690
780
780
mA
3)
840
1500
1500
2400
2400
mA
3)
750
1320
1320
2040
2040
mA
3)
560
940
940
1280
1280
mA
3)
440
700
700
810
810
mA
3)4)
840
1500
1500
2400
2400
mA
3)5)
1560
2940
1810
3030
1900
mA
2)
1650
3120
1900
3210
1990
mA
2)
1650
3120
1900
3210
1990
mA
2)
440
700
700
810
810
mA
3)6)
45
90
90
180
180
mA
3)6)
HYS72T64000HP–3S–A
Product Type
HYS72T128000HP–3S–A
IDD Specification for HYS72T[64/128/256]xx0HP-3S-A
Organization 512 MB
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
Units
Note1)
2)
1960
3330
2050
mA
1) Module IDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are
2)
3)
4)
5)
6)
1710
3240
defined with the outputs disabled.
The other rank is in IDD2P Precharge Power-Down Current mode
Both ranks are in the same IDDcurrent mode
Fast: MRS(12)=0
Slow: MRS(12)=1
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.02, 2007-07
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Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 21
IDD Specification for HYS72T[64/128/256]xx0HP-3.7-A
HYS72T128000HP–3.7–A
HYS72T128020HP–3.7–A
HYS72T256220HP–3.7–A
HYS72T256040HP–3.7–A
Note1)
1 GB
2 GB
2 GB
×72
×72
×72
×72
×72
1 Ranks
1 Ranks
2 Ranks
2 Ranks
4 Ranks
–3.7
–3.7
–3.7
–3.7
–3.7
920
1670
1120
1740
1370
mA
2)
1010
1850
1210
1920
1500
mA
2)
370
570
570
640
780
mA
3)
690
1220
1220
1940
2400
mA
3)
600
1040
1040
1580
2040
mA
3)
470
790
790
1080
1280
mA
3)
380
590
590
680
810
mA
3)4)
690
1220
1220
1940
2400
mA
3)5)
1140
2120
1350
2190
1900
mA
2)
1190
2210
1390
2280
1990
mA
2)
1500
2840
1710
2910
1990
mA
2)
380
610
610
720
810
mA
3)6)
36
72
72
144
180
mA
3)6)
Organization 512 MB
IDD0
IDD1
IDD2P
IDD2N
IDD2Q
IDD3P_0 (fast)
IDD3P_1 (slow)
IDD3N
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
Units
1 GB
HYS72T64000HP–3.7–A
Product Type
2)
1800
3100
2050
mA
1) Module IDDis calculated on the basis of component IDDand includes currents of Registers and PLL. ODT disabled. IDD1, IDD4R, and IDD7, are
2)
3)
4)
5)
6)
1590
3030
defined with the outputs disabled.
The other rank is in IDD2P Precharge Power-Down Current mode
Both ranks are in the same IDDcurrent mode
Fast: MRS(12)=0
Slow: MRS(12)=1
IDD5D and IDD6 values are for 0°C ≤ TCase ≤ 85°C
Rev. 1.02, 2007-07
03292006-08VU-L8WK
30
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
• Table 22 “HYS72T[64/128/256]xx0HP-3S-A” on Page 31
• Table 23 “HYS72T[64/128/256]xx0HP-3.7-A” on Page 36
TABLE 22
Product Type
HYS72T64000HP–3S–A
HYS72T128000HP–3S–A
HYS72T128020HP–3S–A
HYS72T256220HP–3S–A
HYS72T256040HP–3S–A
HYS72T[64/128/256]xx0HP-3S-A
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0E
0E
0E
0E
0E
4
Number of Column Addresses
0A
0B
0A
0B
0A
5
DIMM Rank and Stacking Information
60
60
61
61
63
6
Data Width
48
48
48
48
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
30
30
30
30
30
10
45
45
45
45
45
11
Error Correction Support (non-ECC, ECC)
06
06
06
06
06
Rev. 1.02, 2007-07
03292006-08VU-L8WK
31
Internet Data Sheet
Product Type
HYS72T64000HP–3S–A
HYS72T128000HP–3S–A
HYS72T128020HP–3S–A
HYS72T256220HP–3S–A
HYS72T256040HP–3S–A
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
08
04
08
04
08
14
Error Checking SDRAM Width
08
04
08
04
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
01
01
01
01
01
21
DIMM Attributes
04
05
05
07
07
22
Component Attributes
03
03
03
03
03
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
24
25
26
27
28
29
30
3D
3D
3D
3D
3D
50
50
50
50
50
50
50
50
50
50
60
60
60
60
60
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
3C
3C
3C
3C
3C
2D
2D
2D
2D
2D
31
Module Density per Rank
80
01
80
01
80
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
20
20
20
20
20
33
34
35
Rev. 1.02, 2007-07
03292006-08VU-L8WK
32
27
27
27
27
27
10
10
10
10
10
17
17
17
17
17
Internet Data Sheet
Product Type
HYS72T64000HP–3S–A
HYS72T128000HP–3S–A
HYS72T128020HP–3S–A
HYS72T256220HP–3S–A
HYS72T256040HP–3S–A
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
36
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
00
40
00
00
00
00
00
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
46
PLL Relock Time
37
38
41
42
43
44
3C
3C
3C
3C
3C
69
69
69
69
69
80
80
80
80
80
18
18
18
18
18
22
22
22
22
22
0F
0F
0F
0F
0F
47
TCASE.MAX Delta / ∆T4R4W Delta
53
53
53
53
53
48
Psi(T-A) DRAM
78
78
78
78
78
49
∆T0 (DT0)
4B
4B
4B
4B
4B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
2E
2E
2E
2E
2E
51
∆T2P (DT2P)
26
26
26
26
26
52
∆T3N (DT3N)
26
26
26
26
26
53
∆T3P.fast (DT3P fast)
2B
2B
2B
2B
2B
54
∆T3P.slow (DT3P slow)
1B
1B
1B
1B
1B
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
4A
4A
4A
4A
4A
56
∆T5B (DT5B)
20
20
20
20
20
57
∆T7 (DT7)
22
22
22
22
22
58
Psi(ca) PLL
C4
C4
C4
C4
C4
59
Psi(ca) REG
8C
8C
8C
8C
8C
Rev. 1.02, 2007-07
03292006-08VU-L8WK
33
Internet Data Sheet
Product Type
HYS72T64000HP–3S–A
HYS72T128000HP–3S–A
HYS72T128020HP–3S–A
HYS72T256220HP–3S–A
HYS72T256040HP–3S–A
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
60
∆TPLL (DTPLL)
68
68
68
68
68
61
∆TREG (DTREG) / Toggle Rate
94
94
94
94
94
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
47
C2
49
C5
4D
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
37
37
37
37
37
74
Product Type, Char 2
32
32
32
32
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
36
31
31
32
32
77
Product Type, Char 5
34
32
32
35
35
78
Product Type, Char 6
30
38
38
36
36
79
Product Type, Char 7
30
30
30
32
30
80
Product Type, Char 8
30
30
32
32
34
81
Product Type, Char 9
48
30
30
30
30
82
Product Type, Char 10
50
48
48
48
48
83
Product Type, Char 11
33
50
50
50
50
Rev. 1.02, 2007-07
03292006-08VU-L8WK
34
Internet Data Sheet
Product Type
HYS72T64000HP–3S–A
HYS72T128000HP–3S–A
HYS72T128020HP–3S–A
HYS72T256220HP–3S–A
HYS72T256040HP–3S–A
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
PC2–
5300P–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
84
Product Type, Char 12
53
33
33
33
33
85
Product Type, Char 13
41
53
53
53
53
86
Product Type, Char 14
20
41
41
41
41
87
Product Type, Char 15
20
20
20
20
20
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
2x
2x
2x
2x
2x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.02, 2007-07
03292006-08VU-L8WK
35
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
TABLE 23
Product Type
HYS72T64000HP–3.7–A
HYS72T128000HP–3.7–A
HYS72T128020HP–3.7–A
HYS72T256220HP–3.7–A
HYS72T256040HP–3.7–A
HYS72T[64/128/256]xx0HP-3.7-A
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0E
0E
0E
0E
0E
4
Number of Column Addresses
0A
0B
0A
0B
0A
5
DIMM Rank and Stacking Information
60
60
61
61
63
6
Data Width
48
48
48
48
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
3D
3D
3D
3D
3D
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
50
50
50
50
50
11
Error Correction Support (non-ECC, ECC)
06
06
06
06
06
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
08
04
08
04
08
14
Error Checking SDRAM Width
08
04
08
04
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
01
01
01
01
01
Rev. 1.02, 2007-07
03292006-08VU-L8WK
36
Internet Data Sheet
Product Type
HYS72T64000HP–3.7–A
HYS72T128000HP–3.7–A
HYS72T128020HP–3.7–A
HYS72T256220HP–3.7–A
HYS72T256040HP–3.7–A
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
21
DIMM Attributes
04
05
05
07
07
22
Component Attributes
03
03
03
03
03
23
3D
3D
3D
3D
3D
50
50
50
50
50
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
2D
2D
31
Module Density per Rank
80
01
80
01
80
32
25
25
25
25
25
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
00
00
00
00
00
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
Rev. 1.02, 2007-07
03292006-08VU-L8WK
37
50
50
50
50
50
60
60
60
60
60
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
3C
3C
3C
3C
3C
37
37
37
37
37
10
10
10
10
10
22
22
22
22
22
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
3C
3C
3C
3C
3C
69
69
69
69
69
80
80
80
80
80
1E
1E
1E
1E
1E
Internet Data Sheet
Product Type
HYS72T64000HP–3.7–A
HYS72T128000HP–3.7–A
HYS72T128020HP–3.7–A
HYS72T256220HP–3.7–A
HYS72T256040HP–3.7–A
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
45
tQHS.MAX [ns]
28
28
28
28
28
46
PLL Relock Time
0F
0F
0F
0F
0F
47
TCASE.MAX Delta / ∆T4R4W Delta
51
51
51
51
51
48
Psi(T-A) DRAM
78
78
78
78
78
49
∆T0 (DT0)
3F
3F
3F
3F
3F
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
22
22
22
22
22
51
∆T2P (DT2P)
1E
1E
1E
1E
1E
52
∆T3N (DT3N)
1E
1E
1E
1E
1E
53
∆T3P.fast (DT3P fast)
24
24
24
24
24
54
∆T3P.slow (DT3P slow)
17
17
17
17
17
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
34
34
34
34
34
56
∆T5B (DT5B)
1E
1E
1E
1E
1E
57
∆T7 (DT7)
20
20
20
20
20
58
Psi(ca) PLL
C4
C4
C4
C4
C4
59
Psi(ca) REG
8C
8C
8C
8C
8C
60
∆TPLL (DTPLL)
61
61
61
61
61
61
∆TREG (DTREG) / Toggle Rate
78
78
78
78
78
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
19
94
1B
97
1F
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
Rev. 1.02, 2007-07
03292006-08VU-L8WK
38
Internet Data Sheet
Product Type
HYS72T64000HP–3.7–A
HYS72T128000HP–3.7–A
HYS72T128020HP–3.7–A
HYS72T256220HP–3.7–A
HYS72T256040HP–3.7–A
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
37
37
37
37
37
74
Product Type, Char 2
32
32
32
32
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
36
31
31
32
32
77
Product Type, Char 5
34
32
32
35
35
78
Product Type, Char 6
30
38
38
36
36
79
Product Type, Char 7
30
30
30
32
30
80
Product Type, Char 8
30
30
32
32
34
81
Product Type, Char 9
48
30
30
30
30
82
Product Type, Char 10
50
48
48
48
48
83
Product Type, Char 11
33
50
50
50
50
84
Product Type, Char 12
2E
33
33
33
33
85
Product Type, Char 13
37
2E
2E
2E
2E
86
Product Type, Char 14
41
37
37
37
37
87
Product Type, Char 15
20
41
41
41
41
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
2x
2x
2x
2x
2x
92
Test Program Revision Code
xx
xx
xx
xx
xx
Rev. 1.02, 2007-07
03292006-08VU-L8WK
39
Internet Data Sheet
Product Type
HYS72T64000HP–3.7–A
HYS72T128000HP–3.7–A
HYS72T128020HP–3.7–A
HYS72T256220HP–3.7–A
HYS72T256040HP–3.7–A
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Organization
512MB
1 GByte
1 GByte
2 GByte
2 GByte
×72
×72
×72
×72
×72
1 Rank
(×8)
1 Rank
(×4)
2 Ranks
(×8)
2 Ranks
(×4)
4 Ranks
(×8)
Label Code
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
PC2–
4200P–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.02, 2007-07
03292006-08VU-L8WK
40
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 5
Package Outline Raw Card F L-DIM-240-11
$ % &
0$
;
[
&
“
$
“ “
%
“
'HWD
LOR
IF RQWD
FWV “ $ % &
%XUUPD
[
DOORZ
H
G
*/'
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.02, 2007-07
03292006-08VU-L8WK
41
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
FIGURE 6
Package Outline Raw Card G L-DIM-240-12
$ % &
0$
;
[
&
“
$
“ “ %
“
'HWD
LORIFR
QWD
FWV “ $ % &
%XUUPD
[
DOORZ
H
G
*/'
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.02, 2007-07
03292006-08VU-L8WK
42
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
FIGURE 7
Package Outline Raw Card H L-DIM-240-13
$ % &
0
$;
[
&
“ $
“
“
%
“ 'HWDLOR IF RQWD FWV
“ $ % &
%XUUP
D[ D OORZH
G */'
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.02, 2007-07
03292006-08VU-L8WK
43
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
FIGURE 8
Package Outline Raw Card J L-DIM-240-20
$ % &
0$
;
[
&
“
$
“
“
%
0,1
“ 'HWD LORIF RQWD FWV “ $ % &
%XUUPD [ DOORZ
H G
*/' Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.02, 2007-07
03292006-08VU-L8WK
44
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
FIGURE 9
¡ $ % &
Package Outline Raw Card N L-DIM-240-44
0
$;
[
&
“ %
$
“ “ 0,1
“ 'HWDLOR IFR QWDFWV
“ $ % &
%XUUP
D[ D OORZ
H G
*/' Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.02, 2007-07
03292006-08VU-L8WK
45
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda’s nomenclature uses simple coding combined with
some propriatory coding. Table 24 provides examples for
module and component product type number as well as the
field number. The detailed field description together with
possible values and coding explanation is listed for modules
in Table 25 and for components in Table 26.
TABLE 24
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64/128
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512/1G 16
0
A
C
–5
TABLE 25
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
Qimonda Module Prefix
HYS
Constant
2
Module Data Width [bit]
64
Non-ECC
72
ECC
3
DRAM Technology
T
DDR2
4
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
64
512 MByte
128
1 GByte
256
2 GByte
512
4 GByte
5
Raw Card Generation
0 .. 9
Look up table
6
Number of Module Ranks
0, 2, 4
1, 2, 4
7
Product Variations
0 .. 9
Look up table
8
Package, Lead-Free Status
A .. Z
Look up table
9
Module Type
D
SO-DIMM
Rev. 1.02, 2007-07
03292006-08VU-L8WK
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
46
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–2.5F
PC2–6400 5–5–5
–2.5
PC2–6400 6–6–6
11
Die Revision
–3
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 26
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Component Prefix
HYB
Constant
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 Mbit
512
512 Mbit
1G
1 Gbit
2G
2 Gbit
40
×4
80
×8
16
×16
0 .. 9
Look up table
5+6
Number of I/Os
7
Product Variations
8
Die Revision
9
10
Package, Lead-Free Status
Speed Grade
Rev. 1.02, 2007-07
03292006-08VU-L8WK
A
First
B
Second
C
FBGA, lead-containing
F
FBGA, lead-free
–25F
DDR2-800 5-5-5
–2.5
DDR2-800 6-6-6
–3
DDR2-667 4-4-4
–3S
DDR2-667 5-5-5
–3.7
DDR2-533 4-4-4
–5
DDR2-400 3-3-3
47
Internet Data Sheet
HYS72T[64/128/256]xx0HP–[3S/3.7]–A
Registered DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
2
2.1
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grades Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Component AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
IDD Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
6
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
15
15
16
17
17
19
25
27
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Rev. 1.02, 2007-07
03292006-08VU-L8WK
48
Internet Data Sheet
Edition 2007-07
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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