CSD16408Q5C www.ti.com SLPS263A – DECEMBER 2009 – REVISED FEBRUARY 2010 DualCool™ N-Ch NexFET™ Power MOSFET FEATURES 1 • • • • • • • • • 2 PRODUCT SUMMARY Ultra Low Qg and Qgd DualCool™ Package Optimized for 2-Sided Cooling Low Thermal Resistance Avalanche Rated Pb Free Terminal Plating RoHS Compliant Halogen Free SON 5-mm x 6-mm Plastic Package VDS Drain to Source Voltage 25 V Qg Gate Charge Total (4.5V) 6.7 nC Qgd Gate Charge Gate to Drain RDS(on) Drain to Source On Resistance VGS(th) Threshold Voltage 1.9 nC VGS = 4.5V 5.4 mΩ VGS = 10V 3.6 mΩ 1.8 V ORDERING INFORMATION Device Package Media CSD16408Q5C SON 5-mm × 6-mm Plastic Package 13-Inch Reel Qty Ship 2500 Tape and Reel APPLICATIONS • • Point-of-Load Synchronous Buck in Networking, Telecom and Computing Systems Optimized for Control FET Applications DESCRIPTION Drain Gate Source Top View D D D D S G G Bottom View D D D S UNIT Drain to Source Voltage 25 V VGS Gate to Source Voltage +16 / –12 V Continuous Drain Current, TC = 25°C 113 A Continuous Drain Current (1) 22 A IDM Pulsed Drain Current, TA = 25°C (2) 141 A PD Power Dissipation (1) 3.1 W TJ, TSTG Operating Junction and Storage Temperature Range –55 to 150 °C EAS Avalanche Energy, single pulse ID = 23A, L = 0.1mH, RG = 25Ω 126 mJ (1) Typical RqJA = 41°C/W on a 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu pad on a 0.06-inch (1.52-mm) thick FR4 PCB. (2) Pulse duration ≤300ms, duty cycle ≤2% S S VALUE VDS ID The NexFET™ power MOSFET has been designed to minimize losses in power conversion applications. D ABSOLUTE MAXIMUM RATINGS TA = 25°C unless otherwise stated S S S RDS(on) vs VGS GATE CHARGE 12 ID = 25A 14 VGS − Gate to Source Voltage − V RDS(on) − On-State Resistance − mΩ 16 12 10 TC = 125°C 8 6 4 2 TC = 25°C 0 ID = 25A VDS = 12.5V 10 8 6 4 2 0 0 2 4 6 8 VGS − Gate to Source Voltage − V 10 12 G006 0 5 10 Qg − Gate Charge − nC 15 20 G003 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. DualCool, NexFET are trademarks of Texas Instruments. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright © 2009–2010, Texas Instruments Incorporated CSD16408Q5C SLPS263A – DECEMBER 2009 – REVISED FEBRUARY 2010 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ELECTRICAL CHARACTERISTICS TA = 25°C unless otherwise stated PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Static Characteristics BVDSS Drain to Source Voltage VGS = 0V, ID = 250mA IDSS Drain to Source Leakage VGS = 0V, VDS = 20V IGSS Gate to Source Leakage VDS = 0V, VGS = +16/-12V VGS(th) Gate to Source Threshold Voltage VDS = VGS, ID = 250mA RDS(on) Drain to Source On Resistance gfs Transconductance 25 V 1 mA 100 nA 1.8 2.1 V VGS = 4.5V, ID = 25A 5.4 6.8 mΩ VGS = 10V, ID = 25A 3.6 4.5 mΩ VDS = 15V, ID = 25A 60 1.4 S Dynamic Characteristics CISS Input Capacitance COSS Output Capacitance 990 1300 pF 760 1000 CRSS pF Reverse Transfer Capacitance 75 100 pF Rg Series Gate Resistance 0.8 1.6 Ω Qg Gate Charge Total (4.5V) 6.7 8.9 nC Qgd Gate Charge – Gate to Drain Qgs Gate Charge – Gate to Source Qg(th) Gate Charge at Vth QOSS Output Charge td(on) Turn On Delay Time tr Rise Time td(off) Turn Off Delay Time tf Fall Time VGS = 0V, VDS = 12.5V , f = 1MHz VDS = 12.5V, ID = 25A VDS = 13V, VGS = 0V VDS = 12.5V, VGS = 4.5V, ID = 25A, RG = 2Ω 1.9 nC 3.1 nC 1.8 nC 15.7 nC 11.3 ns 25 ns 11 ns 10.8 ns Diode Characteristics VSD Diode Forward Voltage IS = 25A, VGS = 0V 0.8 Qrr Reverse Recovery Charge VDD = 13V, IF = 25A, di/dt = 300A/ms 17 1 nC V trr Reverse Recovery Time VDD = 13V, IF = 25A, di/dt = 300A/ms 21 ns THERMAL CHARACTERISTICS TA = 25°C unless otherwise stated MAX UNIT RqJC Thermal Resistance Junction to Case (Top Source) (1) PARAMETER 3.1 °C/W RqJC Thermal Resistance Junction to Case (Bottom Drain) (1) 1.9 °C/W RqJA Thermal Resistance Junction to Ambient (1) 51 °C/W (1) (2) 2 MIN (2) 2 TYP 2 RqJC is determined with the device mounted on a 1-inch (6.45-cm ), 2-oz. (0.071-mm thick) Cu pad on a 1.5-inch × 1.5-inch (3.81-cm × 3.81-cm), 0.06-inch (1.52-mm) thick FR4 PCB. RqJC is specified by design, whereas RqJA is determined by the user’s board design. Device mounted on FR4 material with 1-inch2 (6.45-cm2), 2-oz. (0.071-mm thick) Cu. Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated CSD16408Q5C www.ti.com SLPS263A – DECEMBER 2009 – REVISED FEBRUARY 2010 GATE GATE Source N-Chan 5x6 QFN TTA MIN Rev3 N-Chan 5x6 QFN TTA MAX Rev3 Max RqJA = 51ºC/W when mounted on 1 inch2 (6.45 cm2) of 2-oz. (0.071-mm thick) Cu. Source Max RqJA = 125ºC/W when mounted on minimum pad area of 2-oz. (0.071-mm thick) Cu. DRAIN DRAIN M0137-02 M0137-01 break break break break TYPICAL MOSFET CHARACTERISTICS TA = 25°C unless otherwise stated ZθJA − Normalized Thermal Impedance 10 1 0.5 0.3 0.1 Duty Cycle = t1/t2 0.1 0.05 P 0.02 0.01 t1 0.01 t2 o Typical RqJA = 100 C/W (min Cu) TJ = P x ZqJA x RqJA Single Pulse 0.001 0.001 0.01 0.1 1 10 100 t P − Pulse Duration − s 1k G012 Figure 1. Transient Thermal Impedance Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3 CSD16408Q5C SLPS263A – DECEMBER 2009 – REVISED FEBRUARY 2010 www.ti.com TYPICAL MOSFET CHARACTERISTICS (continued) TA = 25°C unless otherwise stated break 60 IDS − Drain to Source Current − A IDS − Drain to Source Current − A 60 50 VGS = 3.5V VGS = 10V 40 VGS = 4.5V 30 VGS = 3V VGS = 4V 20 10 0 0.0 0.5 1.0 1.5 2.0 2.5 VDS − Drain to Source Voltage − V VDS = 5V 50 TC = 125°C 40 30 TC = 25°C 20 10 TC = −55°C 0 1.5 3.0 3.5 4.0 G002 3.0 ID = 25A VDS = 12.5V f = 1MHz VGS = 0V 2.5 C − Capacitance − nF 10 8 6 4 2 2.0 COSS = CDS + CGD CISS = CGD + CGS 1.5 1.0 CRSS = CGD 0.5 0 0.0 0 5 10 15 Qg − Gate Charge − nC 20 0 5 10 15 20 VDS − Drain to Source Voltage − V G003 Figure 4. Gate Charge 25 G004 Figure 5. Capacitance 2.25 16 RDS(on) − On-State Resistance − mΩ VGS(th) − Threshold Voltage − V 3.0 Figure 3. Transfer Characteristics 12 ID = 250µA 2.00 1.75 1.50 1.25 1.00 0.75 0.50 0.25 0.00 −75 ID = 25A 14 12 10 TC = 125°C 8 6 4 2 TC = 25°C 0 −25 25 75 125 TC − Case Temperature − °C Figure 6. Threshold Voltage vs. Temperature 4 2.5 VGS − Gate to Source Voltage − V G001 Figure 2. Saturation Characteristics VGS − Gate to Source Voltage − V 2.0 Submit Documentation Feedback 175 G005 0 2 4 6 8 VGS − Gate to Source Voltage − V 10 12 G006 Figure 7. On-State Resistance vs. Gate to Source Voltage Copyright © 2009–2010, Texas Instruments Incorporated CSD16408Q5C www.ti.com SLPS263A – DECEMBER 2009 – REVISED FEBRUARY 2010 TYPICAL MOSFET CHARACTERISTICS (continued) TA = 25°C unless otherwise stated 100 ID = 25A VGS = 10V 1.6 ISD − Source to Drain Current − A Normalized On-State Resistance 1.8 1.4 1.2 1.0 0.8 0.6 0.4 −75 10 1 TC = 125°C 0.1 0.01 TC = 25°C 0.001 0.0001 −25 25 75 125 175 TC − Case Temperature − °C 0.0 0.4 0.6 0.8 VSD − Source to Drain Voltage − V G007 Figure 8. Normalized On-State Resistance vs. Temperature 1.0 G008 Figure 9. Typical Diode Forward Voltage 1k I(AV) − Peak Avalanche Current − A 1k IDS − Drain to Source Current − A 0.2 100 1ms 10 10ms 1 100ms Area Limited by RDS(on) 1s 0.1 Single Pulse o Typical RqJA = 100 C/W (min Cu) 0.01 0.01 0.1 DC 1 10 100 10 TC = 125°C 1 0.001 100 VDS - Drain to Source Voltage - V TC = 25°C 0.01 0.1 1 10 t(AV) − Time in Avalanche − ms G009 Figure 10. Maximum Safe Operating Area 100 G010 Figure 11. Single Pulse Unclamped Inductive Switching IDS − Drain to Source Current − A 120 100 80 60 40 20 0 −50 −25 0 25 50 75 100 125 150 175 TC − Case Temperature − °C G011 Figure 12. Maximum Drain Current vs. Temperature Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 5 CSD16408Q5C SLPS263A – DECEMBER 2009 – REVISED FEBRUARY 2010 www.ti.com MECHANICAL DATA Q5C Package Dimensions E1 K L E2 8 8 7 7 6 4 4 5 5 e 3 6 3 Pin 9 D2 D1 E 2 N 1 Exposed Heat Slug 1 c1 q 2 N1 L b M1 M Top View Bottom View Side View TM DualCool Pinout c E1 A q Pin# Label 1, 2, 3, 9 Source 4 Gate 5, 6, 7, 8 Drain Front View M0162-01 DIM MILLIMETERS MAX MIN MAX A 0.950 1.050 0.037 0.039 b 0.360 0.460 0.014 0.018 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 D1 4.900 5.100 0.193 0.201 D2 4.320 4.520 0.170 0.178 E 4.900 5.100 0.193 0.201 E1 5.900 6.100 0.232 0.240 E2 3.920 4.12 0.154 e 6 INCHES MIN 1.27 TYP 0.162 0.050 K 0.760 – 0.030 – L 0.510 0.710 0.020 0.028 q – – – – M 3.260 3.460 0.128 0.136 M1 0.520 0.720 0.020 0.028 N 2.720 2.920 0.107 0.115 N1 1.227 1.427 0.048 0.056 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated CSD16408Q5C www.ti.com SLPS263A – DECEMBER 2009 – REVISED FEBRUARY 2010 Recommended PCB Pattern DIM MILLIMETERS INCHES MIN MAX MIN MAX F1 6.205 6.305 0.244 0.248 F2 4.46 4.56 0.176 0.18 F3 4.46 4.56 0.176 0.18 F4 0.65 0.7 0.026 0.028 F5 0.62 0.67 0.024 0.026 F6 0.63 0.68 0.025 0.027 F7 0.7 0.8 0.028 0.031 F8 0.65 0.7 0.026 0.028 F9 0.62 0.67 0.024 0.026 F1 F7 F3 8 1 F2 F11 F5 F9 5 4 F6 F8 F4 F10 M0139-01 F10 4.9 5 0.193 0.197 F11 4.46 4.56 0.176 0.18 For recommended circuit layout for PCB designs, see application note Reducing Ringing Through PCB Layout Techniques (SLPA005). K0 4.00 ±0.10 (See Note 1) 0.30 ±0.05 2.00 ±0.05 +0.10 –0.00 12.00 ±0.30 Ø 1.50 1.75 ±0.10 Q5 Tape and Reel Information 5.50 ±0.05 B0 R 0.30 MAX A0 8.00 ±0.10 Ø 1.50 MIN A0 = 6.50 ±0.10 B0 = 5.30 ±0.10 K0 = 1.40 ±0.10 R 0.30 TYP M0138-01 Notes: 1. 10-sprocket hole-pitch cumulative tolerance ±0.2 2. Camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. Material: black static-dissipative polystyrene 4. All dimensions are in mm, unless otherwise specified. 5. A0 and B0 measured on a plane 0.3mm above the bottom of the pocket 6. MSL1 260°C (IR and convection) PbF reflow compatible Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 7 CSD16408Q5C SLPS263A – DECEMBER 2009 – REVISED FEBRUARY 2010 www.ti.com Package Marking Information Location 8 1st Line CSD = Fixed Characters NNNNN = Product Code C = DualCool Package 5 5 8 4 4 1 C SDNNNNNC 2nd Line (Date Code) Y = Last 2 digits of the Year WW = 2-digit Work Week C = Country of Origin > Philippines = P YWWCLLLL > Taiwan = T > China = C 1 3rd Line LLLLL = Last 5 digits of the Wafer Lot # Pin 1 Identifier M0163-01 REVISION HISTORY Changes from Original (December 2009) to Revision A • 8 Page Changed the labels on the Bottom View pinout image ......................................................................................................... 1 Submit Documentation Feedback Copyright © 2009–2010, Texas Instruments Incorporated PACKAGE OPTION ADDENDUM www.ti.com 13-Apr-2010 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing CSD16408Q5C ACTIVE SON DQU Pins Package Eco Plan (2) Qty 8 2500 Pb-Free (RoHS Exempt) Lead/Ball Finish Call TI MSL Peak Temp (3) Level-1-260C-UNLIM (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined. Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes. Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight in homogeneous material) (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. 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