Qimonda HYS64T128020HU-3S-A 240-pin unbuffered ddr2 sdram module Datasheet

May 2007
HYS64T32x00HU–[3/3S/3.7/5]–A
HYS[64/72]T64x00HU–[3/3S/3.7/5]–A
HYS[64/72]T128x20HU–[3/3S/3.7/5]–A
240-Pin Unbuffered DDR2 SDRAM Modules
DDR2 SDRAM
RoHS Compliant
Internet Data Sheet
Rev. 1.41
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
HYS64T32x00HU–[3/3S/3.7/5]–A, HYS[64/72]T64x00HU–[3/3S/3.7/5]–A, HYS[64/72]T128x20HU–[3/3S/3.7/5]–A
Revision History: 2007-01, Rev. 1.41
Page
Subjects (major changes since last revision)
All
Adapted internet edition
42, 43
Table 30 Footnote 4 updated.
Previous Revision: 2007-01, Rev. 1.40
All
Added Products HYS64T[32/64/128]9x0HU–[3S/3.7]–A
Previous Revision: 2006-09, Rev. 1.32
All
Qimonda update
Previous Revision: 2006-03, Rev. 1.31
43, 44, 45, 46
Editorial changes
29, 34, 37
Updated AC Timing Parameter table DQS DQ skew value is the max. value
48
Added 50 ohm data
Previous Revision: 2005-08, Rev. 1.3
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-07
03292006-EZUJ-JY4S
2
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
1
Overview
This chapter gives an overview of the 240-Pin Unbuffered DDR2 SDRAM Modules product family and describes its main
characteristics.
1.1
Features
• 240-Pin PC2-5300, PC2-4200 and PC2-3200 DDR2
SDRAM memory modules for use as main memory when
installed in systems such as mobile personal computers.
• 32M × 64, 64M × 64, 64M × 72, 128M × 64, 128M × 72
module organization, and 32M × 16, 64M × 8 chip
organization
• 256 MByte, 512 MByte and 1 GByte modules built with
512-Mbit DDR2 SDRAMs in P-TFBGA-60 and P-TFBGA84 chipsize packages
• All Speed grades faster than DDR2-400 comply with
DDR2-400 timing specifications.
• Standard Double-Data-Rate-Two Synchronous DRAMs
(DDR2 SDRAM) with a single + 1.8 V (± 0.1 V) power
supply
• Programmable CAS Latencies (3, 4 and 5), Burst Length
(8 & 4) and Burst Type
• Auto Refresh (CBR) and Self Refresh
• All inputs and outputs SSTL_1.8 compatible
• Off-Chip Driver Impedance Adjustment (OCD) and On-Die
Termination (ODT)
• Serial Presence Detect with E2PROM
• Dimensions (nominal): 30 mm high, 133.35 mm wide
• Based on standard reference layouts Raw Card “A”,
“B”“C“,”D”,”E”,”F” and “G“
• RoHS compliant products1)
TABLE 1
Performance table for –3(S)
Product Type Speed Code
–3
–3S
Unit
Speed Grade
PC2–5300 4–4–4
PC2–5300 5–5–5
—
333
333
MHz
333
266
MHz
200
200
MHz
12
15
ns
12
15
ns
45
45
ns
57
60
ns
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
1) RoHS Compliant Product: Restriction of the use of certain hazardous substances (RoHS) in electrical and electronic equipment as defined
in the directive 2002/95/EC issued by the European Parliament and of the Council of 27 January 2003. These substances include mercury,
lead, cadmium, hexavalent chromium, polybrominated biphenyls and polybrominated biphenyl ethers.
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 2
Performance table for –3.7
Product Type Speed Code
–3.7
Unit
Speed Grade
PC2–4200 4–4–4
—
266
MHz
266
MHz
Max. Clock Frequency
@CL5
@CL4
@CL3
Min. RAS-CAS-Delay
Min. Row Precharge Time
Min. Row Active Time
Min. Row Cycle Time
fCK5
fCK4
fCK3
tRCD
tRP
tRAS
tRC
200
MHz
15
ns
15
ns
45
ns
60
ns
TABLE 3
Performance table for –5
Product Type Speed Code
–5
Unit
Speed Grade
PC2-3200 3–3–3
—
max. Clock Frequency
@CL5
fCK5
200
MHz
@CL4
fCK4
200
MHz
fCK3
200
MHz
min. RAS-CAS-Delay
tRCD
15
ns
min. Row Precharge Time
tRP
15
ns
min. Row Active Time
tRAS
40
ns
min. Row Cycle Time
tRC
55
ns
@CL3
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
1.2
Description
The Qimonda HYS[64/72]T[32/64/128]0x0HU–[3/…/5]–A
module family are unbuffered DIMM modules “UDIMMs” with
30,0 mm height based on DDR2 technology. DIMMs are
available as non-ECC modules in 32M × 64 (256MB),
64M × 64 (512MB), 128M × 64 (1GB) and as ECC modules in
64M × 72 (512MB), 128M × 72 (1GB) organization and
density, intended for mounting into 240-pin connector
sockets.
The memory array is designed with 512-Mbit Double-DataRate-Two (DDR2) Synchronous DRAMs. Decoupling
capacitors are mounted on the PCB board. The DIMMs
feature serial presence detect based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and are write protected;
the second 128 bytes are available to the customer.
TABLE 4
Ordering Information for RoHS Compliant Products
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
256MB 1R×16 PC2–5300U–444–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
PC2-5300
HYS64T32000HU–3–A
HYS64T64000HU–3–A
512MB 1R×8 PC2–5300U–444–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–3–A
512MB 1R×8 PC2–5300E–444–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–3–A
1GB 2R×8 PC2–5300U–444–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–3–A
1GB 2R×8 PC2–5300E–444–12–G0
2 Ranks, ECC
512 Mbit (×8)
HYS64T32000HU–3S–A
256MB 1R×16 PC2–5300U–555–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T32900HU–3S–A
256MB 1R×16 PC2–5300U–555–12–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–3S–A
512MB 1R×8 PC2–5300U–555–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS64T64900HU–3S–A
512MB 1R×8 PC2–5300U–555–12–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–3S–A
512MB 1R×8 PC2–5300E–555–12–F0
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–3S–A
1GB 2R×8 PC2–5300U–555–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS64T128920HU–3S–A
1GB 2R×8 PC2–5300U–555–12–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–3S–A
1GB 2R×8 PC2–5300E–555–12–G0
2 Ranks, ECC
512 Mbit (×8)
256MB 1R×16 PC2–4200U–444–11–C1
1 Rank, Non-ECC
512 Mbit (×16)
PC2-4200
HYS64T32000HU–3.7–A
HYS64T32900HU–3.7–A
256MB 1R×16 PC2–4200U–444–11–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–3.7–A
512MB 1R×8 PC2–4200U–444–11–A1
1 Rank, Non-ECC
512 Mbit (×8)
HYS64T64900HU–3.7–A
512MB 1R×8 PC2–4200U–444–11–D0
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–3.7–A
512MB 1R×8 PC2–4200E–444–11–A1
1 Rank, ECC
512 Mbit (×8)
HYS64T128020HU–3.7–A
1GB 2R×8 PC2–4200U–444–11–B1
2 Ranks, Non-ECC
512 Mbit (×8)
HYS64T128920HU–3.7–A
1GB 2R×8 PC2–4200U–444–11–E0
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–3.7–A
1GB 2R×8 PC2–4200E–444–11–B1
2 Ranks, ECC
512 Mbit (×8)
PC2-3200
HYS64T32000HU–5–A
256MB 1R×16 PC2–3200U–333–11–C1
1 Rank, Non-ECC
512 Mbit (×16)
HYS64T64000HU–5–A
512MB 1R×8 PC2–3200U–333–11–A1
1 Rank, Non-ECC
512 Mbit (×8)
HYS72T64000HU–5–A
512MB 1R×8 PC2–3200E–333–11–A1
1 Rank, ECC
512 Mbit (×8)
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Product Type1)
Compliance Code2)
Description
SDRAM
Technology
HYS64T128020HU–5–A
1GB 2R×8 PC2–3200U–333–11–B1
2 Ranks, Non-ECC
512 Mbit (×8)
HYS72T128020HU–5–A
1GB 2R×8 PC2–3200E–333–12–B1
2 Ranks, ECC
512 Mbit (×8)
1) All product types end with a place code, designating the silicon die revision. Example: HYS64T64000HU–3–A, indicating Rev. “A” dies are
used for DDR2 SDRAM components. For all Qimonda DDR2 module and component nomenclature see Chapter 6 of this data sheet.
2) The Compliance Code is printed on the module label and describes the speed grade, for example “PC2–5300U–444–12–C1”, where
4200U means Unbuffered DIMM modules with 4.26 GB/sec Module Bandwidth and “444-12” means Column Address Strobe (CAS)
latency = 4, Row Column Delay (RCD) latency = 4 and Row Precharge (RP) latency = 4 using the latest JEDEC SPD Revision 1.2 and
produced on the Raw Card “C”.
TABLE 5
Address Format
DIMM
Density
Module
Organization
256 MByte
32M ×64
512 MByte
64M ×64
512 MByte
64M ×72
1 GByte
1 GByte
Memory
Ranks
ECC/
Non-ECC
# of SDRAMs # of row/bank/column
bits
Raw
Card
1
Non-ECC
4
13/2/10
C
1
Non-ECC
8
14/2/10
A,D
1
ECC
9
14/2/10
A,F
128M ×64
2
Non-ECC
16
14/2/10
B,E
128M ×72
2
ECC
18
14/2/10
B,G
TABLE 6
Components on Modules
Product Type1)
DRAM Components1)
DRAM Density
DRAM Organisation
HYS64T32000HU
HYB18T512160AF
512 Mbit
32M × 16
HYS64T32900HU
HYB18T512160AF
512 Mbit
32M × 16
HYS64T64000HU
HYB18T512800AF
512 Mbit
64M × 8
HYS64T64900HU
HYB18T512800AF
512 Mbit
64M × 8
HYS72T64000HU
HYB18T512800AF
512 Mbit
64M × 8
HYS64T128020HU
HYB18T512800AF
512 Mbit
64M × 8
HYS64T128920HU
HYB18T512800AF
512 Mbit
64M × 8
HYS72T128020HU
HYB18T512800AF
512 Mbit
64M × 8
Notes2)
1) Green Product
2) For a detailed description of all functionalities of the DRAM components on these modules see the component data sheet.
Rev. 1.41, 2007-05
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
2
Pin Configurations
This chapter contains information to the pin configuration of the modules as well as the block diagrams to the various module
organization
The pin configuration of the Unbuffered DDR2 SDRAM DIMM
and Table 9 respectively. The pin numbering is depicted in
is listed by function in Table 7 (240 pins). The abbreviations
Figure 1 for non-ECC modules (×64) and Figure 2 for ECC
used in columns Pin and Buffer Type are explained in Table 8
modules (×72).
TABLE 7
Pin Configuration of UDIMM
Ball No.
Name
Pin
Type
Buffer
Type
Function
Clock Signals 2:0, Complement Clock Signals 2:0
Clock Signals
185
CK0
I
SSTL
137
CK1
I
SSTL
220
CK2
I
SSTL
186
CK0
I
SSTL
138
CK1
I
SSTL
221
CK2
I
SSTL
52
CKE0
I
SSTL
171
CKE1
I
SSTL
NC
NC
—
Not Connected
Note: 1 Rank module
193
S0#
I
SSTL
Chip Select Rank 1:0
76
S1#
I
SSTL
NC
NC
—
Not Connected
Note: 1 Rank module
192
RAS
I
SSTL
Row Address Strobe
74
CAS
I
SSTL
Column Address Strobe
73
WE
I
SSTL
Write Enable
71
BA0
I
SSTL
Bank Address Bus 1:0
190
BA1
I
SSTL
54
BA2
I
SSTL
Bank Address Bus 2
NC
NC
—
Not Connected
Less than 1Gb DDR2 SDRAMS
Clock Enable Rank 1:0
Control Signals
Address Signals
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
188
A0
I
SSTL
Address Bus 12:0
183
A1
I
SSTL
63
A2
I
SSTL
182
A3
I
SSTL
61
A4
I
SSTL
60
A5
I
SSTL
180
A6
I
SSTL
58
A7
I
SSTL
179
A8
I
SSTL
177
A9
I
SSTL
70
A10
I
SSTL
AP
I
SSTL
57
A11
I
SSTL
176
A12
I
SSTL
196
A13
I
SSTL
Address Signal 13
Note: 1 Gbit based module and 512M ×4/×8
NC
NC
—
Not Connected
Note: Module based on 1 Gbit ×16 Module based on 512 Mbit ×16 or smaller
A14
I
SSTL
Address Signal 14
Note: Modules based on 2 Gbit
NC
NC
—
Not Connected
Note: Modules based on 1 Gbit or smaller
3
DQ0
I/O
SSTL
4
DQ1
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
9
DQ2
I/O
SSTL
10
DQ3
I/O
SSTL
122
DQ4
I/O
SSTL
123
DQ5
I/O
SSTL
128
DQ6
I/O
SSTL
129
DQ7
I/O
SSTL
174
Data Signals
Rev. 1.41, 2007-05
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
12
DQ8
I/O
SSTL
13
DQ9
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
21
DQ10
I/O
SSTL
22
DQ11
I/O
SSTL
131
DQ12
I/O
SSTL
132
DQ13
I/O
SSTL
140
DQ14
I/O
SSTL
141
DQ15
I/O
SSTL
24
DQ16
I/O
SSTL
25
DQ17
I/O
SSTL
30
DQ18
I/O
SSTL
31
DQ19
I/O
SSTL
143
DQ20
I/O
SSTL
144
DQ21
I/O
SSTL
149
DQ22
I/O
SSTL
150
DQ23
I/O
SSTL
33
DQ24
I/O
SSTL
34
DQ25
I/O
SSTL
39
DQ26
I/O
SSTL
40
DQ27
I/O
SSTL
152
DQ28
I/O
SSTL
153
DQ29
I/O
SSTL
158
DQ30
I/O
SSTL
159
DQ31
I/O
SSTL
80
DQ32
I/O
SSTL
81
DQ33
I/O
SSTL
86
DQ34
I/O
SSTL
87
DQ35
I/O
SSTL
199
DQ36
I/O
SSTL
200
DQ37
I/O
SSTL
205
DQ38
I/O
SSTL
206
DQ39
I/O
SSTL
89
DQ40
I/O
SSTL
90
DQ41
I/O
SSTL
95
DQ42
I/O
SSTL
96
DQ43
I/O
SSTL
208
DQ44
I/O
SSTL
209
DQ45
I/O
SSTL
214
DQ46
I/O
SSTL
215
DQ47
I/O
SSTL
Rev. 1.41, 2007-05
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
98
DQ48
I/O
SSTL
99
DQ49
I/O
SSTL
Data Bus 63:0
Data Input/Output pins
107
DQ50
I/O
SSTL
108
DQ51
I/O
SSTL
217
DQ52
I/O
SSTL
218
DQ53
I/O
SSTL
226
DQ54
I/O
SSTL
227
DQ55
I/O
SSTL
110
DQ56
I/O
SSTL
111
DQ57
I/O
SSTL
116
DQ58
I/O
SSTL
117
DQ59
I/O
SSTL
229
DQ60
I/O
SSTL
230
DQ61
I/O
SSTL
235
DQ62
I/O
SSTL
236
DQ63
I/O
SSTL
CB0
I/O
SSTL
Check Bit 0
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB1
I/O
SSTL
Check Bit 1
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB2
I/O
SSTL
Check Bit 2
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB3
I/O
SSTL
Check Bit 3
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB4
I/O
SSTL
Check Bit 4
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB5
I/O
SSTL
Check Bit 5
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
Check Bit Signals
42
43
48
49
161
162
Rev. 1.41, 2007-05
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
167
CB6
I/O
SSTL
Check Bit 6
Note: ECC type module only
NC
NC
—
Not Connected
Note: ECC type module only
CB7
I/O
SSTL
Check Bit 7
Note: ECC type module only
NC
NC
—
Not Connected
Note: Non-ECC module
Data Strobe Bus 8:0
168
Data Strobe Bus
7
DQS0
I/O
SSTL
16
DQS1
I/O
SSTL
28
DQS2
I/O
SSTL
37
DQS3
I/O
SSTL
84
DQS4
I/O
SSTL
93
DQS5
I/O
SSTL
105
DQS6
I/O
SSTL
114
DQS7
I/O
SSTL
46
DQS8
I/O
SSTL
6
DQS0
I/O
SSTL
15
DQS1
I/O
SSTL
27
DQS2
I/O
SSTL
36
DQS3
I/O
SSTL
83
DQS4
I/O
SSTL
92
DQS5
I/O
SSTL
104
DQS6
I/O
SSTL
113
DQS7
I/O
SSTL
45
DQS8
I/O
SSTL
125
DM0
I
SSTL
134
DM1
I
SSTL
146
DM2
I
SSTL
155
DM3
I
SSTL
202
DM4
I
SSTL
211
DM5
I
SSTL
223
DM6
I
SSTL
232
DM7
I
SSTL
164
DM8
I
SSTL
Complement Data Strobe Bus 8:0
Data Mask Signals
Data Mask Bus 8:0
EEPROM
120
SCL
I
CMOS
Serial Bus Clock
119
SDA
I/O
OD
Serial Bus Data
Rev. 1.41, 2007-05
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Ball No.
Name
Pin
Type
Buffer
Type
Function
239
SA0
I
CMOS
Serial Address Select Bus 2:0
240
SA1
I
CMOS
101
SA2
I
CMOS
Power Supplies
VREF
AI
VDDSPD PWR
VDDQ
PWR
—
I/O Reference Voltage
—
EEPROM Power Supply
—
I/O Driver Power Supply
53,59,64,67,69,,
172,178,184,187,
189,197
VDD
PWR
—
Power Supply
2,5,8,11,14,17,,
20,23,26,29,32,
35,38,41,44,47,,
50,65,66,79,82,
85,88,91,94,97,,
100,103,106,
109,112,115,118,
121,124,127,,
130,133,136,139,
142,145,148,,
151,154,157,160,
163,166,169,
198,201,204,207,
210,213,216,,
219,222,225,228,
231,234,237
VSS
GND
—
Ground Plane
195
ODT0
I
SSTL
On-Die Termination Control 0
77
ODT1
I
SSTL
On-Die Termination Control 1
Note: 2 Rank modules
NC
NC
—
Not Connected
Note: 1 Rank modules
18,19,55,68,102,1 NC
26,135,147,
156,165,173,203,
212, 224,233
NC
—
Not connected
Note: Pins not connected on Qimonda UDIMMs
1
238
51,56,62,72,75,,
78,170,175,181,,
191,194
Other Pins
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
12
Internet Data Sheet
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Unbuffered DDR2 SDRAM Modules
TABLE 8
Abbreviations for Pin Type
Abbreviation
Description
I
Standard input-only pin. Digital levels.
O
Output. Digital levels.
I/O
I/O is a bidirectional input/output signal.
AI
Input. Analog levels.
PWR
Power
GND
Ground
NC
Not Connected
TABLE 9
Abbreviations for Buffer Type
Abbreviation
Description
SSTL
Serial Stub Terminated Logic (SSTL_18)
LV-CMOS
Low Voltage CMOS
CMOS
CMOS Levels
OD
Open Drain. The corresponding pin has 2 operational states, active low and tri-state,
and allows multiple devices to share as a wire-OR.
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
13
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 1
Pin Configuration UDIMM ×64 (240 Pin)
62%&
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633
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03292006-EZUJ-JY4S
633
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3!
-004
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 2
Pin Configuration UDIMM ×72 (240 Pin)
62%&
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0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN 0IN Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
633
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3!
-004
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
3
Electrical Characteristics
This chapter contains the electrical characteristics.
3.1
Absolute Maximum Ratings
Caution is needed not to exceed absolute maximum ratings of the DRAM device listed in Table 10 at any time.
TABLE 10
Absolute Maximum Ratings
Symbol
VDD
VDDQ
VDDL
VIN, VOUT
TSTG
Parameter
Rating
Unit
Notes
Min.
Max.
Voltage on VDD pin relative to VSS
–1.0
+2.3
V
1)
Voltage on VDDQ pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on VDDL pin relative to VSS
–0.5
+2.3
V
1)2)
Voltage on any pin relative to VSS
–0.5
+2.3
V
1)
°C
1)2)
Storage Temperature
–55
+100
1) When VDD and VDDQ and VDDL are less than 500 mV; VREF may be equal to or less than 300 mV.
2) Storage Temperature is the case surface temperature on the center/top side of the DRAM.
Attention: Stresses greater than those listed under “Absolute Maximum Ratings” may cause permanent damage to
the device. This is a stress rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
TABLE 11
DRAM Component Operating Temperature Range
Symbol
TOPER
Parameter
Rating
Operating Temperature
Min.
Max.
0
95
Unit
Notes
°C
1)2)3)4)
1) Operating Temperature is the case surface temperature on the center / top side of the DRAM.
2) The operating temperature range are the temperatures where all DRAM specification will be supported. During operation, the DRAM case
temperature must be maintained between 0 - 95 °C under all other specification parameters.
3) Above 85 °C the Auto-Refresh command interval has to be reduced to tREFI= 3.9 µs
4) When operating this product in the 85 °C to 95 °C TCASE temperature range, the High Temperature Self Refresh has to be enabled by
setting EMR(2) bit A7 to “1”. When the High Temperature Self Refresh is enabled there is an increase of IDD6 by approximately 50%
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
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Unbuffered DDR2 SDRAM Modules
3.2
DC Operating Conditions
This chapter contains the DC operating conditions tables.
TABLE 12
Operating Conditions
Parameter
Symbol
Values
Unit
Min.
Max.
0
+65
×C
0
+95
×C
Storage Temperature
TOPR
TCASE
TSTG
– 50
+100
×C
Barometric Pressure (operating & storage)
PBar
+69
+105
kPa
Operating Humidity (relative)
HOPR
10
90
%
Operating temperature (ambient)
DRAM Case Temperature
Notes
1)2)3)4)
5)
1)
2)
3)
4)
DRAM Component Case Temperature is the surface temperature in the center on the top side of any of the DRAMs.
Within the DRAM Component Case Temperature Range all DRAM specifications will be supported
Above 85 °C DRAM Case Temperature the Auto-Refresh command interval has to be reduced to tREFI = 3.9 µs
Self-Refresh period is hard-coded in the DRAMs and therefore it is imperative that the system ensures the DRAM is below 85 °C Case
Temperature before initiating Self-Refresh operation.
5) Up to 3000 m.
TABLE 13
Supply Voltage Levels and DC Operating Conditions
Parameter
Symbol
Values
Unit
Notes
Min.
Nom.
Max.
1.7
1.8
1.9
V
1.7
1.8
1.9
V
1)
0.49 x VDDQ
0.5 x VDDQ
0.51 x VDDQ
V
2)
1.7
—
3.6
V
DC Input Logic High
VDD
VDDQ
VREF
VDDSPD
VIH(DC)
VREF + 0.125
—
V
DC Input Logic Low
VIL(DC)
– 0.30
—
VDDQ + 0.3
VREF – 0.125
Device Supply Voltage
Output Supply Voltage
Input Reference Voltage
SPD Supply Voltage
V
In / Output Leakage Current
IL
–5
—
5
µA
1) Under all conditions, VDDQ must be less than or equal to VDD
2) Peak to peak AC noise on VREF may not exceed ± 2% VREF (DC).VREF is also expected to track noise in VDDQ.
3) Input voltage for any connector pin under test of 0 V ≤ VIN ≤ VDDQ + 0.3 V; all other pins at 0 V. Current is per pin
Rev. 1.41, 2007-05
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Unbuffered DDR2 SDRAM Modules
3.3
AC Characteristics
This chapter contains the AC operating conditions tables.
3.3.1
Speed Grade Definitions
List of speed grade definition tables.
• Table 14 “Speed Grade Definition Speed Bins for DDR2–667” on Page 18
• Table 15 “Speed Grade Definition Speed Bins for DDR2–533C” on Page 19
• Table 16 “Speed Grade Definition Speed Bins for DDR2–400B” on Page 19
TABLE 14
Speed Grade Definition Speed Bins for DDR2–667
Speed Grade
DDR2–667C
DDR2–667D
QAG Sort Name
–3
–3S
CAS-RCD-RP latencies
4–4–4
5–5–5
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Notes
tCK
Symbol
Min.
Max.
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
8
5
8
ns
1)2)3)4)
3
8
3.75
8
ns
1)2)3)4)
3
8
3
8
ns
1)2)3)4)
45
70000
45
70000
ns
1)2)3)4)5)
57
—
60
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
12
—
15
—
ns
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0) .
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
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Unbuffered DDR2 SDRAM Modules
TABLE 15
Speed Grade Definition Speed Bins for DDR2–533C
Speed Grade
DDR2–533C
QAG Sort Name
–3.7
CAS-RCD-RP latencies
4–4–4
Parameter
Clock Frequency
@ CL = 3
@ CL = 4
@ CL = 5
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
3.75
3.75
45
60
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
TABLE 16
Speed Grade Definition Speed Bins for DDR2–400B
Speed Grade
DDR2–400B
QAG Sort Name
–5
CAS-RCD-RP latencies
3–3–3
Parameter
Clock Frequency
Row Active Time
Row Cycle Time
RAS-CAS-Delay
Row Precharge Time
@ CL = 3
@ CL = 4
@ CL = 5
Unit
Note
tCK
Symbol
Min.
Max.
—
tCK
tCK
tCK
tRAS
tRC
tRCD
tRP
5
5
5
40
55
15
15
8
8
8
70000
—
—
—
ns
ns
ns
ns
ns
ns
ns
1)2)3)4)
1)2)3)4)
1)2)3)4)
1)2)3)4)5)
1)2)3)4)
1)2)3)4)
1)2)3)4)
1) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode. Timings are further guaranteed for normal
OCD drive strength (EMRS(1) A1 = 0)
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
3) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
4) The output timing reference voltage level is VTT.
5) tRAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x tREFI.
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
19
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Unbuffered DDR2 SDRAM Modules
3.3.2
AC Timing Parameters
List of AC Timing parameters.
• Table 17 “Timing Parameter by Speed Grade - DDR2–667” on Page 20
• Table 18 “Timing Parameter by Speed Grade - DDR2–533” on Page 25
• Table 19 “Timing Parameter by Speed Grade - DDR2-400” on Page 28
TABLE 17
Timing Parameter by Speed Grade - DDR2–667
Parameter
Symbol
DDR2–667
Unit
Notes1)2)3)4)5)6)
7)8)
tAC
DQS output access time from CK / CK
tDQSCK
Average clock high pulse width
tCH.AVG
Average clock low pulse width
tCL.AVG
Average clock period
tCK.AVG
DQ and DM input setup time
tDS.BASE
DQ and DM input hold time
tDH.BASE
Control & address input pulse width for each input tIPW
DQ and DM input pulse width for each input
tDIPW
Data-out high-impedance time from CK / CK
tHZ
DQS/DQS low-impedance time from CK / CK
tLZ.DQS
DQ low impedance time from CK/CK
tLZ.DQ
DQS-DQ skew for DQS & associated DQ signals tDQSQ
CK half pulse width
tHP
DQ output access time from CK / CK
Min.
Max.
–450
+450
ps
–400
+400
ps
9)
10)11)
9)
0.48
0.52
0.48
0.52
tCK.AVG
tCK.AVG
3000
8000
ps
100
––
ps
12)13)14)
175
––
ps
13)14)15)
0.6
—
0.35
—
tCK.AVG
tCK.AVG
—
ps
9)16)
tAC.MIN
2 x tAC.MIN
tAC.MAX
tAC.MAX
tAC.MAX
ps
9)16)
ps
9)16)
—
240
ps
17)
Min(tCH.ABS,
tCL.ABS)
__
ps
18)
—
340
ps
19)
DQ/DQS output hold time from DQS
tQHS
tQH
tHP – tQHS
—
ps
20)
Write command to DQS associated clock edges
WL
RL–1
DQ hold skew factor
DQS latching rising transition to associated clock tDQSS
edges
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Active to precharge command
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
tDQSH
tDQSL
tDSS
tDSH
tWPST
tWPRE
tLS.BASE
tLH.BASE
tRPRE
tRPST
tRAS
20
10)11)
nCK
21)
– 0.25
+ 0.25
tCK.AVG
0.35
—
0.35
—
0.2
—
0.2
—
0.4
0.6
0.35
—
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
tCK.AVG
200
—
ps
22)23)
275
—
ps
23)24)
0.9
1.1
25)26)
0.4
0.6
tCK.AVG
tCK.AVG
45
70000
ns
28)
21)
21)
25)27)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–667
Unit
Notes1)2)3)4)5)6)
7)8)
Min.
Max.
Active to active command period for 1KB page
size products
tRRD
7.5
—
ns
28)
Active to active command period for 2KB page
size products
tRRD
10
—
ns
28)
Four Activate Window for 1KB page size products tFAW
37.5
—
ns
28)
Four Activate Window for 2KB page size products tFAW
50
—
ns
28)
tCCD
Write recovery time
tWR
Auto-Precharge write recovery + precharge time tDAL
Internal write to read command delay
tWTR
Internal Read to Precharge command delay
tRTP
Exit self-refresh to a non-read command
tXSNR
Exit self-refresh to read command
tXSRD
Exit precharge power-down to any valid
tXP
2
—
nCK
15
—
ns
28)
WR + tnRP
—
nCK
29)30)
7.5
—
ns
28)31)
7.5
—
ns
28)
tRFC +10
—
ns
28)
200
—
nCK
2
—
nCK
tXARD
tXARDS
2
—
nCK
7 – AL
—
nCK
CKE minimum pulse width ( high and low pulse
width)
tCKE
3
—
nCK
ODT turn-on delay
tAOND
tAON
tAONPD
2
2
nCK
tAC.MIN
tAC.MIN + 2
tAC.MAX + 0.7
2 x tCK.AVG +
tAC.MAX + 1
ns
tAOFD
tAOF
tAOFPD
2.5
2.5
nCK
tAC.MIN
tAC.MIN + 2
tAC.MAX + 0.6
ns
2.5 x tCK.AVG + ns
tAC.MAX + 1
tANPD
tAXPD
tMRD
tMOD
tOIT
tDELAY
3
––
nCK
2
—
nCK
0
12
ns
1)
0
12
ns
1)
tLS + tCK .AVG + ––
tLH
ns
CAS to CAS command delay
command (other than NOP or Deselect)
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
ODT turn-on
ODT turn-on (Power down mode)
ODT turn-off delay
ODT turn-off
ODT turn-off (Power down mode)
ODT to power down entry latency
ODT to power down exit latency
Mode register set command cycle time
MRS command to ODT update delay
OCD drive mode output delay
Minimum time clocks remain ON after CKE
asynchronously drops LOW
8
32)
9)33)
ns
34)35)
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) New units, ‘tCK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘tCK.AVG‘ represents the actual tCK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘tCK‘ is used for both concepts. Example: tXP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x tCK.AVG + tERR.2PER(Min).
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272
ps and tERR(6- 10PER).MAX = + 293 ps, then tDQSCK.MIN(DERATED) = tDQSCK.MIN – tERR(6-10PER).MAX = – 400 ps – 293 ps = – 693 ps and
tDQSCK.MAX(DERATED) = tDQSCK.MAX – tERR(6-10PER).MIN = 400 ps + 272 ps = + 672 ps. Similarly, tLZ.DQ for DDR2–667 derates to tLZ.DQ.MIN(DERATED)
= - 900 ps – 293 ps = – 1193 ps and tLZ.DQ.MAX(DERATED) = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations).
12) Input waveform timing tDS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the VIH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the VIL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between Vil(DC)MAX and Vih(DC)MIN. See
Figure 4.
13) If tDS or tDH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
15) Input waveform timing tDH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the VIH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the VIL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between VIL.DC.MAX and
VIH.DC.MIN. See Figure 4.
16) tHZ and tLZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (tHZ), or begins driving (tLZ) .
17) tDQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
18) tHP is the minimum of the absolute half period of the actual input clock. tHP is an input parameter but not an input specification parameter.
It is used in conjunction with tQHS to derive the DRAM output timing tQH. The value to be used for tQH calculation is determined by the
following equation; tHP = MIN (tCH.ABS, tCL.ABS), where, tCH.ABS is the minimum of the actual instantaneous clock high time; tCL.ABS is the
minimum of the actual instantaneous clock low time.
19) tQHS accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual tHP at the input is
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
20) tQH = tHP – tQHS, where: tHP is the minimum of the absolute half period of the actual input clock; and tQHS is the specification value under
the max column. {The less half-pulse width distortion present, the larger the tQH value is; and the larger the valid data eye will be.}
Examples: 1) If the system provides tHP of 1315 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 975 ps minimum. 2) If the system
provides tHP of 1420 ps into a DDR2–667 SDRAM, the DRAM provides tQH of 1080 ps minimum.
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC, etc.), as these are relative to the clock signal
crossing. That is, these parameters should be met whether clock jitter is present or not.
22) Input waveform timing is referenced from the input signal crossing at the VIH.AC level for a rising signal and VIL.AC for a falling signal applied
to the device under test. See Figure 5.
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e. tJIT.PER, tJIT.CC,
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
24) Input waveform timing is referenced from the input signal crossing at the VIL.DC level for a rising signal and VIH.DC for a falling signal applied
to the device under test. See Figure 5.
25) tRPST end point and tRPRE begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
(tRPST), or begins driving (tRPRE). Figure 3 shows a method to calculate these points when the device is no longer driving (tRPST), or begins
driving (tRPRE) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
calculation is consistent.
Rev. 1.41, 2007-05
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.PER of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.PER.MIN = – 72 ps
and tJIT.PER.MAX = + 93 ps, then tRPRE.MIN(DERATED) = tRPRE.MIN + tJIT.PER.MIN = 0.9 x tCK.AVG – 72 ps = + 2178 ps and tRPRE.MAX(DERATED) = tRPRE.MAX
+ tJIT.PER.MAX = 1.1 x tCK.AVG + 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual tJIT.DUTY of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has tJIT.DUTY.MIN = – 72 ps
and tJIT.DUTY.MAX = + 93 ps, then tRPST.MIN(DERATED) = tRPST.MIN + tJIT.DUTY.MIN = 0.4 x tCK.AVG – 72 ps = + 928 ps and tRPST.MAX(DERATED) = tRPST.MAX
+ tJIT.DUTY.MAX = 0.6 x tCK.AVG + 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support tnPARAM = RU{tPARAM / tCK.AVG}, which is in clock
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support tnRP = RU{tRP / tCK.AVG}, which is in
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which tRP = 15 ns, the device will support
tnRP = RU{tRP / tCK.AVG} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
29) DAL = WR + RU{tRP(ns) / tCK(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For tRP, if the result
of the division is not already an integer, round up to the next highest integer. tCK refers to the application clock period. Example: For
DDR2–533 at tCK = 3.75 ns with tWR programmed to 4 clocks. tDAL = 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
30) tDAL.nCK = WR [nCK] + tnRP.nCK = WR + RU{tRP [ps] / tCK.AVG[ps] }, where WR is the value programmed in the EMR.
31) tWTR is at lease two clocks (2 x tCK) independent of operation frequency.
32) tCKE.MIN of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of tIS + 2 x tCK + tIH.
33) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from tAOND.
34) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD.
35) When the device is operated with input clock jitter, this parameter needs to be derated by {–tJIT.DUTY.MAX – tERR(6-10PER).MAX} and {–tJIT.DUTY.MIN
– tERR(6-10PER).MIN } of the actual input clock. (output deratings are relative to the SDRAM input clock.) For example, if the measured jitter
into a DDR2–667 SDRAM has tERR(6-10PER).MIN = – 272 ps, tERR(6- 10PER).MAX = + 293 ps, tJIT.DUTY.MIN = – 106 ps and tJIT.DUTY.MAX = + 94 ps,
then tAOF.MIN(DERATED) = tAOF.MIN + {– tJIT.DUTY.MAX – tERR(6-10PER).MAX} = – 450 ps + {– 94 ps – 293 ps} = – 837 ps and tAOF.MAX(DERATED) = tAOF.MAX
+ {– tJIT.DUTY.MIN – tERR(6-10PER).MIN} = 1050 ps + {106 ps + 272 ps} = + 1428 ps. (Caution on the MIN/MAX usage!)
FIGURE 3
Method for calculating transitions and endpoint
VOH - x mV
VTT + 2x mV
VOH - 2x mV
VTT + x mV
tLZ
tHZ
tRPRE begin point
tRPST end point
VOL + 2x mV
VTT - x mV
VOL + x mV
VTT - 2x mV
T1 T2
T1 T2
tHZ,tRPST end point = 2*T1-T2
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
tLZ,tRPRE begin point = 2*T1-T2
23
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 4
Differential input waveform timing - tDS and tDS
DQS
DQS
tDS
tDH
tDS
tDH
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
FIGURE 5
Differential input waveform timing - tlS and tlH
CK
CK
tIS
tIH
tIS
tIH
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 18
Timing Parameter by Speed Grade - DDR2–533
Parameter
Symbol
DDR2–533
Unit
Notes1)2)3)4)5)
6)7)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–500
+500
ps
2
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
––
ns
9)
DQ and DM input hold time (differential data
strobe)
tDH(base)
225
––
ps
10)
–25
—
ps
11)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
0.35
—
tCK
–450
+450
ps
0.35
—
tCK
—
300
ps
tDQSS
tDS(base)
– 0.25
+ 0.25
tCK
100
—
ps
11)
–25
—
ps
11)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
37.5
—
ns
50
—
ns
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
Write command to 1st DQS latching transition
DQ and DM input setup time (differential data
strobe)
DQ and DM input setup time (single ended data tDS1(base)
strobe)
DQS falling edge hold time from CK (write
cycle)
Four Activate Window period
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
tFAW
tHP
tHZ
tIH(base)
tIPW
25
11)
13)
12)
MIN. (tCL, tCH)
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
8)18)
—
tAC.MAX
ps
13)
375
—
ps
11)
0.6
—
tCK
250
—
ps
11)
2 × tAC.MIN
ps
14)
tAC.MIN
tAC.MAX
tAC.MAX
ps
14)
2
—
tCK
0
12
ns
tHP –tQHS
—
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–533
Unit
Notes1)2)3)4)5)
6)7)
Data hold skew factor
Average periodic refresh Interval
tQHS
tREFI
Min.
Max.
—
400
ps
—
7.8
µs
14)15)
—
3.9
µs
16)18)
—
ns
17)
Auto-Refresh to Active/Auto-Refresh
command period
tRFC
105
Precharge-All (4 banks) command period
tRP
tRP
tRPRE
tRPST
tRRD
tRP + 1tCK
—
ns
15 + 1tCK
—
ns
0.9
1.1
14)
0.40
0.60
tCK
tCK
7.5
—
ns
14)18)
10
—
ns
16)20)
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
0.25 x tCK
—
0.40
0.60
tCK
tCK
15
—
ns
Write recovery time for write with AutoPrecharge
WR
tWR/tCK
Internal Write to Read command delay
tWTR
tXARD
7.5
Exit active power-down mode to Read
command (slow exit, lower power)
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
14)
19)
tCK
20)
—
ns
21)
2
—
tCK
22)
tXARDS
6 – AL
—
tCK
22)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
200
—
tCK
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
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Unbuffered DDR2 SDRAM Modules
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 4 “Ordering Information for RoHS
Compliant Products” on Page 5.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
Rev. 1.41, 2007-05
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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 19
Timing Parameter by Speed Grade - DDR2-400
Parameter
Symbol
DDR2–400
Unit
Notes1)2)3)4)5)
6)7)
Min.
Max.
tAC
tCCD
tCH
tCKE
tCL
tDAL
–600
+600
ps
2
—
0.45
0.55
3
—
0.45
0.55
WR + tRP
—
tCK
tCK
tCK
tCK
tCK
Minimum time clocks remain ON after CKE
asynchronously drops LOW
tDELAY
tIS + tCK + tIH
––
ns
9)
DQ and DM input hold time (differential data
strobe)
tDH(base)
275
––
ps
10)
–25
—
ps
11)
0.35
—
tCK
–500
+500
ps
0.35
—
tCK
—
350
ps
– 0.25
+ 0.25
tCK
DQ output access time from CK / CK
CAS A to CAS B command period
CK, CK high-level width
CKE minimum high and low pulse width
CK, CK low-level width
Auto-Precharge write recovery + precharge
time
DQ and DM input hold time (single ended data tDH1(base)
strobe)
DQ and DM input pulse width (each input)
DQS output access time from CK / CK
DQS input low (high) pulse width (write cycle)
DQS-DQ skew (for DQS & associated DQ
signals)
tDIPW
tDQSCK
tDQSL,H
tDQSQ
Write command to 1st DQS latching transition tDQSS
8)22)
11)
DQ and DM input setup time (differential data
strobe)
tDS(base)
150
—
ps
11)
DQ and DM input setup time (single ended
data strobe)
tDS1(base)
–25
—
ps
11)
DQS falling edge hold time from CK (write
cycle)
tDSH
0.2
—
tCK
DQS falling edge to CK setup time (write cycle) tDSS
0.2
—
tCK
37.5
—
ns
50
—
ns
Four Activate Window period
Clock half period
Data-out high-impedance time from CK / CK
Address and control input hold time
Address and control input pulse width
(each input)
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
Mode register set command cycle time
OCD drive mode output delay
Data output hold time from DQS
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
tFAW
tHP
tHZ
tIH(base)
tIPW
12)
MIN. (tCL, tCH)
tIS(base)
tLZ(DQ)
tLZ(DQS)
tMRD
tOIT
tQH
28
13)
—
tAC.MAX
ps
13)
475
—
ps
11)
0.6
—
tCK
350
—
ps
11)
2 × tAC.MIN
ps
14)
tAC.MIN
tAC.MAX
tAC.MAX
ps
14)
2
—
tCK
0
12
ns
tHP –tQHS
—
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Parameter
Symbol
DDR2–400
Unit
Notes1)2)3)4)5)
6)7)
Min.
Max.
—
450
ps
—
7.8
µs
14)15)
—
3.9
µs
16)18)
105
—
ns
17)
tRP + 1tCK
15 + 1tCK
—
ns
—
ns
0.9
1.1
14)
0.40
0.60
tCK
tCK
7.5
—
ns
14)18)
10
—
ns
16)20)
tRTP
tWPRE
tWPST
tWR
7.5
—
ns
0.25 x tCK
—
0.40
0.60
tCK
tCK
15
—
ns
Write recovery time for write with AutoPrecharge
WR
tWR/tCK
Internal Write to Read command delay
tWTR
tXARD
10
Exit active power-down mode to Read
command (slow exit, lower power)
Data hold skew factor
Average periodic refresh Interval
tQHS
tREFI
Auto-Refresh to Active/Auto-Refresh
command period
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without AutoPrecharge
tRP
tRP
tRPRE
tRPST
tRRD
14)
19)
tCK
20)
—
ns
21)
2
—
tCK
22)
tXARDS
6 – AL
—
tCK
22)
Exit precharge power-down to any valid
command (other than NOP or Deselect)
tXP
2
—
tCK
Exit Self-Refresh to non-Read command
tXSNR
tXSRD
tRFC +10
—
ns
200
—
tCK
Exit power down to any valid command
(other than NOP or Deselect)
Exit Self-Refresh to Read command
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ±0.1 V. See notes 5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until VREF stabilizes. During the period before VREF stabilizes, CKE = 0.2 x VDDQ is recognized as low.
7) The output timing reference voltage level is VTT.
8) For each of the terms, if not already an integer, round to the next highest integer. tCK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (tCL, tCH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for tCL and tCH).
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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
13) The tHZ, tRPST and tLZ, tRPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(tHZ, tRPST), or begins driving (tLZ, tRPRE). tHZ and tLZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ TCASE ≤ 85 °C
16) 85 °C < TCASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The tRRD timing parameter depends on the page size of the DRAM organization. See Table 4 “Ordering Information for RoHS
Compliant Products” on Page 5.
19) The maximum limit for the tWPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) WR must be programmed to fulfill the minimum requirement for the tWR timing parameter, where WRMIN[cycles] = tWR(ns)/tCK(ns) rounded
up to the next integer value. tDAL = WR + (tRP/tCK). For each of the terms, if not already an integer, round to the next highest integer. tCK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
21) Minimum tWTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
22) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active powerdown mode” (MR, A12 = “0”) a fast power-down exit timing tXARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing tXARDS has to be satisfied.
Rev. 1.41, 2007-05
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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
3.3.3
ODT AC Electrical Characteristics
This chapter contains the ODT AC electrical characteristics tables.
TABLE 20
ODT AC Characteristics and Operating Conditions for DDR2-667
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Min.
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MIN
tAC.MIN + 2 ns
tAC.MAX + 0.7 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
Note
1)
ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
2)
ns
tCK
tCK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD.
TABLE 21
ODT AC Characteristics and Operating Conditions for DDR2-533/DDR2-400
Symbol
tAOND
tAON
tAONPD
tAOFD
tAOF
tAOFPD
tANPD
tAXPD
Parameter / Condition
Values
Unit
Min.
Max.
ODT turn-on delay
2
2
tCK
ODT turn-on
tAC.MIN
tAC.MIN + 2 ns
tAC.MAX + 1 ns
2 tCK + tAC.MAX + 1 ns
ns
ODT turn-on (Power-Down Modes)
Note
1)
ns
ODT turn-off delay
2.5
2.5
tCK
ODT turn-off
tAC.MAX + 0.6 ns
2.5 tCK + tAC.MAX + 1 ns
ns
ODT turn-off (Power-Down Modes)
tAC.MIN
tAC.MIN + 2 ns
ODT to Power Down Mode Entry Latency
3
—
ODT Power Down Exit Latency
8
—
tCK
tCK
2)
ns
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from tAOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from tAOFD.
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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
3.4
Currents Specifications and Conditions
Chapter contains current tables for each of the product types and the definitions of the various currents.
• Table 22 “IDD Measurement Conditions” on Page 32
• Table 23 “Definitions for IDD” on Page 33
• Table 24 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3–A” on Page 34
• Table 25 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3S–A” on Page 35
• Table 26 “IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3.7–A” on Page 36
TABLE 22
IDD Measurement Conditions
Parameter
Symbol Note
1)2)3)4)5)
Operating Current 0
IDD0
One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between
valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.
Operating Current 1
One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,
tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and
control inputs are SWITCHING, Databus inputs are SWITCHING.
IDD1
6)
Precharge Standby Current
IDD2N
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,
Databus inputs are SWITCHING.
Precharge Power-Down Current
Other control and address inputs are STABLE, Data bus inputs are FLOATING.
IDD2P
Precharge Quiet Standby Current
All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,
Data bus inputs are FLOATING.
IDD2Q
Active Standby Current
Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.
IDD3N
Active Power-Down Current
IDD3P(0)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);
Active Power-Down Current
IDD3P(1)
All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs
are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);
Operating Current - Burst Read
IDD4R
All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCKMIN; tRAS = tRASMAX;
tRP = tRPMIN; CKE is HIGH, CS is HIGH between valid commands; Address inputs are SWITCHING; Data
bus inputs are SWITCHING; IOUT = 0mA.
Operating Current - Burst Write
All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;
tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are
SWITCHING; Data Bus inputs are SWITCHING;
IDD4W
Burst Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5B
Rev. 1.41, 2007-05
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6)
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Parameter
Symbol Note
1)2)3)4)5)
Distributed Refresh Current
tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid
commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.
IDD5D
Self-Refresh Current
IDD6
CKE ≤ 0.2 V; external clock off, CK and CK at 0 V; Other control and address inputs are FLOATING, Data
bus inputs are FLOATING. IDD6 current values are guaranteed up to TCASE of 85 °C max.
6)
All Bank Interleave Read Current
IDD7
All banks are being interleaved at minimum tRC without violating tRRD using a burst length of 4. Control
and address bus inputs are STABLE during DESELECTS. Iout = 0 mA.
1) VDDQ = 1.8 V ± 0.1 V; VDD = 1.8 V ± 0.1 V
2) IDD specifications are tested after the device is properly initialized and IDD parameter are specified with ODT disabled.
3) Definitions for IDD see Table 23
4) For two rank modules: All active current measurements in the same IDD current mode. The other rank is in IDD2P Precharge Power-Down
Mode
5) For details and notes see the relevant Qimonda component data sheet
6) IDD1, IDD4R and IDD7 current measurements are defined with the outputs disabled (IOUT = 0 mA). To achieve this on module level the output
buffers can be disabled using an EMRS(1) (Extended Mode Register Command) by setting A12 bit to HIGH.
TABLE 23
Definitions for IDD
Parameter
Description
LOW
VIN ≤ VIL(ac).MAX, HIGH is defined as VIN ≥ VIH(ac).MIN
STABLE
Inputs are stable at a HIGH or LOW level
FLOATING
Inputs are VREF = VDDQ /2
SWITCHING
Inputs are changing between HIGH and LOW every other clock (once per 2 cycles) for address and control
signals, and inputs changing between HIGH and LOW every other data transfer (once per cycle) for DQ
signals not including mask or strobes
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Unbuffered DDR2 SDRAM Modules
TABLE 24
IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3–A
760
860
mA
2)
450
800
900
mA
3)
40
50
80
90
mA
3)
160
320
360
640
720
mA
3)
200
400
450
800
900
mA
3)
80
150
170
300
340
mA
3)
20
50
50
100
110
mA
3)
600
1040
1170
1080
1220
mA
2)
680
1120
1260
1160
1310
mA
2)
560
1120
1260
1160
1310
mA
2)
20
50
50
100
110
mA
3)
20
40
45
80
90
mA
3)
960
1240
1400
1280
1440
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down mode
3) Both ranks are in the same IDDcurrent mode
2)
HYS72T128020HU–3–A
2)
HYS64T128020HU–3–A
mA
HYS72T64000HU–3–A
720
HYS64T64000HU–3–A
Note1)
HYS64T32000HU–3–A
Unit
Product Type
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
–3
–3
–3
–3
–3
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
380
600
680
640
440
720
810
200
400
20
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HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 25
IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3S–A
720
810
mA
2)
450
800
900
mA
3)
40
50
80
90
mA
3)
160
320
360
640
720
mA
3)
200
400
450
800
900
mA
3)
80
150
170
300
340
mA
3)
20
50
50
100
110
mA
3)
600
1040
1170
1080
1220
mA
2)
680
1120
1260
1160
1310
mA
2)
560
1120
1260
1160
1310
mA
2)
20
50
50
100
110
mA
3)
20
40
45
80
90
mA
3)
910
1180
1320
1220
1370
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down mode
3) Both ranks are in the same IDDcurrent mode
2)
HYS72T128020HU–3S–A
2)
HYS64T128020HU–3S–A
HYS64T128920HU–3S–A
mA
HYS72T64000HU–3S–A
680
HYS64T64000HU–3S–A
HYS64T64900HU–3S–A
Note1)
HYS64T32000HU–3S–A
HYS64T32900HU–3S–A
Unit
Product Type
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
–3S
–3S
–3S
–3S
–3S
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
360
570
640
610
420
680
770
200
400
20
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Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 26
Product Type
HYS64T32000HU–3.7–A
HYS64T32900HU–3.7–A
HYS64T64000HU–3.7–A
HYS64T64900HU–3.7–A
HYS72T64000HU–3.7–A
HYS64T128020HU–3.7–A
HYS64T128920HU–3.7–A
HYS72T128020HU–3.7–A
IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–3.7–A
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
–3.7
–3.7
–3.7
–3.7
–3.7
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
320
520
590
550
360
600
680
160
320
20
Unit
Note1)
620
mA
2)
630
710
mA
2)
360
640
720
mA
3)
30
40
60
70
mA
3)
120
240
270
480
540
mA
3)
160
320
360
640
720
mA
3)
60
130
140
260
290
mA
3)
20
40
50
80
90
mA
3)
400
720
810
750
850
mA
2)
440
760
860
790
890
mA
2)
520
1040
1170
1070
1210
mA
2)
20
50
50
100
110
mA
3)
16
32
36
64
72
mA
3)
880
1120
1260
1160
1300
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down mode
3) Both ranks are in the same IDDcurrent mode
2)
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Unbuffered DDR2 SDRAM Modules
TABLE 27
IDDSpecification for HYS[64/72]T[32/64/128]xxxHU–5–A
510
580
mA
2)
290
510
580
mA
3)
30
40
60
70
mA
3)
100
200
230
400
450
mA
3)
140
280
320
560
630
mA
3)
50
100
120
210
230
mA
3)
20
40
50
80
90
mA
3)
340
560
630
590
670
mA
2)
360
600
680
630
710
mA
2)
480
960
1080
990
1120
mA
2)
20
50
50
100
110
mA
3)
16
32
36
64
72
mA
3)
840
1040
1170
1070
1210
mA
1) Calculated values from component data. ODT disabled. IDD1, IDD4R, and IDD7, are defined with the outputs disabled.
2) The other rank is in IDD2P Precharge Power-Down mode
3) Both ranks are in the same IDDcurrent mode
2)
HYS72T128020HU–5–A
2)
HYS64T128020HU–5–A
mA
HYS72T64000HU–5–A
530
HYS64T64000HU–5–A
Note1)
HYS64T32000HU–5–A
Unit
Product Type
Organization
256MB
512MB
512MB
1GB
1GB
1 Rank
1 Rank
1 Rank
2 Ranks
2 Ranks
×64
×64
×72
×64
×72
–5
–5
–5
–5
–5
Symbol
Max.
Max.
Max.
Max.
Max.
IDD0
IDD1
IDD2N
IDD2P
IDD2Q
IDD3N
IDD3P( MRS = 0)
IDD3P( MRS = 1)
IDD4R
IDD4W
IDD5B
IDD5D
IDD6
IDD7
280
440
500
470
300
480
540
130
260
20
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
37
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
4
SPD Codes
This chapter lists all hexadecimal byte values stored in the EEPROM of the products described in this data sheet. SPD stands
for serial presence detect. All values with XX in the table are module specific bytes which are defined during production.
List of SPD Code Tables
•
•
•
•
•
•
Table 28 “HYS[64/72]T[32/64/128]0x0HU-3-A” on Page 38
Table 29 “HYS[64/72]T[32/64]x00HU-3S-A” on Page 43
Table 30 “HYS[64/72]T128x20HU-3S-A” on Page 48
Table 31 “HYS[64/72]T[32/64]x00HU-3.7-A” on Page 52
Table 32 “HYS[64/72]T128x20HU-3.7-A” on Page 57
Table 33 “HYS[64/72]T[32/64/128]0x0HU-5-A” on Page 61
TABLE 28
Product Type
HYS64T32000HU–3–A
HYS64T64000HU–3–A
HYS72T64000HU–3–A
HYS64T128020HU–3–A
HYS72T128020HU–3–A
HYS[64/72]T[32/64/128]0x0HU-3-A
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0D
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
61
61
6
Data Width
40
40
48
40
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
38
Internet Data Sheet
Product Type
HYS64T32000HU–3–A
HYS64T64000HU–3–A
HYS72T64000HU–3–A
HYS64T128020HU–3–A
HYS72T128020HU–3–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
30
30
30
30
30
45
45
45
45
45
11
Error Correction Support (non-ECC, ECC)
00
00
02
00
02
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
10
08
08
08
08
14
Error Checking SDRAM Width
00
00
08
00
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
02
02
02
02
02
21
DIMM Attributes
00
00
00
00
00
22
Component Attributes
03
03
03
03
03
23
30
30
30
30
30
45
45
45
45
45
50
50
50
50
50
60
60
60
60
60
10
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
2D
2D
31
Module Density per Rank
40
80
80
80
80
32
tAS.MIN and tCS.MIN [ns]
20
20
20
20
20
24
25
26
27
28
29
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
39
30
30
30
30
30
28
1E
1E
1E
1E
30
30
30
30
30
Internet Data Sheet
Product Type
HYS64T32000HU–3–A
HYS64T64000HU–3–A
HYS72T64000HU–3–A
HYS64T128020HU–3–A
HYS72T128020HU–3–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
33
27
27
27
27
27
10
10
10
10
10
17
17
17
17
17
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
38
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
34
35
36
37
41
42
43
44
45
1E
1E
1E
1E
1E
00
00
00
00
00
00
00
00
00
00
39
39
39
39
39
69
69
69
69
69
80
80
80
80
80
18
18
18
18
18
22
22
22
22
22
46
PLL Relock Time
00
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
55
53
53
53
53
48
Psi(T-A) DRAM
72
78
78
78
78
49
∆T0 (DT0)
67
4F
4F
4F
4F
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
36
39
39
39
39
51
∆T2P (DT2P)
24
26
26
26
26
52
∆T3N (DT3N)
24
26
26
26
26
53
∆T3P.fast (DT3P fast)
29
2B
2B
2B
2B
54
∆T3P.slow (DT3P slow)
1A
1B
1B
1B
1B
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
52
4A
4A
4A
4A
56
∆T5B (DT5B)
1E
20
20
20
20
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
40
Internet Data Sheet
Product Type
HYS64T32000HU–3–A
HYS64T64000HU–3–A
HYS72T64000HU–3–A
HYS64T128020HU–3–A
HYS72T128020HU–3–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
57
∆T7 (DT7)
34
23
23
23
23
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
A2
B0
C2
B1
C3
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
37
36
37
74
Product Type, Char 2
34
34
32
34
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
33
36
36
31
31
77
Product Type, Char 5
32
34
34
32
32
78
Product Type, Char 6
30
30
30
38
38
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
30
30
30
32
32
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
41
Internet Data Sheet
Product Type
HYS64T32000HU–3–A
HYS64T64000HU–3–A
HYS72T64000HU–3–A
HYS64T128020HU–3–A
HYS72T128020HU–3–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
5300U–
444
PC2–
5300U–
444
PC2–
5300E–
444
PC2–
5300U–
444
PC2–
5300E–
444
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
81
Product Type, Char 9
48
48
48
30
30
82
Product Type, Char 10
55
55
55
48
48
83
Product Type, Char 11
33
33
33
55
55
84
Product Type, Char 12
41
41
41
33
33
85
Product Type, Char 13
20
20
20
41
41
86
Product Type, Char 14
20
20
20
20
20
87
Product Type, Char 15
20
20
20
20
20
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
7x
9x
9x
9x
9x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
42
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 29
Product Type
HYS64T32000HU–3S–A
HYS64T32900HU–3S–A
HYS64T64000HU–3S–A
HYS64T64900HU–3S–A
HYS72T64000HU–3S–A
HYS[64/72]T[32/64]x00HU-3S-A
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0D
0D
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
60
60
6
Data Width
40
40
40
40
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
30
30
30
30
30
10
45
45
45
45
45
11
Error Correction Support (non-ECC, ECC)
00
00
00
00
02
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
10
10
08
08
08
14
Error Checking SDRAM Width
00
00
00
00
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
01
01
20
DIMM Type Information
02
02
02
02
02
21
DIMM Attributes
00
00
00
00
00
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
43
Internet Data Sheet
Product Type
HYS64T32000HU–3S–A
HYS64T32900HU–3S–A
HYS64T64000HU–3S–A
HYS64T64900HU–3S–A
HYS72T64000HU–3S–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
22
Component Attributes
03
03
03
03
03
23
3D
3D
3D
3D
3D
50
50
50
50
50
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
2D
2D
2D
2D
2D
31
Module Density per Rank
40
40
80
80
80
32
20
20
20
20
20
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
00
00
00
00
00
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
44
50
50
50
50
50
60
60
60
60
60
3C
3C
3C
3C
3C
28
28
1E
1E
1E
3C
3C
3C
3C
3C
27
27
27
27
27
10
10
10
10
10
17
17
17
17
17
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
3C
3C
3C
3C
3C
69
69
69
69
69
80
80
80
80
80
18
18
18
18
18
22
22
22
22
22
Internet Data Sheet
Product Type
HYS64T32000HU–3S–A
HYS64T32900HU–3S–A
HYS64T64000HU–3S–A
HYS64T64900HU–3S–A
HYS72T64000HU–3S–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
46
PLL Relock Time
00
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
55
55
53
53
53
48
Psi(T-A) DRAM
72
72
78
78
78
49
∆T0 (DT0)
5F
5F
4B
4B
4B
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
36
36
39
39
39
51
∆T2P (DT2P)
24
24
26
26
26
52
∆T3N (DT3N)
24
24
26
26
26
53
∆T3P.fast (DT3P fast)
29
29
2B
2B
2B
54
∆T3P.slow (DT3P slow)
1A
1A
1B
1B
1B
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
52
52
4A
4A
4A
56
∆T5B (DT5B)
1E
1E
20
20
20
57
∆T7 (DT7)
31
31
22
22
22
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
12
12
12
12
12
63
Checksum of Bytes 0-62
CA
CA
DE
DE
F0
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
45
Internet Data Sheet
Product Type
HYS64T32000HU–3S–A
HYS64T32900HU–3S–A
HYS64T64000HU–3S–A
HYS64T64900HU–3S–A
HYS72T64000HU–3S–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
36
36
37
74
Product Type, Char 2
34
34
34
34
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
33
33
36
36
36
77
Product Type, Char 5
32
32
34
34
34
78
Product Type, Char 6
30
39
30
39
30
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
30
30
30
30
30
81
Product Type, Char 9
48
48
48
48
48
82
Product Type, Char 10
55
55
55
55
55
83
Product Type, Char 11
33
33
33
33
33
84
Product Type, Char 12
53
53
53
53
53
85
Product Type, Char 13
41
41
41
41
41
86
Product Type, Char 14
20
20
20
20
20
87
Product Type, Char 15
20
20
20
20
20
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
4x
2x
4x
2x
4x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
46
Internet Data Sheet
Product Type
HYS64T32000HU–3S–A
HYS64T32900HU–3S–A
HYS64T64000HU–3S–A
HYS64T64900HU–3S–A
HYS72T64000HU–3S–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300U–
555
PC2–
5300E–
555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
HEX
HEX
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
47
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 30
Product Type
HYS64T128020HU–3S–A
HYS64T128920HU–3S–A
HYS72T128020HU–3S–A
HYS[64/72]T128x20HU-3S-A
Organization
1 GByte
1 GByte
1 GByte
×64
×64
×72
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–5300U–555
PC2–5300U–555
PC2–5300E–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
61
61
61
6
Data Width
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
30
30
30
45
45
45
11
Error Correction Support (non-ECC, ECC)
00
00
02
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
08
08
08
10
14
Error Checking SDRAM Width
00
00
08
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
DIMM Mechanical Characteristics
01
01
01
20
DIMM Type Information
02
02
02
21
DIMM Attributes
00
00
00
22
Component Attributes
03
03
03
23
tCK @ CLMAX -1 (Byte 18) [ns]
3D
3D
3D
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
48
Internet Data Sheet
Product Type
HYS64T128020HU–3S–A
HYS64T128920HU–3S–A
HYS72T128020HU–3S–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
1 GByte
1 GByte
1 GByte
×64
×64
×72
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–5300U–555
PC2–5300U–555
PC2–5300E–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
24
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
50
50
50
50
50
50
25
26
27
28
29
30
60
60
60
3C
3C
3C
1E
1E
1E
3C
3C
3C
2D
2D
2D
31
Module Density per Rank
80
80
80
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
20
20
20
27
27
27
10
10
10
17
17
17
3C
3C
3C
1E
1E
1E
1E
1E
1E
33
34
35
36
37
38
39
Analysis Characteristics
00
00
00
40
00
00
00
3C
3C
3C
69
69
69
80
80
80
18
18
18
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
22
22
22
46
PLL Relock Time
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
53
53
53
48
Psi(T-A) DRAM
78
78
78
49
∆T0 (DT0)
4B
4B
4B
41
42
43
44
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
49
Internet Data Sheet
Product Type
HYS64T128020HU–3S–A
HYS64T128920HU–3S–A
HYS72T128020HU–3S–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
1 GByte
1 GByte
1 GByte
×64
×64
×72
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–5300U–555
PC2–5300U–555
PC2–5300E–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
39
39
39
51
∆T2P (DT2P)
26
26
26
52
∆T3N (DT3N)
26
26
26
53
∆T3P.fast (DT3P fast)
2B
2B
2B
54
∆T3P.slow (DT3P slow)
1B
1B
1B
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
4A
4A
4A
56
∆T5B (DT5B)
20
20
20
57
∆T7 (DT7)
22
22
22
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
12
12
12
63
Checksum of Bytes 0-62
DF
DF
F1
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
37
74
Product Type, Char 2
34
34
32
75
Product Type, Char 3
54
54
54
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
50
Internet Data Sheet
Product Type
HYS64T128020HU–3S–A
HYS64T128920HU–3S–A
HYS72T128020HU–3S–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
1 GByte
1 GByte
1 GByte
×64
×64
×72
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–5300U–555
PC2–5300U–555
PC2–5300E–555
JEDEC SPD Revision
Rev. 1.2
Rev. 1.2
Rev. 1.2
Byte#
Description
HEX
HEX
HEX
76
Product Type, Char 4
31
31
31
77
Product Type, Char 5
32
32
32
78
Product Type, Char 6
38
38
38
79
Product Type, Char 7
30
39
30
80
Product Type, Char 8
32
32
32
81
Product Type, Char 9
30
30
30
82
Product Type, Char 10
48
48
48
83
Product Type, Char 11
55
55
55
84
Product Type, Char 12
33
33
33
85
Product Type, Char 13
53
53
53
86
Product Type, Char 14
41
41
41
87
Product Type, Char 15
20
20
20
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
4x
2x
4x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
51
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 31
Product Type
HYS64T32000HU–3.7–A
HYS64T32900HU–3.7–A
HYS64T64000HU–3.7–A
HYS64T64900HU–3.7–A
HYS72T64000HU–3.7–A
HYS[64/72]T[32/64]x00HU-3.7-A
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200E–
444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0D
0D
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
60
60
6
Data Width
40
40
40
40
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
3D
3D
3D
3D
3D
10
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
50
50
50
50
50
11
Error Correction Support (non-ECC, ECC)
00
00
00
00
02
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
10
10
08
08
08
14
Error Checking SDRAM Width
00
00
00
00
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
38
19
DIMM Mechanical Characteristics
00
00
00
00
00
20
DIMM Type Information
02
02
02
02
02
21
DIMM Attributes
00
00
00
00
00
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
52
Internet Data Sheet
Product Type
HYS64T32000HU–3.7–A
HYS64T32900HU–3.7–A
HYS64T64000HU–3.7–A
HYS64T64900HU–3.7–A
HYS72T64000HU–3.7–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200E–
444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
22
Component Attributes
01
03
01
03
01
23
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
24
25
26
27
28
29
30
3D
3D
3D
3D
3D
50
50
50
50
50
50
50
50
50
50
60
60
60
60
60
3C
3C
3C
3C
3C
28
28
1E
1E
1E
3C
3C
3C
3C
3C
2D
2D
2D
2D
2D
31
Module Density per Rank
40
40
80
80
80
32
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
25
25
25
25
25
33
34
35
36
37
38
37
37
37
37
37
10
10
10
10
10
22
22
22
22
22
3C
3C
3C
3C
3C
1E
1E
1E
1E
1E
1E
1E
1E
1E
1E
39
Analysis Characteristics
00
00
00
00
00
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
00
00
00
00
00
41
42
43
44
45
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
53
3C
3C
3C
3C
3C
69
69
69
69
69
80
80
80
80
80
1E
1E
1E
1E
1E
28
28
28
28
28
Internet Data Sheet
Product Type
HYS64T32000HU–3.7–A
HYS64T32900HU–3.7–A
HYS64T64000HU–3.7–A
HYS64T64900HU–3.7–A
HYS72T64000HU–3.7–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200E–
444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
46
PLL Relock Time
00
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
53
53
51
51
51
48
Psi(T-A) DRAM
72
72
78
78
78
49
∆T0 (DT0)
53
53
3F
3F
3F
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
2B
2B
2E
2E
2E
51
∆T2P (DT2P)
1D
1D
1E
1E
1E
52
∆T3N (DT3N)
1D
1D
1E
1E
1E
53
∆T3P.fast (DT3P fast)
23
23
24
24
24
54
∆T3P.slow (DT3P slow)
16
16
17
17
17
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
36
36
34
34
34
56
∆T5B (DT5B)
1C
1C
1E
1E
1E
57
∆T7 (DT7)
30
30
20
20
20
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
11
12
11
12
11
63
Checksum of Bytes 0-62
BA
BD
D0
D3
E2
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
54
Internet Data Sheet
Product Type
HYS64T32000HU–3.7–A
HYS64T32900HU–3.7–A
HYS64T64000HU–3.7–A
HYS64T64900HU–3.7–A
HYS72T64000HU–3.7–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200E–
444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
36
36
37
74
Product Type, Char 2
34
34
34
34
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
33
33
36
36
36
77
Product Type, Char 5
32
32
34
34
34
78
Product Type, Char 6
30
39
30
39
30
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
30
30
30
30
30
81
Product Type, Char 9
48
48
48
48
48
82
Product Type, Char 10
55
55
55
55
55
83
Product Type, Char 11
33
33
33
33
33
84
Product Type, Char 12
2E
2E
2E
2E
2E
85
Product Type, Char 13
37
37
37
37
37
86
Product Type, Char 14
41
41
41
41
41
87
Product Type, Char 15
20
20
20
20
20
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
5x
2x
5x
2x
5x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
55
Internet Data Sheet
Product Type
HYS64T32000HU–3.7–A
HYS64T32900HU–3.7–A
HYS64T64000HU–3.7–A
HYS64T64900HU–3.7–A
HYS72T64000HU–3.7–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
256MB
512MB
512MB
512MB
×64
×64
×64
×64
×72
1 Rank
(×16)
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
1 Rank
(×8)
Label Code
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200U–
444
PC2–
4200E–
444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
56
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 32
Product Type
HYS64T128020HU–3.7–A
HYS64T128920HU–3.7–A
HYS72T128020HU–3.7–A
HYS[64/72]T128x20HU-3.7-A
Organization
1 GByte
1 GByte
1 GByte
×64
×64
×72
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
PC2–4200U–444
PC2–4200E–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
2
Memory Type (DDR2)
08
08
08
3
Number of Row Addresses
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
5
DIMM Rank and Stacking Information
61
61
61
6
Data Width
40
40
48
7
Not used
00
00
00
8
Interface Voltage Level
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
3D
3D
3D
10
50
50
50
11
Error Correction Support (non-ECC, ECC)
00
00
02
12
Refresh Rate and Type
82
82
82
13
Primary SDRAM Width
08
08
08
14
Error Checking SDRAM Width
00
00
08
15
Not used
00
00
00
16
Burst Length Supported
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
18
Supported CAS Latencies
38
38
38
19
DIMM Mechanical Characteristics
00
00
00
20
DIMM Type Information
02
02
02
21
DIMM Attributes
00
00
00
22
Component Attributes
01
03
01
23
tCK @ CLMAX -1 (Byte 18) [ns]
3D
3D
3D
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
57
Internet Data Sheet
Product Type
HYS64T128020HU–3.7–A
HYS64T128920HU–3.7–A
HYS72T128020HU–3.7–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
1 GByte
1 GByte
1 GByte
×64
×64
×72
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
PC2–4200U–444
PC2–4200E–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
24
50
50
50
50
50
50
60
60
60
30
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
31
Module Density per Rank
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
40
45
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
28
28
28
46
PLL Relock Time
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
51
51
51
25
26
27
28
29
33
34
35
36
37
41
42
43
44
3C
3C
3C
1E
1E
1E
3C
3C
3C
2D
2D
2D
80
80
80
25
25
25
37
37
37
10
10
10
22
22
22
3C
3C
3C
1E
1E
1E
1E
1E
1E
00
00
00
00
00
00
3C
3C
3C
69
69
69
80
80
80
1E
1E
1E
48
Psi(T-A) DRAM
78
78
78
49
∆T0 (DT0)
3F
3F
3F
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
58
Internet Data Sheet
Product Type
HYS64T128020HU–3.7–A
HYS64T128920HU–3.7–A
HYS72T128020HU–3.7–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
1 GByte
1 GByte
1 GByte
×64
×64
×72
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
PC2–4200U–444
PC2–4200E–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
2E
2E
2E
51
∆T2P (DT2P)
1E
1E
1E
52
∆T3N (DT3N)
1E
1E
1E
53
∆T3P.fast (DT3P fast)
24
24
24
54
∆T3P.slow (DT3P slow)
17
17
17
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
34
34
34
56
∆T5B (DT5B)
1E
1E
1E
57
∆T7 (DT7)
20
20
20
58
Psi(ca) PLL
00
00
00
59
Psi(ca) REG
00
00
00
60
∆TPLL (DTPLL)
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
62
SPD Revision
11
12
11
63
Checksum of Bytes 0-62
D1
D4
E3
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
72
Module Manufacturer Location
xx
xx
xx
73
Product Type, Char 1
36
36
37
74
Product Type, Char 2
34
34
32
75
Product Type, Char 3
54
54
54
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
59
Internet Data Sheet
Product Type
HYS64T128020HU–3.7–A
HYS64T128920HU–3.7–A
HYS72T128020HU–3.7–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
1 GByte
1 GByte
1 GByte
×64
×64
×72
2 Ranks (×8)
2 Ranks (×8)
2 Ranks (×8)
Label Code
PC2–4200U–444
PC2–4200U–444
PC2–4200E–444
JEDEC SPD Revision
Rev. 1.1
Rev. 1.2
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
76
Product Type, Char 4
31
31
31
77
Product Type, Char 5
32
32
32
78
Product Type, Char 6
38
38
38
79
Product Type, Char 7
30
39
30
80
Product Type, Char 8
32
32
32
81
Product Type, Char 9
30
30
30
82
Product Type, Char 10
48
48
48
83
Product Type, Char 11
55
55
55
84
Product Type, Char 12
33
33
33
85
Product Type, Char 13
2E
2E
2E
86
Product Type, Char 14
37
37
37
87
Product Type, Char 15
41
41
41
88
Product Type, Char 16
20
20
20
89
Product Type, Char 17
20
20
20
90
Product Type, Char 18
20
20
20
91
Module Revision Code
5x
2x
5x
92
Test Program Revision Code
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
94
Module Manufacturing Date Week
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
99 - 127 Not used
00
00
00
128 255
FF
FF
FF
Blank for customer use
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
60
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
TABLE 33
Product Type
HYS64T32000HU–5–A
HYS64T64000HU–5–A
HYS72T64000HU–5–A
HYS64T128020HU–5–A
HYS72T128020HU–5–A
HYS[64/72]T[32/64/128]0x0HU-5-A
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
0
Programmed SPD Bytes in EEPROM
80
80
80
80
80
1
Total number of Bytes in EEPROM
08
08
08
08
08
2
Memory Type (DDR2)
08
08
08
08
08
3
Number of Row Addresses
0D
0E
0E
0E
0E
4
Number of Column Addresses
0A
0A
0A
0A
0A
5
DIMM Rank and Stacking Information
60
60
60
61
61
6
Data Width
40
40
48
40
48
7
Not used
00
00
00
00
00
8
Interface Voltage Level
05
05
05
05
05
9
tCK @ CLMAX (Byte 18) [ns]
tAC SDRAM @ CLMAX (Byte 18) [ns]
50
50
50
50
50
60
60
60
60
60
11
Error Correction Support (non-ECC, ECC)
00
00
02
00
02
12
Refresh Rate and Type
82
82
82
82
82
13
Primary SDRAM Width
10
08
08
08
08
14
Error Checking SDRAM Width
00
00
08
00
08
15
Not used
00
00
00
00
00
16
Burst Length Supported
0C
0C
0C
0C
0C
17
Number of Banks on SDRAM Device
04
04
04
04
04
18
Supported CAS Latencies
38
38
38
38
38
19
DIMM Mechanical Characteristics
00
00
00
00
00
20
DIMM Type Information
02
02
02
02
02
21
DIMM Attributes
00
00
00
00
00
10
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
61
Internet Data Sheet
Product Type
HYS64T32000HU–5–A
HYS64T64000HU–5–A
HYS72T64000HU–5–A
HYS64T128020HU–5–A
HYS72T128020HU–5–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
22
Component Attributes
01
01
01
01
01
23
50
50
50
50
50
60
60
60
60
60
50
50
50
50
50
60
60
60
60
60
30
tCK @ CLMAX -1 (Byte 18) [ns]
tAC SDRAM @ CLMAX -1 [ns]
tCK @ CLMAX -2 (Byte 18) [ns]
tAC SDRAM @ CLMAX -2 [ns]
tRP.MIN [ns]
tRRD.MIN [ns]
tRCD.MIN [ns]
tRAS.MIN [ns]
31
Module Density per Rank
32
38
tAS.MIN and tCS.MIN [ns]
tAH.MIN and tCH.MIN [ns]
tDS.MIN [ns]
tDH.MIN [ns]
tWR.MIN [ns]
tWTR.MIN [ns]
tRTP.MIN [ns]
39
Analysis Characteristics
40
tRC and tRFC Extension
tRC.MIN [ns]
tRFC.MIN [ns]
tCK.MAX [ns]
tDQSQ.MAX [ns]
tQHS.MAX [ns]
24
25
26
27
28
29
33
34
35
36
37
41
42
43
44
45
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
62
3C
3C
3C
3C
3C
28
1E
1E
1E
1E
3C
3C
3C
3C
3C
28
28
28
28
28
40
80
80
80
80
35
35
35
35
35
47
47
47
47
47
15
15
15
15
15
27
27
27
27
27
3C
3C
3C
3C
3C
28
28
28
28
28
1E
1E
1E
1E
1E
00
00
00
00
00
00
00
00
00
00
37
37
37
37
37
69
69
69
69
69
80
80
80
80
80
23
23
23
23
23
2D
2D
2D
2D
2D
Internet Data Sheet
Product Type
HYS64T32000HU–5–A
HYS64T64000HU–5–A
HYS72T64000HU–5–A
HYS64T128020HU–5–A
HYS72T128020HU–5–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
46
PLL Relock Time
00
00
00
00
00
47
TCASE.MAX Delta / ∆T4R4W Delta
51
51
51
51
51
48
Psi(T-A) DRAM
72
78
78
78
78
49
∆T0 (DT0)
43
33
33
33
33
50
∆T2N (DT2N, UDIMM) or ∆T2Q (DT2Q, RDIMM)
23
24
24
24
24
51
∆T2P (DT2P)
1D
1E
1E
1E
1E
52
∆T3N (DT3N)
19
1B
1B
1B
1B
53
∆T3P.fast (DT3P fast)
1C
1E
1E
1E
1E
54
∆T3P.slow (DT3P slow)
16
17
17
17
17
55
∆T4R (DT4R) / ∆T4R4W Sign (DT4R4W)
2E
28
28
28
28
56
∆T5B (DT5B)
1A
1B
1B
1B
1B
57
∆T7 (DT7)
2D
1E
1E
1E
1E
58
Psi(ca) PLL
00
00
00
00
00
59
Psi(ca) REG
00
00
00
00
00
60
∆TPLL (DTPLL)
00
00
00
00
00
61
∆TREG (DTREG) / Toggle Rate
00
00
00
00
00
62
SPD Revision
11
11
11
11
11
63
Checksum of Bytes 0-62
02
1A
2C
1B
2D
64
Manufacturer’s JEDEC ID Code (1)
7F
7F
7F
7F
7F
65
Manufacturer’s JEDEC ID Code (2)
7F
7F
7F
7F
7F
66
Manufacturer’s JEDEC ID Code (3)
7F
7F
7F
7F
7F
67
Manufacturer’s JEDEC ID Code (4)
7F
7F
7F
7F
7F
68
Manufacturer’s JEDEC ID Code (5)
7F
7F
7F
7F
7F
69
Manufacturer’s JEDEC ID Code (6)
51
51
51
51
51
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
63
Internet Data Sheet
Product Type
HYS64T32000HU–5–A
HYS64T64000HU–5–A
HYS72T64000HU–5–A
HYS64T128020HU–5–A
HYS72T128020HU–5–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
70
Manufacturer’s JEDEC ID Code (7)
00
00
00
00
00
71
Manufacturer’s JEDEC ID Code (8)
00
00
00
00
00
72
Module Manufacturer Location
xx
xx
xx
xx
xx
73
Product Type, Char 1
36
36
37
36
37
74
Product Type, Char 2
34
34
32
34
32
75
Product Type, Char 3
54
54
54
54
54
76
Product Type, Char 4
33
36
36
31
31
77
Product Type, Char 5
32
34
34
32
32
78
Product Type, Char 6
30
30
30
38
38
79
Product Type, Char 7
30
30
30
30
30
80
Product Type, Char 8
30
30
30
32
32
81
Product Type, Char 9
48
48
48
30
30
82
Product Type, Char 10
55
55
55
48
48
83
Product Type, Char 11
35
35
35
55
55
84
Product Type, Char 12
41
41
41
35
35
85
Product Type, Char 13
20
20
20
41
41
86
Product Type, Char 14
20
20
20
20
20
87
Product Type, Char 15
20
20
20
20
20
88
Product Type, Char 16
20
20
20
20
20
89
Product Type, Char 17
20
20
20
20
20
90
Product Type, Char 18
20
20
20
20
20
91
Module Revision Code
5x
5x
5x
5x
5x
92
Test Program Revision Code
xx
xx
xx
xx
xx
93
Module Manufacturing Date Year
xx
xx
xx
xx
xx
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
64
Internet Data Sheet
Product Type
HYS64T32000HU–5–A
HYS64T64000HU–5–A
HYS72T64000HU–5–A
HYS64T128020HU–5–A
HYS72T128020HU–5–A
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Organization
256MB
512MB
512MB
1 GByte
1 GByte
×64
×64
×72
×64
×72
1 Rank
(×16)
1 Rank
(×8)
1 Rank
(×8)
2 Ranks
(×8)
2 Ranks
(×8)
Label Code
PC2–
3200U–
333
PC2–
3200U–
333
PC2–
3200E–
333
PC2–
3200U–
333
PC2–
3200E–
333
JEDEC SPD Revision
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Rev. 1.1
Byte#
Description
HEX
HEX
HEX
HEX
HEX
94
Module Manufacturing Date Week
xx
xx
xx
xx
xx
95 - 98
Module Serial Number
xx
xx
xx
xx
xx
99 - 127 Not used
00
00
00
00
00
128 255
FF
FF
FF
FF
FF
Blank for customer use
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
65
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
5
Package Outlines
This chapter contains the package outlines of the products.
FIGURE 6
! " #
Package Outline Raw Card A L-DIM-240-1
-!8
›
›
#
›
›
›
›
›
›
›
›
!
›
"
-).
›
$ETAIL OF CONTACTS
›
! " #
/N %## MODULES ONLY
"URR MAX ALLOWED
',$
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
66
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 7
! " #
Package Outline Raw Card B L-DIM-240-2
-!8
›
›
#
›
›
›
›
›
›
›
›
!
›
"
-).
›
$ETAIL OF CONTACTS
›
! " #
/N %## MODULES ONLY
"URR MAX ALLOWED
',$
Notes
1.
2.
3.
4.
The chip is only found on ECC modules.
Drawing according to ISO 8015
Dimensions in mm
General tolerances +/- 0.15
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
67
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 8
Package Outline Raw Card C L-DIM-240-3
! " #
-!8
X
#
›
›
!
›
"
›
$ETAIL OF CONTACTS
›
! " #
"URR MAX ALLOWED
',$
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
68
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 9
’ ! " #
Package Outline L-DIM-240-8
-!8
›
›
#
›
›
›
›
›
›
›
›
!
›
"
-).
›
$ETAIL OF CONTACTS
›
! " #
"URR MAX ALLOWED
',$
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
69
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 10
’ ! " #
Package Outline L-DIM-240-9
-!8
›
›
#
›
›
›
›
›
›
›
›
!
›
"
-).
›
$ETAIL OF CONTACTS
›
! " #
"URR MAX ALLOWED
',$
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
70
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 11
’ ! " #
Package Outline Raw Card F L-DIM-240-6
-!8
›
›
#
›
›
›
›
›
›
›
›
!
›
"
-).
›
$ETAIL OF CONTACTS
›
! " #
"URR MAX ALLOWED
',$
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
71
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
FIGURE 12
’ ! " #
Package Outline Raw Card G L-DIM-240-7
-!8
›
›
#
›
›
›
›
›
›
›
›
!
›
"
-).
›
$ETAIL OF CONTACTS
›
! " #
"URR MAX ALLOWED
',$
Notes
1. Drawing according to ISO 8015
2. Dimensions in mm
3. General tolerances +/- 0.15
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
72
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
6
Product Type Nomenclature
Qimonda´s nomenclature uses simple coding combined with some propriatory coding. Table 34 provides examples for module
and component product type number as well as the field number. The detailed field description together with possible values
and coding explanation is listed for modules in Table 35 and for components in Table 36.
TABLE 34
Nomenclature Fields and Examples
Example for
Field Number
1
2
3
4
5
6
7
8
9
10
11
Micro-DIMM
HYS
64
T
64/128
0
2
0
K
M
–5
–A
DDR2 DRAM
HYB
18
T
512/1G 16
0
A
C
–5
TABLE 35
DDR2 DIMM Nomenclature
Field
Description
Values
Coding
1
Qimonda Module Prefix
HYS
Constant
2
Module Data Width [bit]
64
Non-ECC
72
ECC
3
DRAM Technology
T
DDR2
4
Memory Density per I/O [Mbit];
Module Density1)
32
256 MByte
64
512 MByte
128
1 GByte
256
2 GByte
512
4 GByte
5
Raw Card Generation
0 .. 9
Look up table
6
Number of Module Ranks
0, 2, 4
1, 2, 4
7
Product Variations
0 .. 9
Look up table
8
Package, Lead-Free Status
A .. Z
Look up table
9
Module Type
D
SO-DIMM
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
M
Micro-DIMM
R
Registered
U
Unbuffered
F
Fully Buffered
73
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Field
Description
Values
Coding
10
Speed Grade
–2.5F
PC2–6400 5–5–5
–2.5
PC2–6400 6–6–6
11
Die Revision
–3
PC2–5300 4–4–4
–3S
PC2–5300 5–5–5
–3.7
PC2–4200 4–4–4
–5
PC2–3200 3–3–3
–A
First
–B
Second
1) Multiplying “Memory Density per I/O” with “Module Data Width” and dividing by 8 for Non-ECC and 9 for ECC modules gives the overall
module memory density in MBytes as listed in column “Coding”.
TABLE 36
DDR2 DRAM Nomenclature
Field
Description
Values
Coding
1
2
Qimonda Component Prefix
HYB
Constant
Interface Voltage [V]
18
SSTL_18
3
DRAM Technology
T
DDR2
4
Component Density [Mbit]
256
256 Mbit
512
512 Mbit
1G
1 Gbit
2G
2 Gbit
40
×4
80
×8
16
×16
0 .. 9
Look up table
5+6
Number of I/Os
7
Product Variations
8
Die Revision
9
10
Package, Lead-Free Status
Speed Grade
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
A
First
B
Second
C
FBGA, lead-containing
F
FBGA, lead-free
–25F
DDR2-800 5-5-5
–2.5
DDR2-800 6-6-6
–3
DDR2-667 4-4-4
–3S
DDR2-667 5-5-5
–3.7
DDR2-533 4-4-4
–5
DDR2-400 3-3-3
74
Internet Data Sheet
HYS[64/72]T[32/64/128]xx0HU–[3/3S/3.7/5]–A
Unbuffered DDR2 SDRAM Modules
Table of Contents
1
1.1
1.2
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2
Pin Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
3
3.1
3.2
3.3
3.3.1
3.3.2
3.3.3
3.4
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
DC Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Speed Grade Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
AC Timing Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
ODT AC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Currents Specifications and Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16
16
17
18
18
20
31
32
4
SPD Codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
5
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
6
Product Type Nomenclature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Rev. 1.41, 2007-05
03292006-EZUJ-JY4S
75
Internet Data Sheet
Edition 2007-05
Published by Qimonda AG
Gustav-Heinemann-Ring 212
D-81739 München, Germany
© Qimonda AG 2007.
All Rights Reserved.
Legal Disclaimer
The information given in this Internet Data Sheet shall in no event be regarded as a guarantee of conditions or characteristics
(“Beschaffenheitsgarantie”). With respect to any examples or hints given herein, any typical values stated herein and/or any
information regarding the application of the device, Qimonda hereby disclaims any and all warranties and liabilities of any kind,
including without limitation warranties of non-infringement of intellectual property rights of any third party.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest Qimonda Office.
Warnings
Due to technical requirements components may contain dangerous substances. For information on the types in question please
contact your nearest Qimonda Office.
Qimonda Components may only be used in life-support devices or systems with the express written approval of Qimonda, if a
failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect
the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human
body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health
of the user or other persons may be endangered.
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