ETC1 M512X Mega i/o controller with plug & play Datasheet

Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
M512x : Mega I/O Controller with Plug & Play
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Supports Windows 95 Plug and Play
Supports 2 serial/1 parallel/FDC/RTC/KB and PS/2 mouse functions
Supports 22 General Purpose I/O pins
Enhanced ESD/LATCH up to over 4KV/300 mA
Supports SPP, PS/2, EPP, ECP and 1284 compliance
Supports 5 GPIO Alternative function pins for Remote Control
Supports IR via UART1, UART2 and two additional IR pins
Supports Fast Gate A20 and RC functions
Supports KBC and RTC enable/disable functions
Single-chip Notebook/Desktop solution
n
FEATURES
n
Supports Windows 95 Plug-and-Play
n
Supports 2 Serial / 1 Parallel / FDC / RTC / KB / PS/2
Mouse functions
n
Supports ECP/ EPP / PS/2 / SPP and 1284 Compliance
- IBM PC/XT, PC/AT and PS/2 compatible Bi-directional
parallel port
Supports 22 General Purpose I/O pins
- Enhanced Parallel Port (EPP) compatible
- 3 GPIO ports (Ports 1, 2, 3)
- Microsoft and Hewlett Packard Extended Capabilities Port
- 5 GPIO-ALT function pins for Remote Control (Pins 30-34)
- 2 General Purpose chip select pins (Pins 24-25)
(ECP) compatible
n
2
- Supports I C Control Pins
n
Various modes of Parallel Port
- Two high performance 16550 compatible UARTs with
send/receive 16-byte FIFOs
2.88 MB Floppy Disk Controller
- Serial Infra Red (SIR) for wireless communications
- Software compatible with 82077 and supports 16-byte
- MIDI (Musical Instrument Digital Interface) compatible
data FIFOs
- High performance internal data separator
- Supports standard 1 Mbps / 500 Kbps / 300 Kbps / 250
Kbps data rate
Serial ports
n
High performance Power Management for FDC, UART
and Parallel Port
n
Supports XD-To-SD Bus Buffer and Control Pins
n
Supports Enable/Disable KBC and RTC
- Supports 3 modes of 3.5" FDD (720K/1.2M/1.44MB)
n
Supports Fast Gate A20 and RC function
- Swappable drives A and B
n
Supports External KBC programming pin functions
n
Supports FDC through Parallel Port pins
n
Supports additional IrDA and ASK IR Pins
n
Supports AT PS/2 KB and PS/2 Mouse
n
Supports Phoenix KBC (M5123), AMI KBC(M5125)
n
Built-in Keyboard Controller and Real Time Clock
n
160-pin PQFP package
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
Page 1
Fax: 762-6060
--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Table of Contents :
Section 1 : Introduction .............................................................................................................. 3
1.1 Features and Function ................................................................................................ 3
1.2 Block Diagram............................................................................................................ 4
1.3 Register Overview ...................................................................................................... 5
Section 2 : Pin Description ......................................................................................................... 6
2.1 Pinout Diagram .......................................................................................................... 6
2.2 Pin Description ........................................................................................................... 7
2.3 Numerical Pin List ...................................................................................................... 13
2.4 Alphabetical Pin List ................................................................................................... 15
Section 3 : Configuration Description and Power Management Features ................................ 17
3.1 Configuration Port ...................................................................................................... 17
3.2 Power Management Features ..................................................................................... 29
Section 4 : Floppy Disk Controller.............................................................................................. 31
4.1 Register Overview ...................................................................................................... 31
4.2 Register Description ................................................................................................... 32
4.3 Result Phase Status Registers.................................................................................... 39
4.4 Processor Software Interface ...................................................................................... 41
4.5 Command Set Descriptions ........................................................................................ 42
4.6 Command Description Table ...................................................................................... 51
Section 5 : Serial Port Registers ................................................................................................ 58
5.1 Line Control Register .................................................................................................. 60
5.2 Programmable Baud Generator .................................................................................. 61
5.3 Line Status Register ................................................................................................... 61
5.4 Interrupt Identification Register ................................................................................... 62
5.5 Interrupt Enable Register ............................................................................................ 63
5.6 FIFO Control Register................................................................................................. 63
5.7 Modem Control Register ............................................................................................. 64
5.8 Modem Status Register .............................................................................................. 65
5.9 Scratchpad Register ................................................................................................... 65
5.10 Infrared Interface ....................................................................................................... 65
Section 6 : Keyboard Controller and Real Time Clock Functional Description ........................ 66
6.1 Keyboard and RTC lSA Interface ................................................................................ 66
6.2 Keyboard Controller.................................................................................................... 66
6.3 Real Time Clock ......................................................................................................... 73
Section 7 : BIOS .......................................................................................................................... 79
7.1 BIOS Buffer ................................................................................................................ 79
Section 8 : Parallel Port .............................................................................................................. 80
8.1 Parallel Port Interface ................................................................................................. 80
8.2 IBM XT/AT compatible, Bi-directional and EPP modes................................................ 81
Section 9 : Common I/O Ports .................................................................................................... 95
Section 10 : Electrical Characteristics ....................................................................................... 99
10.1 Absolute Maximum Ratings ........................................................................................ 99
10.2 DC Characteristics...................................................................................................... 99
10.3 AC Characteristics...................................................................................................... 101
10.4 AC Test Conditions..................................................................................................... 102
Section 11 : Packaging Information ........................................................................................... 120
Section 12 : Ordering Information.............................................................................................. 121
Section 13 : Revision History ..................................................................................................... 122
Worldwide Distributors and Sales Offices ................................................................................. 123
Page 2
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Section 1 : Introduction
Features and Functions
The Acer Labs' M512x chip has two full-function universal
asynchronous receiver/ transmitters (UARTs), a keyboard
interface, real time clock, a floppy disk controller (FDC) with
data separator, parallel port, standard XT/AT address
decoding for on-chip functions, and a configuration register.
It offers a single-chip solution to the most common IBM PC,
XT, AT and Notebook peripherals.
The floppy disk controller is fully compatible with the
industry-standard 765A and 82077SL architecture.
It
includes more advanced options such as a high
performance data separator, extended track range to 4096,
high performance power management, implied seek
command, scan command, and supports both IBM and ISO
360K/1.2M/720K/1.44M/2.88M FDD formats. The UARTs
are compatible with either the INS8250N-B, NS16450 and
16550. It has complete compatibility with the IBM AT's
parallel port. The configuration register is one-byte wide
and can be programmed via hardware or software. By
controlling this register, the user can assign standard AT
addresses and disable any major on-chip function (e.g., the
FDC, either UART, or the parallel port) independent of the
others. This allows for flexibility in system configuration
when adapter boards contain duplicate functions.
The M512x provides support for the ISA Plug-and-Play
standard and recommended functionality to support
Windows ‘ 95. Through internal configuration registers,
each of the M512x’ s logic device’ s I/O address, DMA
channel and IRQ channel may be programmed. There are
96 I/O address location options, 13 IRQ options, and three
DMA channel options for each logical device except KBC
and RTC. KBC’ s I/O address is not routable. RTC’ s I/O
address and IRQ are not routable as well.
1.2 M512x Block Diagrams
The following figures show the overall block diagram of the
M512x.
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
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--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
ISA Bus
interface
Floppy
disk
interface
BIOS
Buffer
Common
I/O
Figure 1-1
Page 4
SD0-SD7
IORJ
IOWJ
AEN
SA0-SA15
DACK0J-DACK3J
DRQ0-DRQ3
TC
IRQ1,IRQ3-12,IRQ14-15
MR
RDATAJ
WGATEJ
WDATAJ
HDSELJ
DIRJ
STEPJ
DSKCHGJ
DRV0-1
PDIR
MOT0-1
WPJ
TRK0J
DENSEL
INDEXJ
ROMOEJ
ROMCSJ
RD0-7
CIO 10-17,20-25,30-34
ALi
M512x
SIN1, SOUT1
RTS1J
DTR1J
CTS1J
DSR1J
DCD1J
RI1J
SIN2,SOUT2
RTS2J
DTR2J
CTS2J
DSR2J
DCD2J
RI2J
AUTOFDJ
INITJ
SLCTINJ
STROBEJ
BUSY
ACKJ
PE
SLCT
ERRORJ
IOCHRDY
PD0-PD7
XTAL1,2
VBAT
PWG
KDAT,KCLK
MDAT,MCLK
Serial port 1
Serial port 2
Printer port
interface
RTC
KBC
M512x Block Diagram
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
1.3 Register Overview
Table 1-1
I/O Address Decode
Address Range
Base + (0-5) and + (7)
Base + (0-7)
Base + (0-7)
Base + (0-3)
Base + (0-7)
Base + (0-3), + (400-402)
Base + (0-7), + (400-402)
0x60, 0x64
0x70, 0x71
Block Name
Floppy Disk
Serial Port COM1
Serial Port COM2
Parallel port
SPP
EPP
ECP
ECP+EPP+SPP
KBC
RTC
Logical Device
0
4
5
3
Function
IR support
IR support
7
6
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
Page 5
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--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Section 2 : Pin Description
2.1 Pinout Diagram
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
GND
DRVDEN0
DRVDEN1
MOT0J
DRV1J
DRV0J
MOT1J
GND
DIRJ
STEPJ
WDATAJ
WGATEJ
HDSELJ
INDEXJ
TRK0J
WPROTJ
RDATAJ
DSKCHGJ
MID1
MID0
VDD
14CLKI
CIO30/KBCCLK
CIO31/CS0J
CIO32/CS1J
PDIR/PS2DRV
SA[13]
SA[14]
SA[15]
CIO33/ALT_KCLK
CIO34/ALT_KDAT
CIO35/ALT_MCLK
CIO36/ALT_MDAT
CIO37/ALT_KBC
X24TAL1
X24TAL2
CLK01
CLK02
ROMOEJ
GND
ALi
M512x
PWG
ROMCSJ
RD7
RD6
RD5
RD4
RD3
RD2
RD1
RD0
CIO25
CIO24
CIO23
CIO22
CIO21
CIO20
CIO17/I2C_DAT
CIO16/I2C_CLK
CIO15/P20
VDD
CIO14/P21
CIO13/IRTX
CIO12/IRRX
CIO11/IRQIN2
CIO10/IRQIN1
GND
MCLK
MDAT
KCLK
KDAT
IOCHRDY
TC
DRQ3
DACK3J
DRQ2
DACK2J
DRQ1
DACK1J
DRQ0
DACK0J
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
Figure 2-1. M512x Pin Diagram
Page 6
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
2.2 Pin Description
Table 2-1 lists the functions of all M512x pins. A low represents a logic 0 (0V nominal) and a high represents a logic 1 (+2.4V
nominal).
Table 2-1
M512x Pin Description Table
Name
Number
HOST Processor Interface
SD0-SD7
70-72
Type
Description
I/O
IORJ
68
I
IOWJ
69
I
AEN
70
I
SA0-SA15
41-53, 27-29
I
DACK0JDACK3J
DRQ0DRQ3
81,83,85,87
I
82,84,86,88
O
TC
89
I
IRQ1,
IRQ3-12,
IRQ14-15
67,66,65,64,
63,62,61,59,
58,57,56,55,
54
80
O
Data bus. These signals are used by the host microprocessor to transmit data
to and from the M512x. These pins are in high impedance state when not in the
output mode.
I/O Read. This active low signal is issued by the host microprocessor to
indicate a read operation.
I/O Write. This active low signal is issued by the host microprocessor to
indicate a write operation.
Address Enable. This active high signal indicates DMA operations on the host
data bus.
I/O Address. These bits determine the I/O address to be accessed during IORJ
and IOWJ cycles.
DMA Acknowledge. An active low input signal acknowledging the request for a
DMA data transfer. This input enables the DMA read or write internally.
DMA request. This active high output is the DMA request for byte transfers of
data to the host. This signal is cleared on the last byte of the data transfer by
the DACKJ signal going low.
Terminal Count. This signal indicates to the M512x that data transfer is
complete. TC is only accepted when DACKJ is low. TC is active high in AT
mode and active low in PS/2 mode.
Interrupt Requests.
MR
IS
Reset. This active high signal resets the M512x and must be valid for 500 ns
minimum. In M512x, the falling edge of reset latches the jumper configuration.
The jumper select lines must be valid 50 ns prior to this edge.
Floppy Disk Interface
RDATAJ
17
IS
WGATEJ
12
O
WDATAJ
11
O
HDSELJ
13
O
DIRJ
9
O
STEPJ
10
O
DSKCHGJ
18
IS
Read Disk Data. This raw data read signal from the disk is connected here.
Each falling edge represents a flux transition of the encoded data.
Write Gate. This active-low, high-drive output enables the write circuitry of the
selected disk drive. This signal prevents glitches during power-up and powerdown. Unstable power prevents writing to the disk.
Write Data. This active low output is a write- precompensated serial data to be
written onto the selected disk drive. Each falling edge causes a flux change on
the media.
Head Select. This active low output determines which disk drive head is active.
Low = Head 0, high (open) = Head 1.
Direction. This active low output determines the direction of the head
movement (low = step-in, high = step-out). During write or read modes, this
output is high.
Step. This active low signal produces a pulse to move the head during a seek
operation.
Disk Change. This disk interface signal indicates when the disk drive door is
open. This signal is read from bit D7 of address xx7h.
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
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M512x : Mega I/O Controller with PnP
Table 2-1
M512x Pin Description Table (continued)
Name
Number
Type
Description
Floppy Disk Interface :
DRV0J,
6, 5
O
Drive Select 0, 1. Active low, output select drives 0-1.
DRV1J
PDIR
26
O
This bit is used to indicate the direction of the Parallel port data bus.
0= output/write, 1= input / read.
PS2DRV
I
Drive 2. In PS/2 mode, this input indicates whether a second drive is connected;
this signal should be low if a second drive is connected. This status is reflected in
a read of Status Register A.
MID0-1
20,19
IS
Media ID inputs. In floppy enhanced mode, these inputs are the media ID inputs.
MOT0J,
4, 7
O
Motor on 0, 1. These active-low outputs select motor drives 0-1.
MOT1J
WPROTJ
16
IS
Write Protected. This active-low Schmitt Trigger input senses from the disk drive
that a disk is write-protected. Any write command is ignored.
TRK0J
15
IS
Track 00. This Schmitt Trigger input signal senses from the disk drive that the
head is positioned over the outermost track.
INDEXJ
14
IS
Index. This active low Schmitt Trigger input senses from the disk drive that the
head is positioned over the beginning of a track, as marked by an index hole.
DRVDEN
2-3
O
Data Rate 0-1. This output reflects bits 0-1 of the Data Rate Register.
0-1
Serial Port Interface :
SIN1, SIN2 145,155
I
Receive Data. Receiver serial data input.
SOUT1,
146,156
O
Transmit Data. Transmitter serial data output from Serial Port.
SOUT2
RTS1J
148
O
Request to send. Active low Request to send output for Primary Serial port.
Handshake output signal notifies modem that the UART is ready to transmit data.
This signal can be programmed by writing to bit 1 of Modem Control Register
(MCR). The hardware reset will clear the RTSJ signal to inactive mode (high).
Forced inactive during loop mode operation.
CFGPORT
I
Configuration port select. During reset active, this input is read and latched to
define the configuration register’ s base address.
RTS2J
158
O
Request to send. This active low signal for Secondary Serial Port. Handshake
output signal notifies modem that the UART is ready to transmit data. This signal
can be programmed by writing to bit 1 of Modem Control Register (MCR). The
hardware reset will clear the RTSJ signal to inactive mode (high). Forced inactive
during loop mode operation.
KBC_EN
I
KBC enable control. During reset active, this input is read and latched to enable
KBC after reset. The signal can be overwritten by configuration register.
DTR1J
150
O
Data Terminal Ready. This is an active low output for primary serial port.
Handshake output signal signifies to modem that the UART is ready to establish
data communication link. This signal can be programmed by writing to bit 0 of
Modem Control Register (MCR). The hardware reset will clear the DTRJ signal to
inactive during loop mode operation.
RTC_EN
I
RTC enable control. During reset active, this input is read and latched to enable
RTC after reset. This signal can be overwritten by configuration register.
Page 8
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Table 2-1
M512x Pin Description Table (continued)
Name
Number
Type
Description
Serial Port Interface :
DTR2J
160
O
Data Terminal Ready. This active low output is for secondary serial port.
Handshake output signal notifies modem that the UART is ready to establish
data communication link. This signal can be programmed by writing to bit 0 of
Modem Control Register (MCR). The hardware reset will clear the DTRJ signal
to inactive mode (high). Forced inactive during loop mode operation.
PS2_ATJ
I
KBC PS2 mode or AT mode select. When active, this input is read and
latched to define the KBC PS-2 or AT mode.
CTS1J
149, 159
I
Clear to Send. This active low input for primary and secondary serial ports.
CTS2J
Handshake signal which notifies the UART that the modem is ready to receive
data. The CPU can monitor the status of CTSJ signal by reading bit 4 of
Modem Status Register (MSR). A CTSJ signal state is directly comparative with
the MSR bit after the last MSR read. If bit 3 of Interrupt Enable Register is set,
the interrupt is generated when CTSJ changes state. The CTSJ signal has no
effect on the transmitter. Note : Bit 4 of MSR is the complement of CTSJ.
DSR1J
147, 157
I
Data Set Ready. This active low input is for primary and secondary serial
DSR2J
ports. Handshake signal which notifies the UART that the modem is ready to
establish the communication link. The CPU can monitor the status of DSRJ
signal by reading bit5 of Modem Status Register (MSR). A DSRJ signal state
change from low to high after the last MSR read will raise the MSR bit 1. If bit 3
of Interrupt Enable Register is set, the interrupt is generated when DSRJ
changes state. Note: Bit 5 of MSR is the complement of DSRJ.
DCD1J,
152, 154
I
Data Carrier Detect. This active low input is for primary and secondary serial
DCD2J
ports. Handshake signal which notifies the UART that carrier signal is detected
by the modem. The CPU can monitor the status of DCDJ signal by reading bit
7 of Modem Status Register (MSR). A DCDJ signal state rises after the last
MSR read will raise MSR bit 3. If bit 3 of Interrupt Enable Register is set, the
interrupt is generated when DCDJ changes state. Note : bit 7 of MSR is the
complement of DCDJ.
RI1J, RI2J
151, 153
I
Ring Indicator. This active low input is for primary and secondary serial ports.
Handshake signal that notifies the UART that the telephone ring signal is
detected by the modem. The CPU can monitor the status of RIJ signal by
reading bit 6 of Modem Status Register (MSR). A risen RIJ signal state after the
last MSR read will raise MSR bit 2 to a 1. If bit 3 of Interrupt Enable Register is
set, the interrupt is generated when RIJ changes state. Note : bit 6 of MSR is
the complement of RIJ.
07-02-1997 Document Number: 512xDS02.doc
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M512x : Mega I/O Controller with PnP
Table 2-1
M512x Pin Description Table (continued)
Name
Number
Type
Description
Printer Port Interface
AUTOFDJ
143
O
Autofeed Output. This active low output causes the printer to automatically
feed one line after each line is printed. This signal is the complement of bit 1 of
the Printer Control Register.
INITJ
141
O
Initiate Output. This active low signal is bit 2 of the printer control register.
This signal is used to initialize the printer.
SLCTINJ
140
O
Printer select input. This active low signal selects the printer. This is the
complement of bit 3 of the Printer Control Register.
STROBEJ
144
O
Strobe Output. This active low pulse is used to strobe the printer data into the
printer. This output signal is the complement of bit 0 of the Printer Control
Register.
BUSY
128
IS
Busy. This signal indicates the status of the printer. A high indicates the printer
is busy and not ready to receive new data. Bit 7 of the Printer Status Register is
the complement of the BUSY input.
ACKJ
129
IS
Acknowledge. This active low signal from the printer indicates it has received
the data and is ready to accept new data. Bit 6 of the Printer Status Register
reads the ACKJ input.
PE
127
IS
Paper End. This signal indicates that the printer is out of paper. Bit 5 of the
Printer Status Register reads the PE input.
SLCT
126
IS
Printer Selected Status. This active high signal from the printer indicates that
it has power on. Bit 4 of the Printer Status Register reads the SLCT input.
ERRORJ
142
I
Error. This active low signal indicates an error condition at the printer.
PD0-PD7
138-131
I/O
Port Data. This bi-directional parallel data bus is used to transfer information
between CPU and peripherals.
IOCHRDY
90
OD
IOCHRDY. In EPP mode, this pin is pulled low to extend the read/write
command.
Real-Time Clock
XTAL1
122
ICLK
32Khz Crystal Input.
XTAL2
124
OCLK
32Khz Crystal Output.
VBAT
121
P
Battery Voltage.
PWG
120
IS
Power Good Input.
Keyboard Controller
KDAT
91
I/O
Keyboard Data.
KCLK
92
I/O
Keyboard Clock.
MDAT
93
I/O
Mouse Data.
MCLK
94
I/O
Mouse Clock.
Page 10
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Table 2-1
M512x Pin Description Table (continued)
Name
Number
Type
Description
BIOS Buffer :
ROMOEJ
39
IS
ROM Output Enable.
ROMCSJ
119
IS
ROM Chip Select.
RD0-7
111-118
I/O
ROM Bus.
Common I/O :
CIO10-11
96-97
I/O
Common I/O pin.
I
IRQ In.
CIO12
98
I/O
Common I/O pin.
I
IRRX.
CIO13
99
I/O
Common I/O pin.
O
IRTX.
CIO14
100
I/O
Common I/O pin.
O
KBC P21 function.
CIO15
102
I/O
Common I/O pin.
O
KBC P20 function.
CIO16
103
I/O
Common I/O pin.
O
I2C_CLK.
CIO17
104
I/O
Common I/O pin.
I/O
I2C_DAT.
CIO20-24
105-109
I/O
Common I/O pin.
CIO25
110
I/O
Common I/O pin.
I
KEYLOCKJ.
CIO30
23
I/O
Common I/O pin.
I
KBC_CLK.
CIO31
24
I/O
Common I/O pin.
O
General Chip Select decoder CS0J.
CIO32
25
I/O
Common I/O pin.
O
General Chip Select decoder CS1J.
CIO33
30
I/O
Common I/O pin.
O
Alternative Keyboard Clock.
CIO34
31
I/O
Common I/O pin.
O
Alternative Keyboard Data.
CIO35
32
I/O
Common I/O pin.
O
Alternative Mouse Clock.
CIO36
33
I/O
Common I/O pin.
O
Alternative Mouse Data.
CIO37
34
I/O
Common I/O pin.
I
Alternative KBC select.
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
Page 11
Fax: 762-6060
--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Table 2-1
M512x Pin Description Table (continued)
Name
Number
Type
Description
Miscellaneous
X24TAL1
35
ICLK
Clock 1. This is an external connection for a parallel resonant 24 MHz crystal.
A CMOS compatible oscillator is required if crystal is not used.
X24TAL2
36
OCLK
Clock 2. This is a 24 MHz crystal. If an external clock is used, this pin should
not be connected. This pin should not be used to drive any other drivers.
X14CLKI
22
I
Clock 14 In. This is a 14.318 MHz clock source in.
XCLKO1
37
O
Clock 14 out. This is a 14.318 MHz clock out.
XCLKO2
38
O
Clock 14 out. This is the second 14.318 MHz clock out.
Power Pins
Vcc
21,60,101,
P
Power. +5 Volt supply pin.
125,139
Vss
1,8,40,71,95, P
Ground pins.
123,130
Type Description :
I
IS
ICLK
OCLK
O4
OD24
Page 12
Input TTL compatible.
Input with Schmitt Trigger.
CLK input.
CLK output.
Output with 4 mA sink @ 0.4 V, source 4 mA @ 2.4 V.
Open drain outputs, sinks 24 mA @ 0.4 V.
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
2.3 Numerical Pin List
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
Pin No.
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
Pin Name
SA0
SA1
SA2
SA3
SA4
SA5
SA6
SA7
SA8
SA9
SA10
SA11
SA12
IRQ15
IRQ14
IRQ12
IRQ11
IRQ10
IRQ9
Vcc
IRQ8
IRQ7
IRQ6
IRQ5
IRQ4
IRQ3
IRQ1
IORJ
IOWJ
AEN
Vss
SD0
SD1
SD2
SD3
SD4
SD5
SD6
SD7
MR
07-02-1997 Document Number: 512xDS02.doc
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Fax: 762-6060
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
Pin Name
Vss
DRVDEN0
DRVDEN1
MOT0J
DRV1J
DRV0J
MOT1J
Vss
DIRJ
STEPJ
WDATAJ
WGATEJ
HDSELJ
INDEXJ
TRK0J
WPROTJ
RDATAJ
DSKCHGJ
MID1
MID0
Vcc
X14CLKI
CIO30/
KBC_CLK
CIO31/CS0J
CIO32/CS1J
PDIR/PS2DRV
SA13
SA14
SA15
CIO33/
ALT_KCLK
CIO34/
ALT_KDAT
CIO35/
ALT_MCLK
CIO36/
ALT_MDAT
CIO37/
ALT_KBC
X24TAL1
X24TAL2
XCLKO1
XCLKO2
ROMOEJ
Vss
Type
P
O
O
O
O
O
O
P
O
O
O
O
O
IS
IS
IS
IS
IS
IS
IS
P
I
I/O
I/O
I/O
I/O
IS
IS
IS
I/O
I/O
I/O
I/O
I/O
ICLK
OCLK
O
O
IS
P
Type
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
O
O
O
O
O
O
P
O
O
O
O
O
O
O
IS
IS
IS
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IS
Page 13
--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Numerical Pin List (continued)
Pin No.
Pin Name
81
DACK0J
82
DRQ0
83
DACK1J
84
DRQ1
85
DACK2J
86
DRQ2
87
DACK3J
88
DRQ3
89
TC
90
IOCHRDY
91
KDAT
92
KCLK
93
MDAT
94
MCLK
95
Vss
96
CIO10/IRQIN1
97
CIO11/IRQIN2
98
CIO12/IRRX
99
CIO13/IRTX
100
CIO14/GA20
101
Vcc
102
CIO15/KBRCJ
103
CIO16/I2C_CLK
104
CIO17/I2C_DAT
105
CIO20
106
CIO21
107
CIO22
108
CIO23
109
CIO24
110
CIO25
111
RD0
112
RD1
113
RD2
114
RD3
115
RD4
116
RD5
117
RD6
118
RD7
119
ROMCSJ
120
PWG
Page 14
Type
IS
O
IS
O
IS
O
IS
O
IS
OD
I/O
I/O
I/O
I/O
P
I/O
I/O
I/O
I/O
I/O
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IS
IS
Pin No.
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
Pin Name
VBAT
X32TAL1
Vss
X32TAL2
Vcc
SLCT
PE
BUSY
ACKJ
Vss
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
Vcc
SLCTINJ
INITJ
ERRORJ
AUTOFDJ
STROBJ
SIN1
SOUT1
DSR1J
RTS1J/
CFG_PORT
CTS1J
DTR1J/RTC_EN
RI1J
DCD1J
RI2J
DCD2J
SIN2
SOUT2
DSR2J
RTS2J/KBC_EN
CTS2J
DTR2J/PS2_ATJ
Type
P
ICLK
P
OCLK
P
IS
IS
IS
IS
P
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
P
O
O
I
O
O
IS
O
IS
I/O
IS
I/O
IS
IS
IS
IS
IS
O
IS
I/O
IS
I/O
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
2.4 Alphabetical Pin List
Pin No.
129
70
143
128
96
97
98
99
100
102
103
104
105
106
107
108
109
110
23
24
25
30
31
32
33
34
149
159
81
83
85
87
152
154
9
82
84
86
88
2
Pin Name
ACKJ
AEN
AUTOFDJ
BUSY
CIO10/IRQIN1
CIO11/IRQIN2
CIO12/IRRX
CIO13/IRTX
CIO14/GA20
CIO15/KBRCJ
CIO16/I2C_CLK
CIO17/I2C_DAT
CIO20
CIO21
CIO22
CIO23
CIO24
CIO25
CIO30/KBC_CLK
CIO31/CS0J
CIO32/CS1J
CIO33/ALT_KCLK
CIO34/ALT_KDAT
CIO35/ALT_MCLK
CIO36/ALT_MDAT
CIO37/ALT_KBC
CTS1J
CTS2J
DACK0J
DACK1J
DACK2J
DACK3J
DCD1J
DCD2J
DIRJ
DRQ0
DRQ1
DRQ2
DRQ3
DRVDEN0
Type
IS
IS
O
IS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IS
IS
IS
IS
IS
IS
IS
IS
O
O
O
O
O
O
Pin No.
3
5
6
18
147
157
150
160
142
13
14
141
90
68
69
67
66
65
64
63
62
61
59
58
57
56
55
54
91
92
94
93
19
20
4
7
80
138
137
136
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
Pin Name
DRVDEN1
DRV1J
DRV0J
DSKCHGJ
DSR1J
DSR2J
DTR1J/RTC_EN
DTR2J/PS2_ATJ
ERRORJ
HDSELJ
INDEXJ
INITJ
IOCHRDY
IORJ
IOWJ
IRQ1
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
IRQ8
IRQ9
IRQ10
IRQ11
IRQ12
IRQ14
IRQ15
KDAT
KCLK
MCLK
MDAT
MID1
MID0
MOT0J
MOT1J
MR
PD0
PD1
PD2
Type
O
O
O
IS
IS
IS
I/O
I/O
I
O
IS
O
OD
IS
IS
O
O
O
O
O
O
O
O
O
O
O
O
O
I/O
I/O
I/O
I/O
IS
IS
O
O
IS
I/O
I/O
I/O
Page 15
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--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Alphabetical Pin List (continued)
Pin No.
Pin Name
135
PD3
134
PD4
133
PD5
132
PD6
131
PD7
26
PDIR/PS2DRV
127
PE
120
PWG
111
RD0
112
RD1
113
RD2
114
RD3
115
RD4
116
RD5
117
RD6
118
RD7
17
RDATAJ
151
RI1J
153
RI2J
119
ROMCSJ
39
ROMOEJ
RTS1J/CFG_PORT
148
158
RTS2J/KBC_EN
41
SA0
42
SA1
43
SA2
44
SA3
45
SA4
46
SA5
47
SA6
48
SA7
49
SA8
50
SA9
51
SA10
52
SA11
53
SA12
27
SA13
28
SA14
29
SA15
72
SD0
Page 16
Type
I/O
I/O
I/O
I/O
I/O
I/O
IS
IS
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IS
IS
IS
IS
IS
I/O
I/O
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
IS
I/O
Pin No.
73
74
75
76
77
78
79
145
155
140
126
146
156
10
144
89
15
121
21
60
101
125
139
1
8
40
71
95
123
130
11
16
12
22
35
36
122
124
37
38
Pin Name
SD1
SD2
SD3
SD4
SD5
SD6
SD7
SIN1
SIN2
SLCTINJ
SLCT
SOUT1
SOUT2
STEPJ
STROBJ
TC
TRK0J
VBAT
Vcc
Vcc
Vcc
Vcc
Vcc
Vss
Vss
Vss
Vss
Vss
Vss
Vss
WDATAJ
WPROTJ
WGATEJ
X14CLKI
X24TAL1
X24TAL2
X32TAL1
X32TAL2
XCLKO1
XCLKO2
Type
I/O
I/O
I/O
I/O
I/O
I/O
I/O
IS
IS
O
IS
O
O
O
O
IS
IS
P
P
P
P
P
P
P
P
P
P
P
P
P
O
IS
O
I
ICLK
OCLK
ICLK
OCLK
O
O
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Section 3 : Configuration Description and Power Management Features
3.1 Configuration Port
CHIP LEVEL REGISTERS
This configuration is based on the typical Plug-and-Play
architecture and allows the BIOS to assign resources at
POST.
Index name
Hard reset, Soft reset default values
Index 0x02h
0x00, 0x00
To assign M512x a configuration key, <0x51, 0x23> must
be written to CONFIG PORT to enter the CONFIGURE
mode.
Then follow the Plug-and-Play procedure to
configure each device.
Bit 0
1 : Soft reset the configuration registers.
This bit is automatically cleared after
write. This register is write only.
A configuration key = < 0xBB > must be written to CONFIG
PORT to exit the CONFIGURE mode and enter the RUN
mode.
Index 0x03h
0x03, N/A
Bit 1-0
Set CIO1, CIO2, and CIO3 selection
register address.
00 : 0xE0
01 : 0xE2
10 : 0xE4
11 : 0xEA
Bit 7
0 : Disable access
1 : Enable access to CIO1, CIO2, and
CIO3.
Index 0x07h
0x00, 0x00
Bit 3-0
Select
the
current
logic
device.
This allows the access to each
logical device’ s registers.
Bit 7-4
Read as 0.
Index 0x20h
0x23, 0x23
ALi
defined
Read only.
device
identification.
0x51, 0x51
ALi
defined
Read only.
device
identification.
Note : After exiting the CONFIGURE mode, the current
logic device select is cleared. You must select the logic
device before you program it.
After a hard reset or Power on reset, the M512x is in the
RUN mode with all logical devices disable except KBC and
RTC. The hardware setting pins control the KBC and RTC.
Then the normal configure procedure is also suitable for
KBC and RTC. The hardware setting is listed on table 3-2.
All logical devices may be configured through 2 standard
Configuration I/O Ports ( INDEX and DATA ) by placing the
M512x into Configuration Mode. The BIOS uses these
configuration ports to initialize the logical devices at POST.
The INDEX and DATA ports are only valid when the M512x
is in Configuration Mode.
A hardware setting pin CFG_PORT is latched to select the
CFG_PORT as 3F0h or 370h.
Port Name
CONFIG PORT
INDEX PORT
DATA PORT
CFG_PORT=0
0x3F0
0x3F0
0x3F1
CFG_PORT=1
0x370
0x370
0x371
Type
W
W
R/W
Index 0x21h
07-02-1997 Document Number: 512xDS02.doc
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Page 17
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--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Index 0x22h
0x00, 0x00
Index 0x2Dh
Bit 0
Direct powerdown FDC (Note 3)
0 : disable
1 : enable
Reserved for test purposes only
Bit 2-1
read as 0.
Bit 3
Direct powerdown Parallel Port (Note 3)
0 : disable
1 : enable
Bit 4
Direct powerdown UART1 (Note 3)
0 : disable
1 : enable
Bit 5
Direct powerdown UART2 (Note 3)
0 : disable
1 : enable
0x00, N/A
LOGICAL DEVICE 0 REGISTERS (FDC)
Index 0x30h
0x00, 0x00
Bit 0
FDC (Note 4)
0 : disable
1 : enable
Bit 7-1
read as 0.
Index 0x60h
0x03, 0x03
The higher address of the FDC’ s I/O
base address.
Bit 6
1: Turn off the oscillator.
Bit 7
read as 0.
Bit 7-2
read as 0.
Index 0x23h
0x00, N/A
Index 0x61h
Bit 2-0
read as 0.
0xF0, 0xF0
The lower address of the FDC’ s I/O base
address.
Bit 3
Auto powerdown Parallel Port.
0 : disable
1 : enable
Bit 2-0
set to 0.
Bit 4
Auto powerdown UART1.
0 : disable
1 : enable
Bit 5
Auto powerdown UART2.
0 : disable
1 : enable
Bit 7-6
read as 0
Index 0x24h
0x00, N/A
Bit 5-0
read as 0.
Bit 6
0 : pin26 functions as PDIR
1 : pin26 functions as SDRV.
Bit 7
0 : IRQ8 is active high
1 : IRQ8 is active low.(Note 1)
Page 18
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Index 0x70h
0x06, 0x06
Index 0xF1h
0x00, N/A
Bit 3-0
Select IRQ channel used by FDC.
0000 : None
0001 : IRQ1
0010 : N/A
0011 : IRQ3
0100 : IRQ4
0101 : IRQ5
0110 : IRQ6
0111 : IRQ7
1000 : N/A
1001 : IRQ9
1010 : IRQ10
1011 : IRQ11
1100 : IRQ12
1101 : N/A
1110 : IRQ14
1111 : IRQ15
Bit 1-0
External Floppy Select.
0x : internal FDC
10 : external FDC
11 : Drive A internal, Drive B external
Bit 3-2
Density Select.
0x : Normal
10 : force to 1
11 : force to 0
Bit 5-4
Media ID[1-0] polarity.
0 : normal
1 : inverted
Bit 7-6
Boot Floppy.
00 : FDD 0
01 : FDD 1
10 : FDD 2
11 : FDD 3
Bit 7-4
read as 0.
Index 0x74h
0x02, 0x02
Index 0xF2h
0xFF, N/A
Bit 2-0
Select DMA channel used by FDC
000 : DMA0
001 : DMA1
010 : DMA2
011 : DMA3
100 : None
Bit 1-0
Floppy Drive A type.
Bit 3-2
Floppy Drive B type.
Bit 5-4
Floppy Drive C type.
Bit 7-6
Floppy Drive D type.
Index 0xF4h
0x00, N/A
Bit 1-0
DRVDEN[1-0] signal definition (refer to
Table 3-4).
Bit 2, 7-5
read as 0.
Bit 4-3
Data Rate Table Select (refer to Table
3-3).
Bit 7-3
read as 0.
Index 0xF0h
0x08, N/A
Bit 0
0 : Normal mode
1 : Enhanced OS2 mode
Bit 1
0 : Burst DMA mode.
1 : Non-burst DMA mode
Bit 2, 7-5
read as 0.
Bit 3
0 : PS2 mode
1 : AT mode
Bit 4
0 : No swap.
1 : Swap Drive 0 and Drive 1
07-02-1997 Document Number: 512xDS02.doc
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Page 19
Fax: 762-6060
--Preliminary, Confidential, Proprietary--
Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
LOGICAL DEVICE 3 REGISTERS (Parallel Port)
Index 0x30h
0x00, 0x00
Index 0xF0h
0xBC, N/A
Bit 0
Activate Parallel Port. (Note 4)
0 : disable
1 : enable
Bit 2-0
Bit 7-1
read as 0.
Index 0x60h
0x03, 0x03
The higher address of the Parallel Port’ s
I/O base address.
EPP Compatible mode.
000 : PS2
001 : EPP 1.9
010 : ECP
011 : ECP+EPP1.9
100 : SPP
101 : EPP 1.7
111 : ECP+EPP 1.7
Bit 6-3
Bit 7-2
read as 0.
ECP FIFO threshold value.
Default is 0001.
Index 0x61h
0x78, 0x78
The lower address of
Port’ s I/O base address.
Bit 7
PP interrupt type (not valid when PP is
in SPP or PS2 mode).
1 : IRQ active low.
0 : IRQ active high.
Note : An 8-byte boundary is required if EPP is available
Index 0xF1h
0x05, N/A
Index 0x70h
0x05, 0x05
Bit 0
0 : Non-burst DMA mode.
1 : Burst DMA transfer mode in ECP
Bit 3-0
Bit 1
EPP time-out interrupt.
0 : disable
1 : enable
Bit 2
PP operation clock.
0 : 24 Mhz.
1 : 12 Mhz
Bit 7-3
read as 0.
Bit 7-4
Select IRQ channel used by Parallel Port.
0000 : None
0001 : IRQ1
0010 : N/A
0011 : IRQ3
0100 : IRQ4
0101 : IRQ5
0110 : IRQ6
0111 : IRQ7
1000 : N/A
1001 : IRQ9
1010 : IRQ10
1011 : IRQ11
1100 : IRQ12
1101 : N/A
1110 : IRQ14
1111 : IRQ15
read as 0.
Index 0x74h
0x04, 0x04
Bit 2-0
Select DMA channel used by Parallel
Port.
000 : DMA0
001 : DMA1
010 : DMA2
011 : DMA3
100 : None
Bit 7-3
read as 0.
Bit 1-0
Page 20
the
Parallel
set to 0.
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, ROC Tel: 886-(02) 762-8800 Fax: 762-6060
Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
LOGICAL DEVICE 4 REGISTERS (UART1)
Index 0x30h
0x00, 0x00
Index 0xF0h
0x00, N/A
Bit 0
UART1 (Note 4)
0 : disable
1 : enable
Bit 0
MIDI support
0 : disable
1 : enable
Bit 7-1
read as 0.
Bit 1
High speed mode
0 : disable
1 : enable
Index 0x60h
0x03, 0x03
The higher address of the UART1’ s I/O
base address.
Bit 2
0 : Normal
1 : 8Mhz clock source for UART1
Bit 7-2
read as 0.
Bit 7-3
read as 0.
Index 0xF1h
0x00, N/A
Index 0x61h
0xF8, 0xF8
The lower address of the UART1’ s
I/O base address.
Bit 0
IR receive polarity.
0 : active high
1 : active low
Bit 1
Bit 7-5
IR transmit polarity.
0 : active high
1 : active low
0 : Full duplex in IR
1 : Half duplex in IR
IR mode.
00 : Normal
01 : IrDA
10 : ASK IR
11 : Normal
read as 0.
Index 0xF2h
0x0C, N/A
Bit 0
Baud Rate output on RI1.
0 : disable
1 : enable
Bit 1
IR half-duplex Tx-to-Rx time- out timer.
0 : disable
1 : enable
IR half-duplex Rx-to-Tx time-out timer.
0 : disable
1 : enable
IR half-duplex time-out time control.
00: 41-bit time for TR, 39-bit time for RX.
01: 42-bit time for TR, 39-bit time for RX
1x: 40-bit time for TR and RX
Bit 2-0
is set to 0.
Index 0x70h
0x04, 0x04
Bit 3-0
Select IRQ used by UART1.
0000 : None
0001 : IRQ1
0010 : N/A
0011 : IRQ3
0100 : IRQ4
0101 : IRQ5
0110 : IRQ6
0111 : IRQ7
1000 : N/A
1001 : IRQ9
1010 : IRQ10
1011 : IRQ11
1100 : IRQ12
1101 : N/A
1110 : IRQ14
1111 : IRQ15
Bit 2
Bit 4-3
Bit 2
Bit 7-4
read as 0.
Bit 4-3
Bit 7-5
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read as 0.
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M512x : Mega I/O Controller with PnP
LOGICAL DEVICE 5 REGISTERS (UART2)
Index 0x30h
0x00, 0x00
Index 0xF0h
0x00, N/A
Bit 0
UART2 (Note 4)
0 : disable
1 : enable
Bit 0
MIDI support
0 : disable
1 : enable
Bit 7-1
read as 0.
Bit 1
High speed mode
0 : disable
1 : enable
Index 0x60h
0x02, 0x02
The higher address of the UART2’ s I/O
base address.
read as 0.
Bit 2
1 : 8 Mhz clock source for UART2
0 : Normal
Bit 7-3
read as 0.
Index 0xF1h
0x02, N/A
Bit 0
IR receive polarity.
0 : active high
1 : active low
Bit 1
IR transmit polarity.
0: active high
1: active low
Bit 2
1 : Half duplex in IR
0 : Full duplex in IR.
Bit 4-3
IR mode.
00 : Normal
01 : IrDA
10 : ASK IR
11 : Normal
Bit 5, 7
read as 0.
Bit 6
IR input source.
0 : use TX2 and RX2
1 : use IRRX2 and IRTX2
Bit 7-2
Index 0x61h
Bit 2-0
0xF8, 0xF8
The lower address of the UART2’ s I/O
base address.
set to 0.
Index 0x70h
0x03, 0x03
Bit 3-0
Select IRQ channel used by UART2.
0000 : None
0001 : IRQ1
0010 : N/A
0011 : IRQ3
0100 : IRQ4
0101 : IRQ5
0110 : IRQ6
0111 : IRQ7
1000 : N/A
1001 : IRQ9
1010 : IRQ10
1011 : IRQ11
1100 : IRQ12
1101 : N/A
1110 : IRQ14
1111 : IRQ15
Bit 7-4
Page 22
read as 0.
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M512x : Mega I/O Controller with PnP
Index 0xF2h
0x0C, N/A
LOGICAL DEVICE 7 REGISTERS (KEYBOARD)
Bit 0
Baud Rate output on RI2
0 : disable
1 : enable
Index 0x30h
0x00, 0x00
Bit 0
Keyboard controller. This is a hardware
setting bit by RTS2J. (Note 4)
0 : disable
1 : enable
Bit 7-1
read as 0.
Index 0x70h
0x01, 0x01
Bit 3-0
Select IRQ channel used by Keyboard.
0000 : None
0001 : IRQ1
0010 : N/A
0011 : IRQ3
0100 : IRQ4
0101 : IRQ5
0110 : IRQ6
0111 : IRQ7
1000 : N/A
1001 : IRQ9
1010 : IRQ10
1011 : IRQ11
1100 : IRQ12
1101 : N/A
1110 : IRQ14
1111 : IRQ15
Bit 7-4
read as 0.
Index 0x72h
0x00, 0x00
Bit 3-0
Select IRQ channel used by PS/2 Mouse.
0000 : None
0001 : IRQ1
0010 : N/A
0011 : IRQ3
0100 : IRQ4
0101 : IRQ5
0110 : IRQ6
0111 : IRQ7
1000 : N/A
1001 : IRQ9
1010 : IRQ10
1011 : IRQ11
1100 : IRQ12
1101 : N/A
1110 : IRQ14
1111 : IRQ15
Bit 7-4
read as 0.
Bit 1
IR half-duplex Tx-to-Rx time-out timer.
0 : disable
1 : enable
Bit 2
IR half-duplex Rx-to-Tx time-out timer
0 : disable
1 : enable
Bit 4-3
IR half-duplex time-out time control.
1x : 40-bit time for TR and RX
01 : 42-bit time for TR, 39-bit time for RX
00 : 41-bit time for TR, 39-bit time for RX.
Bit 7-5
read as 0.
LOGICAL DEVICE 6 REGISTERS (RTC)
Index 0x30h
0x00, 0x00
Bit 0
0 : Deactivate RTC (Note 4)
1 : Activate RTC.
This is a hardware setting bit by DTR1J.
Bit 7-1
read as 0.
Index 0xF0h
0x00, N/A
Bit 0
CMOS RAM 0x80-0x9F
0 : Unlock
1 : Lock
Bit 1
CMOS RAM 0xA0-0xBF.
0 : Unlock
1 : Lock
Bit 2
CMOS RAM 0xC0-0xDF
0 : Unlock
1 : Lock
Bit 3
CMOS RAM 0xE0-0xFF.
0 : Unlock
1 : Lock
Bit 6-4
read as 0.
Bit 7
1: Select upper 128-byte bank of RAM
0: Select lower bank
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M512x : Mega I/O Controller with PnP
Index 0xF0h
0x00, 0x00
Index 0xE1h
0x01, N/A
CIO11 function definition.
Bit 0
0 : KBC clock source is 8Mhz
1 : KBC clock source is 7.16Mhz.
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity.
0 : non-inverted
1 : inverted
Bit 2
read as 0.
Bit 3
0 : Normal function.
1 : Input function as IRQIN2
Bit 7-4
IRQ mapping for IRQIN2
0000 : None
0001 : IRQ1
0010 : N/A
0011 : IRQ3
0100 : IRQ4
0101 : IRQ5
0110 : IRQ6
0111 : IRQ7
1000 : N/A
1001 : IRQ9
1010 : IRQ10
1011 : IRQ11
1100 : IRQ12
1101 : N/A
1110 : IRQ14
1111 : IRQ15
Index 0xE2h
0x01, N/A
CIO12 function definition.
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity
0 : non-inverted
1 : inverted
Bit 2
read as 0.
Bit 3
0 : Normal function
1 : Input function as IRRX2
Bit 7-4
read as 0.
Bit 1
Bit 7-2
Read only. Indicates the type of keyboard
0 : PS2.
1 : AT
read as 0.
LOGICAL DEVICE 8 REGISTERS (Common I/O)
Index 0x30h
0x00, 0x00
Bit 0
Common I/O port.
0 : disable
1 : enable
Bit 7-1
read as 0.
Index 0xE0h
0x01, N/A
CIO10 function definition
Bit 0
1 : input
0 : output
Bit 1
Input/Output signal polarity
0 : non-inverted
1 : inverted
Bit 2
read as 0.
Bit 3
0 : Normal function.
1 : Input function as IRQIN1
Bit 7-4
IRQ mapping for IRQIN1.
0000 : None
0001 : IRQ1
0010 : N/A
0011 : IRQ3
0100 : IRQ4
0101 : IRQ5
0110 : IRQ6
0111 : IRQ7
1000 : N/A
1001 : IRQ9
1010 : IRQ10
1011 : IRQ11
1100 : IRQ12
1101 : N/A
1110 : IRQ14
1111 : IRQ15
Page 24
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--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Index 0xE3h
0x01, N/A
CIO13 function definition.
Index 0xE6h
0x01, N/A
CIO16 function definition.
Bit 0
0 : output
1 : input
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity.
0 : non-inverted.
1 : inverted
Bit 1
Input/Output signal polarity.
0 : non-inverted.
1 : inverted
Bit 2, 7-4
read as 0.
Bit 2, 7-4
read as 0.
Bit 3
0 : Normal function.
1 : Output function as IRTX2
Bit 3
0 : Normal function
1 : Output function as I2C CLK (Note2).
Index 0xE4h
0x01, N/A
CIO14 function definition.
Index 0xE7h
0x01, N/A
CIO17 function definition.
Bit 0
0 : output
1 : input
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity
0 : non-inverted.
1 : inverted
Bit 1
Input/Output signal polarity.
0 : non-inverted
1 : inverted
Bit 2, 7-4
read as 0.
Bit 2, 7-4
read as 0
Bit 3
0 : Normal function.
1 : Select KBC P21 function
Bit 3
0 : Normal function.
1 : Select I2C DAT function (Note2).
Index 0xE5h
0x01, N/A
CIO15 function definition.
Index 0xE8
0x01, N/A
CIO20 function definition.
0 : output.
1 : input
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity.
0 : non-inverted.
1 : inverted
Bit 7-2
read as 0.
Bit 0
Bit 1
Input/Output signal polarity.
0 : non-inverted
1 : inverted
Bit 2, 7-4
read as 0.
Bit 3
0 : Normal function
1 : Select KBC P20 function
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M512x : Mega I/O Controller with PnP
Index 0xE9h
0x01, N/A
CIO21 function definition.
Index 0xEDh
0x01, N/A
CIO25 function definition.
Bit 0
0 : output.
1 : input
Bit 0
0 : output
1 : input.
Bit 1
Input/Output signal polarity.
0 : non-inverted.
1 : inverted
Bit 1
Input/Output signal polarity.
0 : non-inverted.
1 : inverted
Bit 7-2
read as 0.
Bit 2, 7-4
read as 0.
Bit 3
Index 0xEAh
0x01, N/A
CIO22 function definition.
0 : Normal function.
1 : Select KEYLOCK function
Bit 0
0 : output
1 : input
Index 0xEEh
0x00, N/A
Bit 5-0
Address line[13-8] of CS0J.
Bit 1
Input/Output signal polarity.
0 : non-inverted.
1 : inverted.
Bit 7-6
CS0J decoding range.
00 : A[3-0]=0000b
01 : A[3-0]=00xxb
10 : A[3-0]=0xxxb
11 : A[3-0]=xxxxb
Index 0xEFh
0x00, N/A
Bit 3-0
read as 0.
Bit 7-4
Address line[7-4] of CS0J.
Index 0xF5h
0x01, N/A
CIO30 function definition.
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity.
0 : non-inverted
1 : inverted.
Bit 2, 7-4
read as 0.
Bit 3
0 : Normal.
1 : Input function as the new KBC clock
source
Bit 7-2
read as 0.
Index 0xEBh
0x01, N/A
CIO23 function definition.
Bit 0
0 : output
1 : input.
Bit 1
Input/Output signal polarity.
0 : non-inverted
1 : inverted.
Bit 7-2
Index 0xECh
read as 0
0x01, N/A
CIO24 function definition
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity
0 : non-inverted
1 : inverted.
Bit 7-2
Page 26
read as 0.
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Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Index 0xF6h
0x01, N/A
CIO31 function definition.
Index 0xFAh
0x01, N/A
CIO35 function definition.
Bit 0
0 : output
1 : input
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity.
0 : non-inverted.
1 : inverted
Bit 1
Input/Output signal polarity.
0 : non-inverted.
1 : inverted
Bit 2, 7-4
read as 0.
Bit 7-2
read as 0
Bit 3
0 : Normal function.
1 : Output function as CS0J
Index 0xFBh
0x01, N/A
CIO36 function definition
0x01, N/A
CIO32 function definition.
Bit 0
0 : output
1 : input
0 : output
1 : input
Bit 1
Input/Output signal polarity.
0 : non-inverted
1 : inverted
Input/Output signal polarity
0 : non-inverted
1 : inverted
Bit 7-2
read as 0
Index 0xFCh
0x01, N/A
CIO37 function definition.
Bit 0
0 : output.
1 : input
Bit 1
Input/Output signal polarity
0 : non-inverted
1 : inverted
Bit 2, 7-4
read as 0.
Bit 3
0 : Normal function
1 : enable the secondary KBC signal
source.
CIO33 functions as ALT_KCLK
CIO34 functions as ALT_KDAT
CIO35 functions as ALT_MCLK
CIO36 functions as ALT_MDAT
CIO37 input functions as the switch
control of the traditional and secondary
KBC signal source. When CIO37 is 1, the
traditional one is selected. When 0, the
secondary is selected.
Index 0xF7h
Bit 0
Bit 1
Bit 2, 7-4
read as 0.
Bit 3
0 : Normal function.
1 : Output function as CS1J
Index 0xF8h
Bit 0
Bit 1
0x01, N/A
CIO33 function definition.
0 : output
1 : input
Input/Output signal polarity.
0 : non-inverted.
1 : inverted
Bit 7-2
read as 0.
Index 0xF9h
0x01, N/A
CIO34 function definition.
Bit 0
0 : output
1 : input
Bit 1
Input/Output signal polarity.
0 : non-inverted
1 : inverted
Bit 7-2
read as 0.
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M512x : Mega I/O Controller with PnP
Index 0xFDh
0x00, N/A
Bit 5-0
Address line[13-8] of CS1J.
Bit 7-6
CS1J decoding range.
00 : A[3-0]=0000b
01 : A[3-0]=00xxb
10 : A[3-0]=0xxxb
11 : A[3-0]=xxxxb
Index 0xFEh
0x00, N/A
Bit 3-0
read as 0.
Bit 7-4
Address line[7-4] of CS1J.
Index 0xFFh
0x00, N/A
Bit 0
CS0J assertion on write cycle.
0 : disable
1 : enable
Table 3-2
Bit 1
CS0J assertion on read cycle.
0 : disable
1 : enable
Bit 2
CS1J assertion on write cycle.
0 : disable
1 : enable
Bit 3
CS1J assertion on read cycle.
0 : disable
1 : enable
Note 1 : IRQ8 is reserved for use by RTC only.
Note 2 : The access port address of the I2C device is
determined by CS0J. The signals on XSD[0] and
XSD[1] will reflect on I2C_CLK and I2C_DAT
individually.
Note 3 : During direct powerdown, access to I/O ports are
denied. To wake up the device, setting 1 to
corresponding bit is required.
Note 4 : The disable function of the device has the same
behavior as direct powerdown function except the
device remains at reset state.
M512x Hardware Setting Configuration
Pin Name
RTS1J
0
1
RTS2J
0
1
DTR1J
0
1
DTR2J
0
1
Function
CFG_PORT
0x3F0
0x370
KBC_EN
disable
enable
RTC_EN
disable
enable
PS2_ATJ (KBC)
AT mode
PS2 mode
Table 3-3
Drive Option 1 and 2
Data Rate
Register Settings (3F7)
FDC 0xF4[4:3]*
KB/sec
Drate Sel 1
Drate Sel 0
Drate Opt1
Drate Opt0
1000
1
1
0
0
500
0
0
0
0
300
0
1
0
0
250
1
0
0
0
1000
1
1
0
1
500
0
0
0
1
500
0
1
0
1
250
1
0
0
1
Note : *Drive Table 00 = Regular drives and 2.88MB
01 = 3-mode drive
Table 3-4
Page 28
Densel
(1)
1
1
0
0
1
1
0
0
Drate
Drate1
1
0
0
1
1
1
0
0
Drate0
1
0
1
0
1
0
1
0
Drvden Output Mapping for Drive Type Table
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Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
0xF4 [1:0]
DT1
Drvden Signal Definition
DT0
DRVDEN1
DRVDEN0
0
0
DRATE0
DENSEL
1
0
DRATE0
DRATE1
0
1
DRATE0
nDENSEL
1
1
DRATE1
DRATE0
3.2 Power Management Features
The M512x contains power management features that
makes it ideal for design of notebook and desktop personal
computers. These features can be classified into power
management of the part and the internal oscillator. The
powerdown of the part is done independently of the internal
oscillator in the M512x.
3.2.1 Oscillator Power Management
The M512x supports a built-in crystal oscillator that can be
programmed to be either powered down or active,
independent of the power state of the chip. This capability is
implemented by the OSC-OFF bit in the 0x22. When OSCOFF is set high, the internal oscillator is off.
When the external oscillator is used, power can be saved by
turning off the internal oscillator. If the internal oscillator is
used, the oscillator may be powered up (even when the rest
of the chip is powered off) allowing the chip to wake up
quickly and be in a stable state. It is recommended to keep
the internal oscillator on even at the powerdown state. The
main reason for this is that the recovery time of the
oscillator during wake-up may take tens of milli-seconds
under the worst case, which may create problems with any
sensitive application software. In a typical application, the
internal oscillator should be on unless the system goes into
a power saving or standby mode. Such a mode request
would be made by a system time-out or by a user. In this
case, the system software would take over and must turn on
the oscillator sufficiently ahead of awakening the part.
In the case of the external oscillators, the power-up
characteristics are similar. If the external source remains
active during the time the M512x is powered down, then the
recovery time effect is minimized.
3.2.2 Part Power Management
This section deals with the power management of the rest of
the chip excluding the oscillator. This part shows how
powerdown modes and wake up modes are activated.
3.2.2.1 Powerdown Modes of FDC
The rest of the chip is powered down in two ways: direct
powerdown and automatic powerdown. Direct powerdown
results in immediate shutdown of the part without regard to
the current state of the part. Automatic powerdown results
when certain conditions become true within the part.
A.
Direct Powerdown
Direct powerdown is conducted via the powerdown bit in the
DSR register (bit 6) or FDC_PWD bit in 0X22.
Programming this bit high will powerdown M512x after the
part is internally reset. All current status is lost if this type of
powerdown mode is used. The part can exit powerdown
from this mode via any hardware or software reset. This
type of powerdown will override the automatic powerdown.
If the part is in automatic powerdown when the DSR
powerdown is issued, then all the previous status of the part
will be lost, and the M512x will be reset to its default values.
B.
Auto Powerdown
Automatic powerdown is conducted via a "Set Powerdown
Mode" command. There are four conditions required before
the part will enter powerdown. All these conditions must be
true for the part to initiate the powerdown sequence. These
conditions are listed as follows:
1.
2.
3.
4.
The motor enable pins ME[0:3] must be inactive,
The part must be idle; this is indicated by MSR = 80H
and INT = 0 (INT may be high even if MSR = 80H due
to polling interrupt),
The head unload timer must have expired, and
The auto powerdown timer must have timed out.
The command can be used to enable powerdown by setting
the AUTOPD bit in the command to high. The command
also provides a capability of programming a minimum
power-up time via the MIN DLY bit in the command. The
minimum power-up time refers to a minimum amount of
time the part will remain powered-up after being awakened
or reset. An internal timer is initiated as soon as the auto
powerdown command is enabled. The part is then powered
down provided all the remaining conditions are met. Any
software reset will reinitialize the timer. Changing of data
rate extends the auto powerdown timer by up to 10 ms, but
only if the data rate is changed during the countdown.
Disabling the auto powerdown mode cancels the timers and
holds the M512x out of auto powerdown.
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M512x : Mega I/O Controller with PnP
3.2.2.2 Powerdown Mode of UART and Printer
UART1, UART2 and printer can enter direct powerdown or
auto powerdown respectively by setting their relative
powerdown bit in the 0X22 and 0x23.
3.2.2.3 WAKE UP MODES of FDC
This section describes the conditions for awakening the part
from both direct and automatic powerdown.
Power
conservation of battery life is the main reason power
management is required. This means that the M512x must
be kept in powerdown state as long as possible and should
be powered up as late as possible without compromising
software transparency.
To keep the part in powerdown mode as late as possible
implies that the part should wake-up as fast as possible.
However, some amount of time is required for the part to
exit powerdown state and prepare the internal
microcontroller to accept commands. Application software
is very sensitive to such a delay and in order to maintain
software transparency, the recovery time of the wake-up
process must be carefully controlled by the system software.
A.
Wake Up from DSR Powerdown
If the M512x enters powerdown through the DSR
powerdown bit, it must be reset to exit. Any form of
software or hardware reset will serve, although DSR is
recommended. No other register access will wake up the
part, including writing to the DOR's motor enable (ME[0:3])
bits.
If DSR powerdown is used when the part is in auto
powerdown, the DSR powerdown will override the auto
powerdown. However, when the part is awakened by a
software reset, the auto powerdown command (including the
minimum delay timer) will again become effective as
previously programmed. If the part is awakened via a
hardware reset, the auto powerdown is disabled.
After reset, the part will go through a normal sequence. The
drive status will be initialized. The FIFO mode will be set to
default mode on a hardware reset or on a software reset if
the LOCK command is not blocking it. Finally, after a delay,
the polling interrupt will be issued.
B.
Wake Up from Auto Powerdown
If the part enters the powerdown state through the auto
powerdown mode, then the part can be awakened by reset
or by appropriate access to certain registers.
If a hardware or software reset is used, then the part goes
through the normal reset sequence. If the access is through
the selected registers, then the M512x resumes operation as
though it was never in powerdown. Besides activating the
RESET pin or one of the software reset bits in the DOR or
DSR, the following register accesses will wake-up the part:
1.
2.
3.
Enabling any one of the motor enable bits in the DOR
register (reading the DOR does not wake-up the part)
A read from the MSR register
A read or write to the FIFO register
Any of these actions will wake-up the part. Once awake,
M512x will initiate the auto powerdown time for 10 ms or 0.5
sec. (Depending on the MIN DLY bit the auto powerdown
command). The part will powerdown again when all the
powerdown conditions stated in the Auto Powerdown
section are satisfied.
Page 30
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--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Section 4 : Floppy Disk Controller
4.1 Register Overview
map of the FDC controller. Table 4-2 is the summary of
FDC register hardware reset.
The integrated FDC of the M512x part is register- and
hardware-level compatible with the industry standard 765A
and 82077SL standards. Table 4-1 lists the I/O address
Table 4-1
FDC Controller I/O Address Map
A2
0
0
0
0
1
1
1
1
1
1
A0
0
1
0
1
0
0
1
0
1
1
A1
0
0
1
1
0
0
0
1
1
1
R/W
R
R
R/W
R/W
R
W
R/W
R
W
Register
SRA (PS/2 mode only)
SRB (PS/2 mode only)
Digital Output Register DOR
Tape Drive Register TDR
Main Status Register MSR
Data Rate Select Register DSR
Data (First In First Out) FIFO
reserved
Digital Input Register DIR
Configuration Control Register CCR
* When this location is accessed, only bit 7 is driving, all other bits are held tristate.
Table 4-2
Summary of FDC Register Hardware Reset and Powerdown State
Register
Bits State
7
6
5
4
3
2
1
0
DOR(R/W)
H/W Reset State
0
0
0
0
0
0
0
0
3F2
TDR(R/W)
H/W Reset State
_
_
_
_
_
_
0
0
3F3
MSR(R)
H/W Reset State
0
X
X
X
X
X
X
X
3F4
DSR(W)
H/W Reset State
0
0
0
0
0
0
1
0
3F4
DIR(R)
H/W Reset State
na
_
_
_
_
_
_
_
3F7
CCR(W)
H/W Reset State
_
_
_
_
_
_
1
0
3F7
SRA(R)
H/W Reset State
0
na
0
na
0
na
na
0
3F0
SRB(R)
H/W Reset State
1
1
0
0
0
0
0
0
3F1
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I/O Address Map
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4.2 Register Description
4.2.2 Status Register B (SRB)
This section describes the register bits for all the registers
that are directly accessible to the CPU.
4.2.1 Status Register A (SRA)
Address 3F0 Read only
This register is read-only and monitors the state of the
IRQ6 pin and several disk interface pins in PS/2 modes.
The SRA can be accessed any time when it is in PS/2
mode. In AT mode, the data bus pins D0-D7 are held in a
high impedance state for a read of address 3F0h.
PS/2 mode
Bit
7
6
5
4
3
2
1
0
Name
Int Pending
DRV2J
STEP
TRK0J
HDSEL
INDXJ
WPJ
DIR
Bit 7
Interrupt Pending : The state of the
Floppy Disk Interrupt output (active high).
Bit 6
DRV2J : DRV2 disk interface input pin,
indicates that a second drive has been
installed.
Bit 5
Step : Step output disk interface output
pin (active high)
Bit 4
Track 0 : TRK0 disk interface input (active
low)
Bit 3
Head Select : HDSEL disk interface input.
A logic "1" selects side 1 and a logic "0"
selects side 0.
Bit 2
Index : Index disk interface input (active
low)
Bit 1
Write Protect : Write protect disk
interface input. A logic "0" indicates that
the disk is write protected.
Bit 0
Direction : Head movement direction
(active
high).
A
logic
"1"
indicates inward direction a logic "0"
outward.
Page 32
Address 3F1 Read only
This register is read-only and monitors the state of several
disk interface pins, in PS/2 modes. The SRB can be
accessed at any time during PS/2 mode. In AT mode, the
data bus pins D0-D7 are held in a high impedance state for
a read of address 3F1h.
PS/2 mode
Bit
7
6
5
4
3
2
1
0
Name
1
1
Drive Sel0
Wdata Toggle
Rdata Toggle
Wgate
MOTEN1
MOTEN0
Bit 7
Reserved : Always read as a logic "1"
Bit 6
Reserved : Always read as a logic "1"
Bit 5
Drive Select 0 : Reflects the status of the
Drive Select bit 0 of DOR (address 3F2 bit
0). This bit is cleared after a hardware
reset, it is unaffected by a software reset
Bit 4
Write Data Toggle : This bit changes
Bit 3
Read Data Toggle : Every inactive edge
of the RDATA input causes this bit to
change state.
state at every inactive edge of the WDATA
Bit 2
Write Gate : The WGATE disk interface
output (active high)
Bit 1
Motor Enable 1 : The MTR1 disk interface
output pin.
This bit is low after a
hardware reset and unaffected by a
software reset.
Bit 0
Motor Enable 0 : The MTR0 disk interface
output pin.
This bit is low after a
hardware reset and unaffected by a
software reset.
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4.2.3 Digital Output Register (R/W)
Address 3F2
Table 4-3
R/W
Digital Output Register Description
Bit
Description
D7
Motor Enable 3: This controls the Motor for drive 3, MTR3. The output is high when it is inactive, and low
when it is active. This bit and DOR bit 6 provide information that control the MTR1 and 0 pins, respectively
when bit 7 of the configuration register is set.
D6
Motor Enable 2: Same function as D7 except for drive 2's motor. Note that this signal is not brought out to
a pin.
Motor Enable 1: This bit controls the Motor for drive 1's motor. When this bit is 0, the MTR1 output is
high.
D5
D4
D3
D2
D1~D0
Table 4-4
D7
x
x
x
1
0
Table 4-5
D7
x
x
x
1
0
Motor Enable 0: Same as D5 except for drive 0's motor.
DMA Enable: When set to a 1, this enables the DRQ, DAK, and INT pins. A zero disables these signals.
Reset Controller: This bit resets the controller when 0 and enables normal operation when it is a 1. It
does not affect the drive control or data rate registers which are reset only by a hardware reset.
Drive Select: These two pins are encoded for the four drive select, and are gated with the motor enable
lines, so that only one drive is selected when its motor enable is active.
Internal 4 Drive Decode - Normal
Digital Output Register
D6
D5
D4
D1
x
x
1
0
x
1
x
0
1
x
x
1
x
x
x
1
0
0
0
x
D0
0
1
0
1
x
Drive Select Outputs
DS1J
DS0J
1
0
0
1
1
1
1
1
1
1
Motor on Outputs
MTR1J
MTR0J
/D5
/D4
/D5
/D4
/D5
/D4
/D5
/D4
/D5
/D4
Internal 4 Drive Decode - Drives 0 and 1 Swapped
Digital Output Register
D6
D5
D4
D1
x
x
1
0
x
1
x
0
1
x
x
1
x
x
x
1
0
0
0
x
D0
0
1
0
1
x
Drive Select Outputs
DS1J
DS0J
0
1
1
0
1
1
1
1
1
1
Motor on Outputs
MTR1J
MTR0J
/D4
/D5
/D4
/D5
/D4
/D5
/D4
/D5
/D4
/D5
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4.2.4 Tape Drive Register (TDR)
Address 3F3 R/W
This register is included for 82077 software compatibility. The robust data separator used in the M512x does not require its
characteristics modified for tape support. The contents of this register are not used internally to the device. The TDR is
unaffected by a software reset. Bits 2-7 are tri-stated when read in this mode.
Normal Floppy mode
Normal mode. Register 3F3h contains only bits 0 and 1. When this register is read, bits 2- 7 are at high impedance.
REG 3F3
DB7
Tri-state
DB6
Tristate
DB5
Tri-state
DB4
Tri-state
DB3
Tri-state
DB2
Tristate
DB1
tapesel1
DB0
tapesel0
Enhanced Floppy mode 2 (OS2)
Register 3F3 for Enhanced Floppy mode 2 operation
REG 3F3
DB7
Media ID1
DB6
Media ID0
DB5
DB4
Drive type ID
DB3
DB2
Floppy boot drive
DB1
tapesel1
DB0
tapesel0
For this mode, DRATE0 and DRATE1 pins are inputs and these inputs are gated into bits 6 and 7 of the 3F3 register. These two
bits are not affected by any reset.
Bit 7 Media ID 1 Read only (pin 19) see table next page
Bit 6 Media ID 0 Read only (pin 20) see table next page
Bits 5 and 4 Drive Type ID - These bits reflect two of FDC 0XF2 configuration register bits. (please see next page).
Bits 3 and 2 Floppy boot Drive. These bits show the value of FDC 0xF1 configuration register bits.
Bits 1 and 0 - Tape Drive select (R/W). Same as in Normal and Enhanced Floppy mode 1.
Page 34
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Media ID1
Drate1
pin 19
0
1
Media ID1
FDC
0xF1-db5=0
0
1
Drive type ID
Digital Output Register
bit 1
bit 0
0
0
0
1
1
0
1
1
FDC
0xF1--db5=1
1
0
Media ID0
Drate0
pin 20
0
1
Media ID0
FDC
0xF1-db4=0
0
1
FDC
0xF1-db4=1
1
0
Register 3F3 - drive type ID
bit 5
bit 4
FDC
FDC
0xF2 - bit 1
0xF2 - bit 0
FDC
FDC
0xF2 - bit 3
0xF2 - bit 2
FDC
FDC
0xF2 - bit 5
0xF2 - bit 4
FDC
FDC
0xF2 - bit 7
0xF2 - bit 6
4.2.5 Main Status Register
Address 3F4h
Read only
The read-only main status register indicates the current status of the disk controller. It is always available to be read. One of its
functions is to control the flow of data to and from the data register. It also indicates when the disk controller is ready to send or
receive data. It should be read before each byte is transferred to or from the data register except during a DMA transfer. No
delay is required when reading this register after a data transfer.
Table 4-8
Bit
D7
D6
Main Status Register Description
Description
Request for Master: Indicates that the data register is ready to send or receive data from the
CPU. This bit is cleared immediately after a byte transfer, and is set again as soon as the
M512x is ready for the next byte.
Data Direction: Indicates whether the controller is expecting a byte to be written to (0) or
read from (1) the data register.
D5
Non-DMA Execution: Bit is set only during the execution phase of a command if it is in the
non-DMA mode. In other words, if this bit is set, the multiple byte data transfer (in the
execution phase) must be monitored by the CPU either through interrupts, or software polling
as described in the processor software interface section.
D4
Command in Progress: Bit is set after the first byte of the command phase is written. Bit is
cleared after the last byte of the result phase is read. If there is no result phase in a
command, the bit is cleared after the last byte of the command phase is written.
Drives 3~0 Seeking: Set after the last byte of the command phase of a seek or recalibrate
command is issued for drives 3~0, respectively. Cleared after reading the first byte in the
result phase of the sense interrupt command for this drive.
D3~D0
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4.2.6 Data Rate Select Register (DSR)
Address 3F4
Table 4-9
Write only
Datarate Select Register Description
Bit
Description
D7
S/W RESET behaves the same as DOR RESET except that this reset is self clearing.
D6
POWERDOWN bit implements direct powerdown. Setting this bit high puts the FDC into the
powerdown state regardless of the state of the part. The part is reset internally and then goes
into powerdown. No status is saved and any operation in progress is aborted. This
powerdown mode does not turn off the internal oscillator. Any hardware or software reset will
exit the M512x from this powerdown state.
D5
reserved
D4~D2
PRECOMP 0-2 adjusts the WRDATA output to the and disk to compensate for magnetic
media phenomena known as bit shifting. The data patterns that are susceptible to bit shifting
are well understood and the M512x offsets the data pattern as it is written to the disk. The
amount of precompensation depends upon the drive and media but in most cases the default
value is acceptable.
The M512x starts precompensating the data pattern starting on Track 0. The CONFIGURE
command can change the starting track for precompensation. Table 4-10 lists the
precompensation values that can be selected and Table 4-11 lists the default
precompensation values. The default value is selected if the three bits are zeros.
D1~D0
DRATE 0-1 select one of the four data rates as listed in Table 4-12. The default value is 250
Kbps upon a chip ("Hardware") reset. Other ("Software") Resets do not affect the DRATE or
PRECOMP bits.
Table 4-10
Precompensation Delay Values
PRECOMP
Precompensation Delay--
432 bits
DISABLED
111
001
010
011
100
101
110
000
Page 36
0.00ns
41.67ns
83.34ns
125.00ns
166.67ns
208.33ns
250.00ns
DEFAULT
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Table 4-11
Data Rate
1 Mbps
500 Kbps
300 Kbps
250 Kbps
Default Precompensation Delay Values
Precompensation Delay
41.67ns
125ns
125ns
125ns
Table 4-12
DRATESEL
1
0
0
1
1
0
1
0
Data Rates
Data Rate
MFM
1 Mbps
500 Kbps
300 Kbps
250 Kbps
FM
Illegal
250 Kbps
150 Kbps
125 Kbps
4.2.7 Data Register (R/W)
Address 3F5
R/W
This is the location through which all commands, data, and status flow between the CPU and the FDC. During the command
phase, the CPU loads the controller's commands into this register based on the status register request for master and data
direction bits. The result phase transfers the status registers and header information to the CPU in the same fashion.
All command parameter information and disk data transfers go through the FIFO. The 16-byte FIFO has programmable threshold
values. Data transfers are generated by the RQM and DIO bits in the Main Status Register.
The FIFO defaults to an M5105 compatible mode after a "Hardware" reset (Reset via pin 1). "Software" Resets (Reset via DOR or
DSR register) can also place the M512x into M5105-A3/A4-compatible mode if the LOCK bit is set to "0" This maintains PC-AT
hardware compatibility.
The default values can be changed through the CONFIGURE command (enable full FIFO operation with threshold control). The
advantage of the FIFO is that it allows the system a larger DMA latency without causing disk error. Table 4-13 gives several
examples of the delays with a FIFO. The data is based upon the following formula:
Threshold# * 1/DATA RATE * 8 - 1.5us = DELAY
Table 4-13
FIFO Service Delay
FIFO Threshold
Examples
1 byte
2 bytes
8 bytes
15 bytes
Maximum Delay to Servicing
at 1 Mbps Data Rate
1 * 8us - 1.5us = 6.5us
2 * 8us - 1.5us = 14.5us
8 * 8us - 1.5us = 62.5us
15 * 8us - 1.5us = 118.5us
FIFO Threshold
Examples
1 byte
2 bytes
8 bytes
15 bytes
Maximum Delay to Servicing
at 500 Mbps Data Rate
1 * 16us - 1.5us = 14.5us
2 * 16us - 1.5us = 30.5us
8 * 16us - 1.5us = 126.5us
15 * 16us - 1.5us = 238.5us
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At the start of a command, the FIFO action is always
disabled and command parameters must be sent based
upon the RQM and DIO bit settings. As the M512x enters
the command execution phase, it clears the FIFO of any
data to ensure that invalid data is not transferred.
An overrun or underrun will terminate the current command
and the transfer of data. Disk writes will complete the
current sector by generating a 00 pattern and valid CRC.
4.2.8 Configuration Control Register (CCR, PC-AT
Modes)
Address 3F7
Write only
Table 4-14 Configuration Control Register Description
Bit
D7~D2
D1, D0
Description
Not used.
Data Rate Select: These bits set the datarate and write-precompensation values for
the disk controller. After a hardware reset,
these bits are set to 1, 0 (250 Kbps). (please
refer to table 4-12)
4.2.9 Digital Input Register (DIR, Read)
Address 3F7
Read only
Table 4-15 Digital Input Register Description (PC/AT mode)
Bit
D7
D6~D0
Description
DSKCHG monitors the pin of the same name
and reflects the opposite value seen on the disk
cable, regardless of the value of /INVERT/. The
DSKCHG bit is forced inactive along with all the
inputs from the floppy disk drive. All the other
bits remain tri-stated.
These bits are reserved for use by the hard disk
controller, thus during a read of this register,
these bits are in high impedance state.
Table 4-15b
Bit
D7
D6~D3
D2~D1
D0
Page 38
Digital Input Register (PS/2 mode)
Description
DSKCHG monitors the pin of the same name
and reflects the opposite value seen on the disk
cable.
undefined, always read as logic "1".
Data rate select. These bits control the data rate
of
the floppy controller.
These bits are
unaffected by a software reset, and are set to
250 kbps after a hardware reset.
High density. This bit is low whenever the 500
kbps or 1 Mbps data rates are selected, and high
when 250 kbps and 300 kbps are selected.
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4.3 Result Phase Status Registers
The result phase of a command contains bytes that hold status information. The format of these bytes are described in the
following sections. Do not confuse these register bytes with the main status register which is a read-only register that is always
available. The result phase status registers are read from the data register only during the result phase.
4.3.1 Status Register 0 (ST0)
Table 4-16
Status Register 0 Description
Bit
Description
D7~D6
Interrupt Code :
00 =
Normal termination of command.
01 =
Abnormal termination of command.
Command was executed, but not successfully completed.
10 =
Invalid command issue. Command issued was not recognized as a valid command.
11 =
Ready changed state during the polling mode.
D5
Seek End: This bit is set after a seek or recalibrate command is completed by the controller. Used
during sense interrupt command.
D4
Equipment Check: This bit is set after a recalibrate command track 0 signal failed to occur. Used
during sense interrupt command.
D3
Not Used: 0
D2
Head Number: At end of execution phase.
D1, D0
Drive Select: At end of execution phase.
00 = Drive 0 selected
01 = Drive 1 selected
10 = Drive 2 selected
11 = Drive 3 selected
4.3.2 Status Register 1 (ST1)
Table 4-17
Status Register 1 Description
Bit
Description
D7
End of Track: This bit is set when the controller has transferred the last byte of the last sector
without the TC pin becoming active. The last sector is the end-of-track sector number programmed
in the command phase.
D6, D3
Not Used: 0
D5
CRC Error: If this bit is set and bit 5 of ST2 is clear, then there was a CRC error in the address field
of the correct sector. If bit 5 of ST2 is set, then there was a CRC error in the data field.
D4
Over Run: This bit is set when the controller was not serviced by the CPU soon enough during a
data transfer in the execution phase. Table 4-18 shows the time values.
D2
No Data: This bit is set for any three possible problems:
1. Controller cannot find the sector specified in the command phase during the execution of a
read, write, or scan command. An address mark was found even if it is not a blank disk.
2. Controller cannot read any address fields without a CRC error during read ID command.
3. Controller cannot find the starting sector during execution of read a track command.
D1
Not Writable: Set if the write protect pin is active when a write or format command is issued.
D0
Missing Address Mark: If this bit is set and bit 0 of ST2 is clear then the disk controller cannot
detect any address field address mark after two disk revolutions. If bit 0 of ST2 is set, then the disk
controller cannot detect the data field address mark.
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Table 4-18
Maximum Time Allowed to Service an Interrupt or Acknowledge a DMA Request in Execution Phase
Data Rate
125
250
500
125
Time to Service
62.0 us
30.0 us
14.0 us
6.0 us
4.3.3 Status Register 2 (ST2)
Table 4-19
Status Register 2 Description
Bit
Description
D7
Not Used: 0
D6
Control Mark: This bit is set if the controller tries to read a sector which contained a deleted data
address mark during execution of read-data or scan commands. Or, if a read-deleted-data command
was executed, a regular address mark is detected.
D5
CRC Error in Data Field: This bit is set if the controller detects a CRC error in the data field. Bit 5 of
ST1 is also set.
D4
Wrong Track: This bit is only set if the desired sector is not found, and the track number recorded on
any sector of the current track is different from that stored in the track register.
D3
Scan Equal Hit: This bit is only set if the equal condition is satisfied during any scan command.
D2
Scan Not Satisfied: This bit is set if the controller cannot find a sector on the track number recorded
on any sector on the track which meets the desired condition during scan commands.
D1
Bad Track: This bit is only set if the desired sector is not found, and the track number recorded on any
sector on the track is different from that stored in the track register and the recorded track number is
FF.
D0
Missing Address Mark in Data Field: This bit is set if the controller cannot find the data field address
mark during read/scan command. Bit 0 of ST1 is also set.
Page 40
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4.3.4 Status Register 3 (ST3)
Table 4-20
Status Register 3 Description
Bit
Description
D7
Not Used: 0
D6
Write Protect Status: This bit is the complement of the associated FDC interface pin for the drive
selected in DCR.
D5
Not Used: 1
D4
Track 0 Status: This bit is the complement of the associated FDC interface pin for the drive selected
in the DCR.
D3
Not Used: 0
D2
Head Select Status:
command phase.
D1, D0
Drive Selected: These bits show the status of the associated bits in the sense-drive-status command
phase. These bits show the same status as ST0 bits 1, 0.
00 = Drive 0 selected
01 = Drive 1 selected
10 = Drive 2 selected
11 = Drive 3 selected
This bit shows the status of the associated bit in the sense-drive-status
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4.4 Controller Functional Description
4.4.1 Controller Phases
4.4.1.2.2 Interrupt Mode
The FDC handles commands in three phases—
command,
execution and result. Each phase is described below.
If the non-DMA mode is selected, an interrupt is generated
in the execution phase when each byte is ready to be
transferred. The Main Status Register should be read to
verify that the interrupt is for a data transfer. Bits 5 and 7 of
the Main Status Register is set. The interrupt is cleared
when the byte is transferred to or from the data register.
The CPU should transfer the byte within the allotted time. If
the byte is not transferred within the time allotted, an
overrun error is indicated in the result phase when the
command terminates at the end of the current sector.
4.4.1.1 Command Phase
The CPU writes a series of bytes to the data register. These
bytes indicate the command desired and the particular
parameters required for the command. All the bytes must
be written in the order specified in the command description
table. The execution phase starts immediately after the last
byte in the command phase is written.
The Main Status Register controls the flow of command
bytes, and must be polled by the software before writing
each Command Phase byte to the Data Register. Prior to
writing a command byte, the bit 7 must be set and bit 6
must be cleared in the MSR. After the first command byte is
written to the Data Register, the bit 4 in MSR is also set and
remain set until the last Result Phase byte is read. If there is
no Result Phase, it is cleared after the last command byte is
written. A new command may be initiated after reading all
the result bytes from the previous command.
4.4.1.2 Execution Phase
The disk controller performs the desired command. Some
commands require the CPU to read or write data to or from
the data register during this phase. Some commands such
as Seek control the read/write head movement on the disk
drive. Some commands does not involve any action by the
uP or disk drive, and consists of an internal operation by the
controller.
If there is data to be transferred between the uP and the
controller, there are three methods that can be used, DMA
mode, interrupt mode, and software polling mode. All of
these data transfer modes work with the FIFO enabled or
disabled.
An interrupt is also generated after the last byte is
transferred. This indicates the beginning of the Result
Phase.
4.4.1.2.3 Software Polling
If the non-DMA mode is selected and interrupts are not
suitable, the CPU can poll the Main Status Register during
the execution phase to determine when a byte is ready to be
transferred. The bit 7 of the Main Status Register reflects
the state of the interrupt pin. Otherwise, the data transfer is
similar to the interrupt mode described above.
4.4.1.3 Result Phase
During the Result Phase, the uP reads a series of bytes
from the data register. These bytes indicate the status of the
command. This status may indicate whether the command
executed properly, or contain some control information. The
bit 7 and bit 6 in the MSR must both be set before each
result byte can be read. After the last result byte is read, the
bit 4 in the MSR is cleared, and the controller is ready for
the next command.
4.4.1.2.1 DMA Mode
If the DMA mode is selected, a DMA request is generated in
the execution phase when each byte is ready to be
transferred. To enable DMA operations during the execution
phase, the DMA mode bit in the Specify command must be
enabled, and the DMA signals must be enabled in the Drive
Control Register. The DMA controller responds to the DMA
request with a DMA-acknowledge and a read- or writestrobe. The DMA request is cleared by the active edge of the
DMA-acknowledge. After the last byte is transferred, an
interrupt is generated, indicating the beginning of the result
phase. TC is asserted to terminate an operation. Due to
internal gating, TC is only recognized when the -DAK input
is low.
Page 42
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--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Table 4-21
M512x FDC Command Set
READ DATA
READ A TRACK
Command Phase
MT
MFM
SK
IPS
0
0
Command Phase
0
MFM
0
IPS
0
0
0
0
1
1
0
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data read from disk drive is transferred
to system via DMA or Non-DMA modes.
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
0
0
0
1
0
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data read from disk drive is transferred
to system via DMA or Non-DMA modes.
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
READ DELETED DATA
READ ID
Command Phase
MT
MFM
SK
IPS
0
0
Command Phase
0
MFM
0
0
1
0
1
0
0
0
0
0
0
HD
DR1 DR0
Execution Phase: Controller reads first ID Field header
bytes it can find and reports these bytes to the system in the
result bytes
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
0
1
1
0
0
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data read from disk drive is transferred
to system via DMA or Non-DMA modes.
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
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M512x : Mega I/O Controller with PnP
WRITE DATA
FORMAT A TRACK
Command Phase
MT
MFM
0
IPS
0
0
Command Phase
0
MFM
0
0
0
0
0
0
1
0
1
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data is transferred from the system to
the controller via DMA or Non-DMA modes and written to
the disk.
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
0
1
0
0
1
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data is transferred from the system to
the controller via DMA or Non-DMA modes and written to
the disk.
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
Page 44
SCAN EQUAL
Command Phase
MT
MFM
SK
IPS
0
0
WRITE DELETED DATA
Command Phase
MT
MFM
0
IPS
0
0
0
1
1
0
1
0
0
HD
DR1 DR0
Bytes per Sector
Sector per Track
Format Gap
Data Pattern
Execution Phase: System transfers four ID bytes per sector
to the floppy controller via DMA or Non-DMA modes. The
entire track is formatted. The data block in the Data Field of
each sector is filled with the data pattern byte
Result Phase
Status Register 0
Status Register 1
Status Register 2
Undefined
Undefined
Undefined
Undefined
1
0
0
0
1
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data transfer from system to controller is
compared to data read from disk
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
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--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
SCAN HIGH OR EQUAL
VERIFY
Command Phase
MT
MFM
SK
IPS
0
0
Command Phase
MT
MFM
SK
0
0
0
1
1
1
0
1
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data transfer from system to controller is
compared to data read from disk
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
1
0
1
1
0
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data is read from disk but not transferred
to the system.
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
SCAN LOW OR EQUAL
DUMPREG
Command Phase
MT
MFM
SK
IPS
0
0
Command Phase
0
0
0
0
1
1
1
0
Execution Phase: Internal registers read
Result Phase
Present Track Number on Drive 0
Present Track Number on Drive 1
Present Track Number on Drive 2
Present Track Number on Drive 3
Step Rate Time
Motor Off Time
Motor On Time
DMA
Sector per Track/End of Track
LOCK
0
D3
D2
D1
D0
GAP WG
0
EIS FIFO POLL
FIFOTHR
PRETRK
1
0
0
0
1
0
0
HD
DR1 DR0
Track Number
Drive Head Number
Sector Number
Bytes per Sector
End of Track Sector Number
Intersector Gap Number
Data Length
Execution Phase: Data transfer from system to controller is
compared to data read from disk
Result Phase
Status Register 0
Status Register 1
Status Register 2
Track Number
Head Number
Sector Number
Bytes per Sector
PERPENDICULAR MODE
Command Phase
0
0
0
1
0
0
1
OW
0
D3
D2
D1
D0
GAP
Execution Phase: Internal registers are written.
No Result Phase.
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0
WG
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M512x : Mega I/O Controller with PnP
CONFIGURE
SENSE INTERRUPT
Command Phase
0
0
0
1
0
0
1
0
0
0
0
0
0
0
0
EIS FIFO POLL
FIFOTHR
PRETRK
Execution Phase: Internal registers are written.
No Result Phase
1
0
Command Phase
0
0
0
0
1
0
0
Execution Phase: Status of interrupt is reported
Result Phase
Status Register 0
Present Track Number
0
SPECIFY
RECALIBRATE
Command Phase
0
0
0
0
0
1
1
1
0
0
0
0
0
0
DR1 DR0
Execution Phase: Disk drive head is stepped out to Track
0.
No Result Phase
Command Phase
0
0
0
0
0
0
1
1
Step Rate Time
Motor Off Time
Motor On Time
DMA
Execution Phase: Internal registers are written.
No Result Phase
POWERDOWN MODE
RELATIVE SEEK
Command Phase
1
DIR
0
0
1
1
1
1
0
0
0
0
0
HD
DR1 DR0
Relative Track Number
Execution Phase: Disk drive head stepped in or out a
programmable number of tracks.
No Result Phase
SEEK
Command Phase
0
0
0
0
0
0
0
1
1
1
1
0
0
HD
DR1 DR0
New Track Number
Execution Phase: Disk drive head is stepped in or out to a
desired track.
No Result Phase
SENSE DRIVE STATUS
Command Phase
0
0
0
0
0
1
0
0
0
0
0
0
0
HD
DR1 DR0
Execution Phase: Disk drive status information is detected
and reported.
Result Phase
Status Register 3
Page 46
Command Phase
0
0
0
1
0
1
1
0
0
0
0
0
0
DLY
Execution Phase: Internal registers are written
Result Phase
0
0
0
0
0
0
DLY
1
APD
APD
VERSION
Command Phase
0
0
0
Result Phase
1
0
0
1
0
0
0
0
1
0
0
0
0
LOCK
Command Phase
LOCK
0
0
1
0
1
0
Execution Phase: Internal registers are written.
Result Phase
0
0
0
LOCK
0
0
0
0
0
INVALID
Command Phase
Invalid Codes
Result Phase
Status Register 0 (80H)
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4.6 Command Description
4.6.1 Read Data
The read data op-code is written to the data register
followed by 8 bytes as specified in the command description
table. After the last byte is written, the controller starts
looking for the correct sector header. Once the controller is
found, the controller sends data to the CPU. After one
sector is finished, the sector number is incremented by one
and this new sector is searched for. If MT (multi-track) is
set, both sides of one track can be read. Starting on side
zero, the sectors are read until the sector number specified
by end of track sector number is reached. Then, side one is
read by starting with sector number one.
In DMA mode, the read-data command continues to read
until the TC pin is set. This means that the DMA controller
should be programmed to transfer the correct number of
bytes. TC should be controlled by the CPU and be asserted
when enough bytes are received. An alternative to these
methods of stopping the read-data command is to program
the end of track sector number as the last sector number
that to be read. The controller stops reading the disk with
an error message indicating that it tried to access a sector
number beyond the end of the track.
The number of data bytes per sector parameter is defined in
Table 4-27. If this is set to zero, the data length parameter
defines the number of bytes that the controller transfers to
the CPU. If the data length specified is smaller than 128,
the controller still reads the entire 128 byte sector and
checks the CRC, though only the number of bytes specified
by the data length parameter are transferred to the CPU.
Data length parameter should not be set to zero. If the
number of bytes per sector parameter is not zero, the data
length parameter has no meaning and should be set to FFh.
Table 4-27
Bytes/Sector
Code
0
1
2
3
4
5
6
Sector Size Selection
Number of Bytes
in Data Field
128
256
512
1024
2048
4096
8192
If the implied seek mode is enabled by both the mode
command and the IPS bit in this command, a seek is
performed to the track number specified in the command
phase. The controller also waits for the head-settle-time if
the implied seek is enabled. After all these conditions are
met, the controller searches for the specified sector by
comparing the track number, head number, sector number,
and number of bytes/sector given in the command phase
with the appropriate bytes read off the disk in the address
fields.
If the correct sector is found, but there is a CRC error in the
address field, bit 5 of ST1 (CRC error) is set and an
abnormal termination is indicated. If the correct sector is
not found, bit 2 of ST1 (no data) is set and an abnormal
termination is indicated. In addition to this, if any address
field track number is FF, bit 1 of ST2 (bad track) is set or, if
any address field track number is different from that
specified in the command phase, bit 4 of ST2 (wrong track)
is set.
After finding the correct sector, the controller reads that data
field. If a deleted data mark is found and the SK bit is set,
the sector is not read, bit 6 of ST2 (control mark) is set, and
the next sector is searched for. If a deleted data mark is
found and the SK bit is not set, the sector is read, bit 6 of
ST2 (control mark) is set, and the read terminates with a
normal termination. If a CRC error is detected in the data
field, bit 5 is set to both ST1 and ST2 (CRC error) and an
abnormal termination is indicated.
If no problems occur in the read command, the read
continues from one sector to the next in logical order (not
physical order) until either TC is set or an error occurs. If a
disk has not been inserted into the disk drive, there are
many opportunities for the controller to hang. It does this if
it is waiting for a certain number of disk revolutions. If this
occurs, the controller can be forced to abort the command
by writing a byte to the data register.
An interrupt is generated when an execution phase of the
read data command terminates. Table 4-28 shows the
values that are read back in the result phase. If an error
occurs, the result bytes indicate the sector being read when
the error occurred.
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M512x : Mega I/O Controller with PnP
Table 4-24
Result Phase Termination Values with No Error
Last
MT
0
0
0
0
1
1
1
1
ID Information at Result Phase
HD
Sector
Track
0
< EOT
NC
0
= EOT
T+1
1
< EOT
NC
1
= EOT
T+1
0
< EOT
NC
0
= EOT
NC
1
< EOT
NC
1
= EOT
T+1
EOT = End of track sector number from command phase
S = Sector number last operated on by controller
4.6.2 Read-Deleted-Data
This command is the same as the read-data command
except for how it handles a deleted data mark. If a deleted
data mark is read, the sector is read normally. If a regular
data mark is found and the SK bit is set, the sector is not
read, bit 6 of ST2 (control mark) is set, and the next sector
is searched for. If a regular data mark is found and the SK
bit is not set, the sector is read, bit 6 of ST2 (control mark)
is set, and the read terminates with a normal termination.
4.6.3 Write-Data
The write-data command is very similar to the read-data
command except that data is transferred from the CPU to
the disk rather than the other way around. If the controller
detects the write-protect signal, bit 1 of ST1 (not writable) is
set and an abnormal termination is indicated.
4.6.4 Write-Deleted-Data
This command is the same as the write-data command
except that a deleted-data mark is written at the beginning of
the data field instead of the normal data mark.
4.6.5 Read a Track
This command is similar to the read-data command except
for the following: the controller starts at the index hole and
reads the sectors in their physical order, not their logical
order.
Even though the controller reads sectors in their physical
order, it still compares the header ID bytes with the data
programmed in the command phase. The exception to this
is the sector number. Internally, this is set to one, then
incremented for each successive sector read. Whether or
not the programmed address field matches that read from
Page 48
Head
NC
NC
NC
NC
NC
1
NC
0
Sector
S+1
1
S+1
1
S+1
1
S+1
1
B/S
NC
NC
NC
NC
NC
NC
NC
NC
NC = No change in value
T = Track number programmed in command phase
the disk, the sectors are still read in their physical order. If a
header ID comparison fails, bit 2 of ST1 (No data) is set, but
the operation continues. If there is a CRC error in the
address or data field, the read also continues.
The
command terminates when it has read the number of
sectors programmed in the EOT parameter.
4.6.6 Read ID
This command causes the controller to read the first
address field it finds. The result phase contains the header
bytes that are read. There is no data transfer during the
execution phase of this command. An interrupt is generated
when the execution phase is completed.
4.6.7 Format-a-Track
This command formats one track on the disk. After the
index hole is detected, data patterns are written on the disk
including all gaps, address marks, address fields, and data
fields. The exact details of the number of bytes for each
field is controlled by the parameters given in the format-atrack command, and the IAF (Index Address Field) bit in the
mode command. The data field consists of the fill-byte
specified in the command, repeated to fill the entire sector.
To allow for floppy formatting, the CPU must supply the four
address field bytes (track, head, sector, number of bytes) for
each sector formatted during the execution phase. In other
words, as the controller formats each sector, it requests four
bytes through either DMA requests or interrupts. This allows
for non-sequential sector interleaving. Table 4-29 shows
some typical values for the programmable gap size.
The format command terminates when the index hole is
detected a second time, at which point an interrupt is
generated. Only the first three status bytes in the result
phase are significant.
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--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Table 4-25A Gap Length for Various Sector Sizes and Disk Types
Mode
FM
MFM
FM
MFM
FM
MFM
Sector
Size
(Dec)
128
256
512
1024
2048
4096
256
512
1024
2048
4096
8192
128
128
256
512
1024
2048
256
256
512
1024
2048
4096
128
256
512
256
512
1024
Sector
Sector
Code
EOT
Gap
(Dec)
(Hex)
(Hex)
8-inch Drives (360 RPM, 500 kb/s)
00
1A
07
01
0F
0E
02
08
1B
03
04
47
04
02
C8
05
01
C8
01
0F
0E
02
0F
1B
03
08
35
04
04
99
05
02
C8
06
01
C8
5.25-inch Drives (300 RPM, 250 kb/s)
00
12
07
00
10
10
01
08
18
02
04
46
03
02
C8
04
01
C8
01
12
0A
01
10
20
02
08
2A
03
04
80
04
02
C8
05
01
C8
3.5-inch Drives (300 RPM, 250 kb/s)
00
0F
07
01
09
0E
02
05
1B
01
0F
0E
02
09
1B
03
05
35
Format*
Gap
(Hex)
1B
2A
3A
8A
FF
FF
36
54
74
FF
FF
FF
09
19
30
87
FF
FF
0C
32
50
F0
FF
FF
1B
2A
3A
36
54
74
Table 4-25B Format Table for PC-Compatible Diskette Media
Media
Type
360 K
1.2 M
720 M
1.44 M
2.88 M
Sector
Size
(Dec)
512
512
512
512
512
Sector
Code
(Hex)
02
02
02
02
02
EOT
(Hex)
09
0F
09
12
24
Sector
Gap
(Hex)
2A
1B
1B
1B
1b
Format*
Gap
(Hex)
50
54
50
6C
54
* Format gap is the gap length used only for the format command.
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M512x : Mega I/O Controller with PnP
Index pulse
Gap0 Sync IAM Gap1 Sync AM
80 of 12 of
50 of 12 of
Perpendicular MFM FF
00 3 of F 4E
00 3 of F
C2* C
A1* E
format
T
R
A
C
K
H Se #
E c t Byt
A o r es
D
C
R
C
Gap2 Sync
41 of 12 of
4E
00
Gap0 Sync IAM Gap1 Sync AM
80 of 12 of
50 of 12 of
4E
00 3 of F 4E
00 3 of F
MFM
C2* C
A1* E
T
R
A
C
K
H Se #
E c t Byt
A o r es
D
C
R
C
Gap2 Sync
22 of 12 of
4E
00
IBM
format
Index
address field
AM
3 FB
of or
A1 F8
*
Data
C
R
C
Gap3
Prog GAP4
ram
mable
Data
C
R
C
Gap3
Prog GAP4
ram
mable
C
R
C
Gap3
Prog GAP4
ram
mabl
e
AM
3 FB
of or
A1 F8
*
Address field
Data field
Repeated for each
sector
ISO
format
MFM
Gap1 Sync AM
32 of 12 of
4E
00 3 of F
A1* E
T
R
A
C
K
H Se #
E c t By
A o r tes
D
C
R
C
Gap2 Sync
22 of 12 of
4E
00
AM
3 FB
of or
A1 F8
*
Data
Figure 4-4 IBM, Perpendicular, and ISO Formats Supported by the Format Command
4.6.8 Scan Commands
The scan commands allow data read from the disk to be
compared against data sent from the CPU. There are three
scan commands to choose from:
Scan equal
Scan less than or equal
Scan greater than or equal
Disk data = CPU data
Disk data < CPU data
Disk data > CPU data
Each sector is interpreted with the most significant byte first.
If the wildcard mode is enabled from the mode command,
an FFh from either the disk or CPU is used as a "don't care"
byte that always matches equal. If each sector is read, the
desired condition has not been met, and the next sector is
read. The next sector is defined as the current sector
number plus the sector step-size specified.
Table 4-30
Scan Command Termination Values
Status Register
Command
Scan equal
Scan low
or equal
Scan high
or equal
D2 D3
0
1
1
0
0
1
0
0
1
0
0
1
0
0
1
0
Conditions
Disk = CPU
Disk <> CPU
Disk = CPU
Disk < CPU
Disk > CPU
Disk = CPU
Disk < CPU
Disk > CPU
4.6.9 Seek
The scan command continues until the scan condition has
been met, or the end of track sector number has been
reached, or if TC is asserted. If the SK bit is set, sectors
with deleted data marks are ignored. If all sectors read are
skipped, the command terminates with D3 of ST2 set (scan
equal hit). Table 4-30 shows the result phase of the
command.
Page 50
There are two ways to move the disk drive head to the
desired track number. The first method is to enable the
implied seek mode. This way, each individual read or write
command automatically moves the head to the track
specified in the command.
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The second method is by using the seek command. During
the execution phase of the seek command, the track number
to seek for is compared with the present track number, and
a step pulse is produced to move the head one track closer
to the desired track number. This is repeated at the rate
specified by the specify command until the head reaches the
correct track. At this point, an interrupt is generated and a
sense-interrupt command is required to clear the interrupt.
During the execution phase of the seek command, the only
indication via software that a seek command is in progress
is bits 0~3 (drive busy) of the main status register. Bit 4 of
the main status register (command in progress) is not set.
While the internal micro-engine is capable of multiple seeks
on two or more drives at the same time since the drives are
selected via the drive-control register in software, software
should ensure that only one drive performs the seek
command at one time. No other command except the
sense-interrupt command is issued while a seek command
is in progress.
If the extended track range mode is enabled, write a fourth
byte in the command phase to indicate the four most
significant bits of the desired track number. Otherwise, write
only three bytes.
4.6.10 Relative Seek
The Relative Seek command steps the selected drive in or
out a given number of steps. This command will step the
read/write head an incremental number of tracks from the
current track number, contrasting to step it to the desired
track number as Seek command. The Relative Seek
parameters are defined as follows:
DIR: Read/Write Head Step Direction Control
0=Step Head Out, 1=Step Head In
RTN: Relative Track Number. This value will determine how
many incremental tracks to step the head in or out
from
the current track number.
4.6.11 Recalibrate
The recalibrate command is very similar to the seek
command. It is used to step a drive head out to track zero.
Step pulses are produced until the track zero signal from the
drive becomes true. If the track zero signal does not go
before 77 step pulses are issued, an error is generated. If
the extended track range mode is enabled, an error is not
generated until 3,917 pulses are issued.
4.6.12 Sense-Interrupt Status
An interrupt is generated by the controller when any of the
following conditions occur:
1.
Upon entering the result phase of:
a. Read-data command
b. Read-deleted-data command
c. Write-data command
d. Write-deleted-data command
e. Read-a-track command
f. Read-ID command
g. Format command
h. Scan commands
2.
During data transfers in the execution phase while in the
non-DMA mode
3.
Internal ready signal changes state (only occurs
immediately after a hardware or software reset).
4.
Seek or recalibrate command termination
An interrupt generated for reasons 1 and 2 above occurs
during normal command operations and are easily
recognized by the CPU. During an execution phase in nonDMA mode, bit 5 (execution mode) in the MSR is set to 1.
Upon entering result phase, this bit is set to 0.
Reasons 1 and 2 do not require the sense interrupt status
command. The interrupt is cleared by reading or writing
information to the data register. Interrupts caused by
reasons 3 and 4 are identified with the aid of the sense
interrupt status command.
This command resets the
interrupt when the command byte is written.
Table 4-31 shows how to identify the cause of the interrupt
by using bits 5, 6 and 7 of ST0.
Issuing a sense-interrupt status command without an
interrupt pending is treated as an invalid command. If the
extended track range mode is enabled, a third byte should
be read in the result phase which indicates the four most
significant bits of the present track number. Otherwise, only
two bytes should be read.
Recalibrations on more than one drive at a time should not
be issued for the same reason as explained in the seek
command. No other command except the sense-interrupt
command should be issued while a recalibrate command is
in progress.
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4.6.13 Specify
The specify command sets the initial values for each of the
three internal timers.
Table 4-32 shows the timer
programming values.
The head-load and head-unload timers are artifacts of the
UPD765A. These timers determine the delay from loading
the head until a read or write command is started, and
unloading the head sometime after the command was
completed. Since the M512x head-load signal is now the
software-controlled motor lines in the drive-control register,
these timers only provide some delay from the initialization
of a command until it is actually started. Similar to the
DP8474, extend these timers setting the TMR bit in the
mode command.
The step-rate time defines the time interval between
adjacent step pulses during a seek, implied-seek, or
recalibrate command. The times stated in Table 4-32 are
affected by the data rate. These values are for 500 kb/s
MFM (250 Kb/s FM) and 1 Mb/s MFM (500 Kb/s FM). For
300 kb/s MFM data rate (150 Kb/s FM), these values,
multiply by 1.6667, and for 250 Kb/s MFM (125 Kb/s FM)
double these values.
The choice of DMA or non-DMA operation is made by the
non-DMA bit. When this bit is 1, the non-DMA mode is
selected, and when this bit is 0, DMA mode is selected.
This command does not generate an interrupt.
Table 4-31 Status Register 0 Termination Codes
Interrupt Code
D7
1
0
0
D6
1
0
1
D5
0
1
1
Seek End
Cause
Internal ready went true
Normal seek termination
Abnormal seek termination
Table 4-32 Step, Head, Load and Unload Timer Definitions (500 kb/s MFM)
Timer
Step Rate
Head Unload
Head Load
Mode 1
Value
Range
Mode 2
Value
Range
Unit
(16 - N)
N x 16
Nx2
1~16
0~240
0~254
(16 - N)
N x 512
N x 32
1~16
0~7680
0~4064
ms
ms
ms
4.6.14 Sense Drive Status
4.6.16 Version
This two-byte command obtains the status of a disk drive.
Status register 3 is returned in the result phase and contains
the drive status. This command does not generate an
interrupt.
The Version command can be used to determine the floppy
controller being used. The result phase uniquely identifies
the floppy controller version. The FDC returns a value of 90h
in order to be compatible with the 82077. For older version
compatible with NEC765 controller, a value of 80h (invalid
command) will return.
4.6.15 Verify
The VERIFY command is used to verify the data stored on a
disk. This command acts exactly like a READ DATA
command except that no data is transferred to the host.
Data is read from the disk and CRC is computed and
checked against the previously stored value.
Page 52
4.6.17 Dumpreg
The DUMPREG command is designed to support system
run-time diagnostics and application software development
and debug. The command returns important information
regarding the status of many of the programmed field in the
FDC. This can be used to verify the values initialized in the
FDC.
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4.6.18 Configure
4.6.20 Lock
The Configure command controls some operation modes of
the controller. It should be issued during the initialization of
the FDC after power up. These bits are set to their default
values after a hardware reset.
EIS: Enable implied seek. When EIS=1, the FDC will
perform a SEEK operation before executing a read/write
command. The default value is 0 (no implied seek).
The Lock command allows the user full control of the FIFO
parameters after a software reset. If the LOCK bit is set to 1,
then the EFIFO, FIFOTHR and PRETRK bits in the
Configure command are not affected by a software reset.
After the command byte is written, the result byte must be
read before continuing to the next command.
4.6.21 Invalid
EFIFO: Enable FIFO. When EFIFO=1, the FIFO is disabled
(NEC765A compatible mode). This means data is
transferred on a byte by byte basis. The default value is 1
(FIFO disable).
POLL: Disable Polling. When POLL=1, polling of the drives
is disabled. POLL defaults to 0 (polling enable). When
enabled, a single interrupt is generated after reset.
FIFOTHR: The FIFO threshold in the execution phase of a
read/write command. This is programmable from 1 to 16
bytes. FIFOTHR defaults to 00. A 00h selects one byte and
0Fh selects 16 bytes.
PRETRK:
Precompensation
start
track
number.
Programmable from track 0 to 255. PRETRK defaults to
track 0. A 00h selects track 0 and a FFh selects track 255.
4.6.19. Powerdown Mode
The Powerdown mode command allows the automatic
power management. The use of the command can extend
the battery life in portable PC applications. To enable auto
powerdown the command may be issued during the BIOS
power on self test (POST).
DLY: Minimum powerup timer. This bit is active only if APD
bit is enabled. Set this bit to 0 assigns a 10msec timer, and
to 1 assigns a 0.5sec timer. The timer will be re-initialized
after a command execution is finished (idle state) and start
to countdown. When the timer is expired, the FDC will enter
the powerdown state automatically.
APD: Enable auto powerdown. When set to 1, the auto
powerdown is enabled.
If an invalid command (illegal Opcode byte in the command
phase) is received by the controller, the controller responds
with ST0 in the Result Phase. The controller does not
generate an interrupt during this condition. The system
reads an 80h from ST0 indicating an invalid command was
received.
4.6.22 Perpendicular Mode
The Perpendicular Mode command is designed to support
the Perpendicular Recording disk drives (4Mbytes
unformatted capacity). The Perpendicular Mode command
configures each of the four logical drives as a perpendicular
or conventional disk drive. Configuration of the four logical
disk drives is done via the D3-D0 bits, or with the GAP and
WG control bits. This command should be issued during the
initialization of the floppy controller.
A 0 written to Dn sets drive n to conventional mode, and a 1
sets drive n to perpendicular mode. Also, the OW bit offers
additional control. When OW=1, changing the values of D3D0 is enabled. When OW=0, the internal values of D3-D0
are unaffected, regardless of what is written to D3-D0.
The function of the Dn bits must also be qualified by setting
both WG and GAP to 0. If WG and GAP are not set to 00,
they overrides whatever is programmed in the Dn bits. Table
4-4 below indicates the operation of the FDC based on the
values of GAP and WG. D3-D0 are unaffected by a software
reset, but WG and GAP are both cleared to 0 after a
software reset. A hardware reset resets all the bits to zero.
Table 4-4 Effects of WG and GAP bits
GAP
0
0
WG
0
1
1
0
1
1
Mode
GAP2 Length during Format
Conventional
22 Bytes
Perpendicular
22 Bytes
(500kbps)
Reserved
22 Bytes
(Conventional)
Perpendicular
41 Bytes
(1Mbps)
Portion of GAP2 re-written by Write Data Command
0 Bytes
19 Bytes
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0 Bytes
38 Bytes
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4.7 Parallel Port Mode FDC
In this mode, the floppy disk control signals are available on
the parallel port pins. When this mode is selected, the
parallel port is not available. There are four modes of
operation. These modes can be selected in index 0xF1 of
FDC configuration space. The FDC signals are multiplexed
onto the Parallel port pins as shown in table below.
0xF1[1:0]
0
0
0
1
1
0
1
1
Parallel port function
Printer
Printer
FDC(drive 0 or 1)
FDC(drive 1)
The FDC signals are multiplexed onto the Parallel port pins
as shown in table below.
Conn
Pin no.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
Page 54
Chip
pin no.
144
138
137
136
135
134
133
132
131
129
128
127
126
143
142
141
140
SPP
mode
STBJ
PD0
PD1
PD2
PD3
PD4
PD5
PD6
PD7
ACKJ
BUSY
PE
SLCT
AFDJ
ERRJ
INITJ
SLINJ
Type
FDC mode
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I
I
I
I
I/O
I
I/O
I/O
DS0J
INDEXJ
TRK0J
WPJ
RDATAJ
DSKCHGJ
Pin
direction
O
I
I
I
I
I
MTR0J
O
DS1J
MTR1J
WDATAJ
WGATEJ
DENSEL
HDSELJ
DIRJ
STEPJ
O
O
O
O
O
O
O
O
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--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Section 5 : Serial Port Registers
Each of the serial ports function as data input/output
interface in a microcomputer system. The system software
determines the functional configuration of the UARTs via a
tri-state 8-bit bi-directional data bus.
The UARTs are completely independent and perform serialto-parallel conversion on data characters received from a
peripheral device or a modem, and parallel-to-serial
conversion on data characters received from the CPU. The
CPU can read the complete status of any of the UARTs at
any time during the functional operation. Status information
reported includes the type and condition of the transfer
operations performed by the UART, as well as any error
conditions (parity, overrun, framing, or break interrupt).
The UARTs have programmable baud rate generator
capable of dividing the timing reference clock input by
divisors of 1 to (216 - 1), and producing a 16 X clock for
driving the internal transmitter logic. Provisions are also
included to use this 16 X clock to drive the receiver logic.
The UARTs have complete modem-control capability and a
processor-interrupt system. Interrupts can be programmed
to the user's requirements, minimizing the computing
required to handle communications link.
Table 5-1 lists the register addresses A2 ~ A0 (AEN is equal to zero). DLAB is the divisor latch access bit.
Table 5-1
Register
Address
Base +
0h
0h
0h
1h
1h
2h
2h
3h
4h
5h
6h
7h
Serial Port Registers
Access
(AEN=0)
DLAB
0
0
1
1
0
-
Abbreviation
Register Name
Access
THR
RBR
DLL
DLM
IER
IIR
FCR
LCR
MCR
LSR
MSR
SCR
Transmit Holding Register
Receiver Buffer Register
Divisor Latch LSB
Divisor Latch MSB
Interrupt Enable Register
Interrupt Identification Register
FIFO Control Register
Line Control Register
Modem Control Register
Line Status Register
Modem Status Register
Scratch Pad Register
W
R
R/W
R/W
R/W
R
W
R/W
R/W
R
R
R/W
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Table 5-2
Register Summary for Each UART Channel
Bit no.
0
1
2
3
4
5
6
7
Receiver
Buffer
Register
(Read only)
Transmitter
Holding
Register
(Write only)
Interrupt
Enable
Register
R
B
R
Data bit 0
(note 1)
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
T
H
R
Data bit 0
Data bit 1
Data bit 2
Data bit 3
Data bit 4
Data bit 5
Data bit 6
Data bit 7
I
E
R
Enable
received
data
available
interrupt
(ERDAI)
Enable
Receiver
Line
Status
Interrupt
(ELSI)
Enable
Modem
Status
Interrupt
(EMSI)
0
0
0
0
Interrupt
Ident.
Register
(Read only)
FIFO
control
register
(write only)
Line control
register
II
R
‘ 0’ if
interrupt
pending
Enable
Transmitter
Holding
Register
Empty
Interrupt
(ETHREI)
Interrupt ID
bit
Interrupt
ID bit
0
0
0
FIFO
enable
FIFO
enable
F
C
R
FIFO
enable
RCVR FIFO
Reset
Xmit FIFO
reset
reserved
reserved
reserved
RCVR
Trigger
(LSB)
RCVR
Trigger
(MSB)
L
C
R
Word
length
select bit 0
(WLS0)
Word
Length
Select bit 1
(WLS1)
Number of
Stop Bits
(STB)
Parity
Enable
(PEN)
Even
Parity
Select
(EPS)
Stick
Parity
Set Break
4
Modem
control
register
M
C
R
Request to
send (RTS)
Out 1
(Note 3)
IRQ
Enable
(Note 3)
Loop
0
0
5
Line status
register
L
S
R
Data
Terminal
ready
(DTR)
Data ready
(DR)
Divisor
Latch
Access
Bit
(DLAB)
0
Overrun
error (OE)
Parity
Error (PE)
Framing
Error (FE)
Break
Interrupt
(BI)
6
Modem
status
register
M
S
R
Delta Clear
to Send
(DCTS)
Delta Data
Set Ready
(DDSR)
Clear to
Send
(CTS)
Bit 0
Bit 1
Bit 4
Bit 5
Bit 6
Bit 0
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
1
DLAB=1
Divisor
latch (MS)
S
C
R
D
L
L
D
L
M
Data
Carrier
Detect
(DCD)
Bit 7
0
DLAB=1
Scratch
register
(note 4)
Divisor
latch (LS)
Delta Data
Carrier
Detect
(DDCD)
Bit 3
Transmitte
r Empty
(TEMT)
note 2
Ring
Indicator
(RI)
7
Trailing
Edge ring
indicator
(TERI)
Bit 2
Transmitte
r Holding
Register
(THRE)
Data Set
Ready
(DSR)
Bit 8
Bit 9
Bit 10
Bit 11
Bit 12
Bit 13
Bit 14
Bit 15
0
DLAB=0
0
DLAB=0
1
DLAB=0
2
2
3
Note :
Page 56
Error in
RCVR
FIFO
1. Bit 0 is the least significant bit. It is the first bit serially transmitted or received.
2. When operating in the XT mode, this bit will be set any time that the transmitter shift register is empty.
3. This bit no longer has a pin associated with it.
4. When operating in the XT mode, this register is not available.
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M512x : Mega I/O Controller with PnP
5.1 Line Control Register (LCR)
The system programmer uses this read/write register to specify the format of the asynchronous data communications exchange
and set the divisor latch access bit.
Table 5-3
Bit
7
6
5
4
3
2
0-1
LCR Registers
Function
Divisor latch access bit (DLAB).
1 = To access divisor latches of the baud generator or the alternate function register during a read
or write operation.
0 = To access any other register.
Break control bit. This bit causes a break condition to be transmitted to the receiving UART.
1 = Serial output (SOUT) is forced to the spacing logic
0 = Break is disabled
This bit acts only on SOUT and has no effect on transmitter logic. This enables the CPU to alert a
terminal in a computer communications system. If the following sequence is followed, no erroneous
or extraneous characters are transmitted because of the break :
1.
Load all 0s, pad character in response to THRE.
2.
Set break after the next THRE.
3.
Wait for the transmitter to be idle, (TEMT = 1), and clear break when normal transmission has
to be restored. During the break, the transmitter can be used as a character timer to
accurately establish the break duration.
Stick parity bit. When parity is enabled, it is used in conjunction with bit 4 to select, mark or space
parity.
1 = Enable stick parity
0 = Disable stick parity
Parity select bit. Selects either an odd or even number of 1's to be transmitted/checked in the data
word bit and parity bit.
0 = Odd number of 1's (parity bit is a logic 1, mark parity)
1 = Even number of 1's (parity bit is a logic 0, space parity)
Parity enable bit. The parity bit is used to produce an even or odd number of 1's when the data bits
and the parity bit are added. A parity bit is generated (transmit data) or checked (received data)
between the last data bit and the stop bit of the serial data.
0 = Parity bit is not generated/checked
1 = Parity bit is generated/checked
Specifies the number of stop bits transmitted with each serial character. The receiver checks the first
stop bit only, regardless of the number of stop bits selected.
0 = 1 stop bit
1 = 1.5 stop bits, when a 5-bit data length is selected
1 = 2 stop bits, when 6-, 7-, or 8-bit data length is selected
Specify the number of data bits (data length) in each transmitted or received serial character. The
following are the bit values:
00 = 5 bits
01 = 6 bits
10 = 7 bits
11 = 8 bits
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5.2 Programmable Baud Generator
The UART contains two independently programmable baud
generators. The 24-MHz crystal oscillator frequency input is
divided by 13, resulting in a frequency of 1.8462-MHz. This
is sent to each baud generator and divided by the divisor for
the associated UART. The output frequency of the baud
generator is 16 X the baud rate, [divisor # = (frequency
input) / (baud rate x 16)]. The output of each baud
generator drives the transmitter and receiver sections of the
associated serial channel. Two 8-bit latches per channel
store the divisor in a 16-bit binary format. These divisor
latches must be loaded during initialization to ensure proper
operation of the baud generator. Upon loading either of the
divisor latches, a 16-bit baud counter is loaded.
Table 5-5 provides decimal divisors to use with crystal
frequencies of 24-MHz. The oscillator input to the chip
should always be 24-MHz to ensure that the FDC timing is
accurate and that the UART divisors are compatible with
existing software.
Using a divisor of zero is not
recommended.
5.3 Line Status Register (LSR)
This register provides status information to the CPU
concerning the data transfer. LSR is intended for read
Table 5-4
operations only. Writing to this register is not recommended
as this operation is only used for factory testing.
Line Status Register Function Definition
Bit
Function
7
In 16450 mode, this bit is set to 0. In FIFO, LSR7 is set when there is at least one parity error, framing
error or break indication in the FIFO LSR7 is cleared when the CPU reads the LSR, if there are no
subsequent errors in the FIFO.
This bit changes its function depending on whether the device is operating in XT/AT mode. When in
the AT mode, this bit is the transmitter empty (TEMT) indicator. It is set to 1 whenever the transmitter
holding register (THR) and the transmitter shift register (TSR) are both empty. It is reset to 0 whenever
either the THR or TSR contains a data character.
Transmitter holding register empty (THRE) indicator. It indicates that the UART is ready to accept a
new character for transmission. It also causes the UART to issue an interrupt to the CPU when the
THRE interrupt enable is set high. It is set to 1 when a character is transferred from the THRE into
TSR. It is reset to 0 whenever the CPU loads the THRE.
Break interrupt (BI) indicator. It is set to 1 when the received data input is held in the spacing (logic 0)
state for longer than a full word transmission time (that is, the total time of start bit data bits parity
stop bits). It is reset whenever the CPU reads the contents of the LSR. Restarting after a break is
received requires the SIN pin to be logical 1 for at least 1/2-bit time.
Framing error (FE) indicator. This bit indicates that the received character did not have a valid stop bit.
It is set to 1 whenever the stop bit following the last data bit or parity bit is a logic 0 (spacing level).
The FE indicator is reset whenever the CPU reads the contents of LSR. The UART tries to
resynchronize after a framing error. To do this, it assumes that the FE was due at the next start bit, so
it samples this start bit twice and then takes in the data.
Parity error (PE) indicator. This bit indicates that the received data character does not have the correct
even or odd parity, as selected by the even-parity-select bit. It is set to 1 upon detection of a parity
error and reset to 0 whenever the CPU reads the contents of the LSR.
Overrun error (OE) indicator. It indicates that data in the RBR was not read by the CPU before the next
data was transferred into the RBR, thereby destroying the previous data. It is set to 1 upon detection of
an overrun condition and reset to 0 whenever the CPU reads the contents of the LSR.
Receive data ready (DR) indicator. It is set to 1 whenever a complete incoming character has been
received and transferred into the RBR. It is reset to 0 by reading the data in the RBR.
6
5
4
3
2
1
0
Page 58
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Table 5-5
Desired
baud rate
50
75
110
134.5
150
300
600
1200
1800
2000
2400
3600
4800
7200
9600
19200
38400
57600
115200
230400
460800
Baud rates using 1.8462 MHz Clock (24 MHz/13)
Divisor used to
generate 16x clock
2304
1536
1047
857
768
384
192
96
64
58
48
32
24
16
12
6
3
2
1
32770
32769
C
0.001
0.004
0.005
0.030
0.16
0.16
0.16
0.16
Bit 5 in
CR8 or 9
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
1
1
5.4 Interrupt Identification Register (IIR)
This register keeps a record of the four interrupts prioritized
by the UART to reduce software overhead during data
transfers. The four levels of interrupt conditions in order of
priority are: receiver-line-status, received-data-ready,
transmitter-holding-register-empty, and modem-status.
When the CPU accesses the IIR, the UART freezes all
interrupts and indicates the highest priority pending interrupt
to the CPU. While this CPU access is occurring, the UART
records new interrupts, but does not change its current
indication until the access is complete.
Table 5-6
Interrupt Identification Register
Bit
6~7
Function
These two bits are set when the FIFO
control register bit 0 equals 1.
Always '0'.
ln non-FIFO mode, this bit is a logic 0.
In FIFO mode, this bit is set along with
bit 2 when a timeout interrupt is pending.
Identifies the highest interrupt pending.
Used in an interrupt environment to
indicate whether an interrupt condition is
pending. If yes, the IIR contents may be
used as a pointer to the appropriate
interrupt service routine.
0 = Interrupt pending
1 = No interrupt pending
4~5
3
1~2
0
Note : C refers to % Error Difference between desired and
actual, except where shown otherwise, is 0.2 %.
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Table 5-6
Interrupt Control Table
FIFO
mode
only
D3
Interrupt
ID.
register
D2-D1-D0
0
0
Interrupt Set and Reset Functions
0- 0- 1
1- 1- 0
Priority
level
highest
Interrupt
type
None
Receiver
line status
0
1- 0- 0
second
1
1- 0- 0
second
Received
data
available
Character
timeout
Indication
0
0- 1- 0
third
0
0- 0- 0
fourth
Transmitter
holding
register
empty
MODEM
status
Interrupt source
Interrupt Reset control
None
Overrun error,
Parity error,
Framing error
Break interrupt
Received data available
Reading
register
No characters have been
removed from or input to
the RCVR FIFO during the
last 4 char times and there
is at least 1 char in it during
this time.
Transmitter
Holding
Register Empty
Clear to send or data set
ready
the
line
status
Read receiver buffer or the
FIFO drops below the
trigger level
Reading the Receiver Buffer
Register
Reading the IIR Register or
writing
the
transmitter
holding register
Reading the Modem status
register
5.5 Interrupt Enable Register (IER)
This register enables the four types of UART interrupts.
Each interrupt can individually activate the UR2IRQA or
UR1IRQA output signal. Resetting bits 0 ~ 3 of the IER
disables the interrupt system. Similarly, setting bits of this
register to 1 enables the selected interrupts. Disabling an
interrupt prevents it from being indicated as active in the IIR
and from activating the interrupt output signal. All other
system functions operate in their normal manner, including
the setting of the line status and modem status registers.
Table 5-8
Bit
0
1
2
3
4-7
Interrupt Enable Register
Function
Enables the received-data-available interrupt
Enables the THRE interrupt
Enables the receiver-line-status interrupt
Enables the modem-status interrupt
Always 0
5.6 FIFO Control Register
Bit 1: Writing a 1 to FCR1 clears all bytes in the RCVR
FIFO and resets its counter logic to 0. The shift register is
not cleared. The 1 that is written to this bit position is selfclearing.
Bit 2: Writing a 1 to FCR2 clears all bytes in the XMIT FIFO
and resets its counter logic to 0. The shift register is not
cleared. The 1 that is written to this bit position is selfclearing.
Bit 3: Setting FCR3 to a 1 will cause the RXRDY and
TXRDY pins to change from mode 0 to mode 1 if FCR0 = 1
Bit 4, 5: FCR4 to FCR5 are reserved for future use.
This is a write only register at the same location as the IIR
(the IIR is a read only register). This register is used to
enable the FIFOs, clear the FIFOs, set the RCVR FIFO
trigger level, and select the type of DMA signalling.
Page 60
Bit 0: Writing a 1 to FCR0 enables both the XMIT and
RCVR FIFOs. Resetting FCR0 will clear all bytes in both
FIFOs. When changing from FIFO mode to NS16450 mode
and vice versa, data is automatically cleared from the
FIFOs. This bit must be a 1 when other FCR bits are
written to or they will not be programmed.
Bit 6, 7: FCR6 and FCR7 are used to set the trigger level for
the RCVR FIFO interrupt.
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7
6
0
0
1
1
0
1
0
1
RCVR FIFO
Trigger Level (Bytes)
01
04
08
14
5.7 Modem Control Register (MCR)
This register controls the interface with the modem or data set (or a peripheral emulating a modem).
Table 5-9
Modem Control Register
Bit
Function
7-5
Set to logic 0.
4
This bit provides a local loopback feature for the UART diagnostic testing. When set to 1, the following
occurs: the transmitter serial output (SOUT) is set to the marking (1) state; the receiver serial input
(SIN) is disconnected; the output of the transmitter shift register is looped back into the receiver shift
register input; the four modem control inputs (DSRJ, CTSJ, RIJ, and DCDJ) are disconnected; and the
DTRJ, RTSJ, OUT1, IRQ enable bits in MCR respectively. When operating in AT mode, the modem
control output pins are forced to their high (inactive) states. In the diagnostic mode, data that is
transmitted is immediately received. This feature allows the processor to verify the transmit-andreceive data paths of the serial port. In the diagnostic mode, the receiver and transmitter interrupts are
fully operational. The modem status interrupts are also operational, but the interrupt's sources are the
lower four bits of MCR instead of the four modem control inputs. Writing a 1 to any of them causes an
interrupt. The interrupts are still controlled by the IER.
3
This bit enables the interrupt when set. In local loopback mode, this bit controls bit 7 of the MSR.
2
This is the OUT1 bit. It does not have an output pin associated with it. It can be written to and read by
the CPU. In local loopback mode, this bit controls bit 6 of the MSR.
1
Controls the RTSJ output. In local loopback mode, this bit controls bit 4 of the MSR.
0
Controls the DTRJ output. In local loopback mode, this bit controls bit 5 of the MSR.
1 = DTRJ output is forced to 0
0 = DTRJ output is forced to 1
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5.8 Modem Status Register (MSR)
This register gives the current state of the control lines from
the modem to the CPU. The bits are set to 1 whenever a
Table 5-10
control input from the modem changes state, and set to 0
when CPU reads the MSR.
Modem Status Register
Bit
7
6
5
4
3
2
1
0
Function
Complement of the DCDJ input. If bit 4 (loopback) of the MCR is set to 1, this bit is equivalent to IRQ
enable in the MCR.
Complement of the RIJ input. If bit 4 (loopback) of the MCR is set to 1, this bit is equivalent to OUT1
in the MCR.
Complement of the DSRJ input. If bit 4 (loopback) of the MCR is set to 1, this bit is equivalent to DTR
in the MCR.
Complement of the CTSJ input. If bit 4 (loopback) of the MCR is set to 1, this bit is equivalent to RTS
in the MCR.
Delta data carrier detect (DDCD) indicates that the DCDJ input to the chip has changed state.
Whenever bit 0, 1, 2 or 3 is set to 1, a modem status interrupt is generated.
Trailing edge of ring indicator (TERI) detector indicates that the RIJ input of the chip has changed from
a low to high state.
Delta data set ready (DDSR) indicates that the DSRJ input to the chip has changed its state
since the last time it was read by the CPU.
Delta clear to send (DCTS) indicates that CTSJ input to the chip has changed its state since
the last time it was read by CPU.
5.9 Scratchpad Register (SCR)
The 8-bit read/write register does not control the UART in
any way. It is intended as a scratchpad register to be used
by the programmer to hold data temporarily.
can be programmed in this mode. The transfer signals will
rout to SIN1/SIN2 and SOUT1/SOUT2. Two additional pins,
IRRX and IRTX, are also provided.
5.10 Infrared Interface
5.10.1 Sharp-IR Mode
5.10.2 IrDA SIR Mode
This mode supports bidirectional data communication with a
remote device using infrared radiation as the transmission
medium. Sharp-IR uses Amplitude Shift Key (ASK) and
allows serial communication at baud rates up to 38.4K
Baud. The format of the serial data is similar to the UART
data format, a zero value start bit, followed by up to 8 data
bits, an optional parity bit, and ending with at least one stop
bit with a binary value of one. A zero is signalled by sending
a 500KHz continuous pulse train of infrared radiation. A one
is signalled by the absence of any infrared signal.
The device operation in Sharp-IR mode is similar to the
operation in UART. The main difference is that the data
transfer is normally performed in half duplex fashion, and
the modem control and status signals are not used.
Selection of this mode is controlled by the IR mode bits in
the UART’ s configuration space. Both UART1 and UART2
Page 62
This is an operation mode similar to Sharp-IR. The IrDA 1.0
SIR allows serial communication at baud rates up to 115.2K
Baud. The data format is the same as Sharp-IR mode
except no parity bit is needed. A zero is signalled by
sending a single infrared pulse. A one is signalled by not
sending any pulse. The width of each pulse is 3/16ths of a
single bit time.
The device operation in IrDA 1.0 SIR mode is similar to the
operation in UART. The main difference is that the data
transfer is normally performed in half duplex fashion, and
the modem control and status signals are not used.
Selection of this mode is controlled by the IR mode bits in
the UART’ s configuration space. Both UART1 and UART2
can be programmed in this mode. The transfer signals will
rout to SIN1/SIN2 and SOUT1/SOUT2. Two additional pins,
IRRX and IRTX, are also provided.
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M512x : Mega I/O Controller with PnP
Section 6 : Keyboard Controller and Real Time Clock Functional Description
6.1 Keyboard and RTC ISA Interface
6.2 Keyboard Controller
The M512x ISA interface is functionally compatible with
the M8042 style host interface. It consists of the D0-D7
data bus; the IORJ, IOWJ and the Status register, Input
Data register, and Output Data register. Table below
shows how the interface decodes the control signals. In
addition to the above signals, the host interface includes
keyboard and mouse IRQ’ s.
The Universal Keyboard Controller uses an M8042
microcontroller CPU cord. This section concentrates on
the M512x enhancements to the M8042.
KIRQ
P24
MIRQ
P25
GATE A20
P21
RC Reset
P20
ISA I/O Address Map
ISA Address
0x70 (R/W)
0x71 (R/W)
BLOCK
RTC
RTC
FUNCTION
Address Register (70H)
Data Register (71H)
M8042
LS05
KDAT
P27
P10
KCLK
P26
ST0
MCLK
P23
ISA
Address
0x60
0x64
nIOW
nIOR
Block
Function (Note 1)
TST1
MDAT
P22
0
1
KDATA
1
0
KDATA
0
1
KDCTL
1
0
KDCTL
Keyboard Data
Write (C/D=0) (60h)
Keyboard Data
Read (60h)
Keyboard
Command Write
(C/D=1) (64h)
Keyboard Status
Read (64h)
Note 1 : These registers consist of three separate 8-bit
registers. Status, Data/Command write and Data
Read.
P11
Keyboard and Mouse Interface
KIRQ is the Keyboard IRQ
MIRQ is the Mouse IRQ
P21 is the CIO14 alternate function, can be used for Gate
A20.
P20 can be used to optionally RC reset.
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Keyboard Data Write
Host-to-CPU Communication
This is an 8 bit write only register. When written, the C/D
status bit of the status register is cleared to zero and the
IBF bit is set.
The host system can send both commands and data to
the Input Data register. The CPU differentiates between
commands and data by reading the value of Bit 3 of the
Status register. When bit 3 is “ 1” , the CPU interprets the
register contents as a command. When Bit 3 is “ 0” , the
CPU interprets the register contents as data. During a
host write operation, bit 3 is set to “ 1” if SA2 = 1 or reset
to “ 0” if SA2 = 0.
Keyboard Data Read
This is an 8 bit read only register. If enabled by “ ENABLE
FLAGS” , the KIRQ output is cleared and the OBF flag in
the status register is cleared. If not enabled, the KIRQ
and/or AUXOBF1 must be cleared in software.
KIRQ
Keyboard Command Write
This is an 8 bit write only register. When written, the C/D
status bit of the status register is set to one and the IBF bit
is set.
Keyboard Status Read
This is an 8 bit read only register. Refer to the description
of the Status Register for more information.
If “ ENFLAGS has not been executed: KIRQ can be
controlled by writing to P24. Writing a zero to P24 forces
KIRQ low, a high forces KIRQ high.
CPU-to-Host Communication
The heart of M512x can write to the Output Data register
via register DBB. A write to this register automatically sets
Bit 0 (OBF) in the Status register. See table below
Host Interface Flags
M8042
Instruction
OUT DBB
If “ EN FLAGS” has been executed and P24 is set to a one:
the OBF flag is gated onto KIRQ. The KIRQ signal can be
connected to system interrupt to signify that the M512x
CPU has written to the output data register via “ OUT DBB,
A” . If P24 is set to a zero, KIRQ is forced low. At powerup, after a valid reset pulse has been delivered to the
device, KIRQ is reset to 0. KIRQ normally reflects the
status of “ DBB” .
FLAG
Set OBF, and, if enabled, the
KIRQ output signal goes high
MIRQ
If “ EN FLAGS” has been executed and P25 is set to a one:
IBF is inverted and gated onto MIRQ. The MIRQ signal
can be connected to system interrupt to signify that the
M512x CPU has read the DBB register. If “ ENFLAGS has
not been executed : MIRQ and is controlled by P25.
Writing a zero to P25 forces MIRQ low, a high forces
MIRQ high. (MIRQ is normally selected as IRQ12 for
mouse support.)
Gate A20
A general purpose P21 can be routed out to the Common
I/O pin CIO14 for use as a software controlled Gate A20 or
user defined output.
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M512x : Mega I/O Controller with PnP
External Keyboard and Mouse Interface
Hard Power Down Mode
Industry-standard PC-AT compatible keyboards employ a
two-wire,
bi-directional
TTL
interface
for
data
transmission. Several sources also supply PS/2 mouse
products that employ the same type of interface. To
facilitate system expansion, the M512x provides four
signal pins that may be used to implement this interface
directly for an external keyboard and mouse.
This mode is entered by executing a STOP instruction.
The oscillator is stopped by disabling the oscillator driver
cell. When either RESET is driven active or a data byte is
written to the DBBIN register by a master CPU, the mode
will be exited (as above). However, as the oscillator cell
will require an initialization time, either RESET must be
held active for sufficient time to allow the oscillator to
stabilize. Program execution will resume as above.
The M512x has four high-drive, open-drain output (1),
bidirectional port pins that can be used for external serial
interfaces, such as ISA external keyboard and PS/2-type
mouse interfaces. They are KCLK, KDAT, MCLK and
MDAT.
P26 is inverted and output as KCLK. The KCLK pin is
connected to TESTO. P27 is inverted and output as
KDAT. The KDAT pin is connected to P70. P23 is
inverted and output as MCLK. The MCLK pin is connected
to TEST1. P22 is inverted and output as MDAT. The
MDAT pin is connected to P11. NOTE : External pull-ups
may be required.
Interrupts
The M512x provides the two M8042 interrupts. IBF and
the Timer/Counter Overflow.
Memory Configurations
The M512x provides 2K of on-chip ROM and 256 bytes of
on-chip RAM.
Register Definitions
Keyboard Power Management
Host I/F Data Register
The keyboard provides support for two power saving
modes: soft power down mode and hard power down
mode. In soft power down mode, the clock to the ALU is
stopped but the timer/counter and interrupts are still
active. In hard power down mode, the clock to the M8042
is stopped. Efforts are made to reduce power wherever
possible.
The Input Data register and, Output Data register, are
each 8 bits wide. A write to this 8 bit register will load the
Keyboard Data Read Buffer, set the OBF flag and set the
KIRQ output if enabled. A read of this register will read the
data from the Keyboard Data or Command Write Buffer
and clear the IBF flag. Refer to the KIRQ and Status
register descriptions for more information.
Soft Power Down Mode
Host I/F Status Register
This mode is entered by executing a HALT instruction.
The execution of program code is halted until either
RESET is driven active or a data byte is written to the
DBBIN register by a master CPU. If this mode is exited
using the interrupt, and the IBF interrupt is enabled, then
program execution resumes with a CALL to the interrupt
routine, otherwise the next instruction is executed. If it is
exited using RESET, then a normal reset sequence is
initiated and program execution starts from program
memory location 0.
The Status register is 8 bits wide. Table below shows the
contents of the Status register.
Status Register
D7
UD
D6
UD
D5
UD
D4
UD
D3
C/D
D2
UD
D1
IBF
D0
OBF
This register is cleared on a reset. This register is readonly for the Host and read/write by the M512x.
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UD
Writable by M512x. These bits are userdefinable.
C/D
(Command Data) This bit specifies whether the
input data register contains data or a command
(0 = data, 1 = command).
During a host
data/command write operation, this bit is set to
“ 1” if SA2 = 1 or reset to “ 0” if SA2 = 0.
Default Reset Conditions
The M512x has one source of reset: an external reset via
the RESET pin. Refer to table of Resets below for the
effect of each type of reset on the internal registers.
Resets
IBF
OBF
Page 66
(Input Buffer Full) This flag is set to 1 whenever
the host system writes data into the input data
register. Setting this flag activates the M512x’ s
nIBF (MIRQ) interrupt if enabled. When the
M512x reads the input data register (DBB), this
bit is automatically reset and the interrupt is
cleared. There is no output pin associated with
this internal signal.
(Output Buffer Full) This flag is set to 1 whenever
the M512x writes to the output data register
(DBB). When the host system reads the output
data register, this bit is automatically reset.
DESCRIPTION
KCLK
KDAT
MCLK
MDAT
Host I/F Data Reg
Host I/F Status Reg
HARDWARE RESET
(RESET)
Weak High
Weak High
Weak High
Weak High
N/A
OOH
NC : No Change
N/A : Not Applicable
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Command Byte Bit Definition
Bit
7
RSV
MSB
6
5
IBMPCC
IBMPC
4
DISKBC
3
INHOVR
2
1
FLAG
RSV
0
ENOBFI
LSB
Command Byte Bit Definition
Bit Number
7
6
5
4
3
2
1
0
Bit Definition
Reserved. This bit should be 0.
IBM Personal Computer Compatibility Mode. Writing a 1 to this
bit tells the keyboard controller that it needs to convert the scan
codes received from the keyboard to those used by the IBM PC.
IBM Personal Computer Mode. Writing a 1 to this bit signals
the keyboard controller not to check parity, or convert scan
codes.
Disable Keyboard. Writing a 1 to this bit disables Keyboard I/F
by driving the clock-line low.
Inhibit Override. Writing a 1 to this bit disables the KeyboardInhibit function.
System Flag. The M8042 places the value written to this bit in
the system flag bit of its status register.
Reserved. This bit should be 0.
Enable Output-Buffer-Full interrupt. Writing a 1 to this bit
causes the controller to generate an interrupt when it places
data into its output buffer.
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Status Register Bit Definition
Bit
7
PE
6
RTO
5
XTO
4
INH SW
3
2
COMMAND FLAG
DATA
1
0
IBF
OBF
MSB
LSB
Status Register Bit Definition
Bit Number
7
6
5
4
3
2
1
0
Page 68
Bit Definition
Parity Error.
0 : The last byte of received data had odd parity.
1 : The last byte of received data had even parity.
Receive Time-Out.
0 : No error
1 : The keyboard started a transmission but did not finish within a
specific receive time-out-delay.
Transmit Time-Out
0 : No error
1 : The keyboard started a transmission but was not properly
completed.
Inhibit Switch
0 : Keyboard is inhibited
1 : Keyboard is not inhibited
Command/Data Byte Select
0 : Data byte
1 : Command byte
System Flag. This bit is set to 0 during power-on
Input Buffer Full
0 : Keyboard controller input buffer is empty
1 : Data has been written into the buffer
Output Buffer Full
0 : Keyboard controller output buffer is empty
1 : Keyboard controller output buffer has placed data into
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M512x : Mega I/O Controller with PnP
Commands’ Description
Command
20H
60H
A1H
AAH
ABH
ADH
AEH
D0H
D1H
E0H
F0H ~ FFH
Description
Read keyboard controller's command byte. The keyboard controller puts the
command byte in its output buffer, available at I/O port 60H.
Write keyboard controller's command byte. The next byte from the system at
I/O port 60H is placed as the controller command.
Output controller version number. A single byte of the controller's version
comes at I/O port 60H.
Self test. This commands the controller to do internal diagnostics tests. A Hex 55
is placed in the output buffer if no errors are detected.
Interface test. This command checks the clocks and data lines of the keyboard.
00: no errors detected
01: clock is stuck low
02: clock is stuck high
03: data is stuck low
04: data is stuck high
Disable keyboard. It disables the keyboard clock line, and also sets the
corresponding bit in the command byte. It resumes after giving any keyboard
command.
Enables keyboard. It enables the keyboard clock line, and also resets the
corresponding bit in the command byte.
Read output port. This command places the output port (P2) status of the
controller at I/O port 60H.
Write output port. Data following this command is loaded onto the controller's
output port.
Read test inputs. This makes the current status of the test inputs of the
controller's KBC and KBD available to the system at I/O port 60H as bit 0 and bit
1, respectively.
Pulse output port. Bits 0 ~ 3 of the controller's output port may be pulsed low for
a period of approximately 6 seconds. The same bits of the command itself
indicate the bits to be pulsed. A 0 indicates that the bits should be pulsed, a 1
indicates that the bits should not be modified.
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M512x : Mega I/O Controller with PnP
6.3 Real Time Clock
This RTC Super Cell is a complete time of day clock with alarm and one hundred year calendar, a programmable periodic
interrupt and a programmable square wave generator.
n
Time of day Register Descriptions
The processor program obtains time and calendar information by reading the appropriate locations. The program may
initialize the time, calendar, and alarm by writing to these RAM locations. The contents of the 10 time, calendar and alarm
bytes may either be binary or binary-coded decimal. Table below shows the binary and BCD formats of the 10 time, calendar
and alarm locations.
Time, Calendar and Alarm Data Modes
Address
Function
Decimal Range
Binary Mode
BCD Mode
00
01
0-59
0-59
$0-$3B
$0-$3B
$0-$59
$0-$59
02
03
04
Seconds
Seconds
Alarm
Minutes
Minutes Alarm
Hours
0-59
0-59
1-12
0-23
05
Hours Alarm
1-12
06
07
08
09
Day of Week
Date
Month
Year
0-23
1-7
1-31
1-12
0-99
$0-$3B
$0-$3B
$1-$C(AM)
$81-$8C(PM)
$0-$17
$1-$C(AM)
$81-$8C(PM)
$0-$17
$1-$7
$1-$1F
$1-$C
$0-$63
$0-$59
$0-$59
$1-$12(AM)
$81-$92(PM)
$0-$23
$1-$12(AM)
$81-$92(PM)
$0-$23
$1-$7
$1-$31
$1-$12
$0-$99
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M512x : Mega I/O Controller with PnP
n
Address Map
The memory consists of 242 general purpose RAM bytes,
10 RAM bytes which normally contain the time, calendar,
alarm data, and four control and status bytes. All 256
bytes are directly readable and writable by the processor
program except for the following: 1) Registers C and D are
read only. 2) bit 7 of Register A is read only and 3) the
high order bit of the seconds byte is read only. The
contents of four control and status registers (A, B, C, and
D) are described in Registers.
n
Set Operation
Before initialization of the internal registers of the M512x,
the SET bit in register B should be set to a 1 to prevent
RTC from updating. The CPU then initializes the first ten
locations in the selected format (binary or BCD). The SET
bit should then be cleared to allow updating. After
initialization and enabling, the M512x will perform clock
calendar updates in the selected data mode.
n
BCD and Binary Format
The 24/12 bit in register B determines whether the hour
locations will be updated using a 1-12 or 0-23 format.
After initialization, the 24/12 bit cannot be changed without
reinitializing the hour locations. In 12 hour format, the
high order bit of the hours byte indicates PM when it is a 1.
n
Alarm Operation
The three alarm bytes may be used in two ways. First,
when the program inserts an alarm time in the appropriate
hours, minutes, and seconds alarm locations, the alarm
interrupt is initiated at the specified time each day if the
alarm enable bit is high. The second usage is to insert a
"don't care" state in one or more of three alarm bytes. The
"don't care" code is in any byte from C0h to FFh. An
alarm interrupt each hour is created with "don't care" code
in the hours alarm location. Similarly, an alarm is
generated every minute with "don't care" codes in the
hours and minutes alarm bytes. The "don't care" codes in
all three alarm bytes create an interrupt every second.
n
Interrupts
The RTC plus RAM includes three separate fully automatic
sources of interrupts to the processor. The alarm interrupt
maybe programmed to occur at rates from one-per-second
to one-a-day. The periodic interrupt maybe selected for
rates from half-a-second to 30.517µs. The update ended
interrupt maybe used to indicate to the program that an
update cycle is completed.
The processor program selects which interrupts, if any, it
wishes to receive. Three bits in register B enable the three
interrupts. Writing a 1 to an interrupt enable bit permits
that interrupt to be initiated when the event occurs. A 0 in
the interrupt enable bit prohibits the IRQ pin from being
asserted due to the interrupt cause.
If an interrupt flag is already set when the interrupt
becomes enable, the IRQ pin is immediately activated,
though the interrupt initiating the event may have occurred
much earlier. Thus, there are cases where the program
should clear such earlier initiated interrupts before first
enabling new interrupts.
n
Divider Control
The divider control bits have three uses, as shown in Table
below.
Three usable operating time bases may be
selected. The divider chain maybe held reset, which
allows precision setting of the time. When the divider is
changed from reset to an operating time base, the first
update cycle is one-half second later.
Divider Configurations
OSC1 Frequency
4.194304 MHz
1.048576 MHz
32.768 MHz
Any
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Divider
DV2
0
0
0
1
bits
DV1
0
0
1
1
DV0
0
1
0
*
Mode
Operate
Operate
Operate
Divider reset
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n
n
Periodic Interrupt Selection
The periodic interrupt allows the IRQJ pin to be triggered
from once every 30.517µs. The periodic interrupt is
separate from the alarm interrupt which maybe outputted
from once-per-second to once-per-day.
Table below shows that the periodic interrupt rate is
selected with the same register A bits which select the
square-wave frequency.
Periodic Interrupt Rate Table
RS value
0h
1h
2h
3h
4h
5h
6h
7h
8h
9h
Ah
Bh
Ch
Dh
Eh
Fh
4.194304 MHz
or 1.048576 MHz
Time Base
none
30.517 µs
61.035 µs
122.070 µs
244.141 µs
488.281 µs
976.562 µs
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
125 ms
250 ms
500 ms
32.768 KHz
Time Base
none
3.90625 ms
7.8125 ms
122.070 µs
244.141 µs
488.281 µs
976.562 µs
1.953125 ms
3.90625 ms
7.8125 ms
15.625 ms
31.25 ms
62.5 ms
125 ms
250 ms
500 ms
Update Cycle
The RTC executes an update cycle one-per-second,
assuming one of the proper time bases is in place, the
DV2-DV0 divider is not clear, and the SET bit in register B
is clear. The SET bit in the 1 state permits the program to
initialize the time and calendar bytes by stopping an
existing update and preventing a new one from occurring.
The primary function of the update cycle is to increment
the second byte, check for overflow, increment the minutes
byte when appropriate and so forth through to the year of
the century byte. The update cycle also compares each
alarm byte with the corresponding time byte and issues an
alarm if a match or if a "don't care" code (11xxxxxx) is
present in all three positions.
With a 4.194304 MHz or 1.048576 MHz time base, the
update cycle takes 248µs while a 32.768 KHz time base
update cycle takes 1984 µs. During the update cycle, the
time, calendar and alarm bytes are not accessible by the
processor program. The RTC protects the program from
reading transitional data. This protection is provided by
switching the time, calendar and alarm portion of the RAM
off the microprocessor bus during the entire update cycle.
If the processor reads these RAM locations before the
update is complete, the output will be undefined. The
update in progress (UIP) status bit is set during the
interval.
Three methods of accommodating non-availability during
update are usable by the program. In discussing the three
methods, it is assumed that at random points user
programs are able to call a subroutine to obtain the time of
day.
The first method of avoiding the update cycle uses the
update ended interrupt. If enabled, an interrupt occurs
after every update cycle which indicates that over 999 ms
are available to read valid time and date information.
Before leaving the interrupt service routine, the IRQF bit in
register C should be cleared.
The second method uses the update in progress bit (UIP)
in register A to determine if the update cycle is in progress
or not. The UIP bit will pulse once-per-second. After the
UIP bit goes high, the update cycle begins 244 µs later.
Therefore, if a low is a read in the UIP bit, the user has at
least 244µs before the time/calendar data will be changed.
If a 1 is read in the UIP bit, the time/calendar data may not
be valid. The user should avoid interrupt service routines
that would cause the time needed to read valid
time/calendar data to exceed 244µs.
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The third method uses a periodic interrupt to determine if
an update cycle is in progress. The UIP bit in register A is
set high between the setting of the PF bit in register C.
To properly setup the internal counters for daylight savings
time operation, the user must set the time at least two
seconds before the roll-over will occur. Likewise, the time
must be set at least two seconds before the end of the
29th or 30th day of the month.
n
Register Description
The RTC has four registers which are accessible to the
processor program. The four registers are also fully
accessible during the update cycle.
Register 0AH
Index register port : 70H
Data register port : 71H
Index : 0AH
(Read/Write except UIP)
7
UIP
6
DV
5
DV1
4
DV0
3
RS3
2
RS2
1
RS1
0
RS0
Bits 3-0. The four rate selection bits select one of 15 taps
on the 22-stage divider, or disable the divider output. The
tap selected may be used to generate an output square
wave (SQW pin) and/or a periodic interrupt. The program
may do one of the following 1) enable the interrupt with the
PIE bit, 2) enable the SQW output pin with the SQWE bit,
3) enable both at the same time at the same rate, or 4)
enable neither. Table 7 lists the periodic interrupt rates
and the square wave frequencies that may be chosen with
the RS bits. These four bits are read/write bits which are
not affected by RESETJ.
Bits 6-4. Three bits are used to permit the program to
select various conditions of the 22 stage divider chain.
The divider selection bits identify which of the three timebase frequencies is in use. Table 6 shows that time bases
of 4.194304 MHz, 1.048576 MHz, and 32.768 KHz may be
used. The divider selection bits are also used to reset the
divider chain. When the time/calendar is first initialized,
the program may start the divider at the precise time
stored in the RAM. When the divider reset is removed, the
first update cycle begins one-half second later. These
three read/write bits are not affected by RESET.
Bit 7. The update in progress (UIP) bit is a status flag that
maybe monitored by the program. When UIP is a "1", the
update cycle is in progress or will begin. When UIP is a
"0", the update cycle is not in progress and will not be for
at least 244µs (for all time bases). The time, calendar,
and alarm information in RAM is fully available to the
program when the UIP bit is zero - it is not in transition.
The UIP bit is a read-only bit, and is not affected by Reset.
Writing the SET bit in Register B to a "1" inhibits any
update cycle and then clears the UIP status bit.
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Register 0Bh
Bit 6. The periodic interrupt enable (PIE) bit is read/write
bit which allows the periodic-interrupt flag (PF) bit in
Register C to cause the IRQ pin to be driven low. A
program writes a "1" to the PIE bit in order to receive
periodic interrupts at the rate specified by the RS3, RS2,
RS1, and RS0 bits in Register A. A zero in PIE blocks
IRQ from being initiated by a periodic interrupt, but the
periodic flag (PF) bit is still set at the periodic rate. PIE is
not modified by any internal KS82C6818A functions, but is
cleared to "0" by a RESETJ.
Index register port : 70H
Data register port : 71H
Index : 0BH
(Read/Write)
7
SET
6
PIE
5
AIE
4
UIE
3
SQWE
2
DM
1
24/12
0
DSE
Bit 0. The daylight savings enable (DSE) bit is a
read/write bit which allows the program to enable two
special updates (when DSE is a "1"). On the last Sunday
of April, the time increments from 1:59:59 AM to 3:00:00
AM. On the last Sunday of October when the time first
reaches 1:59:59 AM, it changes to 1:00:00 AM. These
special updates do not occur when the DSE bit is a "0".
DSE is not changed by any internal operations or rest.
Bit 7. When the SET bit is a "0", the update cycle
functions normally by advancing the counts once-persecond. When the SET bit is written to a "1", any update
cycle in progress is aborted and the program may initialize
the time and calendar bytes without an update occurring in
the midst of initializing. SET is a read/write bit which is not
modified by RESET or internal functions of the M512x.
Bit 1. The 24/12 control bit establishes the format of the
hours bytes as either the 24-hour mode (a "1") or the 12hours mode (a "0"). This is a read/write bit, which is
affected only by software.
Bit 2. The data mode (DM) bit indicates whether time and
calendar updates are to use binary or BCD formats. The
DM bit is written by the processor program and may be
read by the program, but is not modified by any internal
functions or RESET. A "1" in DM signifies binary data,
while a "0" in DM specifies binary-coded decimal (BCD)
data.
Bit 3. When the square-wave enable (SQWE) bit is set to
a "1" by the program, a square-wave signal at the
frequency specified in the rate selection bits (RS3 to RS0)
appears on the SQW pin. When the SQWE bit is set to a
zero, the SQW pin is held low. The state of SQWE is
cleared by the RESETJ pin. SQWE is a read/write bit.
Bit 4. The UIE (update-ended interrupt enable) bit is a
read/write bit which enables the update-end flag (UF) bit in
Register C to assert IRQ. The RESETJ pin going low or
the SET bit going high clears the UIE bit.
Bit 5. The alarm interrupt enable (AIE) bit is a read/write
bit which when set to a "1" permits the alarm flag (AF) bit
in Register C to assert IRQ. An alarm interrupt occurs for
each second that the three time bytes and the three alarm
bytes (including a "don't care" alarm code of binary
11xxxxxx). When the AIE bit is a "0", the AF bit does not
initiate an IRQ signal. The RESETJ pin clears AIE to "0".
The internal functions do not affect the AIE bit.
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M512x : Mega I/O Controller with PnP
Register 0Ch
Register 0Dh
Index register port : 70H
Index register port : 70H
Data register port : 71H
Data register port : 71H
Index : 0CH
Index : 0DH
(Read only)
(Read only)
7
IRQF
6
PF
5
AF
4
UF
3
0
2
0
1
0
0
0
7
VRT
6
0
5
0
4
0
3
0
2
0
1
0
0
0
Bits 3-0. The unused bits of Status Register C are read
as 0's and cannot be written.
Bits 6-0. The remaining bits of Register D are unused.
They cannot be written, but are always read as 0's.
Bit 4. The update-ended interrupt flag (UF) bit is set after
each update cycle. When the UIE bit is a "1", the "1" in UF
causes the IRQF bit to be a "1", asserting IRQ, UF is
cleared by a Register C read or a RESETJ.
Bit 7. The valid RAM and time (VRT) bit indicates the
condition of the contents of the RAM, provided the VBAT is
satisfactorily connected. A "0" appears in the VRT bit
when the VBAT is low. The processor program can set
the VRT bit when the time and calendar are initialized to
indicate that the RAM and time are valid. The VRT is a
read only bit which is not modified by the RESETJ pin.
The VRT bit can only be set by reading Register D.
Bit 5. A "1" in the AF (alarm interrupt flag) bit indicates
that the current time has matched the alarm time. A "1" in
the AF causes the IRQ pin to go low, and a "1" to appear
in the IRQF bit, when the AIE bit also is a "1". A reset or a
read of Register C clears AF.
Bit 6. The periodic interrupt flag (PF) is a read-only bit
which is set to a "1" when a particular edge is detected on
the selected tap of the divider chain. The RS3 to RS0 bits
establish the periodic rate. PF is set to a "1" independent
of the state of the PIE bit. PF being a "1" initiates and IRQ
signal and sets the IRQF bit when PIE is also a "1". The
PF bit is cleared by a /RESET/ or a software read of
Register C.
Bit 7. The interrupt request flag (IRQF) is set to a "1"
when one or more of the following are true :
PF = PIE = "1"
AF = AID = "1"
UF = AIE = "1"
Any time the IRQF bit is a "1", the IRQ pin is driven low.
All flag bits are cleared after Register C is read by the
program when the RESET pin is low.
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M512x : Mega I/O Controller with PnP
Section 7 : BIOS
7.1 BIOS BUFFER
The M512x contains one 245 type buffer that can be used for a BIOS Buffer. If the BIOS buffer is not used,
then ROMCSJ and ROMOEJ must be tied high so as not to interfere with the boot ROM.
This function allows data transmission from the RD bus to the SD bus or from the SD bus to the RD bus. The
direction of the transfer is controlled by ROMOEJ. The enable input, ROMCSJ, can be used to disable the
transfer and isolate the buses.
ROMCSJ
L
L
H
ROMOEJ
L
H
X
RD [0:7] data to SD [0:7] bus
SD [0:7] data to RD [0:7]
Isolation
SD[7:0]
ROMCSJ
M5123
BIOS
ROMOEJ
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--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Section 8 : Parallel Port
8.1 Parallel Port Interface
The M512x incorporates one IBM XT/AT compatible parallel
port. The M512x supports the optional PS/2 type bidirectional parallel port (SPP), the Enhanced Parallel Port
(EPP) and the Extended Capabilities Port (ECP) parallel port
modes.
Please refer to the Configuration Description
(Section 3) for information on disabling, power down,
changing the base address of the parallel port, and selecting
the mode of operation.
The M512x also incorporates a protective circuitry, which
prevents possible damage to the parallel port due to printer
power-up.
The functionality of the Parallel Port is achieved through the
use of eight addressable ports with their associated registers
Table 8-1 Bit Mapped Registers
Data Port
D0
D1
PD0
PD1
Status
TMOUT
0
Port
Control
STROBE AUTOFD
Port
EPP ADDR
PD0
PD1
Port
EPP DATA
PD0
PD1
Port 0
EPP DATA
PD0
PD1
Port 1
EPP DATA
PD0
PD1
Port 2
EPP DATA
PD0
PD1
Port 3
and control gating. The control and data port are read/write
by the CPU, the status port is read/write in the EPP mode.
The address map of the Parallel Port is shown below:
DATA PORT
STATUS PORT
CONTROL PORT
EPP ADDR PORT
EPP DATA PORT 0
EPP DATA PORT 1
EPP DATA PORT 2
EPP DATA PORT 3
BASE ADDRESS
BASE ADDRESS
BASE ADDRESS
BASE ADDRESS
BASE ADDRESS
BASE ADDRESS
BASE ADDRESS
BASE ADDRESS
+
+
+
+
+
+
+
+
00H
01H
02H
03H
04H
05H
06H
07H
The bit map of these registers :
D2
PD2
OSLC
D3
PD3
ERRJ
D4
PD4
SLCT
D5
PD5
PE
D6
PD6
ACKJ
D7
PD7
BUSYJ
Note
1
1
INITJ
SLC
IRQE
PCD
0
0
1
PD2
PD3
PD4
PD5
PD6
PD7
2, 3
PD2
DP3
PD4
PD5
PD6
PD7
2, 3
PD2
PD3
PD4
PD5
PD6
PD7
2, 3
PD2
PD3
PD4
PD5
PD6
PD7
2, 3
PD2
PD3
PD4
PD5
PD6
PD7
2, 3
Note 1: These registers are available in all modes.
2: These registers are only available in EPP mode.
3: For EPP mode, IOCHRDY must be connected to the ISA bus.
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Table 8-2
Parallel Port Connector
HOST
Connector
1
2-9
10
11
12
Pin No.
STANDARD
EPP
ECP
77
71-68, 66-63
62
61
60
StrobeJ
PData <0:7>
AckJ
Busy
PE
WriteJ
PData<0:7>
Intr
WaitJ
(NU)
13
14
59
76
Select
AutofdJ
(NU)
DSTRBJ
15
75
ErrorJ
(NU)
16
74
InitJ
(NU)
17
73
SelectinJ
AstrbJ
StrobeJ
PData<0:7>
Ack
Busy,PeriphAck(3)
PError,
nAckReverse(3)
Select
AutoFd,
HostAck(3)
Fault(1)
PeriphRequest(3)
Init(1)
ReverseRqst(3)
Selectin(1,3)
(1) = compatible Mode
(3) = High Speed Mode
Note : For the cable interconnection required for ECP support and the Slave Connector pin numbers, please refer to the IEEE
1284 Extended Capabilities Port Protocol and ISA Standard, Rev. 1.09, Jan. 7, 1993. This document is available from
Microsoft.
8.2 IBM XT/AT Compatible, Bi-Directional and EPP
Modes
DATA PORT
Address Offset = 00H
The Data Port is located at an offset of '00H' from the base
address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register
latches the contents of the data bus with the rising edge of
the IOWJ input. The contents of this register are buffered
(non inverting) and output onto the PD0 -PD7 ports. During
a READ operation in SPP mode, PD0 - PD7 ports are
buffered (not latched) and output to the host CPU.
STATUS PORT
Address Offset = 01H
The Status Port is located at an offset of '01H' from the base
address. The contents of this register are latched for the
duration of an IORJ read cycle. The bits of the Status Port
are defined as follows:
BIT 0 TMOUT - TIME OUT
This bit is valid in EPP mode only and indicates that a 10
µsec time out has occurred on the EPP bus. A logic 0
means that no time out error has occured; a logic 1 means
that a time out error has been detected. This bit is cleared
by a RESET. Writing a one to this bit clears the time out
status bit. On a write, this bit is self clearing and does not
require a write of a zero. Writing a zero to this bit has no
effect.
Page 78
BITS 1, 2 - are not implemented as register bits. During a
read of the Printer Status Register, these bits are at low level.
BIT 3 ERRJ - ERRORJ
The level on the ERRORJ input is read by the CPU as bit 3
of the Printer Status Register. A logic 0 means an error has
been detected; a logic 1 means no error has been detected.
BIT 4 SLCT - PRINTER SELECTED STATUS
The level on the SLCT input is read by the CPU as bit 4 of
the Printer Status Register. A logic 1 means the printer is on
line; a logic 0 means it is not selected.
BIT 5 PE - PAPER END
The level on the PE input is read by the CPU as bit 5 of the
Printer Status Register. A logic 1 indicates a paper end; a
logic 0 indicates the presence of paper.
BIT 6 ACKJ - ACKNOWLEDGEJ
The level on the ACKJ input is read by the CPU as bit 6 of
the Printer Status Register. A logic 0 means that the Printer
has received a character and can now accept another. A
logic 1 means that it is still processing the last character or
has not received the data.
BIT 7 BUSYJ - BUSYJ
The complement of the level on the BUSY input is read by
the CPU as bit 7 of the Printer Status Register. A logic 0 in
this bit means that the printer is busy and cannot accept a
new character. A logic 1 means that it is ready to accept
the next character.
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CONTROL PORT
Address Offset = 02H
The Control Port is located at an offset of ‘ 02H’ from the
base address. The Control Register is initialized by the
RESET input, bits 0 to 5 only being affected; bits 6 and 7 are
hard wired low.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the STROBEJ output.
BIT 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the AUTOFDJ output. A
logic 1 causes the printer to generate a line feed after each
line is printed. A logic 0 means no autofeed.
BIT 2 INITJ - INITIATE OUTPUTJ
This bit is output onto the INITJ output without inversion.
BIT 3 SLCTIN - PRINTER SELECT INPUT
This bit is inverted and output onto the SLCTINJ output. A
logic 1 on this bit selects the printer; a logic 0 means the
printer is not selected.
BIT 4 IRQE - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may
be used to enalbe interrupt requests from the Parallel Port to
the CPU. An interrupt request is generated on the IRQ port
by a positive going ACKJ input. When the IRQE bit is
programmed low the IRQ is disabled.
BIT 5 PCD - PARALLEL CONTROL DIRECTION
Parallel Control Direction is valid in extended mode only
(CRC<7> = 0). In printer mode, the direction is always out
regardless of the state of this bit. In bi-directional mode, a
logic 0 means that the printer port is in output mode (write);
a logic 1 means that the printer port is in input mode (read).
EPP DATA PORT 0
Address Offset = 04H
The EPP Data Port 0 is located at an offset of ‘ 04H’ from
the base address.
The data register is cleared at
initialization by RESET. During a WRITE operation, the
contents of DB0-DB7 are buffered (non-inverting) and
output onto the PD0 - PD7 ports, the leading edge of IOWJ
causes an EPP DATA WRITE cycle to be performed, the
trailing edge of IOW latches the data for the duration of the
EPP write cycle. During a READ operation, PD0- PD7 ports
are read, the leading edge of IOR causes an EPP READ
cycle to be performed and the data output to the host CPU,
the deassertion of DATASTB latches the Pdata for the
duration of the IOR cycle. This register is only available in
EPP mode. To maintain compatibility with Intel’ s 82360SL
device that has 32-bit Host bus interface, four consecutive
byte address locations (data port 0~4) are provided for
transferring data.
EPP DATA PORT 1
Address Offset = 05H
The EPP Data Port 1 is located at an offset of ‘ 05H’ from
the base address. Please refer to EPP DATA PORT 0 for a
description of operation. This register is only available in
EPP mode.
EPP DATA PORT 2
Address Offset = 06H
The EPP Data Port 2 is located at an offset of ‘ 06H’ from
the base address. Please refer to EPP DATA PORT 0 for a
description of operation. This register is only available in
EPP mode.
EPP DATA PORT 3
Address Offset = 07H
Bits 6 and 7 during a read are a low level, and cannot be
written.
The EPP Data Port 3 is located at an offset of ‘ 07H’ from
the base address. Please refer to EPP DATA PORT 0 for a
description of operation. This register is only available in
EPP mode.
EPP ADDRESS PORT
EPP Operation
Address Offset = 03H
The EPP Address Port is located at an offset of ‘ 03H’ from
the base address. The address register is cleared at
initialization by RESET. During a WRITE operation, the
contents of DB0-DB7 are buffered (non inverting) and output
onto the PDO - PD7 ports, the leading edge of IOWJ causes
an EPP Address WRITE cycle to be performed, the trailing
edge of IOW latches the data for the duration of the EPP
Write cycle. During a READ operation, PDO -PD7 ports are
read, the leading edge of IOR causes an EPP ADDRESS
READ cycle to be performed and the data output to the host
CPU, the deassertion of ADDRSTB latches the Pdata for the
duration of the IOR cycle. This register is only available in
EPP mode.
When the EPP mode is selected in the configuration register,
the standard and bi-directional modes are also available. If
no EPP Read, Write or Address cycle is currently executing,
then the PDx bus is in the standard or bi-directional mode,
and all output signals (STROBE, AUTOFD, INIT) are as set
by the SPP Control Port and direction is controlled by PCD of
the Control port.
In EPP mode, the system timing is closely coupled to the
EPP timing. For this reason, a watchdog timer is required to
prevent system lockup. The timer indicates if more than 10
usec have elapsed from the start of the EPP cycle (IORJ or
IOWJ asserted) WAITJ will be deasserted. If a time-out
occurs, the current EPP cycle is aborted and the time-out
condition is indicated in Status bit 0.
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M512x : Mega I/O Controller with PnP
EPP mode version 1.7 Timing
SD7-0
IOWJ
IORJ
WRITEJ
(STROBJ)
DSTRBJ(AUTO
FDJ/SLCTINJ)/
ASTRBJ
PD7-0
WAITJ(BUSY)
IOCHRDY
The timing for a Write/Read EPP 1.7 operation is shown in timing diagram above
The sequence of operation is :
EPP 1.7 Data/Address Write
1. The host writes a byte to Data (Address) port.
IOWJ goes low to drive data to PD7-0.
2. The EPP pulls WRITEJ low to indicate it’ s a
write cycle.
3. The EPP pulls DSTRBJ (ASTRBJ) low to
signal that data is valid.
4. If WAITJ goes low during the cycle,
IOCHRDY is pulled low.
5. When WAITJ goes high, the EPP pulls
IOCHRDY high and then IOWJ will go high
6. When IOWJ goes high, it pulls WRITEJ &
DSTRBJ(ASTRBJ) high, and then the EPP
can change PD7-0
Page 80
EPP 1.7 Data/Address Read
1. The host reads a byte from Data (Address) port.
IORJ goes low to input data from PD7-0.
2. The EPP keeps WRITEJ high to indicate it’ s a read cycle.
3. The EPP pulls DSTRBJ (ASTRBJ) low to indicate that
peripheral have to start sending data.
4. If WAITJ is low during the cycle, IOCHRDY is pulled low.
5. When WAITJ goes high, the EPP pulls IOCHRDY high and
then IORJ will go high
6. When IORJ goes high, it pulls WRITEJ &
DSTRBJ(ASTRBJ) high, and then the peripheral can tristate PD7-0
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M512x : Mega I/O Controller with PnP
EPP mode version 1.9 Timing
SD7-0
IOWJ
IORJ
WRITEJ
(STROBJ)
DSTRBJ(AUTO
FDJ/SLCTINJ)/
ASTRBJ
PD7-0
WAITJ(BUSY)
IOCHRDY
EPP WRITE CYCLE
EPP READ CYCLE
The timing for a Write/Read EPP 1.9 operation is shown in timing diagram above
The sequence of Write/Read operation is :
EPP 1.9 Data/Address Write
1. The host writes a byte to Data (Address) port.
IOWJ goes low to drive data to PD7-0.
2. IOCHRDY goes low and waits for WAITJ to
go low.
3. If WAITJ goes low or already low, the EPP
pulls or keeps WRITEJ low to show being a
write cycle.
4. The EPP pulls DSTRBJ (ASTRBJ) low to
indicate that data is ready and waits for
WAITJ to go high.
5. When WAITJ goes high, it pulls IOCHRDY
and DSTRBJ (ASTRBJ) high, and then
IOWJ will go high to turn off this cycle.
EPP 1.9 Data/Address Read
1. The host reads a byte from Data (Address) port.
IORJ goes low to input data from PD7-0.
2. IOCHRDY goes low and waits for WAITJ to go low.
3. If WAITJ goes low or was already low, the EPP pulls or
keeps WRITEJ high to indicate being a read cycle.
4. The EPP pulls DSTRBJ (ASTRBJ) low to signal the
peripheral to start sending data and waits for WAITJ to go
high.
5. When WAITJ goes high, it pulls IOCHRDY and DSTRBJ
(ASTRBJ) high, and then IORJ will go high to turn off this
cycle.
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Table 8-3 - EPP Pin Descriptions
EPP
SIGNAL
WRITEJ
PD<0:7>
INTR
EPP
NAME
WriteJ
Address/
Data
Interrupt
WAIT
WaitJ
I
DATASTB
DATA
StrobeJ
ResetJ
O
Address
StrobeJ
Paper
End
Printer
Select
Status
Error
Parallel
Port
Direction
O
RESET
ADDRSTB
PE
SLCT
ERRJ
PDIR
EPP DESCRIPTION
TYPE
O
I/O
I
This signal is active low. It denotes a write operation.
Bi-directional EPP byte wide address and data bus.
I
This signal is active high and positive edge triggered.
(Pass through with no inversion, Same as SPP.)
This signal is active low. It is driven inactive as a
positive acknowledgement from the device that the
transfer of data is completed. It is driven active as an
indication that the device is ready for the next transfer.
This signal is active low. It is used to denote data read
or write operation.
This signal is active low. When driven active, the EPP
device is reset to its initial operational mode.
This signal is active low. It is used to denote address
read or write operation.
Same as SPP mode.
I
Same as SPP mode.
I
O
Same as SPP mode.
This output shows the direction of the data transfer on
the parallel port bus. A low means an output /write
condition and a high means an input/read condition.
This signal is normally a low (output/write) uniess PCD
of the control register is set or if an EPP read cycle is
in progress.
O
Note 1: SPP and EPP can use 1 common register.
Note 2: WriteJ is the only EPP output that can be over-ridden by SPP control port during an EPP cycle.
For correct EPP read cycles, PCD is required to be a low.
Extended Capabilities Parallel Port
These terms may be considered synonymous:
ECP provides a number of advantages, some of which are
listed below.
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
High performance half-duplex forward and reverse
channel
Interlocked handshake, for fast reliable transfer
Optional single byte RLE compression for improved
throughput (64:1)
Channel addressing for low-cost peripherals
Maintains link and data layer separation
Permits the use of active output drivers
Permits the use of adaptive signal timing
Peer-to-peer capability
PWord A port word; equal in size to the width of the ISA
interface. For this implementation, PWord is always 8 bits.
1
A high level.
0
A low level.
Page 82
PeriphClk, AckJ
HostAck, AutoFdJ
PeriphAck, Busy
PeriphRequestJ, FaultJ
ReverseRequestJ, InitJ
AckReverseJ, PError
Xflag, Select
ECPMode, SelectinJ
HostClk, StrobeJ
Vocabulary
The following terms are used in this document:
assert When a signal asserts it transitions to
a "true" state, when a signal deasserts
it transitions to a "false" state.
forward Host to Peripheral communication.
reverse Peripheral to Hose communication.
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Reference Document
IEEE 1284 Extended Capabilities Port Protocol
and ISA Interface Standard, Rev 1.09, Jan 7, 1993. This document is available from Microsoft.
The bit map of the Extended Parallel Port registers is :
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
D7
PD7
Addr/ RLE
BusyJ
0
D6
PD6
D5
PD5
AckJ
0
PError
Direction
0
compress
MODE
0
intrValue
0
0
D4
PD4
D3
D2
PD3
PD2
Address or RLE field
Select
FaultJ
0
acklntEn Selectin InitJ
Parallel Port Data FIFO
ECP Data FIFO
Test FIFO
1
0
0
0
0
0
ErrintrEn DmaEn
Service
J
Intr
D1
PD1
D0
PD0
0
autofd
0
strobe
0
0
full
0
0
empty
Note
2
1
1
2
2
2
Note 1: These registers are available in all modes.
Note 2: All FIFOs use one common 16 byte FIFO.
ISA IMPLEMENTATION STANDARD
This specification describes the standard ISA interface to the Extended Capabilities Port (ECP). All ISA devices supporting ECP
must meet the requirements contained in this section or the port will not be supported by Microsoft. For a description of the ECP
Protocol, please refer to the IEEE 1284 Extended Capabilities Port Protocol and ISA Interface Standard, Rev. 1.09, Jan. 7, 1993.
This document is available from Microsoft.
Description
The port is software and hardware compatible with existing parallel ports so that it may be used as a standard LPT port if ECP is
not required. The port is designed to be simple and requires a small number of gates to implement. It does not do any "protocol"
negotiation, rather it provides an automatic high burst-bandwidth channel that supports DMA for ECP in both the forward and
reverse directions.
Small FIFOs are employed in both forward and reverse directions to smooth data flow and improve the maximum bandwidth
requirement. The size of the FIFO is 16 bytes deep. The port supports an automatic handshake for the standard parallel port to
improve compatibility mode transfer speed.
The port also supports run length encoded (RLE) decompression (required) in hardware. Decompression is accomplished by
counting identical bytes and transmitting an RLE byte that indicates how many times the next byte is to be repeated.
Decompression simply intercepts the RLE byte and repeats the following byte the specified number of times. Hardware support
for compression is optional.
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Table 8-4
ECP Pin Descriptions
Name
StrobeJ
Type
O
PData 7:0
AckJ
I/O
I
PeriphAck
(Busy)
I
PError
(Ack
ReverseJ)
I
Select
AutoFdJ
(HostAck)
I
O
FaultJ
(Periph
RequestJ)
I
InitJ
O
SelectlnJ
O
Description
During write operations StrobeJ registers data or address into the
slave on the asserting edge (handshakes with Busy).
Contains address or data or RLE data.
Indicates valid data driven by the peripheral when asserted. This signal handshakes with
AutoFdJ in reverse.
This signal deasserts to indicate that the peripheral can accept data. This signal handshakes
with StrobeJ in the forward direction. In the reverse direction this signal indicates whether the
data lines contain ECP command information or data. The peripheral uses this signal to flow
control in the forward direction. It is an "interlocked" handshake with StrobeJ. PeriphAck also
provides command information in the reverse direction.
Used to acknowledge a change in the direction of the transfer (asserted= forward). The peripheral
drives this signal low to acknowledge ReverseRequestJ. It is an "interlocked" handshake with
ReverseRequestJ. The host relies upon AckReverseJ to determine when it is permitted to drive
the data bus.
Indicates printer on line.
Requests a byte of data from the peripheral when asserted, handshaking with AckJ in the reverse
direction. This signal indicates whether the data lines contain ECP address or data, the host
drives this signal to flow control in the reverse direction. It is an "interlocked" handshake with
AckJ. HostAck also provides command information in the forward phase.
Generates an error interrupt when asserted. This signal provides a mechanism or peer-to-peer
communication. This signal is valid only in the forward direction. During ECP mode, the
peripheral is permitted (but not required) to level this pin to request a reverse transfer. The
request is merely a "hint" to the host; the host has ultimate control over the transfer direction.
This signal would be typically used to generate an interrupt to the host CPU.
Sets the transfer direction (asserted = reverse, deasserted = forward). This pin is driven low to
place the channel in the reverse direction. The peripheral is only allowed to drive the bidirectional data bus while in ECP Mode and HostAck is low and SelectlnJ is high.
Always deasserted in ECP mode.
Register Definitions
The register definitions are based on the standard IBM addresses for LPT. All of the standard printer ports are supported. The
additional registers attach to an upper bit decode of the standard LPT port definition to avoid conflict with standard ISA devices.
The port is equivalent to a generic parallel port interface and may be operated in that mode. The port registers vary depending on
the mode field in the ECR. The table below lists these dependencies. Operation of the devices in modes other than those specified
is undefined.
Table 8-5
NAME
data
ecpAFifo
dsr
dcr
cFifo
ecpDFifo
tFifo
cnfgA
cnfgB
ecr
ECP Register Definitions
ADDRESS (Note 1)
+000h R/W
+000h R/W
+001h R/W
+002h R/W
+400h R/W
+400h R/W
+400h R/W
+400h R
+401h R/W
+402h R/W
ECP MODES
000-001
011
All
All
010
011
110
111
111
All
FUNCTION
Data Register
ECP FIFO (Address)
Status Register
Control Register
Parallel Port Data FIFO
ECP FIFO (DATA)
Test FIFO
Configuration Register A
Configuration Register B
Extended Control Register
Note 1: These addresses are added to the parallel port base address as selected by configuration register or jumpers.
Note 2: All addresses are qualified with AEN. Refer to the AEN pin definition.
Page 84
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Table 8-6
Mode
000
001
010
011
100
Mode Descriptions
Description*
SPP mode
PS/2 Parallel Port mode
Parallel Port Data FIFO mode
ECP Parallel Port mode
EPP mode (If this option is enabled
in the configuration registers)
101
(Reserved)
110
Test mode
111
Configuration mode
* Refer to ECR Register Description
DATA and ECPAFIFO PORT
Address Offset = 00H
Modes 000 and 001 (Data Port)
The Data Port is located at an offset of '00H' from the base
address. The data register is cleared at initialization by
RESET. During a WRITE operation, the Data Register
latches the contents of the data bus on the rising edge of the
IOWJ input. The contents of this register are buffered (non
inverting) and output onto the PD0 - PD7 ports. During a
READ operation, PD0 - PD7 ports are read and output to the
host CPU.
Mode 011 (ECP FIFO- Address/RLE)
A data byte written to this address is placed in the FIFO and
tagged as an ECP Address/RLE. The hardware at the ECP
port transmits this byte to the peripheral automatically. The
operation of this register is only defined for the forward
direction (direction is 0). Refer to the ECP Parallel Port
Forward Timing Diagram, located in the Timing Diagrams
section of this data sheet.
Device Status Register (DSR)
Address Offset = 01H
The Status Port is located at an offset of '01H' from the base
address. Bits 0 - 2 are not implemented as register bits,
during a read of the Printer Status Register these bits are a
low level. The bits of the Status port are defined as follows:
BIT 3 FaultJ
The level on the Fault input is read by the CPU as bit 3 of
the Device Status Register.
BIT 4 Select
The level on the Select input is read by the CPU as bit 4 of
the Device Status Register.
BIT 5 PError
The level on the PError input is read by the CPU as bit 5 of
the Device Status Register. Printer Status Register.
BIT 6 AckJ
The level on the AckJ input is read by the CPU as bit 6 of
the Device Status Register.
BIT 7 BusyJ
The complement of the level on the BUSY input is read by
the CPU as bit 7 of the Device Status Register.
Device Control Register (DCR)
Address Offset = 02H
The Control Register is located at an offset of '02H' from the
base address. The Control Register is initialized to zero by
the RESET input, bits 0 to 5 being affected; bits 6-7 are read
as 0.
BIT 0 STROBE - STROBE
This bit is inverted and output onto the STROBEJ output.
BIT 1 AUTOFD - AUTOFEED
This bit is inverted and output onto the AUTOFDJ output. A
logic 1 causes the printer to generate a line feed after each
line is printed. A logic 0 means no autofeed.
BIT 2 INITJ - INITIATE OUTPUT
This bit is output onto the INITJ output without inversion.
BIT 3 SELECTIN
This bit is inverted and output onto the SLCTINJ output. A
logic 1 on this bit selects the printer; a logic 0 means the
printer is not selected.
BIT 4 acklntEn - INTERRUPT REQUEST ENABLE
The interrupt request enable bit when set to a high level may
be used to enable interrupt requests from the Parallel Port to
the CPU due to a low to high transition on the ACKJ input.
Refer to the description of the interrupt under Operation,
Interrupts.
BIT 5 DIRECTION
If mode = 000 or mode = 010, this bit has no effect and the
direction is always out regardless of the state of this bit. In
all other modes, direction is valid and a logic 0 means that
the printer port is in output mode (write); a logic 1 means
that the printer port is in input mode (read).
Bits 6 and 7 during a read are a low level, and cannot be
written.
CFIFO (Parallel Port Data FIFO) Address Offset = 400h
Mode = 010
Bytes written or DMAed from the system to this FIFO are
transmitted by a hardware handshake to the peripheral
using the standard parallel port protocol. Transfers to the
FIFO are byte aligned. This mode is only defined for the
forward direction.
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ECPDFIFO (ECP Data FIFO)
Address Offset = 400h
CNFGA (Configuration Register A) Address Offset = 400H
Mode = 011
Bytes written or DMAed from the system to this FIFO, when
the direction bit is 0, are transmitted by a hardware
handshake to the peripheral using the ECP parallel port
protocol. Transfers to the FIFO are byte aligned.
Mode = 111
This register is a read only register. When read, 10H is
returned. This indicates to the system that this is an 8-bit
implementation. (Pword = 1 byte)
Data bytes from the peripheral are read under automatic
hardware handshake from ECP into this FIFO when the
direction bit is 1. Reads or DMAs from the FIFO will return
bytes of ECP data to the system.
CNFGB (Configuration Register B) Address Offset = 401H
TFIFO (Test FIFO Mode) Address Offset =400H
Mode = 110
Data bytes may be read, written or DMAed to or from the
system to this FIFO in any direction.
Data in the tFIFO will not be transmitted to the parallel port
lines using a hardware protocol handshake. However, data
in the tFIFO may be displayed on the parallel port data lines.
The tFIFO will not stall when overwritten or underrun. If an
attempt is made to write data to a full tFIFO, the new data is
not accepted into the tFIFO. If an attempt is made to read
data from an empty tFIFO, the last data byte is re-read
again. The full and empty bits must always keep track of the
correct FIFO state. The tFIFO will transfer data at the
maximum ISA rate so that software may generate
performance metrics.
The FIFO size and interrupt threshold can be determined by
writing bytes to the FIFO and checking the full and
servicelntr bits.
Mode = 111
BIT 7 compress
This bit is read only. During a read, it is a low level. This
means that this chip does not support hardware RLE
compression. It does support hardware de-compression.
BIT 6 IntrValue
Returns the value on the ISA IRQ line to determine possible
conflicts.
BITS 5~0 : The ECP Parallel port Configuration register B
must reflect the IRQ and DRQ selected by the Configuration
registers
IRQ
selected
14
13
11
10
9
7
5
Others
Config.Reg. B
Bits 5: 3
110
101
100
011
010
001
111
000
DMA
selected
3
2
1
Others
Config.Reg. B
Bits 5: 3
011
010
001
000
The writelntr Threshold can be determined by starting with a
full tFIFO, setting the direction bit to 0 and emptying it a
byte at a time until servicelntr is set. This may generate a
spurious interrupt, but will indicate that the threshold has
been reached.
ECR (Extended Control Register) Address Offset = 402H
The readlntr Threshold can be determined by setting the
direction bit to 1 and filling the empty tFIFO a byte at a time
until servicelntr is set. This may generate a spurious
interrupt, but will indicate that the threshold has been
reached.
BITS 7, 6, 5
These bits are Read/Write and select the Mode.
Data bytes are always read from the head of tFIFO
regardless of the value of the direction bit. For example if
44h, 33h, 22h is written to the FIFO, then reading the tFIFO
will return 44h, 33h, 22h in the same order as was written.
Mode = all
This register controls the extended ECP parallel port
functions.
BIT 4 ErrlntrEnJ
Read/Write (Valid only in ECP Mode)
1: Disables the interrupt generated on the asserting edge of
FaultJ.
0: Enables an interrupt pulse on the high to low edge of
FaultJ. Note that an interrupt will be generated if Fault is
asserted (interrupting) and this bit is written from a 1 to a
0. This prevents interrupts from being lost in the time
between the read of the ecr and the write of the ecr.
BIT 3 dmaEn
Read/Write
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1: Enables DMA (DMA starts when servicelntr is 0).
0: Disable DMA unconditionally.
BIT 2 servicelntr
Read/Write
1: Disable DMA and all of the service interrupts.
0: Enables one of the following 3 cases of interrupts. Once
one of the 3 service interrupts has occurred, servicelntr bit
shall be set to a 1 by hardware, it must be reset to 0 to reenable the interrupts. Writing this bit to a 1 will not cause
an interrupt.
case dmaEn = 1:
During DMA (this bit is set to a 1 when terminal count is
reached).
case dmaEn = 0 direction = 0:
This bit shall be set to 1 whenever there are writelntr
Threshold or more bytes free in the FIFO.
case dmaEn = 0 direction = 1:
This bit shall be set to 1 whenever there are readlntr
Threshold or more valid bytes to be read from the FIFO.
BIT 1 full
Read only
1: The FIFO cannot accept another byte or the FIFO is
completely full.
0: The FIFO has at least 1 free byte.
BIT 0 empty
Read only
1: The FIFO is completely empty.
0: The FIFO contains at least 1 byte of data.
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OPERATION
Table 8-7 - Extended Control Register
R/W
000
001
010
011
100
101
110
111
Mode
Standard Parallel Port mode. In this mode, the
FIFO is reset and common collector drivers are
used on the control lines (StrobeJ, AutoFdJ,
InitJ and SelectlnJ). Setting the direction bit
will not tri-state the output drivers in this mode.
PS/2 Parallel Port mode. Same as above
except that direction may be used to tri-state
the data lines and reading the data register
returns the value on the data lines and not the
value in the data register. All drivers have
active pull-ups (push-pull).
Parallel Port FIFO mode. This is the same as
000 except that bytes are written or DMAed to
the FIFO. FIFO data is automatically
transmitted using the standard parallel port
protocol. Note that this mode is only useful
when direction is 0. All drivers have active
pull-ups (push-pull).
ECP Parallel Port Mode. In the forward
direction(0), bytes placed into the ecpDFifo and
bytes written to the ecpAFifo are placed in a
single FIFO and transmitted automatically to
the peripheral using ECP Protocol. In the
reverse direction (1), bytes are moved from the
ECP parallel port and packed into bytes in the
ecpDFifo. All drivers have active pull-ups
(push-pull).
Selects EPP Mode: In this mode, EPP is
selected if the EPP supported option is
selected in configuration register CR4. All
drivers have active pull-ups (push-pull)
Reserved
Test Mode. In this mode, the FIFO may be
written and read, but the data will not be
transmitted on the parallel port. All drivers have
active pull-ups (push-pull).
Configuration Mode. In this mode the confgA,
confgB registers are accessible at 0x400 and
0x401. All drivers have active pull-ups (pushpull).
Mode Switching/Software Control
Software will execute P1284 negotiation and all operation
prior to a data transfer phase under programmed I/O control
(mode 000 or 001) hardware provides an automatic control
line handshake, moving data between the FIFO and the
ECP port only in the data transfer phase (modes 011 or
010).
Setting the mode to 011 or 010 will cause the hardware to
initiate data transfer.
If the port is in mode 000 or 001, it may switch to any other
mode. If the port is not in mode 000 or 001, it can only be
switched to mode 000 or 001. The direction can only be
changed in mode 001.
Once in an extended forward mode the software should wait
for the FIFO to be empty before switching back to mode 000
or 001. In this case all control signals will be deasserted
before the mode switch. In an ecp reverse mode, the
software waits for all the data to be read from the FIFO
before changing back to mode 000 or 001. Since the
automatic hardware ecp reverse handshake only cares
about the state of the FIFO, it may have acquired loose data
that will be eliminated. It may in fact be in the middle of a
transfer when the mode is changed back to 000 or 001. In
this case the port will deassert AutoFdJ independent of the
state of the transfer. The design shall not cause glitches on
the handshake signals if the software meets the constraints
above.
ECP Operation
Prior to ECP operation the Host must negotiate on the
parallel port to determine if the peripheral supports the ECP
protocol. This is a somewhat complex negotiation carried
out under program control in mode 000.
After negotiation, it is necessary to initialize some of the port
bits. The following are required:
. Set Direction = 0, enabling the drivers.
. Set strobe = 0, causing the StrobeJ signal to default to the
deasserted state.
. Set autoFd = 0, causing the AutoFdJ signal to default to
the deasserted state.
. Set mode = 011 (ECP Mode)
ECP address/RLE bytes or data bytes may be sent
automatically by writing the ECPAFIFO or ECPDFIFO
respectively.
Note that all FIFO data transfers are byte wide and byte
aligned. Address/RLE transfers are byte-wide and only
allowed in the forward direction.
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Data Compression
The host may switch directions by first switching to mode =
001, negotiating for the forward or reverse channel, setting
direction to 1 or 0, then setting mode = 011. When direction
is 1 the hardware shall handshake for each ECP read data
byte and attempt to fill the FIFO. Bytes may then be read
from the ecpDFifo as long as it is not empty.
ECP transfers may also be accomplished (albeit slowly) by
handshaking individual bytes under program control in mode
= 001, or 000.
Termination from ECP Mode
Termination from ECP Mode is similar to the termination
from Nibble/Byte Modes. The host is permitted to terminate
from ECP Mode only in specific well-defined states. The
termination can only be executed while the bus is in the
forward direction. To terminate while the channel is in the
reverse direction, it must first be changed into the forward
direction.
The M512x supports run length encoded (RLE)
decompression in hardware and can transfer compressed
data to a peripheral.
Run length encoded (RLE)
compression in hardware is not supported. To transfer
compressed data in ECP mode, the compression count is
written to the ecpAFifo and the data byte is written to the
ecpDFifo.
Compression is accomplished by counting identical bytes
and transmitting an RLE byte that indicates how many times
the next byte is to be repeated. Decompression simply
intercepts the RLE byte and repeats the following byte the
specified number of times. When a run-length count is
received from a peripheral, the subsequent data byte is
replicated the specified number of times. a run-length count
of zero specifies that only one byte of data is represented by
the next data byte, whereas a run-length count of 127
indicates that the next byte should be expanded to 128
bytes. To prevent data expansion, however, run-length
counts of zero should be avoided.
Pin Definition
Command/Data
ECP Mode supports two advanced features to improve the
effectiveness of the protocol for some applications. The
features are implemented by allowing the transfer of normal
8-bit data or 8-bit commands.
When in the forward direction, normal data is transferred
when HostAck is high and an 8-bit command is transferred
when HostAck is low.
The most significant bit of the command indicates whether it
is a run-length count (for compression) or a channel
address.
When in the reverse direction, normal data is transferred
when PeriphAck is high and an 8-bit command is transferred
when PeriphAck is low.
The most significant bit of the command is always zero.
Reverse channel addresses are seldom used and may not
be supported in hardware.
Table 8-8
Forward Channel Commands (HostAck Low)
Reverse Channel Commands (PeripAck Low)
D7 D[6:0]
0
Run-Length Count (0-127)
(mode 0011 0x00 only)
1
Channel Address (0-127)
The drivers for StrobeJ, AutoFdJ, InitJ and SelectlnJ are
open-collector in mode 000 and are push-pull in all other
modes.
ISA Connections
The interface can never stall causing the host to hang. The
width of data transfers if strictly controlled on an I/O address
basis per this specification. All FIFO-DMA transfers are byte
wide, byte aligned and end on a byte boundary. (The
PWord value can be obtained by reading Configuration
Register A, cnfgA, described in the next section.) Single
byte wide transfers are always possible with standard or
PS/2 mode using program control of the control signals.
Interrupts
The interrupts are enabled by servicelntr in the ecr register.
servicelntr = 1 Disables the DMA and all of
interrupts.
the service
servicelntr = 0 Enables the selected interrupt condition. If
the interrupting condition is valid, then the interrupt is
generated immediately when this bit is changed from a 1 to
a 0. This can occur during Programmed I/O if the number
of bytes removed or added from/to the FIFO does not
cross the threshold.
The interrupt generated is ISA friendly in that it must pulse
the interrupt line low, allowing for interrupt sharing. After a
brief pulse low following the interrupt event, the interrupt line
is tri-stated so that other interrupts may assert.
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An interrupt is generated when :
DMA Transfers
1. For DMA transfers: When servicelntr is 0, dmaEn is 1 and
the DMA TC is received.
2. For Programmed I/O:
a. When servicelntr is 0, dmaEn is 0, direction is 0 and
ther are writelntr Threshold or more free bytes in the FIFO.
Also, an interrupt is generated when servicelntr is cleared
to 0 whenever there are writelntr Threshold or more free
bytes in the FIFO.
b. (1) When servicelntr is 0, dmaEn is 0, direction is 1
and there are readlntr Threshold or more bytes in the FIFO.
Also, an interrupt is generated when servicelntr is cleared to
0 whenever there are readlntr Threshold or more bytes in the
FIFO.
3. When nErrlntrEn is 0 and nFault transitions from high to
low or when nErrlntrEn is set from 1 to 0 and nFault is
asserted.
4. When acklntEn is 1 and the nAck signal transitions from a
low to a high.
FIFO Operation
The FIFO threshold is set in the chip configuration registers.
All data transfers to or from the parallel port can proceed in
DMA or programmed I/O (non-DMA) mode as indicated by
the selected mode. The FIFO is used by selecting the
Parallel Port FIFO mode or ECP Parallel Port Model. (FIFO
test mode will be addressed separately.) After a reset, the
FIFO is disabled. Each data byte is transferred by a
Programmed I/O cycle or PDRQ depending on the selection
of DMA or Programmed I/O mode.
The following paragraphs detail the operation of the FIFO
flow control. In these descriptions, <threshold> ranges from
1 to 16. The parameter FIFOTHR, which the user programs,
is one less and ranges from 0 to 15.
A low threshold value (i.e.2) results in longer periods of time
between service requests, but requires faster servicing of the
request for both read and write cases. The host must be
very responsive to the service request. This is the desired
case for use with a "fast" system.
A high value of threshold (i.e. 12) is used with a "sluggish"
system by affording a long latency period after a service
request, but results in more frequent service requests.
Page 90
DMA transfers are always to or from the ecpDFifo, tFifo or
CFifo. DMA utilizes the standard PC DMA services. To use
the DMA transfers, the host first sets up the direction and
state as in the programmed I/O case. Then it programs the
DMA controller in the host with the desired count and
memory address. Lastly it sets dmaEn to 1 and servicelntr
to 0. The ECP requests DMA transfers from the host by
activating the PDRQ pin. The DMA will empty or fill the
FIFO using the appropriate direction and mode. When the
terminal count in the DMA controller is reached, an interrupt
is generated and servicelntr is asserted, disabling DMA. In
order to prevent possible blocking of refresh requests dReq
shall not be asserted for more than 32 DMA cycles in a row.
The FIFO is enabled directly by asserting PDACKJ and
addresses need not be valid. PINTR is generated when a TC
is received. PDRQ must not be asserted for more than 32
DMA cycles in a row. After the 32nd cycle, PDRQ must be
kept unasserted until PDACKJ is deasserted for a minimum
of 350 nsec. (Note: The only way to properly terminate
DMA transfers is with a TC.)
DMA may be disabled in the middle of a transfer by first
disabling the host DMA controller. Then setting servicelntr
to 1, followed by setting dmaEn to 0, and waiting for the
FIFO to become empty or full. Restarting the DMA is
accomplished by enabling DMA in the host, setting dmaEn
to 1, followed by setting servicelntr to 0.
DMA Mode - Transfers from the FIFO to the Host
(Note: In the reverse mode, the peripheral may not continue
to fill the FIFO if it turns out of data to transfer, even if the
chip continues to request more data from the peripheral.)
The ECP activates the PDRQ pin whenever there is data in
the FIFO. The DMA controller must respond to the request
by reading data from the FIFO. The ECP will deactivate the
PDRQ pin when the FIFO becomes empty or when the TC
becomes true (qualified by PDACKJ), indicating that no
more data is required. PDRQ goes inactive after PDACKJ
goes active for the last byte of a data transfer (or on the
active edge of IORJ, on the last byte, if no edge is present
on PDACKJ). If PDRQ goes inactive due to the FIFO going
empty, then PDRQ is active again as soon as there is one
byte in the FIFO. If PDRQ goes inactive due to the TC, then
PDRQ is active again when there is one byte in the FIFO,
and servicelntr has been re-enabled. (Note: A data underrun
may occur if PDRQ is not removed in time to prevent an
unwanted cycle.)
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M512x : Mega I/O Controller with PnP
Programmed I/O Mode or Non-DMA Mode
The ECP or parallel port FIFOs may also be operated using
interrupt driven programmed I/O. Software can determine
the writelntrThreshold, readlntrThreshold, and FIFO depth
by accessing the FIFO in Test Mode.
Programmed I/O transfers are to the ecpDFifo at 400H and
ecpAFifo at 000h or from the ecpDFifo located at 400H, or
to/from the tFifo at 400H. to use the programmed I/O
transfers, the host first sets up the direction and state, sets
dmaEn to 0 and servicelntr to 0.
The ECP requests programmed I/O transfers from the host
by activating the PINTR point. The programmed I/O will
empty or fill the FIFO using the appropriate direction and
mode.
Note: A threshold of 16 is equivalent to a threshold of 15.
These two cases are treated the same.
Programmed I/O - Transfers from the FIFO to the Host
In the reverse direction an interrupt occurs when servicelntr
is 0 and readlntr Threshold bytes are available in the FIFO.
If at this time the FIFO is full it can be emptied completely in
a single burst, otherwise readlntr Threshold bytes may be
read from the FIFO in a single burst.
Programmed I/O - Transfers from the Host to the FIFO
In the forward direction, an interrupt occurs when servicelntr
is 0 and there are writelntrThreshold or more bytes free in
the FIFO. At this time if the FIFO is empty it can be filled
with a single burst before the empty bit need to be re-read.
Otherwise it may be filled with writelntrThreshold bytes.
The FIFO threshold value is selected via <THR> = <CRA
bit7-4>
16 data bytes FIFO, if <THR>=0
The readIntr Threshold = {
<THR> data bytes FIFO, if
<THR>=1 to 15
For example, if the <THR>=4, then the serviceIntr is set
whenever there are 4-16 bytes in the FIFO
16 free bytes FIFO, if <THR>=0
The writeIntr Threshold = {
<THR> free bytes
<THR>=1 to 15
FIFO,
if
For example, if the <THR>=4, then the serviceIntr is set
whenever there are 4-16 bytes free in the FIFO.
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M512x : Mega I/O Controller with PnP
Section 9 : Common I/O Ports
The M512x has 22 independently programmable common I/O ports (CIO). Each CIO port is represented as a bit in one of three
8-bit registers, CIO1, CIO2 or CIO3. Only 6 bits of CIO2 are implemented. Each CIO port and its alternate function is listed in
table below.
CIO Port
CIO10
CIO11
CIO12
CIO13
CIO14
CIO15
CIO16
CIO17
CIO20
CIO21
CIO22
CIO23
CIO24
CIO25
CIO30
CIO31
CIO32
CIO33
CIO34
CIO35
CIO36
CIO37
Alternate Function
Interrupt Steering
Interrupt Steering
IRRX Input
IRTX Output
GATEA20 Output
RC Reset Output
I2C Interface CLK Output
I2C Interface DATA I/O
Register Assignment
CIO1, bit 0
CIO1, bit 1
CIO1, bit 2
CIO1, bit 3
CIO1, bit 4
CIO1, bit 5
CIO1, bit 6
CIO1, bit 7
CIO2, bit 0
CIO2, bit 1
CIO2, bit 2
CIO2, bit 3
CIO2, bit 4
CIO2, bit 5
CIO3, bit 0
CIO3, bit 1
CIO3, bit 2
CIO3, bit 3
CIO3, bit 4
CIO3, bit 5
CIO3, bit 6
CIO3, bit 7
Keylock Input
KBC clock source Input
CS0J Output
CS1J Output
ALT_KCLK I/O
ALT_KDAT I/O
ALT_MCLK I/O
ALT_MDAT I/O
ALT_KBC select Input
CIO registers CIO1, CIO2 and CIO3 can be accessed by the host when the chip is in the normal run mode; i.e., not in the
configuration mode. The host uses an index and data register to access the CIO registers. The power on default index and data
registers are 0xEA and 0xEB respectively. When the chip is in configuration mode, these index and data registers are used to
access the internal configuration registers. In configuration mode, the index address may be programmed to reside on address
0xE0, 0xE2, 0xE4 or 0xEA. The data address is automatically set to the index address + 1. Upon exiting the configuration mode,
the new Index and Data registers are used to access registers CIO1, CIO2 and CIO3.
To access the CIO1 register the host should first make sure the chip is in the normal (run) mode. Then it should perform an IOW
of 0x01 to the Index register (at 0xEX) to select CIO1 and then read or write the Data register (at Index+1) to access the CIO1
register.
To access CIO2 the host should perform an IOW of 0x02 to the Index register and then access CIO2 through the Data register.
To access CIO3 the host should perform an IOW of 0x03 to the Index register and then access CIO3 through the Data register.
Register
Index
Data
Address
0xE0,0xE2,
0xE4,0xEA
0xE1,0xE3,
0xE5,0xEB
Normal (Run) Mode
0x01
0x02
access
CIO1
to
access
CIO2
Config Mode
0x00-0xFF
0x03
to
access
CIO3
to
access to
registers
internal
Config
CIO ports can assume alternate functions such as input-type, output-type or I/O type. The CIO port structure for each type is
illustrated in the following figures.
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Common I/O Configuration Registers
Assigned to each CIO port is an 8-bit CIO configuration register which is used to independently program each I/O port. The CIO
configuration registers are only accessible when the M512x is in the configuration mode. Configuration section of this
specification contains more details.
Reading and Writing CIO Ports
When a CIO port is programmed as an input, reading it through the CIO register latches either the inverted or non-inverted logic
value present at the CIO pin; writing to it has no effect. When a CIO port is programmed as an output, the logic value written into
the CIO register is either output to or inverted to the CIO pin; when read the result will reflect the contents of the CIO register bit.
This is summarized in Table 9-1.
Table 9-1 - CIO Read/Write Behavior
CIO Input Port
CIO Output Port
latched value of CIO pin
bit value in CIO register
no effect
bit placed in CIO register
Host Operation
Read
Write
GATEA20
GateA20 is an internal signal from the Keyboard controller (Port 21). The M512x may be configured to drive this signal onto
CIO14 by programming its CIO configuration register.
KBC RC Reset
KBC RC is an internal signal from the Keyboard controller (Port 20). The M512x may be configured to drive this signal onto CIO15
by programming its CIO configuration register.
The M512x provides a set of flexible Input/Output control functions to the system designer through a set of Common I/O pins
(CIO). These CIO pins may perform simple I/O or may be individually configured to provide a predefined alternate function.
Power on reset configures all CIO pins as simple non-inverting inputs.
There are four types of CIO ports as shown in following figures :
CIO
configuration
Register bit-1
(polarity)
CIO
configuration
Register bit-0
(Input/Output)
I/O bit
D-type
nIOW
0
Transparent
nIOR
CIO pin
1
CIO
register
bit-n
CIO having no alternate function (CIO20-CIO24)
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M512x : Mega I/O Controller with PnP
Alternate
Output
Function
I/O bit
CIO
configuration
CIO
Register bit-3
(Alt-function) configuration
Register bit-1
(polarity)
CIO
configuration
Register bit-0
(Input/Output)
1
D-type
0
nIOW
0
Transparent
CIO pin
1
nIOR
CIO
register
bit-n
CIO having an output-type alternate function. (CIO13, CIO14, CIO15, CIO16, CIO31, CIO32)
CIO
configuration
Register bit-1
(Polarity)
CIO
configuration
Register bit-0
(Input/Output)
I/O bit
D-type
nIOW
0
nIOR
Transparent
CIO pin
1
CIO
register
bit-n
Alternate
Input
Function
CIO
configuration
register bit-3
(Alt function)
CIO having an input-type alternate function (CIO10, CIO11, CIO12, CIO30, CIO37, CIO25)
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A
B
C
Alternate
I/O
Function
CIO
configuration
Register bit-1
(polarity)
CIO
configuration
Register bit-0
I/O bit
0
1
B
D-type
Alt bit 3
0
nIOW
1
A
Alt bit 3
0
Transparent
nIOR
CIO pin
1
CIO
register
bit-n
C
CIO having an I/O type alternate function (CIO17, CIO33, CIO34, CIO35, CIO36)
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Section 10 : Electrical Characteristics
10.1 Absolute Maximum Ratings
Unless otherwise specified, all voltages are measured with
respect to ground.
Absolute maximum ratings are those values beyond which
damage to the device may occur. Continuous operation at
these limits is not intended and should be limited to those
conditions specified under DC Electrical Characteristics.
Table 10-1
Absolute Maximum Ratings
Item
Ratings
Supply voltage VDD
Operating supply voltage
-0.5V to +7V
4.5V to 5.5V
All input and output
voltages with respect to VSS
-0.5V to VCC +0.5V
Storage temperature range (TSTG)
-65oC to 150oC
0oC to 70oC
Operating temperature (TA)
Package power dissipation (PD)
750 mW
260oC
Lead temperature (TL)
(soldering, 10 seconds)
|VCC - VCCA|
0.6V
ESD tolerance (CZAP)
100 pF
10.2 DC Characteristics
VDD = 5.0V ± 5%, VSS = 0V, unless otherwise specified. These values are measured under static conditions, and not under
dynamic conditions.
Table 10-2
Symbol
VIH
VIL
IIN
ICCA
ICC
DC Characteristics
Parameter
High level input voltage
Low level input voltage
Input current
Average VDDA
supply current
Quiescent VDDA supply
current in low power mode
Average VDD
supply current
Quiescent VDD supply
current in low power mode
Page 96
Conditions
Except OSC1/CLK
Except OSC1/CLK
Except OSC pins,
VIN = VDD or GND
VIN = 2.4V or 0.5V,
I/O = 0 mA*
VIN = VDD or GND,
I/O = 0 mA*
VDD = 5.5V; no loads on
the outputs: IORJ, IOWJ, SIN,
DSRJ, DCDJ, CTSJ, RIJ = 2V;
All other inputs: 0.8V or
2.4V; CLK = 24 MHz;
DIVISOR = EFFFh
VIN = VDD or GND,
I/O = 0 mA*
Min
2.0
-0.5
Max
VCC
0.8
Unit
V
V
±1.0
10
uA
mA
400
uA
50
mA
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M512x : Mega I/O Controller with PnP
Table 10-2
DC Characteristics (continued)
Symbol
Parameter
Oscillator Pins (OSC1/CLK)
IOSC
OSC1 input current
Conditions
Min
(OSC1 = GND),
VIN = VDD or GND
±1.6
mA
2.4
V
OSC1 high level
input voltage
OSC2 = GND
VIL
OSC1 low level
input voltage
OSC2 = GND
Disk Drive Interface Pins (MTR0~3, DR0~3, WDATA,
WGATE, RDATA, DIR, HDSEL, TRK0, WRTPRT, RPM,
STEP, DSKCHG, INDEX)
VH
Input hysteresis
VOL
Low level output voltage
IOUT = 36 mA
ILKG
Output high
leakage current
VOUT = VDD or GND
VIH
High level input voltage
VIL
Low level input voltage
Microprocessor and Parallel Port Pins
VOL
Output low voltage
IOL = 24 mA on D0~D7;
16 mA on PD0~PD7; 16 mA
on INITJ, AFDJ, STBJ and
SLINJ; 4 mA on all
other outputs
VOH
Output high voltage
IOH = -12 mA on D0~D7;
-16 mA on PD0~PD7; -16 mA
on INITJ, AFDJ, STBJ and
SLINJ; -4 mA on all
other outputs
IIL
Input leakage
VDD = 5.5V, VSS = 0V
All other pins floating
IOZ
Output tri-state leakage
VDD = 5.5V, VSS = 0V
VOUT = 0V, 5.5V
Max
Unit
VIH
0.4
250 typical
0.4
±100
V
mV
V
0.8
uA
V
V
0.4
V
2.2
2.4
V
±10
uA
±20
uA
* ICC is measured with a 0.1 uF supply decoupling capacitor-to-ground.
10.2.1 Capacitance
TA = 25oC, VDD = VSS = 0V)
Table 10-3
Symbol
CIN
COUT
CI/O
Capacitance
Parameter
Input capacitance
Output capacitance
I/O capacitance
Conditions
fC = 1 MHz; Unmeasured
pins returned to VSS
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Typ
5
6
10
Max
7
8
12
Units
pF
pF
pF
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M512x : Mega I/O Controller with PnP
10.3 AC Characteristics
TA = 0oC to +70oC, VDD = +5V ± 5%.
All AC timings can be met with current loads that do not exceed 3.2 mA or -8 uA at 100 pF capacitive loading. For capacitive
loads that exceed 100 pF, the following typical derating factors should be used:
100 pF < CL ≤150 pF, t = (0.10 ns/pF) (CL - 100 pF) typical
150 pF < CL ≤ 200 pF, t = (0.08 ns/pF) (CL - 100 pF) and
t = (0.5 ns/mA) (ISINK mA) or t = -(0.5 ns/mA) (ISOURCE mA)
tSOURCE is always negative, ISINK ≤4.8 mA, ISOURCE ≤ -120 uA, CL ≤ 250 pF.
Table 10-4 lists the AC Characteristics of the M512x.
Table 10-4
Symbol
tAR
tAW
tCH
tCL
tDH
tDS
tHZ
tRA
tRC
tRD
tTPS
tRI
tRVD
tRW
tWA
tWC
tWI
tWO
tWR
RC
WC
AC Characteristics
Parameter
Delay from address to IORJ
Delay from address to IOWJ
Duration of clock high pulse
Duration of clock low pulse
Data hold time
Data setup time
IORJ to floating data delay
Address hold time from IORJ
Read cycle update
IORJ strobe width
Port setup
Read strobe to clear IRQ6
Delay from IORJ to data
Reset pulse width
Address hold time from IOWJ
Write cycle update
Write strobe to clear IRQ6
Write to output
IOWJ strobe width
Read cycle = tAR + tRD + tRC
Write cycle = tAW + tWR + tWC
Conditions
see Note A
see Note A
see Note B
Min
19
19
16
16
10
19
13
0
36
60
13
Max
52
31
100
0
36
52
41
50
115
105
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note: A. External clock (24 MHz maximum).
B. Charge and discharge time is determined by VOL, VOH and the external loading.
Page 98
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M512x : Mega I/O Controller with PnP
10.4 AC Test Conditions
In Table 10-5, CL = 100 pF. This includes jig and scope
capacitance. S1 is open for push-pull outputs. S1 is equal
to VCC for high impedance to active low, and active low to
high impedance measurements. S1 is equal to GND for
high impedance to active high, and active high to high
impedance measurements.
RL = 1.0 kohm for CPU
interface pins. For the open drain drive interface pins S1 =
VCC and RL = 150 ohms.
VCC
S1
0.1µ F
input
RL
Device
under
test
Output
CL
Table 10-5
AC Test Conditions
Input pulse levels
Input rise and fall times
I/O reference levels
Tri-state reference levels
GND to 3.0V
6 ns
1.3V
Active high - 0.5V
Active low + 0.5V
External Clock Input (24 MHz)
tCH
2.4V
2.0V
CLK
0.8V
0.4V
tCL
The 2.4V and 0.4V levels are the voltages tthat tthe inputs are driven to
during AC testing
Table 10-6
Symbol
N
tBHD
tBLD
Serial Interface Baud Generator
Parameter
Baud Divisor
Baud output positive
edge delay
Baud output negative
edge delay
Conditions
Min
1216 - 1
CLK = 24 MHz / 2,
100 pF load
CLK = 24 MHz / 2,
100 pF load
Max
Unit
56
ns
56
ns
BAUDOUTJ Timing
CLK |<-
N
->|
->| |<- tBLD
Baudoutj
->| |<-tBHD
Baudoutj/2
Baudoutj/3
->| |<- tBLD
->| |<-tBHD
->| |<- tBLD
->| |<-tBHD
Baudoutj(/n,n>3)
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M512x : Mega I/O Controller with PnP
CPU Interface
Read Cycle
AEN
A0-A9
Valid
RC
tRD
tRC
IORJ
IOWJ
tAR
tRVD
tRA
D0-D7
Valid data
tHZ
tRI
IRQ6
Write Cycle
AEN
A0-A9
Valid
IOWJ
IORJ
D0-D7
WC
tWR
tWC
tAW
tWA
Valid data
tDS
tDH
tWI
IRQ6
Page 100
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M512x : Mega I/O Controller with PnP
DMA Timing
DMA acknowledge is sufficient to acknowledge a data
transfer. Read or write strobes are necessary only if data is
presented to the data bus. If read/write strobes are applied,
Table 10-7
Symbol
tAA
tAQ
tQA
tQR
tTQ
tTT
Note:
then the read/write strobes and the acknowledge must be
removed within 1 us of each other.
DMA Timing
Parameter
DAK pulse width
End of DRQ from DAK
DAK assertion from DRQ
DRQ to read or write strobe
Time after last DRQ that TC must be asserted
TC strobe width
Min
60
Max
92
8
8
Note
40
Unit
ns
ns
ns
ns
ns
ns
The terminal count pin (TC) terminates the data transfer operation. There are several constraints placed on the timing
of TC. 1) TC is enabled by DAKJ, so TC must be pulsed while DAKJ is low. 2) TC must occur before ((1/data rate x 8)
- 1 us). Data rate is the exact data transfer rate being used.
DRQ
tAQ
tAA
DAKJ
tQA
IORJ or IOWJ
tQR
TC
tTT
tTQ
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M512x : Mega I/O Controller with PnP
Drive Read and Write Timing
Table 10-8
Drive Read and Write Timing
Symbol
tRDW
tWD
tHDS
tHDH
Parameter
Read-data pulse-width
Write-data pulse-width
Head-select setup to write-gate-assertion
Head-select hold from write-gate
300 kb/s (MFM)
500 kb/s (MFM)
1000 kb/s (MFM)
Note :
Conditions
250 kb/s (MFM)
416
250
225
Min
25
500
40
12
ns
ns
ns
Unit
ns
ns
us
ns
Whenever WGATE is asserted, the WDATA line is active. At the end of each write, one dummy byte is written
before WGATE is deasserted.
RDATA
tRDW >| |<
HDSEL
>|
|<tHDS
>|
tHDH
|<
WGATE
>|
|< tWD
WDATA
Page 102
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M512x : Mega I/O Controller with PnP
Drive Track Access Timing
Table 10-9
Drive Track Access Timing
Symbol
tDH
tDRV
tDST
tIW
tSTP
Parameter
Direction hold from end-of-step
Drive-select or motor-time from write-strobe
Direction-setup prior to step
Index pulse-width
Step pulse-width
Min
1 step time
Max
Unit
100
ns
us
ns
us
6
100
8
INDEX
>|
tIW
|<
IOWJ
>| tDRV |<
>| tDRV |<
DR0-3, MTR0-3
>|
tDH
|<
DIR
>|
tDST
|< >|
Programmable
|<
STEP
>| tSTP|<
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M512x : Mega I/O Controller with PnP
Transmitter
Table 10-10
Symbol
tHR
tIR
tIRS
tSI
tSTI
Transmitter
Parameter
Delay from IOWJ (WR THR) to reset interrupt
Delay from IORJ (RD IIR) to reset interrupt (THRE)
Delay from initial INTR reset to transmit start
Delay from initial write to interrupt
Delay from start to interrupt (THRE)
start
Serial out
Data (5-8)
|<-tIRS->|
Interrupt
IOWJ
Min
8
16
Max
50
50
24
24
8
Unit
ns
ns
Baudout cycles
Baudout cycles
Baudout cycles
start
Parity
->|
|<- tHR ->|
|<-
|<-tSTI
|<- tHR ->|
tSI
->|
tIR ->|
|<-
IORJ
Page 104
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M512x : Mega I/O Controller with PnP
Modem Control
Table 10-11
Modem Control
Symbol
tMDO
tRIM
tSIM
Parameter
Delay from IOWJ (WR MCR) to output
Delay to reset interrupt from IORJ (RD MSR)
Delay to set interrupt from modem input
*IOWJ
Max
50
98
50
Unit
ns
ns
ns
|<-tMDO->|
|<- tMDO ->|
RTSJ, DTRJ
CtsJ,DsrJ,DcdJ
Interrupt
|<- tSIM ->|
|<- tRIM ->|
|<- tSIM ->|
|<- tRIM ->|
**IORJ
|<>|
tSIM
-
RIJ
* : See Write Cycle Timing
** : See Read Cycle Timing
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M512x : Mega I/O Controller with PnP
Receiver
Table 10-12
Symbol
tRAI
tRINT
tSCD
tSINT
Receiver
Parameter
Delay from active edge of IORJ to reset interrupt
Delay from inactive edge of IORJ (RD LSR) to reset interrupt
Delay from RCLK to sample time
Delay from stop to set interrupt
SIN
Max
98
50
41
2
Unit
ns
ns
ns
Baudout cycles
DATA(5-8)
Sample CLK1
RDR int.
LSI int.
IORJ(RDRBR)
IORJ(RDLSR)
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M512x : Mega I/O Controller with PnP
Amplitude Shift Keyed IR Transmit Timing
Table 10-13. ASK IR Transmit Timing
Symbol
tmo
tob
tmo3
tmo4
tmo5
tmo6
Parameter
Modulated output bit time
Off bit time
Modulated output “ on”
Modulated output “ on”
Modulated output “ on”
Modulated output “ off”
DATA
0
1
0
Min
Typ
Max
0.79
0.79
0.79
0.79
1
1
1
1
1.21
1.21
1.21
1.21
1
0
0
Unit
us
us
us
us
us
us
1
1
0
1
1
IRTX
tmo
tob
tmo3 tmo4
MIRTX
tmo5 tmo6
Notes :
1. t1, t2 timing referred to IrDA Transmit Timing @ each baud rate.
2. UART1, UART2 0xF1 bit 1: 1 = receive active low
0 = receive active high (default )
3. MIRTX are the modulated outputs. ( 500k )
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M512x : Mega I/O Controller with PnP
IrDA Receive Timing
Table 10-14. IrDA Receive Timing
Symbol
tpw1
tpw1
tpw1
tpw1
tpw1
tpw1
tpw1
tbt2
tbt2
tbt2
tbt2
tbt2
tbt2
tbt2
DATA
Parameter
Pulse width at 115k baud
Pulse width at 57.6k baud
Pulse width at 38.4k baud
Pulse width at 19.2k baud
Pulse width at 9.6k baud
Pulse width at 4.8k baud
Pulse width at 2.4k baud
Bit time at 115k baud
Bit time at 57.6k baud
Bit time at 38.4k baud
Bit time at 19.2k baud
Bit time at 9.6k baud
Bit time at 4.8k baud
Bit time at 2.4k baud
0
1
0
1
Min
1.40
1.40
1.40
1.40
1.40
1.40
1.40
0
0
Typ
1.60
3.22
4.80
9.70
19.50
39.00
78.00
8.68
17.40
26.00
52.00
104.00
208.00
416.00
1
1
Max
2.71
3.69
5.53
11.07
22.13
44.27
88.55
0
Unit
us
us
us
us
us
us
us
us
us
us
us
us
us
us
1
1
IRRX
tpw1
tbt2
Notes :
1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX.
2. UART1, UART2 0xF1 bit 0 : 1 = receive active low
0 = receive active high (default )
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M512x : Mega I/O Controller with PnP
IrDA Transmit Timing
Table 10-15. IrDA Transmit Timing
Symbol
tp1
tp1
tp1
tp1
tp1
tp1
tp1
tb2
tb2
tb2
tb2
tb2
tb2
tb2
DATA
Parameter
Pulse width at 115k baud
Pulse width at 57.6k baud
Pulse width at 38.4k baud
Pulse width at 19.2k baud
Pulse width at 9.6k baud
Pulse width at 4.8k baud
Pulse width at 2.4k baud
Bit time at 115k baud
Bit time at 57.6k baud
Bit time at 38.4k baud
Bit time at 19.2k baud
Bit time at 9.6k baud
Bit time at 4.8k baud
Bit time at 2.4k baud
0
1
0
1
Min
1.39
1.39
1.39
1.39
1.39
1.39
1.39
-
0
0
1
Typ
1.60
3.22
4.80
9.70
19.50
39.00
78.00
8.68
17.40
26.00
52.00
104.00
208.00
416.00
1
0
Max
2.72
3.70
5.54
11.08
22.14
44.28
88.56
-
1
Unit
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
µs
1
IRTX
tp1
tb2
Notes :
1. IrDA @ 115k is HPSIR compatible. IrDA @ 2400 will allow compatibility with HP95LX and 48SX.
2. UART1, UART2 0xF1 bit 1 : 1 = transmit active low
0 = transmit active high (default)
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M512x : Mega I/O Controller with PnP
Parallel Port Interrupt Timing
Table 10-16. Parallel Port Interrupt Timing
Symbol
t1
t2
Parameter
PIRQ delay from ACKJ, nFault
PIRQ active in EPP & ECP modes
t1
Min
Typ
250
Max
30
375
Unit
ns
ns
t1
ACKJ
PIRQ
(SPP & PS2)
t2
PIRQ
(EPP & ECP)
t1
nFault
(ECP)
t2
PIRQ
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M512x : Mega I/O Controller with PnP
EPP Mode Version 1.7 Timing
Table 10-17. EPP Mode Version 1.7 Timing
Symbol
t1
t2
t3
t4
t5
Parameter
IOWJ active to WRITEJ active
IOWJ active to WRITEJ & DSTRBJ/ASTRBJ active
WRITEJ active to PD7-0 valid
WAITJ active to IOCHRDYJ active
DSTRBJ/ASTRBJ inactive to PD7-0 invalid
Min
Typ
Max
45
45
15
40
Unit
ns
ns
ns
ns
ns
50
SD7-0
IOWJ
t1
IORJ
t1
WRITEJ
t2
t2
t2
t2
DSTRBJ
or ASRRBJ
t5
t3
PD7-0
t4
WAITJ
t4
t4
t4
IOCHRDY
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M512x : Mega I/O Controller with PnP
EPP Mode version 1.9 Timing
Table 10-18. EPP Mode version 1.9 Timing
Symbol
t1
t2
t3
t4
t5
t6
t7
Parameter
IOWJ active to WRITEJ active
IOWJ active to DSTRBJ/ASTRBJ active
IOWJ active to IOCHRDY active
WAITJ inactive to DSTRBJ/ASTRBJ inactive
WAITJ inactive to IOCHRDYJ inactive
WAITJ active to WRITEJ inactive
DSTRBJ/ASTRBJ inactive to PD7-0 invalid
Min
Typ
Max
45
65
40
105
40
85
50
Unit
ns
ns
ns
ns
ns
ns
ns
SD7-0
IOWJ
IORJ
t1
WRITEJ
t6
t2
t4
t4
DSTRBJ
or ASRRBJ
t7
t4
PD7-0
t5
WAITJ
t3
t3
t5
IOCHRDY
Page 112
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M512x : Mega I/O Controller with PnP
ECP Mode Timing
Table 10-19. ECP Mode Timing
Symbol
t1
t2
t3
t4
t5
t6
Parameter
DATA valid to STROBEJ active
STROBEJ active to BUSY active
BUSY active to STROBEJ inactive
STROBEJ inactive to BUSY inactive
BUSY inactive to DATA update
BUSY inactive to STROBEJ active
Min
0
0
75
0
0
0
Typ
Max
35
1
Unit
ns
ns
ns
ms
sec
ns
PD7-0
AUTOFDJ
t5
t1
t2
STROBEJ
t3
t4
t6
BUSY
ECP Forward Timing Diagram
PD7-0
BUSY
t5
t1
ACKJ
t2
t3
t4
t6
AUTOFDJ
ECP Backward Timing Diagram
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Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Compatible FIFO Mode Timing
Table 10-20. Compatible FIFO Mode Timing
Symbol
t1
t2
t3
t4
t5
Parameter
Data valid to nSTROBE active
nSTROBE active pulse width
Data hold from nSTROBE inactive
nSTROBE active to BUSY active
BUSY inactive to PDATA TRANSING
Min
Typ
500
500
500
500
Max
80
DATA 1
PDATA
t2
t1
Unit
ns
ns
ns
ns
ns
DATA 2
t3
t1
nSTROBE
t4
t5
BUSY
Page 114
07-02-1997 Document Number: 512xDS02.doc
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Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Parallel Interface
Table 10-21. Parallel Interface
Symbol
tPDH
tPDS
tPI
tSW
Parameter Conditions
Port data hold
Port data setup
Port interrupt
Strobe width
Min
500
500
33
500
Max
Unit
ns
ns
ns
ns
ACKJ
INTP
>|
|<tPI
>|
|<tPI
Interrupt Timing
BUSY
ACKJ
>|
PD0-PD7
tPDS
|<
>|
tPDH
|<
STBJ
>|
tSW
|<
Typical Peripheral Data Exchange
t1
t2
t3
t4
t5
t6
Parameter
Modulated output bit time
Off bit time
Modulated output “ on”
Modulated output “ on”
Modulated output “ on”
Modulated output “ off”
Min
Typ
Max
0.81
0.81
0.81
0.81
1
1
1
1
1.18
1.18
1.18
1.18
07-02-1997 Document Number: 512xDS02.doc
Acer Labs: 7F, 115 Tung Hsing Street, Taipei 110, Taiwan, R.O.C. Tel: 886-(02) 762-8800
Unit
µs
µs
µs
µs
µs
µs
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M512x : Mega I/O Controller with PnP
DATA
0
1
t1
t2
0
1
0
0
1
1
0
1
1
IRRX
t3 t4
MIRRX
t5 t6
Notes :
1. t1, t2 timing referred to IrDA Receive Timing @ each baud rate.
2. UART1, UART2 0xF1 bit 0 : 1 = receive active low
0 = receive active high (default )
3. MIRRX are the modulated outputs. ( 500k )
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Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Section 11 : Packaging Information
HD
160
A2
D
A1
1
E
HE
seating plane
40
c
A
L1
e
b
detail R
€ y
see detail R
o
o
5 ±5
L
Symbol
A
A1
A2
b
c
D
E
e
HD
HE
L1
L
y
Dimensions in Millimeters (nom.)
3.5 (max)
0.20
3.20
0.30
0.15
28.0
28.0
0.65
32.0
32.0
2.01
0.8
0.10
Dimensions in Inches (nom.)
0.138 (max)
0.008
0.126
0.012
0.006
1.102
1.102
0.026
1.260
1.260
0.079
0.031
0.004
07-02-1997 Document Number: 512xDS02.doc
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Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Section 12 : Ordering Information
Ordering Information
M5123 supports Phoenix KBC
M5125 supports AMI KBC
Page 118
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Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
Section 13 : Revision History
p.28 Note : Drive Table 00 = Regular Drives and 2.88MB
01 = 3-mode drive
p.53 Perpendicular Mode
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Acer Laboratories Inc.
M512x : Mega I/O Controller with PnP
Worldwide Distributors and Sales Offices :
Taiwan
Acer Laboratories Inc.
7F, No. 115 Tung Hsing Street,
Taipei 110, Taiwan, R.O.C.
Tel: 886 (2) 762 -8800
Fax: 886 (2) 762 -6060
Japan
ASCII Corporation
8-1, Inarimae, Tsukuba-shi Ibaraki,
305, Japan
Tel: 81 - 298 - 55 - 4004
Fax: 81 - 298 - 55 - 1985
Acer Sertek
11-15F, 135, Sec. 2
Chien Kuo North Road,
Taipei 10479,Taiwan, R.O.C.
Tel: 886 (2) 501-0055
Fax: 886 (2) 501- 2521
Kanematsu Electronic Components Corp.
11F Shin-Ohsaki Kangyo Bldg.,
6-4, Ohsaki 1-Chome,
Shinagawa-Ku, Tokyo, Japan 141
Tel: 81 (3) 3779 - 7850
Fax: 81 (3) 3779 - 7898
Arrow / Ally, Inc.
11F, 678, Sec. 4,
Pa Teh Road,
Taipei, Taiwan, R.O.C.
Tel: 886 (2) 768 - 6399
Fax: 886 (2) 768 - 6390
Macnica Inc.
Hakusan High-Tech Park, 1-22-2 Hakusan,
Midori-Ku, Yokohama City, Japan 226
Tel: 81 (45) 939 - 6116
Fax: 81 (45) 939 - 6117
Asec International Inc.
4F, 223 Chung Yang Road,
Nan Kang, Taipei,
Taiwan, R.O.C.
Tel: 886 (2) 786-6677
Fax: 886 (2) 786 - 5257
Technova Incorporated
9F Daiichi-Seimei Daini Bldg.,
2-14-27, Shin-Yokohama,
Kouhoku-ku, Yokohama-Shi, Kanagawa, 222
Tel: 81 (45) 472-7800
Fax: 81 (45) 472-7830
Korea
Hong Kong
Lestina International Ltd.
14/F, Park Tower 15
Austin Road, Tsimshatsui,
Hong Kong
Tel: 852-2735 -1736
Fax: 852-2730 - 5260
I&C Microsystems Co., Ltd.
801, 8/F, Bethel Bldg.,
324-1, Yangjae-Dong, Seocho-Ku,
Seoul, Korea
Tel: 82 (2) 577 - 9131
Fax: 82 (2) 577 - 9130
Singapore
Texny Glorytact (HK) Ltd.
Unit M, 6/F, Kaiser Estate
Phase 3, 11 Hok Yuen
Street, Hunghom,
Kowloon, Hong Kong
Tel: 852 - 2765 - 0118
Fax: 852 - 2765 - 0557
Page 120
Electronic Resources Ltd.
205 Kallang Bahru, # 04-00,
Singapore 339341
Tel: 65 - 298 - 0888
Fax: 65 - 298 - 1111
ALi U. S. Sales Office
1830-B Bering Drive
San Jose, CA 95112 USA
Tel: 1 (408) 467 - 7456
Fax: 1 (408) 467 - 7474
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Acer Laboratories Inc.
--Preliminary, Confidential, Proprietary--
M512x : Mega I/O Controller with PnP
This material is recyclable.
Acer Labs products are not licensed for use in medical applications, including, but not limited to, use in life support
devices without proper authorization from medical officers. Buyers are requested to inform ALi sales office when
planning to use the products for medical applications.
Product names used in this publication are for identification purposes only and may be trademarks of
their respective companies.
Acer Laboratories Inc. makes no warranty for the use of its products and assumes no responsibility for
any errors which may appear in this document nor does it make a commitment to update the information
contained herein.
Acer Laboratories Inc. retains the right to make changes to these specifications at any time, without
notice.
Contact your local sales office to obtain the latest specifications before placing your order.
ALi is a registered trademark of Acer Laboratories Incorporated and may only be used to identify
ALi’ s products.
© ACER LABORATORIES INCORPORATED 1993
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