TI1 ADC0809 Adc0808/adc0809 8-bit p compatible a/d converters with 8-channel Datasheet

ADC0808,ADC0809
ADC0808/ADC0809 8-Bit P Compatible A/D Converters with 8-Channel
Multiplexer
Literature Number: SNAS535G
ADC0808/ADC0809
8-Bit μP Compatible A/D Converters with 8-Channel
Multiplexer
General Description
Features
The ADC0808, ADC0809 data acquisition component is a
monolithic CMOS device with an 8-bit analog-to-digital converter, 8-channel multiplexer and microprocessor compatible
control logic. The 8-bit A/D converter uses successive approximation as the conversion technique. The converter features a high impedance chopper stabilized comparator, a
256R voltage divider with analog switch tree and a successive
approximation register. The 8-channel multiplexer can directly access any of 8-single-ended analog signals.
The device eliminates the need for external zero and full-scale
adjustments. Easy interfacing to microprocessors is provided
by the latched and decoded multiplexer address inputs and
latched TTL TRI-STATE outputs.
The design of the ADC0808, ADC0809 has been optimized
by incorporating the most desirable aspects of several A/D
conversion techniques. The ADC0808, ADC0809 offers high
speed, high accuracy, minimal temperature dependence, excellent long-term accuracy and repeatability, and consumes
minimal power. These features make this device ideally suited to applications from process and machine control to consumer and automotive applications. For 16-channel multiplexer with common output (sample/hold port) see ADC0816
data sheet. (See AN-247 for more information.)
■ Easy interface to all microprocessors
■ Operates ratiometrically or with 5 VDC or analog span
■
■
■
■
■
■
adjusted voltage reference
No zero or full-scale adjust required
8-channel multiplexer with address logic
0V to VCC input range
Outputs meet TTL voltage level specifications
ADC0808 equivalent to MM74C949
ADC0809 equivalent to MM74C949-1
Key Specifications
■
■
■
■
■
Resolution
Total Unadjusted Error
Single Supply
Low Power
Conversion Time
8 Bits
±½ LSB and ±1 LSB
5 VDC
15 mW
100 μs
Block Diagram
567201
See Ordering Information
© 2009 National Semiconductor Corporation
5672
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ADC0808/ADC0809 8-Bit μP Compatible A/D Converters with 8-Channel Multiplexer
July 8, 2009
ADC0808/ADC0809
Connection Diagrams
Dual-In-Line Package
Molded Chip Carrier Package
567211
Order Number ADC0808CCN or ADC0809CCN
See NS Package NA28E
567212
Order Number ADC0808CCV or ADC0809CCV
See NS Package V28A
Ordering Information
Temperature Range
NA28E Molded DIP
V28A Molded Chip Carrier
V28A Molded Chip Carrier
(Tape and Reel)
±½ LSB Unadjusted
ADC0808CCN
ADC0808CCV
ADC0808CCVX
±1 LSB Unadjusted
ADC0809CCN
ADC0809CCV
ADC0809CCVX
Package Outline
Error
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−40°C to +85°C
2
Operating Conditions
(Notes 2, 1)
(Notes 1, 2)
Supply Voltage (VCC) (Note 3)
Voltage at Any Pin
TMIN≤TA≤TMAX
Temperature Range
If Military/Aerospace specified devices are required,
please contact the National Semiconductor Sales Office/
Distributors for availability and specifications.
−40°C≤TA≤+85°C
4.5 VDC to 6.0 VDC
Range of VCC
6.5V
−0.3V to (VCC
+0.3V)
Except Control Inputs
Voltage at Control Inputs
−0.3V to +15V
(START, OE, CLOCK, ALE, ADD A, ADD B, ADD C)
Storage Temperature Range
−65°C to +150°C
Package Dissipation at TA=25°C
875 mW
Lead Temp. (Soldering, 10 seconds)
Dual-In-Line Package (plastic)
260°C
Molded Chip Carrier Package
Vapor Phase (60 seconds)
215°C
Infrared (15 seconds)
220°C
ESD Susceptibility (Note 8)
400V
Electrical Characteristics – Converter Specifications
Converter Specifications: VCC=5 VDC=VREF+, VREF(−)=GND, TMIN≤TA≤TMAX and fCLK=640 kHz unless otherwise stated.
Symbol
Parameter
ADC0808
Total Unadjusted Error
(Note 5)
ADC0809
Total Unadjusted Error
(Note 5)
VREF(+)
Conditions
Min
Max
Units
25°C
±½
LSB
TMIN to TMAX
±¾
LSB
0°C to 70°C
TMIN to TMAX
±1
±1¼
LSB
LSB
VCC + 0.1
VDC
VCC
VCC + 0.1
V
(VCC/2) − 0.1
VCC/2
(VCC/2) + 0.1
V
Input Resistance
From Ref(+) to Ref(−)
1.0
Analog Input Voltage Range
(Note 4) V(+) or V(−)
GND − 0.1
Voltage, Top of Ladder
Measured at Ref(+)
Voltage, Center of Ladder
Typ
2.5
VREF(−)
Voltage, Bottom of Ladder
Measured at Ref(−)
−0.1
0
IIN
Comparator Input Current
fc=640 kHz, (Note 6)
−2
±0.5
kΩ
V
μA
2
Electrical Characteristics – Digital Levels and DC Specifications
Digital Levels and DC Specifications: ADC0808CCN, ADC0808CCV, ADC0809CCN and ADC0809CCV, 4.75≤VCC≤5.25V,
−40°C≤TA≤+85°C unless otherwise noted
Symbol
Parameter
Conditions
Min
Typ
Max
Units
10
200
nA
1.0
μA
ANALOG MULTIPLEXER
VCC=5V, VIN=5V,
IOFF(+)
OFF Channel Leakage Current
TA=25°C
TMIN to TMAX
VCC=5V, VIN=0,
IOFF(−)
OFF Channel Leakage Current
TA=25°C
−200
TMIN to TMAX
−1.0
−10
nA
μA
CONTROL INPUTS
VIN(1)
Logical “1” Input Voltage
VIN(0)
Logical “0” Input Voltage
(VCC − 1.5)
V
1.5
3
V
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ADC0808/ADC0809
Absolute Maximum Ratings
ADC0808/ADC0809
Symbol
Parameter
Conditions
IIN(1)
Logical “1” Input Current (The Control
VIN=15V
Inputs)
IIN(0)
Logical “0” Input Current (The Control
VIN=0
Inputs)
ICC
Supply Current
Min
Typ
Max
Units
1.0
μA
μA
−1.0
fCLK=640 kHz
0.3
3.0
mA
DATA OUTPUTS AND EOC (INTERRUPT)
VOUT(1)
Logical “1” Output Voltage
VCC = 4.75V
IOUT = −360µA
IOUT = −10µA
VOUT(0)
Logical “0” Output Voltage
IO=1.6 mA
0.45
V
VOUT(0)
Logical “0” Output Voltage EOC
IO=1.2 mA
0.45
V
3
μA
IOUT
TRI-STATE Output Current
V
V
2.4
4.5
VO=5V
VO=0
μA
−3
Electrical Characteristics – Timing Specifications
Timing Specifications VCC=VREF(+)=5V, VREF(−)=GND, tr=tf=20 ns and TA=25°C unless otherwise noted.
Symbol
Parameter
Conditions
Max
Units
900
ns
100
200
ns
(Figure 5)
100
200
ns
(Figure 5)
25
50
ns
(Figure 5)
25
50
ns
tSTCLK
Start Time Delay from Clock
(Figure 5)
tWS
Minimum Start Pulse Width
(Figure 5)
tWALE
Minimum ALE Pulse Width
ts
Minimum Address Set-Up Time
tH
Minimum Address Hold Time
tD
Analog MUX Delay Time From ALE RS=0Ω (Figure 5)
tH1, tH0
OE Control to Q Logic State
CL=50 pF, RL=10k (Figure 8)
t1H, t0H
OE Control to Hi-Z
CL=10 pF, RL=10k (Figure 8)
tc
Conversion Time
fc=640 kHz, (Figure 5) (Note 7)
fc
Clock Frequency
MIn
Typ
300
1
2.5
μs
125
250
ns
125
250
ns
90
100
116
μs
10
640
1280
kHz
8 + 2 μS
Clock
Periods
tEOC
EOC Delay Time
(Figure 5)
CIN
Input Capacitance
At Control Inputs
10
15
pF
COUT
TRI-STATE Output Capacitance
At TRI-STATE Outputs
10
15
pF
0
Note 1: Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications do not apply when operating
the device beyond its specified operating conditions.
Note 2: All voltages are measured with respect to GND, unless otherwise specified.
Note 3: A Zener diode exists, internally, from VCC to GND and has a typical breakdown voltage of 7 VDC.
Note 4: Two on-chip diodes are tied to each analog input which will forward conduct for analog input voltages one diode drop below ground or one diode drop
greater than the VCCn supply. The spec allows 100 mV forward bias of either diode. This means that as long as the analog VIN does not exceed the supply voltage
by more than 100 mV, the output code will be correct. To achieve an absolute 0VDC to 5VDC input voltage range will therefore require a minimum supply voltage
of 4.900 VDC over temperature variations, initial tolerance and loading.
Note 5: Total unadjusted error includes offset, full-scale, linearity, and multiplexer errors. See Figure 3. None of these A/Ds requires a zero or full-scale adjust.
However, if an all zero code is desired for an analog input other than 0.0V, or if a narrow full-scale span exists (for example: 0.5V to 4.5V full-scale) the reference
voltages can be adjusted to achieve this. See Figure 13.
Note 6: Comparator input current is a bias current into or out of the chopper stabilized comparator. The bias current varies directly with clock frequency and has
little temperature dependence (Figure 6). See paragraph 4.0.
Note 7: The outputs of the data register are updated one clock cycle before the rising edge of EOC.
Note 8: Human body model, 100 pF discharged through a 1.5 kΩ resistor.
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4
MULTIPLEXER
The device contains an 8-channel single-ended analog signal
multiplexer. A particular input channel is selected by using the
address decoder. Table 1 shows the input states for the address lines to select any channel. The address is latched into
the decoder on the low-to-high transition of the address latch
enable signal.
TABLE 1. Analog Channel Selection
ADDRESS LINE
SELECTED ANALOG
CHANNEL
C
B
A
IN0
IN1
IN2
IN3
IN4
IN5
IN6
IN7
L
L
L
L
H
H
H
H
L
L
H
H
L
L
H
H
L
H
L
H
L
H
L
H
CONVERTER CHARACTERISTICS
The Converter
The heart of this single chip data acquisition system is its 8bit analog-to-digital converter. The converter is designed to
give fast, accurate, and repeatable conversions over a wide
range of temperatures. The converter is partitioned into 3 major sections: the 256R ladder network, the successive approximation register, and the comparator. The converter's
digital outputs are positive true.
The 256R ladder network approach (Figure 1) was chosen
over the conventional R/2R ladder because of its inherent
monotonicity, which guarantees no missing digital codes.
Monotonicity is particularly important in closed loop feedback
control systems. A non-monotonic relationship can cause oscillations that will be catastrophic for the system. Additionally,
the 256R network does not cause load variations on the reference voltage.
5
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ADC0808/ADC0809
The bottom resistor and the top resistor of the ladder network
in Figure 1 are not the same value as the remainder of the
network. The difference in these resistors causes the output
characteristic to be symmetrical with the zero and full-scale
points of the transfer curve. The first output transition occurs
when the analog signal has reached +½ LSB and succeeding
output transitions occur every 1 LSB later up to full-scale.
The successive approximation register (SAR) performs 8 iterations to approximate the input voltage. For any SAR type
converter, n-iterations are required for an n-bit converter. Figure 2 shows a typical example of a 3-bit converter. In the
ADC0808, ADC0809, the approximation technique is extended to 8 bits using the 256R network.
The A/D converter's successive approximation register (SAR)
is reset on the positive edge of the start conversion start pulse.
The conversion is begun on the falling edge of the start conversion pulse. A conversion in process will be interrupted by
receipt of a new start conversion pulse. Continuous conversion may be accomplished by tying the end-of-conversion
(EOC) output to the SC input. If used in this mode, an external
start conversion pulse should be applied after power up. Endof-conversion will go low between 0 and 8 clock pulses after
the rising edge of start conversion.
The most important section of the A/D converter is the comparator. It is this section which is responsible for the ultimate
accuracy of the entire converter. It is also the comparator drift
which has the greatest influence on the repeatability of the
device. A chopper-stabilized comparator provides the most
effective method of satisfying all the converter requirements.
The chopper-stabilized comparator converts the DC input signal into an AC signal. This signal is then fed through a high
gain AC amplifier and has the DC level restored. This technique limits the drift component of the amplifier since the drift
is a DC component which is not passed by the AC amplifier.
This makes the entire A/D converter extremely insensitive to
temperature, long term drift and input offset errors.
Figure 4 shows a typical error curve for the ADC0808 as
measured using the procedures outlined in AN-179.
Functional Description
ADC0808/ADC0809
567202
FIGURE 1. Resistor Ladder and Switch Tree
567213
567214
FIGURE 2. 3-Bit A/D Transfer Curve
FIGURE 3. 3-Bit A/D Absolute Accuracy Curve
567215
FIGURE 4. Typical Error Curve
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6
ADC0808/ADC0809
Timing Diagram
567204
FIGURE 5.
7
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ADC0808/ADC0809
Typical Performance Characteristics
567216
FIGURE 6. Comparator IIN vs. VIN
(VCC=VREF=5V)
567217
FIGURE 7. Multiplexer RON vs. VIN
(VCC=VREF=5V)
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8
ADC0808/ADC0809
TRI-STATE Test Circuits and Timing Diagrams
t1H, tH1
t0H, tH0
567218
567221
t1H, CL = 10 pF
t0H, CL = 10 pF
567222
567219
tH0, CL = 50 pF
tH1, CL = 50 pF
567223
567220
FIGURE 8. TRI-STATE Test Circuits and Timing Diagrams
proportion of full-scale, reference requirements are greatly
reduced, eliminating a large source of error and cost for many
applications. A major advantage of the ADC0808, ADC0809
is that the input voltage range is equal to the supply range so
the transducers can be connected directly across the supply
and their outputs connected directly into the multiplexer inputs, (Figure 9).
Ratiometric transducers such as potentiometers, strain
gauges, thermistor bridges, pressure transducers, etc., are
suitable for measuring proportional relationships; however,
many types of measurements must be referred to an absolute
standard such as voltage or current. This means a system
reference must be used which relates the full-scale voltage to
the standard volt. For example, if VCC=VREF=5.12V, then the
full-scale range is divided into 256 standard steps. The smallest standard step is 1 LSB which is then 20 mV.
Applications Information
OPERATION
1.0 RATIOMETRIC CONVERSION
The ADC0808, ADC0809 is designed as a complete Data
Acquisition System (DAS) for ratiometric conversion systems.
In ratiometric systems, the physical variable being measured
is expressed as a percentage of full-scale which is not necessarily related to an absolute standard. The voltage input to
the ADC0808 is expressed by the equation
(1)
VIN= Input voltage into the ADC0808
Vfs= Full-scale voltage
VZ= Zero voltage
DX= Data point being measured
DMAX= Maximum data limit
DMIN= Minimum data limit
A good example of a ratiometric transducer is a potentiometer
used as a position sensor. The position of the wiper is directly
proportional to the output voltage which is a ratio of the fullscale voltage across it. Since the data is represented as a
2.0 RESISTOR LADDER LIMITATIONS
The voltages from the resistor ladder are compared to the
selected into 8 times in a conversion. These voltages are
coupled to the comparator via an analog switch tree which is
referenced to the supply. The voltages at the top, center and
bottom of the ladder must be controlled to maintain proper
operation.
The top of the ladder, Ref(+), should not be more positive than
the supply, and the bottom of the ladder, Ref(−), should not
be more negative than ground. The center of the ladder volt9
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ADC0808/ADC0809
age must also be near the center of the supply because the
analog switch tree changes from N-channel switches to Pchannel switches. These limitations are automatically satisfied in ratiometric systems and can be easily met in ground
referenced systems.
Figure 10 shows a ground referenced system with a separate
supply and reference. In this system, the supply must be
trimmed to match the reference voltage. For instance, if a
5.12V is used, the supply should be adjusted to the same
voltage within 0.1V.
567207
FIGURE 9. Ratiometric Conversion System
The ADC0808 needs less than a milliamp of supply current
so developing the supply from the reference is readily accomplished. In Figure 11 a ground referenced system is
shown which generates the supply from the reference. The
buffer shown can be an op amp of sufficient drive to supply
the milliamp of supply current and the desired bus drive, or if
a capacitive bus is driven by the outputs a large capacitor will
supply the transient supply current as seen in Figure 12. The
LM301 is overcompensated to insure stability when loaded by
the 10 μF output capacitor.
The top and bottom ladder voltages cannot exceed VCC and
ground, respectively, but they can be symmetrically less than
VCC and greater than ground. The center of the ladder voltage
should always be near the center of the supply. The sensitivity
of the converter can be increased, (i.e., size of the LSB steps
decreased) by using a symmetrical reference system. In Figure 13, a 2.5V reference is symmetrically centered about
VCC/2 since the same current flows in identical resistors. This
system with a 2.5V reference allows the LSB bit to be half the
size of a 5V reference system.
567224
FIGURE 10. Ground Referenced
Conversion System Using Trimmed Supply
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10
ADC0808/ADC0809
567225
FIGURE 11. Ground Referenced Conversion System with
Reference Generating VCC Supply
567226
FIGURE 12. Typical Reference and Supply Circuit
11
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ADC0808/ADC0809
567227
RA=RB
*Ratiometric transducers
FIGURE 13. Symmetrically Centered Reference
VREF(+)÷512)
3.0 CONVERTER EQUATIONS
The transition between adjacent codes N and N+1 is given
by:
4.0 ANALOG COMPARATOR INPUTS
The dynamic comparator input current is caused by the periodic switching of on-chip stray capacitances. These are connected alternately to the output of the resistor ladder/switch
tree network and to the comparator input as part of the operation of the chopper stabilized comparator.
The average value of the comparator input current varies directly with clock frequency and with VIN as shown in
Figure 6.
If no filter capacitors are used at the analog inputs and the
signal source impedances are low, the comparator input current should not introduce converter errors, as the transient
created by the capacitance discharge will die out before the
comparator output is strobed.
If input filter capacitors are desired for noise reduction and
signal conditioning they will tend to average out the dynamic
comparator input current. It will then take on the characteristics of a DC bias current whose effect can be predicted
conventionally.
(2)
The center of an output code N is given by:
(3)
The output code N for an arbitrary input are the integers within
the range:
(4)
Where:
VIN=Voltage at comparator input
VREF(+)=Voltage at Ref(+)
VREF(−)=Voltage at Ref(−)
VTUE=Total unadjusted error voltage (typically
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12
ADC0808/ADC0809
Typical Application
567210
*Address latches needed for 8085 and SC/MP interfacing the ADC0808 to a microprocessor
TABLE 2. Microprocessor Interface Table
PROCESSOR
8080
8085
Z-80
SC/MP
6800
READ
WRITE
MEMR
RD
RD
NRDS
MEMW
WR
WR
NWDS
VMA•φ2•R/W
VMA•φ•R/W
13
INTERRUPT (COMMENT)
INTR (Thru RST Circuit)
INTR (Thru RST Circuit)
INT (Thru RST Circuit, Mode 0)
SA (Thru Sense A)
IRQA or IRQB (Thru PIA)
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ADC0808/ADC0809
Physical Dimensions inches (millimeters) unless otherwise noted
Molded Dual-In-Line Package (N)
Order Number ADC0808CCN or ADC0809CCN
NS Package Number NA28E
Molded Chip Carrier (V)
Order Number ADC0808CCV or ADC0809CCV
NS Package Number V28A
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14
ADC0808/ADC0809
15
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ADC0808/ADC0809 8-Bit μP Compatible A/D Converters with 8-Channel Multiplexer
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Following are URLs where you can obtain information on other Texas Instruments products and application solutions:
Products
Applications
Audio
www.ti.com/audio
Communications and Telecom www.ti.com/communications
Amplifiers
amplifier.ti.com
Computers and Peripherals
www.ti.com/computers
Data Converters
dataconverter.ti.com
Consumer Electronics
www.ti.com/consumer-apps
DLP® Products
www.dlp.com
Energy and Lighting
www.ti.com/energy
DSP
dsp.ti.com
Industrial
www.ti.com/industrial
Clocks and Timers
www.ti.com/clocks
Medical
www.ti.com/medical
Interface
interface.ti.com
Security
www.ti.com/security
Logic
logic.ti.com
Space, Avionics and Defense
www.ti.com/space-avionics-defense
Power Mgmt
power.ti.com
Transportation and Automotive www.ti.com/automotive
Microcontrollers
microcontroller.ti.com
Video and Imaging
RFID
www.ti-rfid.com
OMAP Mobile Processors
www.ti.com/omap
Wireless Connectivity
www.ti.com/wirelessconnectivity
TI E2E Community Home Page
www.ti.com/video
e2e.ti.com
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