ANADIGICS ACD2206 Catv/tv/video downconverter with dual synthesizer Datasheet

ACD2206
CATV/TV/Video Downconverter
with Dual Synthesizer
PRELIMINARY DATA SHEET - Rev 1.0
FEATURES
•
•
•
•
•
•
•
•
•
•
Integrated Downconverter
Integrated Dual Synthesizer
256 QAM Compatibility
Single +5 V Power Supply Operation
Low Noise Figure: 8 dB
High Conversion Gain: 31 dB
Low Distortion: -53 dBc
Three-Wire Interface
Small Size
-40 °C to +85 °C
APPLICATIONS
•
•
•
•
•
Set Top Boxes
CATV Video Tuners
Digital TV Tuners
CATV Data Tuners
Cable Modems
S8 Package
28 Pin SSOP
PRODUCT DESCRIPTION
The ACD2206 uses both GaAs and Si technology
to provide the downconverter and dual synthesizer
functions in a double conversion tuner gain block,
local oscillator, balanced mixer, IF Amplifier, and
dual synthesizer. The specifications meet the
requirements of CATV/TV/Video and Cable Modem
Data applications. The ACD2206 is supplied in a 28
lead SSOP package and requires a single +5 V
supply voltage. The IC is well suited for applications
where small size, low cost, low auxiliary parts count,
and no-compromise performance is important. It
provides for cost reduction by lowering the
component and packaged IC count and decreasing
the amount of labor-intensive production alignment
steps, while significantly improving performance
and reliability.
RFD
VIF+IFOUT-
RFIN+
RFINLow Noise
VGA
VIF+IFOUT+
18 Bit RF2
N Counter
RF2
Phase
Detector
RF2
Charge
Pump
CPD
RF1
Phase
Detector
RF1
Charge
Pump
CPU
15 Bit RF2
R Counter
REFIN
REFOUT
Oscillator
Mixer
15 Bit RF1
R Counter
RFU
Phase Splitter
TCKT
RF2: 64/65
Prescaler
OSC OUT
Clock
Data
Enable
RF1: 64/65
Prescaler
18 Bit RF1
N Counter
22 Bit
Data Registar
Figure 2: Dual Synthesizer Block Diagram
Figure 1: Downconverter Block Diagram
10/2003
ACD2206
1
RFIN+
VIF + IFOUT+
28
2
RFIN-
VIF + IFOUT-
27
3
GND
GND
26
4
ISET
VSUP
25
5
TCKT
OSCOUT
24
6
OSCGND
GND
23
7
OSCGND
GND
22
8
VSS
VSS
21
9
VSS
VSS
20
10
EN
RFD
19
11
DATA
CPD
18
12
CLK
CPU
17
13
REFIN
RFU
16
14
REFOUT
VSYN
15
Figure 3: Pinout
2
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
ACD2206
Table 1: Pin Description
P IN
N AM E
1
RFIN+
2
D E S C R IP T ION
P IN
N AM E
Downconverter
Di fferenti al RFInput
28
VIF+IFOUT+
RFIN-
Downconverter
Di fferenti al RFInput
27
3
GND
Downconverter Ground
(Must be connected)
26
GND
Downconverter Ground
(Must be connected)
4
ISET
Downconverter Gi lbert
Cell Current Source
Resi stor
25
VSUP
Downconverter Supply
(+VDD)
5
TCKT
Osci llator Input Port
(Tank ci rcui t connecti on)
24
OSCOUT
Osci llator Output
(Connected to
Synthesi zer RF Input)
6
OSCGND
Osci llator Tank Ci rcui t
Ground (Not to be
connected to any other
ci rcui t ground)
23
GND
Downconverter Ground
(Must be connected)
7
OSCGND
Same as Pi n 6
22
GND
Downconverter Ground
(Must be connected)
8
V SS
Synthesi zer Ground
(Requi red)
21
V SS
Synthesi zer Ground
(Requi red)
9
V SS
Synthesi zer Ground
(Requi red)
20
V SS
Synthesi zer Ground
(Requi red)
10
EN
3-Wi re Interface Enable
19
RFD
Synthesi zer
Downconverter RFInput
11
DATA
3-Wi re Interface Data
18
CPD
Synthesi zer
Downconverter
Charge Pump Output
12
CLK
3-Wi re Interface Clock
17
CPU
Synthesi zer Upconverter
Charge Pump Output
13
REFIN
Crystal Reference Input
16
RFU
Synthesi zer Upconverter
RFInput
14
REFOUT
Crystal Reference Output
15
VSYN
Synthesi zer Supply
(+VDD)
VIF+IFOUT -
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
D E S C R IP T ION
Di fferenti al IF Ampli fi er
Output, Inducti vely
coupled to +VDD
Di fferenti al IF Ampli fi er
Output, Inducti vely
coupled to +VDD
3
ACD2206
ELECTRICAL CHARACTERISTICS
Table 2: Absolute Minimum and Maximum Ratings
PARAMETER
MIN
MAX
UNIT
Supply Voltage (pins 25, 27 & 28)
(pin 15)
-
+9
+6.5
VDC
Voltage on pins 10 through 14, 16
through 19 with VSS = 0 V
-0.3
VSYN +0.3
VDC
Input Voltages (pins 1, 2 & 5)
-
0
VDC
Input Power (pins 1 & 2)
(pin 5)
(pins 13, 16 & 19)
-
+10
+17
+20
dBm
-55
+150
°C
Soldering Temperature
-
260
°C
Soldering Time
-
4
Sec
Thermal Impedance, θJC
-
40
°C/W
Storage Temperature
Stresses in excess of the absolute ratings may cause permanent damage.
Functional operation is not implied under these conditions. Exposure to absolute
ratings for extended periods of time may adversely affect reliability.
Table 3: Operating Ranges
PAR AME T E R
Downconverter Frequenci es
RF Input (RF)
IF Output (IF)
Local Osci llator (LO)
MIN
T YP
M AX
U N IT
900
35
865
-
1200
150
1350
MHz
400
400
2
-
4
-
2100
1400
20
10
MHz
+4.75
+5
+5.25
VDC
-40
-
+85
°C
(1)
Synthesi zer Frequenci es
Upconverter Synthesi zer (RFU)
Downconverter Synthesi zer (RFD)
Reference Osci llator (REFIN)
Phase Detector
Supply Voltage: VDD (pi ns 15, 25, 27, 28)
Ambi ent Operati ng Temperature: TA
The device may be operated safely over these conditions; however, parametric
performance is guaranteed only over the conditions defined in the electrical
specifications.
Notes:
(1) Mixer operation is possible beyond these frequencies with slightly reduced
performance.
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PRELIMINARY DATA SHEET - Rev 1.0
10/2003
ACD2206
Table 4: Electrical Specifications - Downconverter Section
(TA = 25 ×C, VDD = +5 VDC, RFIN = 1087 MHz, IFOUT = 45 MHz)
PAR AME T E R
MIN
T YP
M AX
U N IT
28
31
-
dB
-
8
10
dB
Cross Modulati on (1), (2), (4)
-
-59
-
dBc
3rd Order Intermodulati on Di storti on
(IMD3) (1), (3), (4)
-
-
-53
dBc
-10
-
-
dBm
LO Phase Noi se (@ 10 KHz Offset) (1)
-
-90
-85.5
dBc/Hz
LO Output Power (pi n 24)
-
-5
-
dBm
Spuri ous @ IF Output
LO Si gnals and Harmoni cs
Beats Wi thi n Output Channel
Other Beats from 2 to 200 MHz
Other Spuri ous
-
-10
-70
-50
-10
-
dBm
dBc
dBm
dBm
IF Supply Current (pi n 27 & 28) (1), (4)
-
110
-
mA
Osc, Phase Spli tter and Mi xer Supply
Current (pi n 25)
-
70
-
mA
Power Consumpti on
-
900
-
mW
Conversi on Gai n (1)
SSB Noi se Fi gure
(1)
2-Tone 3rd Order Input Intercept Poi nt
(IIP3) (1), (3), (4)
(1)
Notes:
(1) As measured in ANADIGICS test fixture.
(2) Two tones: 1085 and 1091 MHz, -40 dBm each, 1091 MHz tone AM-modulated 99% at 15 kHz.
(3) Two tones: 1085 and 1091 MHz, -30 dBm each.
(4) R1 = 0 Ohms
Table 5: Electrical Specifications - Synthesizer Section
(TA = +25 ×C, VDD = +5 VDC)
PAR AME T E R
MIN
T YP
M AX
U N IT
Prescalar Input Sensi ti vi ty
Upconverter: RFU (pi n 16) (1)
Downconverter: RFD (pi n 19) (2)
-7
-13
-
+20
+20
dBm
-
0.5
-
Vp-p
-
1.25
-1.25
-
mA
Supply Current
-
35
50
mA
Power Consumpti on
-
165
250
mW
Reference Osci llator Sensi ti vi ty (pi n 13)
C OMME N T S
(over operating frequency)
Charge Pump Output Current (3)
SINK
SOURCE
Notes:
(1) Measured at 250 kHz comparison frequency.
(2) Measured at 62.5 kHz comparison frequency.
(3) CPU and CPD = Vcc/2.
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
5
ACD2206
Table 6: Digital Interface Specifications
(TA = 25 ×C, VDD = +5 VDC, ref. Figure 4)
DATA
P AR AM E T E R
MIN
TYP
M AX
U N IT
Logi c Hi gh Input: VH (pi ns 10, 11, 12)
2.0
-
-
V
Logi c Low Input: VL (pi ns 10, 11, 12)
-
-
0.8
V
Logi c Input Current Consumpti on
(pi ns 10, 11, 12)
-
-
0.01
mA
Data to Clock Set Up Ti me: tCS
50
-
-
ns
Data to Clock Hold Ti me: tCH
10
-
-
ns
Clock Pulse Wi dth Hi gh: tCWH
50
-
-
ns
Clock Pulse Wi dth Low: tCWL
50
-
-
ns
Clock to Load Enable Setup Ti me: tES
50
-
-
ns
Load Enable Pulse Wi dth: tEW
50
-
-
ns
Ri se Ti me: tR
-
10
-
ns
Fall Ti me: tF
-
10
-
ns
N20: MSB
(R20: MSB)
N19
N10
(R19)
R10
N9
C2
(R9)
(R8)
(C2)
C1: LSB
(C1: LSB)
CLOCK
tCWL
LE
OR
LE
t CS
t CH
t CWH
Figure 4: Serial Data Input Timing
6
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
t ES
t EW
ACD2206
PERFORMANCE DATA
Figure 5: Typical Upconverter Prescalar
Sensitivity vs. Supply Voltage
(TA = +25 °C, fLO1 = 2100 MHz)
Figure 6: Typical Upconverter Prescalar
Sensitivity vs. Local Oscillator Frequency
(TA = +25 °C, VDD = +5 V)
-5
Prescalar Sensitivity (dBm)
Prescalar Sensitivity (dBm)
-7.0
-7.5
-8.0
-8.5
-9.0
4.7
4.8
4.9
5.0
5.1
5.2
-10
-15
-20
-25
-30
-35
500
5.3
700
900
Supply Voltage (V)
1300
1500
1700
1900
2100
LO1 Frequency (MHz)
Figure 7: Typical Downconverter Prescalar
Sensitivity vs. Supply Voltage
(TA = +25 °C, fLO2 = 1000 MHz)
Figure 8: Typical Downconverter Prescalar
Sensitivity vs. Local Oscillator Frequency
(TA = +25 °C, VDD = +5 V)
-16.0
-12
Prescalar Sensitivity (dBm)
Prescalar Sensitivity (dBm)
1100
-16.5
-17.0
-17.5
-14
-16
-18
-20
-22
-18.0
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Supply Voltage (V)
-24
400
600
800
1000
1200
1400
LO2 Frequency (MHz)
Figure 9: Typical Local Oscillator
Output Power vs. Supply Voltage
(TA = +25 °C, fLO2 = 1042 MHz)
-4.5
Output Power (dBm)
-5.0
-5.5
-6.0
-6.5
-7.0
4.7
4.8
4.9
5.0
5.1
5.2
5.3
Supply Voltage (V)
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
7
ACD2206
LOGIC PROGRAMMING
Synthesizer Register Programming
The ACD2206 includes two PLL synthesizers. Each
synthesizer contains programmable Reference and
Main dividers, which allow a wide range of local
oscillator frequencies. The 22-bit registers that control
the dividers are programmed via a shared three-wire
bus, consisting of Data, Clock and Enable lines.
Table 7: Register Select Bits
SELEC T
B IT S
The data word for each register is entered serially
in order with the most significant bit (MSB) first and
the least significant bit (LSB) last. The rising edge
of the Clock pulse shifts each data value into the
register. The Enable line must be low for the duration
of the data entry, then set high to latch the data into
the register. (See Figure 4.)
S
1
0
0
Reference Divider Register for PLL2
0
1
Main Divider Register for PLL2
1
0
Reference Divider Register for PLL1
1
1
Mai n Di vi der Regi ster for PLL1
Table 8: Reference Divider Registers
MSB
21 20
19
18
17
16
15
P ro g ram Mo d e
D
5
S
2
Reference Divider Programming
The reference divider register for each synthesizer
consists of fifteen divider bits, five program mode
bits and the two register select bits, as shown in
Table 8. The fifteen divider bits allow a divide ratio
from 3 to 32767, inclusive, as shown in Table 9.
Register Select Bits
The two least significant bits of each register are
register select bits that determine which register is
programmed during a particular data entry cycle.
Table 7 indicates the register select bit settings used
to program each of the available registers.
22
D E S T IN AT ION R E GIS T E R F OR
S E R IAL D ATA
D
4
D
3
D
2
14
13
12
11
10
9
8
LSB
7
6
5
4
3
R eferen ce D ivid er D ivid e R atio , R
D
1
R
15
R
14
R
13
R
12
R R
11 10
R
9
R
8
R
7
R
6
R
5
2
1
S elect
R
4
R
3
R
2
R
1
S
2
Table 9: Reference Divider R Counter Bits
D IV ID E
R AT IO R
R
15
R
14
R
13
R
12
R
11
R
10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
3
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
32767
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
Notes:
Divide ratios less than 3 are prohibited.
8
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
S
1
ACD2206
Main Divider Programming
The main divider register for each synthesizer
consists of seven A counter bits, eleven B counter
bits, two program mode bits and the two register
select bits, as shown in Table 10. The main divider
divide ratio, N, is determined by the values in the A
and B counters. The eleven B Counter bits and
allowed values are shown in Table 11, and the seven
A Counter bits and allowed values are shown in
21
20
19
18
17
P ro g ram
Mo d e
C
2
Pulse Swallow Function
The VCO output frequency for the local oscillator is
computed using the following equation; the
variables are defined in Table 13:
fVCO = N x fOSC/R, where N = [(P x B) + A]
Table 10: Main Divider Registers
MSB
22
Table 12. Note that there are some limitations on
the ranges of the values for each counter.
C
1
16
15
14
13
12
11
10
LSB
9
8
7
B C o u n te r
B B
11 10
B
9
B
8
B
7
B
6
6
5
4
3
A C o u n te r
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
2
1
S elect
A
2
A
1
S
2
S
1
Table 11: Main Divider B Counter Bits
VAL U E OF B
C OU N T E R
B
11
B
10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
3
0
0
0
0
0
0
0
0
0
1
1
4
0
0
0
0
0
0
0
0
1
0
0
-
-
-
-
-
-
-
-
-
-
-
-
2047
1
1
1
1
1
1
1
1
1
1
1
Notes:
B > A, Divide ratios less than 3 are prohibited.
Table 13: Variable Definitions
Table 12: Main Divider A Counter Bits
VAL U E OF A
C OU N T E R
A
7
A
6
A
5
A
4
A
3
A
2
A
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
1
B
Divide ratio of B counter (3 to 2047)
-
-
-
-
-
-
-
-
A
Divide ratio of A counter (0 < A < P, A < B)
127
1
1
1
1
1
1
1
fOSC
Frequency of external reference crystal or
oscillator
Notes:
B > A, A < P
VAR
D EF IN IT ION
fVCO
Desired output frequency of external voltage
controlled oscillator (VCO)
R
Divide ratio of R counter (3 to 32767)
P
Preset modulus of prescalar (P = 64)
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
9
ACD2206
Programmable Modes
Each register contains bits set aside for programming
different modes of operation in the synthesizers.
Currently, the only programmable mode is the polarity
of the phase detector in each of the synthesizers. Bit
D1 in each reference divider register controls this
feature. Bits D2 through D5 in the reference divider
registers and bits C1 and C2 in the main divider
registers are reserved for future use, and have no
Table 14: Phase Detector Polarity Bit
S
2
S
1
D
1
0
0
PLL2 Phase Detector Polarity
1
0
PLL1 Phase Detector Polarity
current function. They can be set either high or low
without affecting synthesizer performance.
Setting Phase Detector Polarity
Table 14 shows how bit D1 of each reference divider
register controls the polarity of the phase detector
associated with each PLL. The correct setting is
determined by using Table 15 and Figure 10.
Figure 10: VCO Characteristics
(1)
Table 15: Phase Detector Polarity Selection
D
1
P H AS E
D E T E C T OR
P OL AR IT Y
VC O
C H AR AC T E R IS T IC S
(S E E F IGU R E 12)
0
Negati ve
curve (2)
1
Posi ti ve
curve (1)
VCO OUTPUT
FREQUENCY
(2)
VCO INPUT VOLTAGE
Synthesizer Programming Example
The following example for programming the two synthesizers in the ACD2206 details the calculations used to
determine the required value of each bit in all four registers:
Requirements
Desired CATV input channel: “HHH” - 499.25 MHz picture carrier (501 MHz digital channel center frequency)
(Second) IF picture carrier output frequency: 45.75 MHz (44 MHz digital channel center frequency)
First IF frequency: 1087.75 MHz
Phase detector comparison frequency for down converter (also tuning increment): 62.5 KHz
Phase detector comparison frequency for up converter: 250 KHz
Crystal reference oscillator frequency: 4 MHz
Calculation of Reference Divider Values
The value for each reference divider is calculated by dividing the reference oscillator frequency by the desired
phase detector comparison frequency:
R = fOSC / fPD
For the down converter, the 4 MHz crystal oscillator frequency and the 62.5 KHz phase detector comparison
frequency are used to yield RPLL2 = 4 MHz / 62.5 KHz = 64, and so the bit values for the down converter
R counter are RPLL2 = 000000001000000.
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PRELIMINARY DATA SHEET - Rev 1.0
10/2003
ACD2206
For the up converter, the 4 MHz crystal oscillator frequency and the 250 KHz phase detector comparison
frequency are used to yield RPLL1 = 4 MHz / 250 KHz = 16, and so the bit values for the up converter R counter
are RPLL1 = 000000000010000.
Calculation of Main Divider Values
The values for the A and B counters are determined by the desired VCO output frequency for the local
oscillator and the phase detector comparison frequency:
N = fVCO / f PD
B = trunc(N / P)
A = N - (B x P)
The down converter local oscillator frequency will be 1087.75 MHz - 45.75 MHz = 1042 MHz in this example.
The main divider ratio for the down converter, then, is NPLL2 = 1042 MHz / 62.5 KHz = 16672. Since P = 64 in the
ACD2206, BPLL2 = trunc(16672 / 64) = 260, and APLL2 = 16672 - (260 x 64) = 32. These results give bit values of
BPLL2 = 00100000100 and APLL2 = 0100000 for the B and A counters.
The up converter local oscillator frequency will be 499.25 MHz + 1087.75 MHz = 1587 MHz in this example.
Therefore, NPLL1 = 1587 MHz / 250 KHz = 6348, BPLL1 = trunc(6348 / 64) = 99, and APLL1 = 6348 - (99 x 64) = 12.
These results give bit values of BPLL1 = 00001100011 and APLL1 = 0001100 for the B and A counters.
Phase Detector Polarity
Assuming the VCO for the up converter has a negative slope, the phase detector polarity for PLL1 should be
negative, and D1PLL1 = 1. If the VCO for the down converter has a positive slope, the phase detector polarity for
PLL2 should be positive, and D1PLL2 = 0.
In summary, for this example, the four register programming words are shown in Tables 16 and 17:
Table 16: PLL1 and PLL2 Reference Divider Register Bits
for Synthesizer Programming Example
MSB
22
21
20
19
18
P ro g ram
Mo d e
17
16
15
14
13
12
11
10
9
Main D ivid er B C o u n ter
8
7
6
LSB
5
4
3
Main D ivid er A C o u n ter
2
1
S elect
C
2
C
1
B B
11 10
B
9
B
8
B
7
B
6
B
5
B
4
B
3
B
2
B
1
A
7
A
6
A
5
A
4
A
3
A
2
A
1
S
2
S
1
0
0
0
0
1
0
0
0
0
0
1
0
0
0
1
0
0
0
0
0
0
1
0
0
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
1
0
0
1
1
Table 17: PLL1 and PLL2 Main Divider Register Bits
for Synthesizer Programming Example
MSB
22
21 20
19
18
17
16
15
14
P ro g ram Mo d e
13
12
11
10
9
8
7
6
LSB
5
4
3
R eferen ce D ivid er R C o u n ter
2
1
S elect
D
5
D
4
D
3
D
2
D
1
R
15
R
14
R
13
R
12
R R
11 10
R
9
R
8
R
7
R
6
R
5
R
4
R
3
R
2
R
1
S
2
S
1
0
0
0
0
1
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
1
0
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
11
ACD2206
APPLICATION INFORMATION
Figure 11: PC Board Layout Top View
Figure 12: PC Board Layout Mid View
RF
RF
AFC
Out
ACD 220 6
4M Hz Xtal
J1
1
LO
In
Figure 13: PC Board Layout Bottom View
Figure 14: Evaluation Fixture
Table 18: J1 Header Pinout
Table 19: Fixture Pinout
F U N C T ION
PIN
FUNCTION
1
Clock
RF
Downconverter RF Input
2
Data
RF
Downconverter RF Input
3
Ground
IF
IF Output (Single Ended)
4
Enable
AFC Out
To Oscillator Tuning Circuit
5
+5 VDC
LO In
6
+30 VDC
P IN
12
IF
Balun
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
Synthesizer RFU Input
1
2
3
4
5
6
J1
C4
+30V
C5
R5
C6
R2
+5V
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
C7
R6
R3
C8
X1
R7
R4
L1
D1
RF
RF
R1
C1
C3
C2
+5V
14
13
12
11
10
9
8
7
6
5
4
3
2
1
C12
REFOUT
REFIN
CLK
DATA
EN
VSS
VSS
OSCGND
OSCGND
TCKT
ISET
GND
RFIN-
RFIN+
R8
C11
ACD2206
VSUP
C10
VSYN
RFU
CPU
CPD
RFD
VSS
VSS
GND
GND
OSC OUT
L2
27
28
C9
15
16
17
18
19
20
21
22
23
24
25
GND 26
VIF + IFOUT-
VIF + IFOUT+
C24
L3
C21
DT1
C13
R9
C20
IF
C14
R10
R12
C17
C22
R11
C16
C23
C15
Q1
LOIN
AFCOUT
+5V
R13
C18
C19
+30V
ACD2206
Figure 15: Evaluation Fixture Schematic
13
ACD2206
Table 20: Evaluation Fixture Parts List
IT E M #
VAL U E
S IZE
D ESC R IPTION
P AR T #
QT Y
VE N D OR
C1, C2,
C20
100pF
0603
Chi p-capaci tor
GRM39COG101J50V
3
Murata
C3
9pF
0603
Chi p-capaci tor
GRM39COG090C50V
1
Murata
C7, C8
30pF
0603
Chi p-capaci tor
GRM39COG300J50V
2
Murata
C12
220uF
PCE2040CT-ND
1
DIGI-KEY
10V VA Capaci tor
Seri es
C9, C11,
C14, C21,
C22
.1uF
0603
Chi p-capaci tor
GRM39Y5V104Z16V
5
Murata
C10, C23
1000pF
0603
Chi p-capaci tor
GRM39X7R102K50V
2
Murata
C15, C17
4700pF
0603
Chi p-capaci tor
GRM39X7R472K25V
2
Murata
C16
1uF
0603
Radi al-lead
Chi p-capaci tor
RPE113-X7R-105-K-050
1
Murata
C18
.01uF
0603
Chi p-capaci tor
GRM39X7R103K25V
1
Murata
C19
10uF
35 V
TANT
TE Seri es Cap. PCS6106CT-ND
1
DIGI-KEY
C24
15pF
0603
Chi p-capaci tor
GRM39COG150J50V
1
Murata
C13
5600pF
0603
Chi p-capaci tor
GRM39X7R562K50V
1
Murata
33pF
0603
Chi p-capaci tor
GRM39COG330J50V
3
Murata
R8
51
0603
Chi p Resi stor
ERJ-3GSYJ510
1
Panasoni c
R5
10K
0603
Chi p Resi stor
ERJ-3GSYJ103
1
Panasoni c
R2, R3, R4
2K
0603
Chi p Resi stor
ERJ-3GSYJ202
3
Panasoni c
R12
1K
0603
Chi p Resi stor
ERJ-3GSYJ102
1
Panasoni c
R11
2.7K
0603
Chi p Resi stor
ERJ-3GSYJ272
1
Panasoni c
R7
3K
0603
Chi p Resi stor
ERJ-3GSYJ302
1
Panasoni c
R13
22K
0603
Chi p Resi stor
ERJ-3GSYJ223
1
Panasoni c
R10
8.2K
0603
Chi p Resi stor
ERJ-3GSYJ822
1
Panasoni c
C4, C5,
C6
14
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
ACD2206
Table 20: Evaluation Fixture Parts List continued
IT E M #
VAL U E
S IZE
D ESC R IPTION
P AR T #
QT Y
VE N D OR
0
0603
Chi p Resi stor
ZC0603
3
RCD
L1
5.6nH
0805
Inductor
0805CS-050X-BC
1
Coi lcraft
L2
68nH
0805
Inductor
0805CS-680X-BC
1
Coi lcraft
L3
270nH
0805
Inductor
0805CS-271X-BC
1
Coi lcraft
D1
1SV245
Varactor di ode
1SV245
1
Toshi ba
DT1
4:1
Transformer
ETC4-1-2
1
M/A-COM, Inc.
North Ameri ca
Q1
30V
SMD
Transi stor NPN
Darl.
FMMTA13CT-ND
1
DIGI-KEY
X1
4MHZ
Crystal
SE2618CT-ND
1
DIGI-KEY
R1, R6, R9
SOT-23
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
15
ACD2206
PACKAGE OUTLINE
Figure 16: S8 Package Outline - 28 Pin SSOP
16
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
ACD2206
NOTES
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
17
ACD2206
NOTES
18
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
ACD2206
NOTES
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
19
ACD2206
ORDERING INFORMATION
OR D E R N U MB E R
TE MP E R AT U R E
R AN GE
P AC K AGE
D E S C R IP T ION
ACD2206S8P1
-40 °C to +85 °C
28 Pin SSOP
Tape & Reel, 3500 pieces per reel
ACD2206S8P0
-40 °C to +85 °C
28 Pin SSOP
Tubes, 50 pieces per tube
ACD2206S8GP1
-40 °C to +85 °C
Lead-Free
28 Pin SSOP
Tape & Reel, 3500 pieces per reel
ACD2206S8GP0
-40 °C to +85 °C
Lead-Free
28 Pin SSOP
Tubes, 50 pieces per tube
C OMP ON E N T P AC K AGIN G
ANADIGICS, Inc.
141 Mount Bethel Road
Warren, New Jersey 07059, U.S.A
Tel: +1 (908) 668-5000
Fax: +1 (908) 668-5132
URL: http://www.anadigics.com
E-mail: [email protected]
IMPORTANT NOTICE
ANADIGICS, Inc. reserves the right to make changes to its products or to discontinue any product at any time without notice. The
product specifications contained in Advanced Product Information sheets and Preliminary Data Sheets are subject to change
prior to a product’s formal introduction. Information in Data Sheets have been carefully checked and are assumed to be reliable;
however, ANADIGICS assumes no responsibilities for inaccuracies. ANADIGICS strongly urges customers to verify that the
information they are using is current before placing orders.
WARNING
ANADIGICS products are not intended for use in life support appliances, devices, or systems. Use of an ANADIGICS
product in any such application without written consent is prohibited.
20
PRELIMINARY DATA SHEET - Rev 1.0
10/2003
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