ON NCP6868PFCCT1G 2.5 a boost regulator with bypass function Datasheet

NCP6868
Product Preview
2.5 A Boost Regulator
with Bypass Function
The NCP6868 is a synchronous boost converter. It is designed
primarily to boost new generation low-voltage Li-Ion batteries (silicon
anode-like) embedded into cell and smart phones. The objective is to
guarantee a minimum output voltage even in the case for which the
battery voltage is below the minimum voltage required by the system.
The device features a Bypass mode coupled with a Boost mode. It is
capable to drive a continuous load up to 2.5 A and it operates at
a switching frequency of 2.5 MHz. An I2C serial control can also be
enabled for configuring the output voltage and peak current limit. The
NCP6868 is available in a space saving, low profile 1.8 × 1.8 mm
CSP-16 package.
Features
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
2.35 V to 5.5 V Input Voltage
Fixed or Programmable VOUT: from 2.85 V Up to 5.3 V
Bypass Operation when VIN is Above or Close to VOUT
Few External Components & 0.47 mH Inductor
High Efficiency Up to 98%
Output Current Up to 2.5 A Continuous
(VIN = 2.6 V, VOUT = 3.5 V) and up to 4 A Peak Current
Inductor Peak Current up to 9.0 A
Forced Bypass Option through BP Pin
Low Quiescent Current: 50 mA
Voltage Control Pin (VSEL) to Precisely Adjust VOUT
I2C Serial Control as a Software-Mode Option to Program Output
Voltage and Peak Current Limit
Soft-Start Function (SS) to Limit Inrush Current
Current Limitation to Protect Against Short Circuit
Thermal Limit Protection
Small 1.8 × 1.8 mm / 0.4 mm Pitch CSP Package
These Devices are Pb−Free and are RoHS Compliant
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WLCSP16
CASE 567JU
MARKING DIAGRAM
6868x
ALYYWW
G
6868x = Specific Device Code
x = P: NCP6868P
B: NCP6868V315
C: NCP6868V330
E: NCP6868E315
A
= Assembly Location
L
= Wafer Lot
YY
= Year
WW = Work Week
G
= Pb-Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 27 of
this data sheet.
Typical Applications
• Boost Converters for New Generation Low-Voltage Li-Ion
Batteries
• USB OTG (On-The-Go)
• 3G/4G – LTE RF PA
• Cell Phones, Smart Phones, Phablets, Tablets & Webtablets
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2015
August, 2015 − Rev. P4
1
Publication Order Number:
NCP6868/D
NCP6868
TYPICAL APPLICATION
Figure 1. Application Block Diagram
PIN OUT
A1
A2
A3
A4
EN
PG
PVIN
PVIN
B1
B2
B3
B4
VSEL
NC/SCL
VOUT
VOUT
C1
C2
C3
C4
BP
NC/SDA
SW
SW
D1
D2
D3
D4
AGND
PGND
PGND
PGND
Figure 2. Pin Out (Top View)
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1.80 mm
1.80 mm
NCP6868
Table 1. PIN FUNCTION DESCRIPTION
Pin
Name
Type
A1
EN
Input
A2
PG
Input/Output
Interrupt Output pin active Low (Open drain); PG is pulled low if a PG event is
detected that is output out of regulation, over-voltage, overload, UVLO or TWRN
protection is activated. PG is pulled-up High when EN is Low.
A3−A4
PVIN
Power Input
DCDC input power connected to a Li-Ion battery. This pin must be decoupled to
ground by a 10 mF and 1 mF ceramic capacitors. These capacitors should be placed
as close as possible to this pin.
B1
VSEL
Input
Output Voltage Select. This pin can be used to select the voltage when the device
operates in boost mode. VSEL = Low, Low voltage target selected; VSEL = High,
High voltage target selected. There is an internal pull-down resistor on this pin.
B2
MODE/SCL
Input
MODE: B2 pin is configured as a MODE pin when the I2C interface is disabled and
the device output voltage is fixed. When MODE = Low the device is operating in auto
mode. This pin must be set Low during device start-up. When MODE = High the
device is operating in forced CCM mode.
SCL: I2C interface Clock line when the I2C interface is enabled. There is an internal
pull down resistor on this pin.
C2
NC/SDA
Ground or
Input/Output
D1
AGND
Ground
B3−B4
VOUT
Power Output
C1
BP
Input
C3−C4
SW
Power
DC-DC Switch Power pin. This pin connects the power transistors to one end of the
inductor. Typical application (2.5 MHz) uses a 0.470 mH inductor; refer to application
section for more information.
D2−D4
PGND
Ground
Power Ground. This pin is the power ground and carries the high switching current.
High quality ground must be provided to prevent noise spikes.
To avoid high-density current flow in a limited PCB track, a local ground plane that
connects all PGND pins together is recommended. Analog and power grounds
should only be connected together in one location through a printed trace.
Description
Enable Control. Active high will enable the part. There is an internal pull down
resistor on this pin.
NC: For device without I2C interface activated, connect this pin to AGND.
SDA: Bidirectional data line of the I2C bus.
Analog Ground. Analog and digital circuit blocks’ ground. This pin must be connected
to the system ground.
Output voltage. Connect output capacitors as close as possible to the device.
Bypass pin. Active Low. This pin is used to force the device into the bypass mode.
In forced Bypass mode, both Bypass P-MOSFET and P-Channel MOSFET (see
Figure 1) are turned ON and N-Channel MOSFET (see Figure 1) is turned OFF.
There is an internal pull-up resistor on this pin.
Table 2. MODES OF OPERATION
EN
BP
Device State
0
X
All bias circuits are off and the device is in shutdown mode. During shutdown, current flow is
prevented from PVIN to VOUT and from SW to VOUT.
1
0
The device is active and forced in bypass mode. A short circuit protection is embedded in order to
prevent the output voltage going to low.
1
1
The device will switch between Boost mode and Bypass mode automatically.
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NCP6868
Table 3. MAXIMUM RATINGS
Rating
Symbol
Value
Unit
VA
−0.3 to +6.0
V
VOUT Pin
VOUT
−0.3 to +6.0
V
Digital pins: EN, VSEL, BP, MODE/SCL, SDA, PG:
Input Voltage
Input Current
VDG
IDG
−0.3 to VA + 0.3 ≤ 6.0
10
V
mA
Operating Ambient Temperature Range
TA
−40 to +85
°C
Operating Junction Temperature Range (Note 1)
TJ
−40 to +125
°C
Storage Temperature Range
TSTG
−65 to + 150
°C
Maximum Junction Temperature
TJMAX
−40 to +150
°C
Thermal Resistance Junction-to-Ambient (Note 2)
RΘJA
78
°C/W
ESD, Electrostatic Discharge Protection,
Human Body Model (Note 3)
Charged Device Model
HBM
CDM
2
1
Analog and Power Pins: PVIN, SW
kV
Latch Up Current: (Note 4)
Digital Pins
All Other Pins
ILU
mA
10
100
Moisture Sensitivity (Note 5)
MSL
Level 1
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
1. The thermal shutdown set to 150°C (typical) avoids potential irreversible damage on the device due to power dissipation.
2. The Junction-to-Ambient and Junction-to-Board thermal resistances are a function of Printed Circuit Board (PCB) layout and application.
These data are measured using 4-layer PCBs (2s2p). For a given ambient temperature TA it has to be pay attention to not exceed the max
junction temperature TJMAX.
3. This device series contains ESD protection and passes the following ratings:
Human Body Model (HBM) ±2.0 kV per JEDEC standard: JESD22−A114.
Machine Model (MM) ±150 V per JEDEC standard: JESD22−A115.
4. Latch up current per JEDEC standard: JESD78 class II.
5. Moisture Sensitivity Level (MSL): 1 per IPC/JEDEC standard: J−STD−020A.
Table 4. RECOMMENDED OPERATING CONDITIONS
Symbol
Min
Typ
Max
Unit
PVIN
Power Supply (Note 6)
Parameter
Conditions
2.35
−
5.5
V
VOUT
VOUT Range
2.85
−
5.3
V
VOUT
Fixed Output Voltage for Standard Versions
VSEL LOW
−
3.15
−
V
VSEL HIGH
−
3.35
−
V
VSEL LOW
−
3.30
−
V
VSEL HIGH
−
3.50
−
V
VSEL LOW
−
3.15
−
V
VSEL HIGH
−
3.60
−
V
VSEL LOW
−
P*
−
V
VSEL HIGH
−
P*
−
V
0
−
2.5
A
Other Output Voltages in the Range 3 V to
5.3 V are Available by Request.
NCP6868V315
NCP6868V330
NCP6868E315
NCP6868P
IOUT
For VOUT ≤ 3.5 V and PVIN ≥ 2.5 V
Continuous Output Current
ILoadStartMax
Maximum Load Current during Start-up
500
L
Inductor for DCDC Converter (Note 7)
−
mA
0.47
−
mH
Co
Output Capacitor for DCDC Converter (Note 7)
15
20
56
mF
Cin
Input Capacitor for DCDC Converter (Note 7)
3.3
4.7
−
mF
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond
the Recommended Operating Ranges limits may affect device reliability.
* P = Programmable.
6. Operation above 5.5 V input voltage for extended period may affect device reliability.
7. Including de-ratings (refer to application information section of this document for further details)
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NCP6868
ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = 2.35 V to VOUT (Unless otherwise noted). Typical values
are referenced to PVIN = 3.0 V, TA = +25°C and default configuration (Figure 1) (Note 8)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
SUPPLY CURRENT: PIN PVIN
IQBP
Operating Quiescent Current,
Bypass Mode (Auto)
VOUT = 3.5 V, PVIN = 3.7 V
−
30
50
mA
IQBoost
Operating Quiescent Current,
Boost Mode
VOUT = 3.5 V, PVIN = 3.2 V
−
55
70
mA
Shutdown Current
EN = Low, PVIN = 3.0 V
−
1
5
mA
Forced Bypass Mode
VOUT = 3.5 V, PVIN = 3.5 V
Low IQ
−
3
8
mA
VOUT = 3.5 V, PVIN = 3.5 V
OCP ON
−
25
40
mA
2.35
−
5.5
V
ISD
IQBPForced
DCDC CONVERTER
PVIN
VOUT_ACC
Input Voltage Range
Output Voltage Accuracy
Referred to GND, DC,
VOUT – PVIN > 100 mV
−2
−
4
%
Boost Mode
For VOUT ≤ 3.5 V and PVIN ≥ 2.5 V
−
−
2.5
A
Minimum PVIN for 2.5 A load
VOUT = 3.5 V, Tj < 120°C
−
2.5
−
V
VOUT = 3.15 V, Tj < 120°C
−
2.35
−
V
VOUT = 5.0 V, Tj < 120°C
−
3.0
−
V
VOUT = 4.5 V, Tj < 120°C
−
2.8
−
V
VOUT to PVIN Reverse Leakage
Current
VOUT = 5 V, EN = Low
−
0.2
1
mA
ILKout
VOUT Leakage Current
VOUT = 0 V, EN = Low, PVIN = 4.2 V
−
0.1
1
mA
FSW
Switching Frequency
PVIN = 3.0 V, VOUT = 3.35 V, IOUT = 1 A
2
2.5
3
MHz
RONPMOS
P-Channel MOSFET On
Resistance (Synchronous
Rectifier)
From SW to VOUT, VOUT = 3.5 V, PVIN = 3.5 V
−
30
60
mW
RONNMOS
N-Channel MOSFET On
Resistance
(Boost Switch)
From SW to PGND, VOUT = 3.5 V,
PVIN = 3.5 V
−
25
50
mW
RONBP
Bypass P-MOSFET On
Resistance
From PVIN to VOUT, VOUT = 3.5 V,
PVIN = 3.5 V
−
35
60
mW
LOADTR
Load Transient Response
PVIN = 3.0 V, VOUT = 3.5 V,
IOUT = 500 to 1500 mA, TR = TF = 0.1 ms
−
±4
−
%
IPKlim
Boost Peak Current Limit
PVIN = 2.6 V
−
5.0
9.0
A
Boost Peak Current Limit at
Soft-Start
PVIN = 2.6 V
−
2.0
−
A
−
1600
−
mA
−
400
500
ms
IOUTMAX
PVINmin2.5A
PVINmin2A
ILKout-in
ISS_PKlim
ISSPK
Tss
Minimum PVIN for 2A load
Soft-Start Input Peak Current
Limit
Soft-Start EN High to
Regulation
50 W Load, COUT = 2 x 10 mF
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
8. Guaranteed by characterization and design.
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NCP6868
ELECTRICAL CHARACTERISTICS
Min & Max Limits apply for TJ up to +125°C unless otherwise specified. PVIN = 2.35 V to VOUT (Unless otherwise noted). Typical values
are referenced to PVIN = 3.0 V, TA = +25°C and default configuration (Figure 1)
Parameter
Symbol
Conditions
Min
Typ
Max
Unit
CONTROL PINS: EN, BP, VSEL
VIH
Positive Going Input High Voltage
Threshold
1.2
−
−
V
VIL
Negative Going Input Low Voltage
Threshold
−
−
0.4
V
Pull Down Internal Resistor at Control Pins
(EN & VSEL)
−
40
−
mW
Pull Up Internal Resistor at /B/P Pin
−
10
−
mW
1.7
−
5.0
V
0.5
V
RPDown
RPUp
I2C
PROTOCOL
VI2CINT
High Level at SCL/SDA Line
VI2CIL
SCL, SDA Low Input Voltage
SCL, SDA Line (Notes 9, 10)
−
−
VI2CIH
SCL, SDA High Input Voltage
SCL, SDA Line (Notes 9, 10)
0.8 x VI2CINT
−
−
V
VI2COL
SDA Low Output Voltage
SDA Pull Up Current = 3 mA
(Note 10)
−
−
0.4
V
I2C Clock Frequency
(Note 10)
−
−
3.4
MHz
FSCL
POWER GOOD PIN: PG
VOLPG
Power Good Pin Low Voltage Level
IPG = 5 mA
−
−
0.4
V
ILKPG
Power Good Pin Leakage Current
VPG = 5 V
−
−
1
mA
2.30
2.35
V
PROTECTIONS FEATURES
VUVLO_Fall
Under Voltage Lockout Threshold
PVIN Falling
2.25
VUVLO_Rise
Under Voltage Lockout Threshold
PVIN Rising
2.5
2.6
2.65
V
VUVLOHys
Under Voltage Lockout Hysteresis
−
300
−
mV
VOVP
Output Over-Voltage Protection Threshold
−
5.7
6.0
V
VOVPhys
Output Over-Voltage Protection Hysteresis
−
250
−
mV
TPGact
PG Pin Activation Temperature Threshold
(TWARN)
−
120
−
°C
TPGrel
PG Pin Release Temperature Threshold
−
100
−
°C
TSD
Thermal Shut Down Protection
−
150
−
°C
TSDH
Thermal Shut Down Hysteresis
−
20
−
°C
tRST
Fault Restart Timer
−
20
−
ms
(Note 10)
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
9. Devices that use non-standard supply voltages which do not conform to the intent I2C bus system levels must relate their input levels to the
VDD voltage to which the pull-up resistors RP are connected.
10. Guaranteed by characterization and design.
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NCP6868
TYPICAL OPERATING CHARACTERISTICS (SUPPLY CURRENTS)
VOUT = 3.5 V, L = 0.47 mH, COUT = 2 × 22 mF, CIN = 10 mF, TA = 25°C (unless otherwise noted)
10
4.5
1
4.0
3.5
2
+85°C
+25°C
−40°C
3
IQBPForced (mA)
ISD (mA)
5.0
3.0
2.5
1
2.0
2
9
1
8
7
2
3
6
5
4
1
3
2
1.0
2
3
0.5
1
1.5
3
0.0
2.3
2.7
3.1
3.5
3.9
4.3
4.7
5.1
0
2.3
5.5
2.7
3.1
3.5
PVIN (V)
4.3
4.7
5.1
40
90
35
80
1
2
3
1
30
2
70
3
60
25
20
15
1
10
+85°C
+25°C
−40°C
2
5
3
0
2.3
2.7
3.1
3.5
3.9
5.5
Figure 4. Quiescent Current in Forced Bypass
Mode (OCP OFF) vs Input Voltage
IQBoost (mA)
IQBPForced (mA)
3.9
PVIN (V)
Figure 3. Shutdown Current vs Input Voltage
4.3
4.7
50
40
30
1
20
2
0
2.3
5.5
5.1
+85°C
+25°C
−40°C
3
10
2.7
3.1
PVIN (V)
3.5
3.9
4.3
4.7
5.1
5.5
PVIN (V)
Figure 5. Quiescent Current in Forced Bypass
Mode (OCP ON) vs Input Voltage
Figure 6. Boost Quiescent Current vs Input Voltage
3.0
100
2.5
3
1
2
FSW (MHz)
Ripple (mV)
+85°C
+25°C
−40°C
10
1
2
3
VOUT = 3.15 V
VOUT = 3.35 V
VOUT = 3.5 V
500
1000
1500
2000
1.5
1.0
0.5
0.0
500
0
0
2.0
2500
1000
1500
2000
2500
IOUT (mA)
IOUT (mA)
Figure 7. VOUT Ripple vs Output Current
Figure 8. Frequency vs IOUT for VOUT = 3.35 V
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NCP6868
TYPICAL OPERATING CHARACTERISTICS (EFFICIENCY)
100
100
95
95
90
1
2
85
3
Efficiency (%)
Efficiency (%)
L = 0.47 mH (TFM type), COUT = 3 × 22 mF, CIN = 10 mF, TA = 25°C (unless otherwise noted)
80
1
2
75
3
90
1
2
85
3
80
1
PVIN = 3.1 V
PVIN = 3.0 V
PVIN = 2.6 V
70
PVIN = 3.1 V
PVIN = 3.0 V
PVIN = 2.6 V
2
75
3
70
1
10
100
1000
1
10
IOUT (mA)
100
1000
IOUT (mA)
Figure 10. Efficiency vs Output Current,
PVIN with VOUT = 3.5 V
Figure 9. Efficiency vs Output Current,
PVIN with VOUT = 3.15 V
L = 0.47 mH (SPM type), COUT = 3 × 22 mF, CIN = 10 mF, TA = 25°C (unless otherwise noted)
100
100
95
1
2
3
90
Efficiency (%)
Efficiency (%)
95
85
80
1
2
75
3
PVIN = 3.1 V
PVIN = 3.0 V
PVIN = 2.6 V
3
2
1
90
85
80
1
2
75
70
3
70
1
10
100
1000
1
10
IOUT (mA)
100
1000
IOUT (mA)
Figure 12. Efficiency vs Output Current and
Temperature PVIN = 3.0 V and VOUT = 3.15 V
Figure 11. Efficiency vs Output Current,
PVIN with VOUT = 3.15 V
100
100
95
95
1
2
3
90
Efficiency (%)
Efficiency (%)
+85°C
+25°C
−40°C
85
80
1
2
75
3
PVIN = 3.1 V
PVIN = 3.0 V
PVIN = 2.6 V
3
2
1
90
85
80
1
2
75
70
3
+85°C
+25°C
−40°C
70
1
10
100
1000
1
IOUT (mA)
10
100
1000
IOUT (mA)
Figure 13. Efficiency vs Output Current,
PVIN with VOUT = 3.3 V
Figure 14. Efficiency vs Output Current and
Temperature PVIN = 3.0 V and VOUT = 3.3 V
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NCP6868
TYPICAL OPERATING CHARACTERISTICS (EFFICIENCY)
L = 0.47 mH (SPM type), COUT = 3 × 22 mF, CIN = 10 mF, TA = 25°C (unless otherwise noted)
100
100
95
1
2
3
90
Efficiency (%)
Efficiency (%)
95
85
80
1
2
75
3
PVIN = 3.1 V
PVIN = 3.0 V
PVIN = 2.7 V
3
2
1
90
85
80
1
2
75
70
3
70
1
10
100
1
1000
10
IOUT (mA)
1000
Figure 16. Efficiency vs Output Current and
Temperature PVIN = 3.0 V and VOUT = 3.35 V
100
100
95
95
1
2
3
90
Efficiency (%)
Efficiency (%)
100
IOUT (mA)
Figure 15. Efficiency vs Output Current,
PVIN with VOUT = 3.35 V
85
80
1
2
75
3
3
2
1
90
85
80
1
PVIN = 3.1 V
PVIN = 3.0 V
PVIN = 2.6 V
2
75
70
3
+85°C
+25°C
−40°C
70
1
10
100
1000
1
10
IOUT (mA)
100
1000
IOUT (mA)
Figure 17. Efficiency vs Output Current,
PVIN with VOUT = 3.5 V
Figure 18. Efficiency vs Output Current and
Temperature PVIN = 3.0 V and VOUT = 3.5 V
100
100
95
95
1
2
3
90
Efficiency (%)
Efficiency (%)
+85°C
+25°C
−40°C
85
80
1
2
75
3
3
2
1
90
85
80
1
PVIN = 3.1 V
PVIN = 3.0 V
PVIN = 2.6 V
2
75
70
3
+85°C
+25°C
−40°C
70
1
10
100
1000
1
IOUT (mA)
10
100
1000
IOUT (mA)
Figure 19. Efficiency vs Output Current,
PVIN with VOUT = 3.6 V
Figure 20. Efficiency vs Output Current and
Temperature PVIN = 3.0 V and VOUT = 3.6 V
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NCP6868
TYPICAL OPERATING CHARACTERISTICS (START UP AND SHUT DOWN)
L = 0.47 mH (TFM type), COUT = 3 × 22 mF, CIN = 10 mF, TA = 25°C (unless otherwise noted)
VEN (2 V/div)
VEN (2 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
IIN (500 mA/div)
IIN (500 mA/div)
100 ms/div with 100 ns/pt
100 ms/div with 100 ns/pt
Figure 21. Power-Up Response,
50 W Load, VOUT = 3.3 V
Figure 22. Power-Down Response,
50 W Load, VOUT = 3.3 V
VEN (2 V/div)
VEN (2 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
IIN (500 mA/div)
IIN (500 mA/div)
100 ms/div with 100 ns/pt
100 ms/div with 100 ns/pt
Figure 23. Power-Up Response,
50 W Load, VOUT = 3.5 V
Figure 24. Power-Down Response,
50 W Load, VOUT = 3.5 V
VEN (2 V/div)
PVIN (2 V/div)
VEN (2 V/div)
PVIN (2 V/div)
VOUT (1 V/div)
VOUT (1 V/div)
2.0 ms/div with 10 ns/pt
2.0 ms/div with 10 ns/pt
Figure 25. Power-Up/Down Response in
Forced Bypass Mode, PVIN = 3.0 V, 25 W Load
Figure 26. Power-Up/Down Response in Forced
Bypass Mode, PVIN = 3.0 V, 50 W Load
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NCP6868
TYPICAL OPERATING CHARACTERISTICS (DYNAMIC TRANSITION)
L = 0.47 mH (TFM type), COUT = 3 × 22 mF, CIN = 10 mF, TA = 25°C (unless otherwise noted)
VSEL (2 V/div)
VOUT (200 mV/div) Offset: 3.5 V
VOUT (40 mV/div) Offset: 3.3 V
PVIN (200 mV/div) Offset: 3.5 V
100 ms/div with 100 ns/pt
100 ms/div with 100 ns/pt
Figure 27. Bypass Entry/Exit, Slow PVIN Ramp
1 ms Edge PVIN = 3.2 V to 3.8 V,
IOUT = 500 mA & VOUT = 3.5 V
Figure 28. VSEL Step
PVIN = 3 V, IOUT = 500 mA & VOUT = 3.5 V <−> 3.7 V
TYPICAL OPERATING CHARACTERISTICS (LOAD TRANSIENT RESPONSES)
L = 0.47 mH (TFM type), COUT = 3 × 22 mF, CIN = 10 mF, TA = 25°C (unless otherwise noted)
VIN (1 V/div)
VOUT (500 mV/div) AC Coupling
IOUT (500 mA/div)
IOUT (500 mA/div)
VOUT (50 mV/div) Offset: 3.5 V
20 ms/div with 50 ns/pt
50 ms/div with 2 ns/pt (Infinite Persistence)
Figure 29. Load Transient Response
IOUT = 500 to 1500 mA, 100 ns Edge,
PVIN = 3 V & VOUT = 3.5 V
Figure 30. Transient Response during Line Step
(3.3 V to 2.7 V in 10 ms), 1 A IOUT Step between
0 A and 1500 mA, 100 ns Edge, VOUT = 3.5 V
VIN (1 V/div)
PVIN (500 mV/div)
VOUT (500 mV/div) AC Coupling
IOUT (500 mA/div)
VOUT (100 mV/div) Offset: 5.0 V
20 ms/div with 200 ns/pt
50 ms/div with 2 ns/pt (Infinite Persistence)
Figure 32. Transient Response during Line Step
(3.6 V to 3.0 V in 10 ms), 1 A IOUT Step between 0 A
and 1500 mA, 100 ns Edge, VOUT = 5.0 V
Figure 31. Line Transient Response
PVIN = 3 V to 3.6 V, 10 ms Edge,
IOUT = 500 mA & VOUT = 5.0 V
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NCP6868
OPERATING DESCRIPTION
General Description
Shutdown State
The NCP6868 is a standalone synchronous step-up
converter. It is designed primarily to boost new generation
low-voltage Li-Ion batteries (silicon anode-like) embedded
into cell and smart phones. The main function of the device
is to maintain a minimum output voltage even when the
battery voltage is below the system minimum. The device is
capable of driving a continuous load up to 2.5 A when
PVIN = 2.5 V and VOUT = 3.5 V and operates at a switching
frequency of 2.5 MHz in Continuous Conduction Mode
(CCM). The device features a Boost mode coupled with
a Bypass mode. The Bypass mode is activated when PVIN is
above the boost regulator’s VOUT set-point (Low or High
value set-point adjusted through VSEL pin).
In order to reduce the required VOUT supply difference
between heavy and light load the VOUT voltage can be
adjusted through VSEL for anticipating a heavy load
transition. This allows optimizing power consumption
during wide load transitions. The Bypass mode can be
forced by setting the BP pin Low.
The NCP6868 enters the shutdown state when the EN pin
is set Low (below 0.4 V) or when the PVIN pin drops below
its VUVLO_Fall threshold value. in this stat the current
consumption of the product is the Shutdown Current.
Device Power-Up
Applying a voltage above 1.2 V to the EN pin will enable
the device for normal operation. A soft-start sequence is run
when activating EN high. It is recommended when starting
up the device to maintain a DC current load below 500 mA.
During device enabling current flow is prevented from PVIN
to VOUT and conversely from VOUT to PVIN.
Device power up and shutdown modes are detailed in
Figure 33.
In I2C mode the device is configured and programmed
through the I2C bus once it has been powered up (after
Power On Reset) and prior to setting the EN pin High.
VSEL Pin
The VSEL pin controls the device output voltage level in
regards to the anticipated load or line transitions which can
occur, making the output voltage transitions smoother.
The VOUT voltage level is increased to the high value target
by toggling the VSEL pin from Low to High. The output
voltage change is transitioned to the target value in 20 ms.
Boost Mode
The NCP6868 implements an architecture that allows the
device to operate in Continuous Conduction Mode (CCM)
and Discontinuous Conduction Mode (DCM) modes and
smoothly transitions between CCM and DCM. The boost
architecture provides very low transient response.
The NCP6868 operates in DCM mode in order to save
power and improve efficiency at low loads by reducing the
switching frequency. When the load increases and the
current in the inductor becomes continuous, the controller
automatically switches to CCM mode and switches back to
DCM mode when the current in the inductor becomes
discontinuous.
Inductor Peak Current Limitations
During normal operation, peak current limitation will
monitor and limit the current through the inductor. This
current limitation is particularly useful when size and/or
height constrain inductor power.
Under-Voltage Lockout (UVLO)
The NCP6868 core does not operate for voltages below
the Under Voltage Lock Out (UVLO) level. Below the
VUVLO_Fall threshold (typical 2.3 V), all internal circuitries
(both analog and digital) are held in reset. The NCP6868 is
not guaranteed to operate down to the VUVLO_Fall level
when the battery voltage is dropping off. To avoid erratic
ON/OFF behavior, an hysteresis is implemented. Restart is
guaranteed at VUVLO_Rise when VBAT voltage is
recovering or rising.
Bypass Operating Mode
The NCP6868 has been designed to manage conditions
when PVIN or VBAT becomes close to the required output
voltage of VOUT. In this case the NCP6868 automatically
enters the Bypass Operating Mode (or wire mode) from
Boost mode and a low resistance on-state Bypass (BP)
MOSFET is activated while the boost converter
N-MOSFET is turned off. The output voltage is the same as
input voltage minus a drop-out voltage resulting from the
resistance of the BP MOSFET in parallel with the rectifier
P-MOSFET plus the inductor. The consequence is
a resulting resistance from PVIN to VOUT which is smaller
than the resistance from the P-MOSFET + inductor when in
Boost mode at 100% duty cycle. In this specific case the
Bypass mode offers a better efficiency.
The device can be forced into Bypass mode by setting the
BP pin Low.
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NCP6868
Shutdown
State
EN = Low OR
PVIN < UVLOFall
Any
State
EN = High
LIN SS
No
Yes w/ Forced BP OFF
AND PVIN vVOUT + 0.1V
VOUT = VOUT_OK
SS
Fault
Yes w/ Forced BP ON
OR PVIN > VOUT + 0.1V
SS
Forced BP ON
OR PVIN > VOUT + 0.1V
Bypass
Boost
Forced BP OFF
AND PVIN vV OUT + 0.1V
Figure 33. Start-up/Shutdown Diagram
Power Good (PG) Pin and Thermal Management
Features
The Power Good signal during normal operation can be
disabled by clearing the PGDCDC bit in the Configuration
Register CONFIG2 bit D3.
To indicate the output voltage level is established, a power
good signal is available. In shutdown mode (EN = Low) PG
is high.
The power good signal is low when the DC-to-DC
converter is off when EN is High (during device starting up
or precharge). Once the output voltage reaches 95% of the
expected output level, the power good logic signal becomes
high and the open drain output becomes high impedance.
During operation when the output drops below 90% of the
programmed level the power good logic signal goes low
(and the open drain signal transitions to a low impedance
state) which indicates a power failure. When the voltage
rises again to above 95% the power good signal goes high
again.
The Power Good pin can also be used as an interrupt pin
operating as an over-temperature (TPGact/TPGrel),
over-load or over-voltage warning function in order to
prevent a potential device shutdown resulting respectively
from the thermal, overload/short-circuit, or over-voltage
protection.
Table 5. POWER-GOOD DISABLE-LOW SOURCES
Interrupt
Name
Power Good Off Events
POK
Power Good: DC-DC Out of Regulation or Off
TWARN
UVLO
Thermal Warning (See TPGact & TPGrel)
Under Voltage Lock Out
OC
Over-Current (ILIMBP & ILIMBST)
OV
Over-Voltage
Over Current Protection, Bypass Mode
The PG pin is pulled Low when the PMOS current limit
has triggered for more than 64 ms. When this happens, the
device will shut down in 0 s, 64 ms, 128 ms, or 256 ms
depending
on
the
programmed
value
of
(BPSCTIMING[1,0]). The default shutdown delay is 0 s.
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13
NCP6868
After the device shuts down, the device will attempt to
restart after 20 ms. Restarting will be tried 3 times before
definitely shutting down in order to eliminate erratic events
due to negative spikes on VOUT.
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NCP6868
Over Current Protection, Boost Mode
Dynamic Voltage Scaling (DVS)
In boost mode the current protection is enabled by two
separate mechanisms. When the IPEAK limit is triggered,
boost mode will keep regulating for 2 ms and then will shut
down immediately. During this period of time if the short
circuit becomes active and drops the output voltage down to
VIN/2 then the converter will shut down immediately.
Therefore the device is protected in two ways based on an
IPEAK detection timing period of 2 ms and voltage drop
detection. During this process of short circuit protection the
PG pin toggles High to Low when VOUT drops below 90%
of VOUT target.
The output voltage change is operated through the I2C or
pin VSEL using a Dynamic Voltage Scaling (DVS)
approach when the required voltage change is higher than
200 mV (Either by I2C or VSEL pin). The change between
set points is managed in a smooth fashion without disturbing
the operation of the device under power.
When programming a new output voltage that is greater
than a 200 mV-increase, the output raises in steps of 200 mV
every 32 ms (typical) such that the dV/dt is controlled.
The change rate of the voltage can be programmed as 32 ms
or 64 ms with 32 ms being the default value.
The DVS sequence is automatically initiated by changing
output voltage settings. There are two ways to change these
settings:
• Directly Change the Active Setting Register Value
(PROGVOUTLOW [5,0]/PROGVOUTHIGH [5,0]
Registers) via I2C Command
• Change the VSEL Internal Signal Level by Toggling
VSEL Pin
PVIN
Rising
UVLO < 2.6 V
POR
EN
i.e. Short
Circuit Event
VOUT
95% VOUT
PG
90% VOUT
Shut-Down
~2
V2
Internal
Reference
ms
Output
Voltage
nV
nt
Figure 34. Power Good (PG) Behavior Example
V1
Figure 35. DVS Diagram
Over-Voltage Protection
PG is pulled Low when the VOUT voltage limit of 5.7 V
has triggered for more than 64 ms and the device will shut
down. Afterwards the device will attempt to restart 20 ms
after. This will be tried 3 times before definitely shutting
down in order to eliminate erratic events due to negative
spikes on VOUT.
Interrupt Control Process (INTSEN1, INTSEN2, INTACK
& INTMSK Registers):
The interrupt controller continuously monitors internal
interrupt sources, generating an interrupt signal when
a system status change is detected (dual edge monitoring).
Individual bits generating interrupts will be set to 1 in the
INTACK register (I2C read only registers), indicating the
interrupt source. INTACK register is automatically reset by
an I2C read. The INTSEN1 and INTSEN2 registers (read
only register) contains real-time indicators of interrupt
sources.
All interrupt sources can be masked by writing in register
INTMSK. Masked sources will never generate an interrupt
request on PG pin (see Figure 41).
The PG pin is an open drain output. A non masked
interrupt request will result in PG pin being driven low.
When the host reads the INTACK registers the PG pin is
released to high impedance and the interrupt register
INTACK is cleared.
Figure 36 illustrates the Interrupt process.
Thermal Shutdown Feature (TSD)
The thermal capability of an IC can be exceeded due to the
boost converter output stage power level. A thermal
protection circuitry has been implemented to prevent the
device from damage. This protection circuitry is only
activated when the core is in active mode (output voltage is
turned on). During thermal shutdown, the output voltage is
turned off and the device enters shutdown mode.
The thermal shutdown threshold is set at 150°C (typical)
and a 20°C hysteresis has been implemented to avoid erratic
on/off behavior. After a typical 150°C thermal shutdown,
the NCP6868 will return to normal operation when the die
temperature cools down to 130°C. This normal operation
depends on the input conditions and configuration at the
time the device recovers.
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NCP6868
PG Event
PG Drop Low Event
(OVP, UVLO, ILIMBST,
ILIMBP, TWRN)
Removed
PG Event
Removed
Masked
Interrupt Mask (MSK)
Register Bit bx
Interrupt Sense (SEN)
Register Bit bx (Real Time)
Interrupt Acknowledge
(ACK) Register Bit bx
PG Pin
I2C Bus
Interrupt ACK
Register Reading
Interrupt ACK
Register Reading
Interrupt ACK
Register Reading
Figure 36. Interrupt Operation Example
I2C Compatible Interface
I2C Communication Description
The NCP6868 can support a subset of I2C protocol
detailed below.
The NCP6868 communicates with the external processor
by means of a serial link using a 400 kHz up to 3.4 MHz I2C
two-wire interface protocol. The I2C interface provided is
fully compatible with the Standard, Fast and High-Speed
I2C modes. The NCP6868 is not intended to operate as
a master controller. It is under the control of the main
controller (master device), which controls the clock (pin
SCL) and the read or write operations through SDA. The I2C
bus is an addressable interface (7-bit addressing only)
featuring two Read/Write addresses.
The first byte transmitted is the Chip address (with the
LSB bit set to 1 for a read operation, or set to 0 for a Write
operation). The following data will be:
• In case of a Write operation, the register address
(@REG) pointing to the register we want to write is
followed by the data we will write in that location.
The writing process is auto-incremental, so the first
data will be written in @REG, the contents of @REG
are incremented and the next data byte is placed in the
location pointed to by @REG + 1…, etc.
• In case of read operation, the NCP6868 will output the
data from the last register that has been accessed by the
last write operation. Like the writing process,
the reading process is auto-incremental.
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
START
IC ADDRESS
1
ACK
0
ACK
DATA1
ACK
DATA n
/ACK
STOP
READ OUT
FROM PART
STOP
WRITE INSIDE PART
1 à READ
/ACK
START
IC ADDRESS
0 à WRITE
DATA1
ACK
DATA n
ACK
If PART does not Acknowledge, the /NACK will be followed by a STOP or Sr.
If PART Acknowledges, the ACK can be followed by another data or STOP or Sr.
Figure 37. General Protocol Description
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NCP6868
Read Out from Part
then start or a Repeated Start will initiate the read transaction
from the register address the initial write transaction has
pointed to:
The Master will first make a “Pseudo Write” transaction
with no data to set the internal address register. Then, a stop
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
START
SETS INTERNAL
REGISTER POINTER
IC ADDRESS
0
ACK
REGISTER ADDRESS
ACK
STOP
0à WRITE
START
IC ADDRESS
1
ACK
DATA1
ACK
DATA n
REGISTER ADDRESS
VALUE
/ACK
STOP
REGISTER ADDRESS + (n − 1)
VALUE
n REGISTERS READ
1à READ
Figure 38. Read Out from Part
The first WRITE sequence will set the internal pointer to
the register we want access to. Then the read transaction will
start at the address the write transaction has initiated.
Transaction with Real Write then Read
With Stop then Start
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
START
IC ADDRESS
SETS INTERNAL
REGISTER POINTER
0
ACK
WRITE VALUE IN
REGISTER REG0
REGISTER REG 0 ADDRESS ACK
REG VALUE
WRITE VALUE IN
REGISTER REG0 + (n − 1)
REG + (n − 1) VALUE
ACK
ACK
STOP
n REGISTERS WRITE
0 à WRITE
START
IC ADDRESS
1
ACK
DATA1
ACK
REGISTER REG + (n −1)
VALUE
DATA k
k REGISTERS READ
/ACK
STOP
REGISTER ADDRESS + (n − 1)
+ ( k −1) VALUE
1 à READ
Figure 39. Write Followed by Read Transaction
Write in Part
Write operation will be achieved by only one transaction.
After chip address, the MCU first data will be the internal
register we want access to, then following data will be the
data we want to write in Reg, Reg + 1, Reg + 2, …, Reg + n.
Write n Registers:
FROM MCU to NCPxxxx
FROM NCPxxxx to MCU
START
IC ADDRESS
SETS INTERNAL
REGISTER POINTER
0
ACK
REGISTER REG0 ADDRESS
WRITE VALUE IN
REGISTER REG0 + (n − 1)
WRITE VALUE IN
REGISTER REG0
ACK
REG VALUE
ACK
n REGISTERS WRITE
0 à WRITE
Figure 40. Write in n Registers
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17
REG + (n − 1) VALUE
ACK
STOP
NCP6868
I2C Address
NCP6868 has four available I2C address selectable by
factory settings (ADD0 to ADD3). Different address
settings can be generated upon request to
ON Semiconductor. The default address is set to ECh/EDh.
Table 6. I2C ADDRESS
I2C Address
Hex
A7
A6
A5
A4
A3
A2
A1
A0
ADD0
W 0xE8; R 0xE9
1
1
1
0
1
0
0
R/W
ADD1
W 0xEA; R 0xEB
1
1
1
0
1
0
1
R/W
ADD2 (Default)
W 0xEC; R 0xED
1
1
1
0
1
1
0
R/W
ADD3
W 0xEE; R 0xEF
1
1
1
0
1
1
1
R/W
Register Map
Table 7 describes I2C registers.
Registers can be:
R:
Read Only Register
RC:
Read then Clear (Dual Edge)
R/W:
Read and Write Register
Reserved: Address is Reserved and Register is Not
Physically Designed
Spare:
Address is Reserved and Register is Physically
Designed
Table 7. I2C REGISTERS MAP DESCRIPTION
Address
Register Name
Type
Default
Function
00h
RID
R
00h
Revision Identification
01h
CONFIG
R/W
00h
Configuration Programming
02h
PROGVOUT_LOW
R/W
09h
VOUT Programming when VSEL = Low
03h
PROGVOUT_HIGH
R/W
0Dh
VOUT Programming when VSEL = High
04h
ILIM
R/W
03h
Current Limit Programming
05h
INTSEN1
R
00h
Sense Register (Real Time Status Register)
06h
INTSEN2
R
00h
Sense Register (Real Time Status Register)
07h
INTACK
RC
00h
Interrupt Register
08h
INTMSK
R/W
FFh
Mask Register to Enable or Disable Interrupt Sources (Trim)
09h
PID
R
68h
Product Identification
0Ah
FID
R
00h
Features Identification (Trim)
0Bh
CONFIG2
R/W
07h
Configuration Programming 2
0Ch to xxh
−
−
−
Reserved
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NCP6868
Registers Description
Table 8. REVISION ID REGISTER
Name: RID
Address: 00h
Type: R
Default: 00000000b (00h)
D7
D6
D5
D4
D3
D2
D1
D0
RID_7
RID_6
RID_5
RID_4
RID_3
RID_2
RID_1
RID_0
D1
D0
Bit
Bit Description
RID[7..0]
Revision Identification
00000000: Silicon Revision 1.0
00000001: Silicon Revision 1.1
00000010: Silicon Revision 1.2
00000100: Silicon Revision 1.3
Table 9. CONFIGURATION REGISTER
Name: CONFIG
Address: 01h
Type: R/W
Default: 00000000b (00h)
D7
D6
FORCERST
D5
D4
D3
ENABLE
Spare = 0
Bit
MODE
D2
MODE[1,0]
Bit Description
Device Mode of Operation:
0x, 11: Normal Operation, Auto Mode
10: Forced CCM Mode
ENABLE[6:5]
Device Enable Modes:
00: Device Operation Follows Hardware Control Signal (Refer to Table 2)
01: Device Operates in Auto Mode Regardless of the BP Pin (EN = 1)
10: Device is Forced in Bypass Mode Regardless of the BP Pin Value (EN = 1)
11: Device is in Shutdown Mode. During Shutdown, Current Flow is Prevented from VIN to VOUT
and from VOUT to VIN. All Bias Circuits are Off
FORCERST
Force Reset Bit
0: Normal Operation. Self Cleared to 0
1: Force Reset of Internal Registers to Default
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NCP6868
Table 10. DC TO DC OUTPUT VOLTAGE PROGRAMMING REGISTER
Name: PROGVOUTLOW
Address: 02h
Type: R/W
Default: 00001001b (09h)
D7
D6
Spare = 0
Spare = 0
D5
D4
D3
D2
D1
D0
PROGVOUTLOW[5:0]
Bit
Bit Description
PROGVOUT
LOW[5:0]
Sets the DC to DC Converter Output Voltage (see Table 11)
Default 00001001b => 3.3 V (VSEL = 0)
Table 11. DC TO DC OUTPUT VOLTAGE
PROGRAMMING
PROGVOUTLOW[5:0]
VOUT (V) @ VSEL = 0
011000b
4.050
PROGVOUTLOW[5:0]
VOUT (V) @ VSEL = 0
011001b
4.100
000000b
2.850
011010b
4.150
000001b
2.900
011011b
4.200
000010b
2.950
011100b
4.250
000011b
3.000
011101b
4.300
000100b
3.050
011110b
4.350
000101b
3.100
011111b
4.400
000110b
3.150
100000b
4.450
000111b
3.200
100001b
4.500
001000b
3.250
100010b
4.550
001001b
3.300
100011b
4.600
001010b
3.350
100100b
4.650
001011b
3.400
100101b
4.700
001100b
3.450
100110b
4.750
001101b
3.500
100111b
4.800
001110b
3.550
101000b
4.850
001111b
3.600
101001b
4.900
010000b
3.650
101010b
4.950
010001b
3.700
101011b
5.000
010010b
3.750
101100b
5.050
010011b
3.800
101101b
5.100
010100b
3.850
101110b
5.150
010101b
3.900
101111b
5.200
010110b
3.950
110000b
5.250
010111b
4.000
110001b
5.300
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NCP6868
Table 12. DC TO DC OUTPUT VOLTAGE PROGRAMMING REGISTER
Name: PROGVOUTHIGH
Address: 03h
Type: R/W
Default: 00011001b (0Dh)
D7
D6
Spare = 0
Spare = 0
D5
D4
D3
D2
D1
D0
PROGVOUTHIGH[5:0]
Bit
Bit Description
PROGVOUT
HIGH[5:0]
Sets the DC to DC Converter Output Voltage (see Table 13)
Default 00001101b => 3.5 V (VSEL = 1)
Table 13. DC TO DC OUTPUT VOLTAGE
PROGRAMMING
PROGVOUTHIGH[5:0]
VOUT (V) @ VSEL = 1
011000b
4.050
PROGVOUTHIGH[5:0]
VOUT (V) @ VSEL = 1
011001b
4.100
000000b
2.850
011010b
4.150
000001b
2.900
011011b
4.200
000010b
2.950
011100b
4.250
000011b
3.000
011101b
4.300
000100b
3.050
011110b
4.350
000101b
3.100
011111b
4.400
000110b
3.150
100000b
4.450
000111b
3.200
100001b
4.500
001000b
3.250
100010b
4.550
001001b
3.300
100011b
4.600
001010b
3.350
100100b
4.650
001011b
3.400
100101b
4.700
001100b
3.450
100110b
4.750
001101b
3.500
100111b
4.800
001110b
3.550
101000b
4.850
001111b
3.600
101001b
4.900
010000b
3.650
101010b
4.950
010001b
3.700
101011b
5.000
010010b
3.750
101100b
5.050
010011b
3.800
101101b
5.100
010100b
3.850
101110b
5.150
010101b
3.900
101111b
5.200
010110b
3.950
110000b
5.250
010111b
4.000
110001b
5.300
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NCP6868
Table 14. PEAK CURRENT LIMIT REGISTER
Name: ILIM
Address: 04h
Type: R/W
Default: 00000011 (03h)
D7
D6
D5
D4
Spare = 0
SCPBP_DIS
ILIM_DIS
Spare = 0
D3
D2
D1
D0
ILIM [3:0]
Bit
Bit Description
ILIM
Inductor Peak Current Settings (see Table 15)
ILIM_DIS
Enable/Disable Peak Inductor Current Limit
0: Current Limit Enabled
1: Current Limit Disabled
SCPBP_DIS
Enable/Disable Bypass Short Circuit Protection
0: Protection Enabled
1: Protection Disabled
Table 15. DC TO DC PEAK CURRENT LIMIT
PROGRAMMING
ILIM[3:0]
Peak Current Setting
0011b
5A
ILIM[3:0]
Peak Current Setting
0100b
6A
0000b
2A
0101b
7A
0001b
3A
0110b
8A
0010b
4A
0111b
9A
Table 16. INTERRUPT SENSE REGISTER 1
Name: INTSEN1
Address: 05h
Type: R
Default: 00000000b (00h)
D7
D6
D5
D4
D3
D2
D1
D0
SEN_TSD
SEN_
TWARN
SEN_
DCDCMODE
SEN_
OPMODE
SEN_ILIMBP
SEN_
ILIMBST
Spare = 0
SEN_POK
Bit
SEN_POK
Bit Description
Power Good Ok Sense
0: DCDC Output Voltage below Target
1: DCDC Output Voltage within Nominal Range. This Bit is Set if the Converter is Forced in
Bypass Mode
SEN_ILIMBST
Current Limit Status Bit (DC-DC Boost Mode):
0: DCDC Output Current is below Limit
1: DCDC Output Current is over Limit
SEN_ILIMBP
Current Status Bit (Bypass Mode)
0: Bypass Output Current is below Limit
1: Bypass Output Current is over Limit
SEN_OPMODE
SEN_DCDCMODE
SEN_TWARN
SEN_TSD
Device Mode of Operation Status Bit:
0: Device Operates in Bypass Mode
1: Device Operates in Boost Mode
DC-DC Mode of Operation Status Bit:
0: Device Operates in DCM Mode
1: Device Operates in CCM Mode
Thermal Warning Sense
0: Junction Temperature below Thermal Warning Limit
1: Junction Temperature over Thermal Warning Limit
Thermal Shutdown Sense
0: Junction Temperature below Thermal Shutdown Limit
1: Junction Temperature over Thermal Shutdown Limit
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NCP6868
Table 17. INTERRUPT SENSE REGISTER 2
Name: INTSEN2
Address: 06h
Type: R
Default: 00000000b (00h)
D7
D6
D5
Spare = 0
D4
D3
SEN_OV
SEN_UVLO
Bit
D2
D1
D0
Spare = 0
Bit Description
SEN_UVLO
Under Voltage Sense
0: Input Voltage Higher than UVLO Threshold
1: Input Voltage Lower than UVLO Threshold
SEN_OV
Over Voltage Sense
0: Output Voltage Lower than OVP Threshold
1: Output Voltage Higher than OVP Threshold
Table 18. INTERRUPT ACKNOWLEDGE REGISTER
Name: INTACK
Address: 07h
Type: RC
Default: 00000000b (00h)
Trigger: Dual Edge [D7...D0]
D7
D6
D5
D4
D3
D2
D1
D0
ACK_TSD
ACK_
TWARN
ACK_
ILIMBST
ACK_OV
ACK_UVLO
ACK_ILIMBP
Spare = 0
ACK_POK
Bit
Bit Description
ACK_POK
Power Good Sense Acknowledgement
0: Cleared
1: DCDC Power Good Event Detected
ACK_ILIMBP
ByPass Over Current Sense
0: Cleared
1: ByPass Over Current Limit Detected
ACK_UVLO
Under Voltage Sense Acknowledgement
0: Cleared
1: Under Voltage Event Detected
ACK_OV
Over Voltage Sense Acknowledgement
0: Cleared
1: Over Voltage Event Detected
ACK_ILIMBST
DCDC Over Current Sense
0: Cleared
1: DCDC Over Current Limit Detected
ACK_TWARN
Thermal Warning Sense Acknowledgement
0: Cleared
1: Thermal Warning Event Detected
ACK_TSD
Thermal Shutdown Sense Acknowledgement
0: Cleared
1: Thermal Shutdown Event Detected
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23
NCP6868
Table 19. INTERRUPT MASK REGISTER
Name: INTMASK
Address: 08h
Type: RW
Default: 11111111b (FFh)
D7
D6
D5
D4
D3
D2
D1
D0
MASK_TSD
MASK_
TWARN
MASK_
ILIMBST
MASK_OV
MASK_
UVLO
MASK_
ILIMBP
Spare = 1
MASK_POK
Bit
Bit Description
MASK_POK
Power Good Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MASK_ILIMBP
DCDC over Current Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MASK_UVLO
Under Voltage Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MASK_OV
Over Voltage Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MASK_ILIMBST
DCDC over Current Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MASK_TWARN
Thermal Warning Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
MASK_TSD
Thermal Shutdown Interrupt Source Mask
0: Interrupt is Enabled
1: Interrupt is Masked
SEN_TSD (R)
MASK_TSD (RW)
SEN_TWARN (R)
MASK_TWARN (RW)
SEN_ILIMBST (R)
MASK_ILIMBST (RW)
PG PIN
SEN_OV (R)
MASK_OV (RW)
SEN_UVLO (R)
MASK_UVLO (RW)
SEN_ILIMBP (R)
MASK_ILIMBP (RW)
SEN_POK (R)
MASK_POK (RW)
PG pin will go to low state if the corresponding sense goes to 1 AND if the corresponding mask is cleared.
Figure 41. Interruption Masking Logical Diagram
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NCP6868
Table 20. PRODUCT ID REGISTER
Name: PID
Address: 09h
Type: R
Default: 01101000b (68h)
D7
D6
D5
D4
D3
D2
PID[7:4]
D1
D0
PID[3:0]
Bit
Bit Description
PID[7..0]
Product Identification
01101000b = 68h w/ PID[7:4] = 6, PID[3:0] = 8
Table 21. FIRMWARE ID REGISTER
Name: FID
Address: 0Ah
Type: R
Default: 00000000b (00h)
D7
D6
D5
D4
D3
D2
D1
D0
FID_7
FID_6
FID_5
FID_4
FID_3
FID_2
FID_1
FID_0
Bit
Bit Description
FID[7..0]
Firmware Identification
00000000: Firmware Revision 1.0
00000001: Firmware Revision 1.1
00000010: Firmware Revision 1.2
00000011: Firmware Revision 1.3
…
Table 22. CONFIGURATION REGISTER 2
Name: CONFIG2
Address: 0Bh
Type: R/W
Default: 00000111 (07h)
D7
D6
Spare = 0
D5
D4
BPSCTIMING[1,0]
D3
D2
D1
D0
DVSTIMING
PGDCDC
RSTSTATUS
REARM
Bit
REARM
RSTSTATUS
PGDCDC
DVSTIMING
BPSCTIMING[1,0]
Bit Description
Rearming of Device after TSD
0: No Re-Arming after TSD
1: Re-Arming Active after TSD with No Reset of I2C Registers: New Power-Up Sequence
is Initiated with Previously Programmed I2C Registers Values
Reset Indicator Bit
0: Must be Written to 0 after Register Reset
1: Default (Loaded after Registers Reset)
Power Good Enabling
0 = Disable
1 = Enable
DVS Timing Change
0 = 200 mV Step / 32 ms
1 = 200 mV Step / 64 ms
Short-Circuit Protection Activation Delay
00 = 0 s
01 = 64 ms
10 = 128 ms
11 = 256 ms
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NCP6868
APPLICATION INFORMATION
Figure 42. Application Block Diagram
recommended inductor featuring 0.47 mH of nominal value.
Peak-current limit inductor is used.
The inductor also needs to have high enough current
rating based on temperature rise concern. Low DCR is good
for efficiency improvement and temperature rise reduction.
Inductor Selection
The selected inductor must have high enough saturation
current rating to be higher than the maximum peak current
which can reach 4 A for the default configuration for a short
period of time during overload situations. Table 23 shows
Table 23. RECOMMENDED INDUCTORS
Supplier
Part #
Value
(mH)
Size (L y I y T)
(mm)
DC Rated Current
(A)
DCR Max @ 255C
(mW)
Toko
DFE201610A−R47M−T00
0.47
20 × 16 × 1
4.0
53
Toko
DFE201610P−R47M−T00
0.47
20 × 16 × 1
4.1
41
Toko
DFE201612R−R47M−T00
0.47
20 × 16 × 1.2
4.4
40
Toko
DFE201612P−R47M−T00
0.47
20 × 16 × 1.2
4.9
33
CYNTEC
HMLQ20161T−R47MDR−11
0.47
2.0 × 1.6 × 1.0
4.4
26
CYNTEC
HMLQ20161B−R47MDR−11
0.47
2.0 × 1.6 × 1.2
5.1
20
CYNTEC
HMLQ25201T−R47MSR−11
0.47
2.5 × 2.0 × 1.0
4.3
19
TDK
TFM252010A−R47M
0.47
25 × 20 × 1.0
4.5
30
TDK
TFM252010GHM−R47MTAA
0.47
25 × 20 × 1.0
4.3
26
Output Capacitor Selection
rail, a ceramic capacitor is recommended due to low ESR
and ESL.
The input capacitor needs also to be sufficient to protect
the device from over voltage spike and a minimum of 4.7 mF
capacitor is required. The input capacitor should be located
as close as possible to the IC. PGND is connected to the
ground terminal of the input cap which then connects to the
ground plane. The PVIN is connected to the VBAT terminal of
the input capacitor which then connects to the VBAT plane.
The output capacitor selection is determined by the output
voltage ripple and the load transient response requirement.
For high transient load performance a high output capacitor
value must be used. It is recommended to pay attention to the
variation of the capacitor value when the bias voltage across
this capacitor varies. Usually the capacitor value decreases
with the bias voltage and X5R/X7R low ESR ceramic
capacitors are recommended in order to guarantee the
effective capacitor value under operating conditions.
Layout and PCB Design Recommendations
Input Capacitor Selection
Good PCB layout helps high power dissipation from
a small package with reduced temperature rise. Thermal
layout guidelines are:
One criteria for the input capacitor selection is the input
voltage ripple requirement. To minimize the input voltage
ripple and get better decoupling in the input power supply
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26
NCP6868
• A four or more layers PCB board with solid ground
•
•
•
The input capacitor is placed as close as possible to the IC.
PVIN is directly connected to the CIN input capacitor, and
then connected to the PVIN plane. Local mini planes are used
on the top layer (green) and layer just below top layer with
laser vias.
PGND is directly connected to the CIN input capacitor, and
then connected to the GND plane. Local mini planes are used
on the top layer (green) and layer just below top layer with
laser vias.
SW is connected to the LX inductor with local mini planes
used on the top layer (green) and layer just below top layer
with laser vias.
VOUT is directly connected to the COUT output capacitor and
then connected to the PGND plane.
planes is preferred for better heat dissipation.
Adding extra vias around the IC is encouraged to
connect the inner ground layers to reduce thermal
impedance.
Use large area copper especially in the top layer to help
thermal conduction and radiation.
Use two layers for the high current paths (PVIN, PGND,
SW, VOUT) in order to split current in two different
paths and limit PCB copper self heating.
(See demo board example Figure 43)
3.8 mm
4.1 mm
2520
2. 5 x 2.0 mm
PVIN
PVIN
VSEL
MODE/
SCL
VOUT
VOUT
BP
NC/SDA
SW
SW
AGND
PGND
PGND
PGND
0603
RST /
PG
1.6 x 0 .8 mm
0603
1.6 x 0.8 m m
EN
Figure 44. Example of PCB Implementation
S < 16 mm2
Figure 43. Layout Minimum Recommended
Occupied Space
Table 24. ORDERING INFORMATION
Package
Shipping†
NCP6868PFCCT1G
WLCSP16
(Pb-Free)
3000 / Tape & Reel
NCP6868V315FCCT1G
WLCSP16
(Pb-Free)
3000 / Tape & Reel
NCP6868V330FCCT1G
WLCSP16
(Pb-Free)
3000 / Tape & Reel
NCP6868E315FCCT1G
WLCSP16
(Pb-Free)
3000 / Tape & Reel
Device*
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
* Consult Sales Office for specific Output Voltage requirement
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27
NCP6868
PACKAGE DIMENSIONS
WLCSP16 1.80x1.80
CASE 567JU
ISSUE O
È
PIN A1
REFERENCE
D
A
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. COPLANARITY APPLIES TO SPHERICAL
CROWNS OF SOLDER BALLS.
B
E
DIM
A
A1
A2
b
D
E
e
0.25 C
2X
0.25 C
2X
TOP VIEW
A
0.10 C
A2
A1
0.08 C
C
SIDE VIEW
NOTE 3
RECOMMENDED
SOLDERING FOOTPRINT*
SEATING
PLANE
PACKAGE
OUTLINE
e/2
16X
MILLIMETERS
MIN
MAX
0.60
−−−
0.17
0.23
0.36 REF
0.24
0.29
1.80 BSC
1.80 BSC
0.40 BSC
b
e
e/2
0.05 C A B
1
0.03 C
2
0.40
PITCH
A1
0.40
PITCH
3
e
4
A B C D
BOTTOM VIEW
16X
0.25
DIMENSIONS: MILLIMETERS
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
ON Semiconductor and the
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC) or its subsidiaries in the United States and/or other countries.
SCILLC owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of SCILLC’s product/patent coverage may be accessed
at www.onsemi.com/site/pdf/Patent−Marking.pdf. SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation
or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and
specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. “Typical” parameters which may be provided in SCILLC data sheets
and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each
customer application by customer’s technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended,
or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which
the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or
unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim
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PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT:
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Phone: 303−675−2175 or 800−344−3860 Toll Free USA/Canada
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Phone: 81−3−5817−1050
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ON Semiconductor Website: www.onsemi.com
Order Literature: http://www.onsemi.com/orderlit
For additional information, please contact your local
Sales Representative
NCP6868/D