High Performance, Narrow-Band Transceiver IC ADF7021-V FEATURES On-chip fractional-N PLL On-chip, 7-bit ADC and temperature sensor Fully automatic frequency control (AFC) loop Digital received signal strength indication (RSSI) Integrated Tx/Rx switch Leakage current in power-down mode: 0.1 μA High performance, low power, narrow-band transceiver Enhanced performance ADF7021-N with external VCO Frequency bands using external VCO: 80 MHz to 960 MHz Improved adjacent channel power (ACP) and adjacent channel rejection (ACR) compared with the ADF7021-N Programmable IF filter bandwidths: 9 kHz, 13.5 kHz, and 18.5 kHz Modulation schemes: 2FSK, 3FSK, 4FSK, MSK Spectral shaping: Gaussian and raised cosine filtering Data rates: 0.05 kbps to 24 kbps Power supply: 2.3 V to 3.6 V Programmable output power: −16 dBm to +13 dBm in 63 steps Automatic power amplifier (PA) ramp control Receiver sensitivity −125 dBm at 250 bps, 2FSK −122 dBm at 1 kbps, 2FSK Patent pending, on-chip image rejection calibration APPLICATIONS Narrow-band, short-range device (SRD) standards ETSI EN 300 220 500 mW output power capability in 869 MHz g3 subband with external PA High performance receiver rejection, blocking, and adjacent channel power (ACP) FCC Part 90 (meets Emission Mask D requirements) FCC Part 95 ARIB STD-T67 Wireless metering Narrow-band wireless telemetry FUNCTIONAL BLOCK DIAGRAM CE RSET TEMP SENSOR RLNA MUX 2FSK 3FSK 4FSK RSSI/ LOG AMP IF FILTER RFIN MUXOUT LDO[1:4] TEST MUX 7-BIT ADC LNA RFIN CREG[1:4] CLOCK AND DATA RECOVERY DEMODULATOR TxRxCLK Tx/Rx CONTROL TxRxDATA SWD GAIN AGC CONTROL ADF7021-V AFC CONTROL PA RAMP ÷1/÷2 DIV P N/N + 1 2FSK 3FSK 4FSK MOD CONTROL Σ-Δ MODULATOR ÷2 SDATA SREAD SCLK GAUSSIAN/ RAISED COSINE FILTER 3FSK ENCODING BUFFER CP PFD DIV R L2 CPOUT OSC OSC1 OSC2 CLK DIV CLKOUT 08635-001 RFOUT SLE SERIAL PORT Figure 1. Rev. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2010 Analog Devices, Inc. All rights reserved. ADF7021-V TABLE OF CONTENTS Features .............................................................................................. 1 Demodulation, Detection, and CDR ....................................... 30 Applications ....................................................................................... 1 Receiver Setup............................................................................. 32 Functional Block Diagram .............................................................. 1 FSK Demodulator Optimization .............................................. 33 Revision History ............................................................................... 2 AFC Operation ........................................................................... 34 General Description ......................................................................... 3 Automatic Sync Word Detection (SWD) ................................ 35 Specifications..................................................................................... 4 Applications Information .............................................................. 36 RF and PLL Specifications........................................................... 4 IF Filter Bandwidth Calibration ............................................... 36 Transmission Specifications ........................................................ 5 LNA/PA Matching ...................................................................... 37 Receiver Specifications ................................................................ 6 Image Rejection Calibration ..................................................... 38 Digital Specifications ................................................................... 9 Packet Structure and Coding .................................................... 39 General Specifications ............................................................... 10 Programming After Initial Power-Up ..................................... 39 Timing Characteristics .............................................................. 10 Applications Circuit ................................................................... 42 Timing Diagrams........................................................................ 11 Serial Interface ................................................................................ 43 Absolute Maximum Ratings.......................................................... 14 Readback Format........................................................................ 43 ESD Caution ................................................................................ 14 Interfacing to a Microcontroller/DSP ..................................... 44 Pin Configuration and Function Descriptions ........................... 15 Register 0—N Register............................................................... 45 Typical Performance Characteristics ........................................... 17 Register 1—Oscillator Register................................................. 46 Frequency Synthesizer ................................................................... 21 Register 2—Transmit Modulation Register ............................ 47 Reference Input ........................................................................... 21 Register 3—Transmit/Receive Clock Register ........................ 48 MUXOUT.................................................................................... 22 Register 4—Demodulator Setup Register ............................... 49 Voltage Controlled Oscillator (VCO) ...................................... 23 Register 5—IF Filter Setup Register ......................................... 50 Choosing a VCO for Best System Performance ..................... 23 Register 6—IF Fine Calibration Setup Register ..................... 51 Transmitter ...................................................................................... 24 Register 7—Readback Setup Register ...................................... 52 RF Output Stage .......................................................................... 24 Register 8—Power-Down Test Register .................................. 53 Modulation Schemes .................................................................. 24 Register 9—AGC Register ......................................................... 54 Spectral Shaping ......................................................................... 26 Register 10—AFC Register ....................................................... 55 Modulation and Filtering Options ........................................... 27 Register 11—Sync Word Detect Register ................................ 56 Transmit Latency ........................................................................ 27 Register 12—SWD/Threshold Setup Register ........................ 56 Test Pattern Generator ............................................................... 27 Register 13—3FSK/4FSK Demodulation Register ................. 57 Receiver Section .............................................................................. 28 Register 14—Test DAC Register ............................................... 58 RF Front End ............................................................................... 28 Register 15—Test Mode Register ............................................. 59 IF Filter......................................................................................... 28 Outline Dimensions ....................................................................... 60 RSSI/AGC .................................................................................... 28 Ordering Guide .......................................................................... 60 REVISION HISTORY 4/10—Revision 0: Initial Version Rev. 0 | Page 2 of 60 ADF7021-V GENERAL DESCRIPTION The ADF7021-V is a high performance, low power, narrow-band RF transceiver based on the ADF7021-N. The architecture of the ADF7021-V transceiver is similar to that of the ADF7021-N except that an external VCO is used by the on-chip RF synthesizer for applications that require improved phase noise performance. The ADF7021-V is designed to operate in both the license-free ISM bands and in the licensed bands from 80 MHz to 960 MHz. To minimize RF feedthrough and spurious emissions, the external VCO operates at 2× or 4× the desired RF frequency; the ADF7021-V supports a maximum VCO frequency operation of 1920 MHz. The 4× VCO operation is programmable by enabling an additional on-chip divide-by-2 outside the RF synthesizer loop and offers improved phase noise performance. As with the ADF7021-N receiver, the IF filter bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz are supported, making the ADF7021-V ideally suited to worldwide narrow-band telemetry applications. The part has both Gaussian and raised cosine transmit data filtering options to improve spectral efficiency for narrow-band applications. It is suitable for circuit applications targeted at the following: • • • • • European ETSI EN 300 220 North American FCC Part 15, Part 90, and Part 95 Japanese ARIB STD-T67 Korean short-range device regulations Chinese short-range device regulations A complete transceiver can be built using a small number of discrete external components, making the ADF7021-V very suitable for area-sensitive, high performance driven applications. The range of on-chip FSK modulation and data filtering options allows users greater flexibility in their choice of modulation schemes while meeting the tight spectral efficiency requirements. The ADF7021-V also supports protocols that dynamically switch among 2FSK, 3FSK, and 4FSK to maximize communication range and data throughput. The transmit section contains a low noise fractional-N PLL with an output resolution of <1 ppm. The frequency-agile PLL allows the ADF7021-V to be used in frequency-hopping spread spectrum (FHSS) systems. The VCO is external, which provides better phase noise and thus lower adjacent channel power (ACP) and adjacent channel rejection (ACR) compared with the ADF7021-N. The VCO tuning range extends from 0.2 V to 2 V, which should be taken into account when choosing the external VCO. The transmitter output power is programmable in 63 steps from −16 dBm to +13 dBm and has an automatic power amplifier ramp control to prevent spectral splatter and help meet regulatory standards. The transceiver RF frequency, channel spacing, and modulation are programmable using a simple 3-wire interface. The device operates with a power supply range of 2.3 V to 3.6 V and can be powered down when not in use. A low IF architecture is used in the receiver (100 kHz), which minimizes power consumption and the external component count yet avoids dc offset and flicker noise at low frequencies. The IF filter has programmable bandwidths of 9 kHz, 13.5 kHz, and 18.5 kHz. The ADF7021-V supports a wide variety of programmable features, including Rx linearity, sensitivity, and IF bandwidth, allowing the user to trade off receiver sensitivity and selectivity against current consumption, depending on the application. The receiver also features a patented automatic frequency control (AFC) loop with programmable pull-in range that allows the PLL to remove the frequency error in the incoming signal. The receiver achieves an image rejection performance of 50 dB using a patent-pending IR calibration scheme that does not require the use of an external RF source. An on-chip ADC provides readback of the integrated temperature sensor, external analog input, battery voltage, and RSSI signal, which can eliminate the need for an external ADC in some applications. The temperature sensor is accurate to ±10°C over the full operating temperature range of −40°C to +85°C. This accuracy can be improved by performing a one-point calibration at room temperature and storing the result in memory. Rev. 0 | Page 3 of 60 ADF7021-V SPECIFICATIONS VDD = 2.3 V to 3.6 V, GND = 0 V, TA = TMIN to TMAX, unless otherwise noted. Typical specifications are at VDD = 3 V, TA = 25°C. All measurements are performed with the EVAL-ADF7021-VDBxZ using the PN9 data sequence, unless otherwise noted. The version number of ETSI EN 300 200-1 is V2.3.1. LBW = loop bandwidth and IFBW = IF filter bandwidth. RF AND PLL SPECIFICATIONS Table 1. Parameter RF CHARACTERISTICS Phase Frequency Detector (PFD) Frequency PHASE-LOCKED LOOP (PLL) Normalized In-Band Phase Noise Floor 1 PLL Settling EXTERNAL VCO Tuning Range Pin L2 Input Sensitivity REFERENCE INPUT Crystal Reference 2 External Oscillator2, 3 Crystal Start-Up Time 4 XTAL Bias = 20 μA XTAL Bias = 35 μA Input Level for External Oscillator OSC1 Pin OSC2 Pin ADC PARAMETERS Integral Nonlinearity (INL) Differential Nonlinearity (DNL) Min Typ RF/256 Max Unit Test Conditions/Comments 24 MHz Maximum usable PFD at a particular RF frequency is limited by the minimum N divider value −203 dBc/Hz 155 μs 0.2 0 2 3.625 3.625 24 24 V dBm Measured for a 100 kHz frequency step to within 5 ppm accuracy, PFD = 19.68 MHz, LBW = 8 kHz VCO frequency < 1920 MHz MHz MHz 10 MHz XTAL, 33 pF load capacitors, VDD = 3.0 V 0.930 0.438 ms ms 0.8 CMOS levels V p-p V Clipped sine wave VDD = 2.3 V to 3.6 V, TA = 25°C ±0.4 ±0.4 LSB LSB 1 This value can be used to calculate the in-band phase noise for any operating frequency. Use the following equation to calculate the in-band phase noise performance as seen at the power amplifier (PA) output: −203 + 10 log(fPFD) + 20 logN. Guaranteed by design. Sample tested to ensure compliance. 3 A TCXO, VCXO, or OCXO can be used as an external oscillator. 4 Crystal start-up time is the time from chip enable (CE) being asserted to correct clock frequency on the CLKOUT pin. 2 Rev. 0 | Page 4 of 60 ADF7021-V TRANSMISSION SPECIFICATIONS LBW = loop bandwidth. Table 2. Parameter DATA RATE 2FSK 3FSK 4FSK MODULATION Frequency Deviation (fDEV) Frequency Deviation Resolution Gaussian Filter Bandwidth Time (BT) Raised Cosine Filter Alpha TRANSMIT POWER Maximum Transmit Power 1 Transmit Power Variation vs. Temperature Transmit Power Variation vs. VDD Transmit Power Flatness Programmable Step Size ADJACENT CHANNEL POWER (ACP) Min Typ Max Unit 0.05 0.05 0.05 18.5 18.5 24 kbps kbps kbps Test Conditions/Comments Limited by the loop bandwidth LBW must be ≥1.25 × data rate for correct operation LBW = 18.5 kHz LBW = 18.5 kHz 0.056 0.306 56 28.26 156 kHz kHz Hz PFD = 3.625 MHz PFD = 20 MHz PFD = 3.625 MHz 0.5 0.5/0.7 Programmable 13 ±1 dBm dB VDD = 3.0 V, TA = 25°C TA = −40°C to +85°C ±1 ±1 0.3125 dB dB dB VDD = 2.3 V to 3.6 V at 915 MHz, TA = 25°C 902 MHz to 928 MHz, VDD = 3 V, TA = 25°C −16 dBm to +13 dBm Gaussian 2FSK modulation, 13 dBm output power, PFD = 19.68 MHz, LBW = 6 kHz 460 MHz 12.5 kHz Channel Spacing −47 dBm 25 kHz Channel Spacing −53 dBm 868 MHz 12.5 kHz Channel Spacing −44 dBm 25 kHz Channel Spacing −49 dBm Measured in a ±8.5 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, fDEV = 1.2 kHz Measured in a ±16 kHz bandwidth at ±25 kHz offset, 4.8 kbps PN9 data, fDEV = 2.4 kHz Compliant with ETSI EN 300 220 Measured in a ±8.5 kHz bandwidth at ±12.5 kHz offset, 2.4 kbps PN9 data, fDEV = 1.2 kHz Measured in a ±16 kHz bandwidth at ±25 kHz offset, 4.8 kbps PN9 data, fDEV = 2.4 kHz 869.525 MHz, Gaussian 2FSK modulation, 4.8 kbps, fDEV = 2.4 kHz, 10 dBm output power, 2 compliant with ETSI EN 300 220, LBW = 6 kHz −74.5 −79 −69.5 −62 dBm/1 kHz dBm/1 kHz dBm/10 kHz dBm/100 kHz MODULATION BANDWIDTH 125 kHz Offset 125 kHz + 200 kHz 125 kHz + 400 kHz 125 kHz + 1 MHz EMISSION MASK 12.5 kHz Offset 460 MHz OCCUPIED BANDWIDTH 2FSK, Gaussian Data Filtering 12.5 kHz Channel Spacing 25 kHz Channel Spacing 2FSK, Raised Cosine Data Filtering 12.5 kHz Channel Spacing 25 kHz Channel Spacing FCC Part 90 Emission Mask D, 100 Hz resolution bandwidth, Gaussian 2FSK modulation, LBW = 6 kHz, 10 dBm output power, 2.4 kbps PN9 data, fDEV = 1.2 kHz −77 dBc 99.0% of total mean power, LBW = 6 kHz, 10 dBm output power 4.0 8.5 kHz kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz 4.5 9.6 kHz kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz Rev. 0 | Page 5 of 60 ADF7021-V Parameter 3FSK, Raised Cosine Filtering 12.5 kHz Channel Spacing 25 kHz Channel Spacing 4FSK, Raised Cosine Filtering 25 kHz Channel Spacing SPURIOUS EMISSIONS Reference Spurs HARMONICS 3 Second Harmonic Third Harmonic All Other Harmonics OPTIMUM PA LOAD IMPEDANCE fRF = 915 MHz fRF = 868 MHz fRF = 470 MHz fRF = 450 MHz fRF = 426 MHz fRF = 315 MHz fRF = 175 MHz fRF = 169 MHz 1 2 3 Min Typ Max Unit Test Conditions/Comments 4.3 8.5 kHz kHz 2.4 kbps PN9 data, fDEV = 1.2 kHz 4.8 kbps PN9 data, fDEV = 2.4 kHz 11.3 kHz 9.6 kbps PN9 data, fDEV = 1.2 kHz −65 dBc −35/−52 −43/−60 −36/−65 dBc dBc dBc LBW = 8 kHz 13 dBm output power Unfiltered conductive/filtered conductive Unfiltered conductive/filtered conductive Unfiltered conductive/filtered conductive 39 + j61 48 + j54 97.5 + j64.4 98 + j65 100 + j65 129 + j63 173 + j49 74.5 + j48.5 Ω Ω Ω Ω Ω Ω Ω Ω Measured as maximum unmodulated power. Suitable for ETSI 500 mW Tx requirements. Conductive filtered harmonic emissions measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor). RECEIVER SPECIFICATIONS LBW = loop bandwidth and IFBW = IF filter bandwidth. Table 3. Parameter DATA RATE 2FSK 3FSK 4FSK SENSITIVITY 2FSK Sensitivity at 0.25 kbps Sensitivity at 1 kbps Sensitivity at 2.4 kbps Sensitivity at 4.8 kbps Sensitivity at 9.6 kbps Gaussian 2FSK Sensitivity at 0.25 kbps Sensitivity at 1 kbps Sensitivity at 2.4 kbps Sensitivity at 4.8 kbps Sensitivity at 9.6 kbps GMSK Sensitivity at 4.8 kbps Min Typ 0.05 0.05 0.05 0.05 0.05 Max Unit 9.0 13.5 18.5 18.5 24 kbps kbps kbps kbps kbps Test Conditions/Comments Limited by the IF filter bandwidth 1 IFBW = 9 kHz IFBW = 13.5 kHz IFBW = 18.5 kHz IFBW = 18.5 kHz IFBW = 18.5 kHz Bit error rate (BER) = 10−3 −125 −122 −119 −116 −114 dBm dBm dBm dBm dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz −125 −122 −120 −117 −114 dBm dBm dBm dBm dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz −114.5 dBm fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz Rev. 0 | Page 6 of 60 ADF7021-V Parameter Raised Cosine 2FSK Sensitivity at 0.25 kbps Sensitivity at 1 kbps Sensitivity at 2.4 kbps Sensitivity at 4.8 kbps Sensitivity at 9.6 kbps 3FSK Sensitivity at 4.8 kbps Min Typ Max Unit Test Conditions/Comments −125 −121 −120 −115 −114 dBm dBm dBm dBm dBm fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 1 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 1.2 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 2.4 kHz, high sensitivity mode, IFBW = 9.0 kHz fDEV = 4.8 kHz, high sensitivity mode, IFBW = 18.5 kHz −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 18.5 kHz, Viterbi detection on Raised Cosine 3FSK Sensitivity at 4.8 kbps −110 dBm fDEV = 2.4 kHz, high sensitivity mode, IFBW = 13.5 kHz, alpha = 0.5, Viterbi detection on 4FSK Sensitivity at 4.8 kbps −112 dBm fDEV (inner) 2 = 1.2 kHz, high sensitivity mode, IFBW = 13.5 kHz Raised Cosine 4FSK Sensitivity at 4.8 kbps −109 dBm −3 dBm fDEV (inner)2 = 1.2 kHz, high sensitivity mode, IFBW = 13.5 kHz, alpha = 0.5 Two-tone test, fLO = 860 MHz, f1 = fLO + 100 kHz, f2 = fLO − 800 kHz LNA_GAIN = 3, MIXER_LINEARITY = 1 −13.5 −24 dBm dBm LNA_GAIN = 10, MIXER_LINEARITY = 0 LNA_GAIN = 30, MIXER_LINEARITY = 0 INPUT IP3 Low Gain, Enhanced Linearity Mode Medium Gain Mode High Sensitivity Mode ADJACENT CHANNEL REJECTION (ACR) 868 MHz 12.5 kHz Channel Spacing 25 kHz Channel Spacing 12.5 kHz Channel Spacing 25 kHz Channel Spacing 12.5 kHz Channel Spacing 25 kHz Channel Spacing 12.5 kHz Channel Spacing 25 kHz Channel Spacing 25 kHz Channel Spacing 460 MHz −60 −39 −60 −40 −59.5 −42 −63 −45 −57 dBm dBm dBm dBm dBm dBm dBm dBm dBm 12.5 kHz Channel Spacing 25 kHz Channel Spacing 12.5 kHz Channel Spacing 25 kHz Channel Spacing 12.5 kHz Channel Spacing 25 kHz Channel Spacing 12.5 kHz Channel Spacing 25 kHz Channel Spacing 25 kHz Channel Spacing COCHANNEL REJECTION −59.5 −37.5 −60 −41 −62 −43 −61.5 −44.5 −56 dBm dBm dBm dBm dBm dBm dBm dBm dBm −5 dB 868 MHz Rev. 0 | Page 7 of 60 Desired signal is 3 dB above the sensitivity point of −109.5 dBm as per EN 300 220; rejection is measured as the level of an unmodulated interferer to cause a BER of 10−2 for the desired signal IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz IFBW = 18.5 kHz, data rate = 9.6 kbps, fDEV = 4.8 kHz, LBW = 6 kHz Desired signal is at −106.5 dBm; rejection is measured as the level of an unmodulated interferer to cause a BER of 10−2 for the desired signal IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 0.25 kbps, fDEV = 1 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 1 kbps, fDEV = 1 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 2.4 kbps, fDEV = 1.2 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz IFBW = 18.5 kHz, data rate = 9.6 kbps, fDEV = 4.8 kHz, LBW = 6 kHz Desired signal is 3 dB above the sensitivity point of −109.5 dBm; rejection is measured as the level of an interferer to cause a BER of 10−2 for the desired signal IFBW = 9 kHz, data rate = 4.8 kbps, fDEV = 2.4 kHz, LBW = 6 kHz ADF7021-V Parameter IMAGE CHANNEL REJECTION Min Typ Max Unit Test Conditions/Comments Desired signal (2FSK, 9.6 kbps, ±4 kHz deviation) is 3 dB above the sensitivity point (BER = 10−2); modulated interferer (2FSK, 9.6 kbps, ±4 kHz deviation) is placed at the image frequency of fRF − 200 kHz; the interferer level is increased until BER = 10−2 Uncalibrated/calibrated, 3 VDD = 3.0 V, TA = 25°C Uncalibrated/calibrated,3 VDD = 3.0 V, TA = 25°C Desired signal is 3 dB above the sensitivity point of −109.5 dBm; rejection is measured as the level of an unmodulated interferer to cause a BER of 10−2 for the desired signal; as per ETSI EN 300 220-1 868 MHz 460 MHz BLOCKING 26/39 29/50 dB dB ±1 MHz ±2 MHz ±5 MHz ±10 MHz SATURATION (MAXIMUM INPUT LEVEL) RECEIVED SIGNAL STRENGTH INDICATION (RSSI) Input Power Range 4 Linearity Absolute Accuracy Response Time AUTOMATIC FREQUENCY LOOP (AFC) Pull-In Range, Minimum Pull-In Range, Maximum −29.5 −26.5 −26 −25.5 12 dBm dBm dBm dBm dBm 2FSK mode, BER = 10−3 −120 to −47 ±2 ±3 333 dBm dB dB μs Input power range = −100 dBm to −47 dBm Input power range = −100 dBm to −47 dBm As per AGC gain stage, AGC clock = 3 kHz 0.5 1.5 × IF_ FILTER_BW 96 0.5 kHz kHz Range is programmable in Register 10 (Bits[DB31:DB24]) Range is programmable in Register 10 (Bits[DB31:DB24]) Bits kHz Dependent on modulation index Input power range = −100 dBm to +12 dBm −54/−88 dBm External 920 MHz VCO −45/−66 dBm External 1738 MHz VCO −85/−85 dBm External 1738 MHz VCO −39/−52 dBm <1 GHz at antenna input, unfiltered conductive/filtered conductive >1 GHz at antenna input, unfiltered conductive/filtered conductive <1 GHz at antenna input, unfiltered conductive/filtered conductive >1 GHz at antenna input, unfiltered conductive/filtered conductive RFIN to RFGND; refer to the AN-859 Application Note for other frequencies 24 − j60 26 − j63 58 − j124 63 − j129 68 − j134 96 − j160 178 − j190 182.5 − j194 Ω Ω Ω Ω Ω Ω Ω Ω Response Time Accuracy Rx SPURIOUS EMISSIONS 5 External 920 MHz VCO LNA INPUT IMPEDANCE fRF = 915 MHz fRF = 868 MHz fRF = 470 MHz fRF = 450 MHz fRF = 426 MHz fRF = 315 MHz fRF = 175 MHz fRF = 169 MHz 1 Using Gaussian or raised cosine filtering. The frequency deviation should be chosen to ensure that the transmit-occupied signal bandwidth is within the receiver IF filter bandwidth. 2 4FSK fDEV is defined as the frequency spacing from the RF carrier to +fDEV or −fDEV. It is also equal to half the frequency spacing between adjacent symbols. 3 Calibration of the image rejection used an external RF source. 4 For received signal levels < −100 dBm, it is recommended that the RSSI readback value be averaged over a number of samples to improve RSSI accuracy at low input power. 5 Filtered conductive receive spurious emissions are measured on the EVAL-ADF7021-VDBxZ, which includes a T-stage harmonic filter (two inductors and one capacitor). Rev. 0 | Page 8 of 60 ADF7021-V DIGITAL SPECIFICATIONS Table 4. Parameter TIMING INFORMATION Chip Enabled to Regulator Ready Chip Enabled to Tx Mode TCXO Reference XTAL Chip Enabled to Rx Mode Min TCXO Reference XTAL Tx-to-Rx Turnaround Time LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINH/IINL Input Capacitance, CIN Control Clock Input LOGIC OUTPUTS Output High Voltage, VOH Output Low Voltage, VOL CLKOUT Rise/Fall Time CLKOUT Load Typ Max Unit Test Conditions/Comments 50 μs CREG[1:4] = 100 nF 1 2 ms ms 1.2 2.2 AGC settling + (5 × tBIT) ms ms ms 0.7 × VDD 0.2 × VDD ±1 10 50 V V μA pF MHz 0.4 5 10 V V ns pF VDD2 − 0.4 Rev. 0 | Page 9 of 60 32-bit register write time = 50 μs Depends on VCO settling Depends on VCO settling 32-bit register write time = 50 μs, IF filter coarse calibration only Depends on VCO settling Depends on VCO settling Time to synchronized data output; includes AGC settling (three AGC levels) and CDR synchronization; tBIT = data bit period; AFC settling not included IOH = 500 μA IOL = 500 μA ADF7021-V GENERAL SPECIFICATIONS Table 5. Parameter TEMPERATURE RANGE (TA) POWER SUPPLIES Voltage Supply, VDD TRANSMIT CURRENT CONSUMPTION 1, 2 868 MHz 0 dBm 5 dBm 10 dBm 460 MHz 0 dBm 5 dBm 10 dBm RECEIVE CURRENT CONSUMPTION2 868 MHz Low Current Mode High Sensitivity Mode 460 MHz Low Current Mode High Sensitivity Mode POWER-DOWN CURRENT CONSUMPTION2 Low Power Sleep Mode Min −40 Typ 2.3 Max +85 Unit °C Test Conditions/Comments 3.6 V All VDDx pins must be tied together VDD = 3.0 V, PA is matched into 50 Ω 17.6 20.8 27.1 mA mA mA 13.8 17 23 mA mA mA VDD = 3.0 V 19.3 21.7 mA mA 16.3 18.3 mA mA 0.1 1 μA CE low 1 The transmit current consumption tests used the same combined PA and LNA matching network as that used on the EVAL-ADF7021-VDBxZ evaluation boards. Improved PA efficiency is achieved by using a separate PA matching network. 2 Device current only. VCO and TCXO currents are excluded. TIMING CHARACTERISTICS VDD = 3 V ± 10%, GND = 0 V, TA = 25°C, unless otherwise noted. Guaranteed by design but not production tested. Table 6. Parameter t1 t2 t3 t4 t5 t6 t8 t9 t10 t11 t12 t13 t14 t15 Limit at TMIN to TMAX >10 >10 >25 >25 >10 >20 <25 <25 >10 5 < t11 < (¼ × tBIT) >5 >5 5 < t14 < (¼ × tBIT) >¼ × tBIT Unit ns ns ns ns ns ns ns ns ns ns ns ns μs μs Description SDATA to SCLK setup time SDATA to SCLK hold time SCLK high duration SCLK low duration SCLK to SLE setup time SLE pulse width SCLK to SREAD data valid, readback SREAD hold time after SCLK, readback SCLK to SLE disable time, readback TxRxCLK negative edge to SLE TxRxDATA to TxRxCLK setup time (Tx mode) TxRxCLK to TxRxDATA hold time (Tx mode) TxRxCLK negative edge to SLE SLE positive edge to positive edge of TxRxCLK (Rx mode) Rev. 0 | Page 10 of 60 ADF7021-V TIMING DIAGRAMS Serial Interface t3 t4 SCLK t1 SDATA DB31 (MSB) t2 DB2 (CONTROL BIT C3) DB30 DB1 (CONTROL BIT C2) DB0 (LSB) (CONTROL BIT C1) t6 08635-002 SLE t5 Figure 2. Serial Interface Timing Diagram t1 t2 SCLK SDATA REG 7 DB0 (CONTROL BIT C1) SLE t3 t10 RV16 RV2 RV15 RV1 X 08635-003 X SREAD t9 t8 Figure 3. Serial Interface Readback Timing Diagram 2FSK/3FSK Timing ±1 × DATA RATE/32 1/DATA RATE TxRxCLK TxRxDATA 08635-004 DATA Figure 4. TxRxDATA/TxRxCLK Timing Diagram in Receive Mode 1/DATA RATE TxRxCLK TxRxDATA FETCH 08635-005 DATA SAMPLE Figure 5. TxRxDATA/TxRxCLK Timing Diagram in Transmit Mode Rev. 0 | Page 11 of 60 ADF7021-V 4FSK Timing In 4FSK receive mode, MSB/LSB synchronization should be guaranteed by detection of the SWD pin in the receive bit stream. REGISTER 0 WRITE SWITCH FROM Rx TO Tx tSYMBOL t13 t12 t11 tBIT SLE TxRxCLK Rx SYMBOL MSB Rx SYMBOL LSB Tx/Rx MODE Rx SYMBOL MSB Rx SYMBOL LSB Tx SYMBOL MSB Tx SYMBOL LSB Rx MODE Tx SYMBOL MSB Tx MODE 08635-006 TxRxDATA Figure 6. Receive-to-Transmit Timing Diagram in 4FSK Mode REGISTER 0 WRITE SWITCH FROM Tx TO Rx t15 tSYMBOL t14 tBIT SLE TxRxCLK Tx/Rx MODE Tx SYMBOL MSB Tx SYMBOL LSB Tx SYMBOL MSB Tx SYMBOL LSB Rx SYMBOL MSB Tx MODE Figure 7. Transmit-to-Receive Timing Diagram in 4FSK Mode Rev. 0 | Page 12 of 60 Rx SYMBOL LSB Rx MODE 08635-007 TxRxDATA ADF7021-V UART/SPI Mode UART mode is enabled by setting Register 0, Bit DB28 to 1. SPI mode is enabled by setting Register 0, Bit DB28 to 1 and setting Register 15, Bits[DB19:DB17] to 0x7. The transmit/receive data clock is available on the CLKOUT pin. tBIT CLKOUT (TRANSMIT/RECEIVE DATA CLOCK IN SPI MODE. NOT USED IN UART MODE.) Tx BIT SAMPLE Tx BIT TxRxDATA (RECEIVE DATA OUTPUT IN UART/SPI MODE.) Tx BIT Tx BIT Tx BIT HIGH-Z Tx/Rx MODE 08635-008 TxRxCLK (TRANSMIT DATA INPUT IN UART/SPI MODE.) FETCH Tx MODE Figure 8. Transmit Timing Diagram in UART/SPI Mode tBIT CLKOUT (TRANSMIT/RECEIVE DATA CLOCK IN SPI MODE. NOT USED IN UART MODE.) FETCH SAMPLE TxRxCLK (TRANSMIT DATA INPUT IN UART/SPI MODE.) Tx/Rx MODE Rx BIT Rx BIT Rx BIT Rx BIT Rx MODE Figure 9. Receive Timing Diagram in UART/SPI Mode Rev. 0 | Page 13 of 60 Rx BIT 08635-009 TxRxDATA (RECEIVE DATA OUTPUT IN UART/SPI MODE.) HIGH-Z ADF7021-V ABSOLUTE MAXIMUM RATINGS TA = 25°C, unless otherwise noted. Table 7. Parameter VDD to GND1 Analog I/O Voltage to GND1 Digital I/O Voltage to GND1 Operating Temperature Range Industrial (B Version) Storage Temperature Range Maximum Junction Temperature MLF θJA Thermal Impedance Reflow Soldering Peak Temperature Time at Peak Temperature 1 Rating −0.3 V to +5 V −0.3 V to VDDx + 0.3 V −0.3 V to VDDx + 0.3 V −40°C to +85°C −65°C to +125°C 150°C 26°C/W 260°C 40 sec Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. This device is a high performance RF integrated circuit with an ESD rating of <2 kV, and it is ESD sensitive. Proper precautions should be taken for handling and assembly. ESD CAUTION GND = GND1 = GND2 = GND4 = RFGND = 0 V. Rev. 0 | Page 14 of 60 ADF7021-V CVCO GND1 L1 GND L2 VDD CPOUT CREG3 VDD3 OSC1 OSC2 MUXOUT 48 47 46 45 44 43 42 41 40 39 38 37 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS PIN 1 INDICATOR 5 32 6 ADF7021-V VDD2 RFIN 31 CREG2 RFIN 7 TOP VIEW (Not to Scale) 30 ADCIN RLNA 8 29 GND2 VDD4 9 28 SCLK RSET 10 27 SREAD CREG4 11 26 SDATA GND4 12 25 SLE NOTES 1. THE EXPOSED PADDLE MUST BE CONNECTED TO THE GROUND PLANE. 08635-011 CE 24 RFGND TEST_A 23 SWD GND4 22 33 FILT_Q 21 4 FILT_Q 20 TxRxDATA RFOUT GND4 19 34 FILT_I 18 3 FILT_I 17 TxRxCLK VDD1 MIX_Q 16 CLKOUT 35 MIX_Q 15 36 2 MIX_I 14 1 MIX_I 13 VCOIN CREG1 Figure 10. Pin Configuration Table 8. Pin Function Descriptions Pin No. 1 2 Mnemonic VCOIN CREG1 3 VDD1 4 RFOUT 5 6 RFGND RFIN 7 8 9 RFIN RLNA VDD4 10 RSET 11 CREG4 12, 19, 22 13 to 16 23 24 GND4 MIX_I, MIX_I, MIX_Q, MIX_Q FILT_I, FILT_I, FILT_Q, FILT_Q, TEST_A CE 25 SLE 26 SDATA 17, 18, 20, 21 Description Do not connect. Regulator Voltage for PA Block. Place a series 3.9 Ω resistor and a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. Voltage Supply for PA Block. Place decoupling capacitors of 0.1 μF and 100 pF as close as possible to this pin. Tie all VDDx pins together. The modulated signal is available at this pin. Output power levels are from −16 dBm to +13 dBm. The output should be impedance matched to the desired load using suitable components. Ground for Output Stage of Transmitter. Tie all GND pins together. LNA Input for Receiver Section. Input matching is required between the antenna and the differential LNA input to ensure maximum power transfer. Complementary LNA Input. External Bias Resistor for LNA. Optimum resistor is 1.1 kΩ with 5% tolerance. Voltage Supply for LNA/Mixer Block. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins together. External Resistor. Sets charge pump current and some internal bias currents. Use a 3.6 kΩ resistor with 5% tolerance. Regulator Voltage for LNA/Mixer Block. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. Ground for LNA/Mixer Block. Tie all GND pins together. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Signal Chain Test Pins. These pins are high impedance under normal conditions and should be left unconnected. Signal Chain Test Pin. This pin is high impedance under normal conditions and should be left unconnected. Chip Enable. Bringing CE low puts the ADF7021-V into complete power-down. Register values are lost when CE is low, and the part must be reprogrammed after CE is brought high. Load Enable, CMOS Input. When SLE goes high, the data stored in the shift registers is loaded into one of the 16 latches. A latch is selected using the control bits. Serial Data Input. The serial data is loaded MSB first with the four LSBs as the control bits. This pin is a high impedance CMOS input. Rev. 0 | Page 15 of 60 ADF7021-V Pin No. 27 Mnemonic SREAD 28 SCLK 29 30 GND2 ADCIN 31 CREG2 32 VDD2 33 SWD 34 TxRxDATA 35 TxRxCLK 36 CLKOUT 37 MUXOUT 38 OSC2 39 OSC1 40 VDD3 41 CREG3 42 CPOUT 43 VDD 44 45 46 47 48 EP L2 GND L1 GND1 CVCO Exposed Paddle Description Serial Data Output. This pin is used to feed readback data from the ADF7021-V to the microcontroller. The SCLK input is used to clock each readback bit (for example, AFC or ADC) from the SREAD pin. Serial Clock Input. The serial clock is used to clock in the serial data to the registers. The data is latched into the 32-bit shift register on the SCLK rising edge. This pin is a digital CMOS input. Ground for Digital Block. Tie all GND pins together. Analog-to-Digital Converter Input. The internal 7-bit ADC can be accessed through this pin. Full scale is 0 V to 1.9 V. Readback is through the SREAD pin. Regulator Voltage for Digital Block. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. Voltage Supply for Digital Block. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie all VDDx pins together. Sync Word Detect. The ADF7021-V asserts this pin when it finds a match for the sync word sequence. This provides an interrupt for an external microcontroller, indicating that valid data is being received. Transmit Data Input/Received Data Output. This is a digital pin, and normal CMOS levels apply. In UART/SPI receive mode, this pin provides an output for the received data. In UART/SPI transmit mode, this pin is high impedance. Outputs the data clock in both receive and transmit modes. This is a digital pin, and normal CMOS levels apply. The positive clock edge is matched to the center of the received data. In standard transmit mode, this pin outputs an accurate clock to latch the data from the microcontroller into the transmit section at the exact required data rate. In UART/SPI transmit mode, this pin is used to input the transmit data. In UART/SPI receive mode, this pin is high impedance. Divided-Down Version of the Crystal Reference with Output Driver. The digital clock output can be used to drive several other CMOS inputs, such as a microcontroller clock. The output has a 50:50 mark/space ratio and is inverted with respect to the reference. Place a series 1 kΩ resistor as close as possible to the pin in applications where the CLKOUT feature is used. Provides the DIGITAL_LOCK_DETECT signal. This signal is used to determine whether the PLL is locked to the correct frequency. It also provides other signals such as REGULATOR_READY, which is an indicator of the status of the serial interface regulator. Connect the reference crystal between this pin and OSC1. A TCXO reference can be used by driving this pin with CMOS levels and disabling the internal crystal oscillator. Connect the reference crystal between this pin and OSC2. A TCXO reference can be used by driving this pin with ac-coupled 0.8 V p-p levels and by enabling the internal crystal oscillator. Voltage Supply for Charge Pump and PLL Dividers. Decouple this pin to ground with a 10 nF capacitor. Tie all VDDx pins together. Regulator Voltage for Charge Pump and PLL Dividers. Place a 100 nF capacitor between this pin and ground for regulator stability and noise rejection. Charge Pump Output. This output generates current pulses that are integrated in the loop filter. The integrated current changes the control voltage on the input to the VCO. Voltage Supply for RF Circuitry. Place a decoupling capacitor of 10 nF as close as possible to this pin. Tie all VDDx pins together. VCO Buffer Input. Ground. Tie all GND pins together. Do not connect. Ground. Tie all GND pins together. Do not connect. The exposed paddle must be connected to the ground plane. Rev. 0 | Page 16 of 60 ADF7021-V TYPICAL PERFORMANCE CHARACTERISTICS –80 16 RF FREQ = 460MHz TCXO = 19.2MHz 8 –100 –110 ICP = 0.3mA ICP = 0.9mA –120 PA_BIAS = 11µA 12 RF OUTPUT POWER (dBm) PHASE NOISE (dBc/Hz) –90 –130 –140 PA_BIAS = 9µA 4 0 PA_BIAS = 5µA –4 PA_BIAS = 7µA –8 –12 –16 –20 –24 –28 –32 –150 10 100 1k FREQUENCY OFFSET (kHz) 10k 100k –40 08635-077 1 0 8 12 16 20 24 28 32 36 40 44 48 52 56 60 PA SETTING Figure 11. Phase Noise Response at 460 MHz, VDD = 3 V Figure 14. RF Output Power vs. PA Setting –60 20 RF FREQ = 868MHz TCXO = 19.2MHz –70 0 OUTPUT POWER (dBm) –80 PHASE NOISE (dBc/Hz) 4 08635-012 –36 –160 –90 ICP = 0.3mA ICP = 0.9mA ICP = 1.5mA ICP = 2.1mA –100 –110 –120 –130 –20 –40 –60 –140 –80 10 100 1k FREQUENCY OFFSET (kHz) 10k –100 300 Figure 12. Phase Noise Response at 868 MHz, VDD = 2.3 V DEMODULATION = GFSK OUTPUT POWER (dBm) –10 –40 –50 –20 2FSK –30 GFSK –40 –50 25,000 FREQUENCY OFFSET FROM CARRIER (Hz) 08635-079 20,000 –80 867.97 15,000 –80 10,000 –70 5000 –70 0 –60 –5000 –60 –10,000 2800 DATA RATE = 9.6kbps DATA = PRBS9 fDEV = 2.4kHz RF FREQ = 868MHz 0 –30 –15,000 2300 10 –20 –20,000 1300 1800 FREQUENCY (MHz) Figure 15. PA Output Harmonic Response with T-Stage LC Filter FCC PART 90 EMISSION MASK D 10 DATA RATE = 2.4kbps fDEV = 1.2kHz 0 RF FREQ = 470MHz IFBW = 4kHz –10 –25,000 OUTPUT POWER (dBm) 20 800 867.98 867.99 868.00 868.01 FREQUENCY (MHz) 868.02 Figure 16. Output Spectrum in 2FSK and GFSK Modes Figure 13. Output Spectrum in FCC Part 90 Emission Mask D and GFSK Modes Rev. 0 | Page 17 of 60 868.03 08635-014 1 08635-078 –160 08635-013 –150 ADF7021-V 10 DATA RATE = 9.6kbps DATA = PRBS9 fDEV = 2.4kHz RF FREQ = 868MHz 0 –20 –30 2FSK –40 –50 –20 –30 –40 867.99 868.00 868.01 FREQUENCY (MHz) 868.02 868.03 –60 –100 08635-015 867.98 50 100 Figure 20. Output Spectrum in Maximum Hold for Various PA Ramp Rate Options 0 10 DATA RATE = 9.6kbps DATA = PRBS9 fDEV = 2.4kHz RF FREQ = 868MHz 0 –10 DATA RATE = 2.4kbps fDEV = 4.8Hz RF FREQ = 868MHz IFBW = 9kHz –1 –2 –20 LOG BER –30 3FSK –40 –3 –4 –50 –5 –60 RC3FSK –6 –70 867.98 867.99 868.00 868.01 FREQUENCY (MHz) 868.02 868.03 –7 –125 –123 –121 –119 –117 –115 –113 –111 –109 –107 –105 RF INPUT POWER (dBm) 08635-016 –80 867.97 Figure 18. Output Spectrum in 3FSK and Raised Cosine 3FSK Modes Figure 21. 2FSK Sensitivity vs. VDD and Temperature at 868 MHz 0 10 DATA RATE = 9.6kbps DATA = PRBS9 fDEV = 2.4kHz RF FREQ = 868MHz 0 –10 DATA RATE = 1.2kbps fDEV = 2.4Hz RF FREQ = 460MHz IFBW = 9kHz –1 –2 –20 LOG BER –30 4FSK –40 –50 –60 –3 –4 –5 RC4FSK –70 –6 867.96 867.98 868.00 868.02 FREQUENCY (MHz) 868.04 868.06 08635-017 –80 –90 867.94 –40°C, 2.3V –40°C, 3V –40°C, 3.6V +25°C, 2.3V +25°C, 3V +25°C, 3.6V +85°C, 2.3V +85°C, 3V +85°C, 3.6V 08635-019 OUTPUT POWER (dBm) 0 FREQUENCY OFFSET (kHz) Figure 17. Output Spectrum in 2FSK and Raised Cosine 2FSK Modes OUTPUT POWER (dBm) –50 Figure 19. Output Spectrum in 4FSK and Raised Cosine 4FSK Modes –7 –127 –40°C, 2.3V –40°C, 3V –40°C, 3.6V +25°C, 2.3V +25°C, 3V +25°C, 3.6V +85°C, 2.3V +85°C, 3V +85°C, 3.6V –125 –123 –121 –119 –117 –115 RF INPUT POWER (dBm) –113 –111 Figure 22. 2FSK Sensitivity vs. VDD and Temperature at 460 MHz Rev. 0 | Page 18 of 60 08635-018 –50 –70 –80 867.97 TRACE = MAX HOLD PA ON/OFF RATE = 3Hz PA ON/OFF CYCLES = 10,000 VDD = 3.0V –10 RC2FSK –60 RAMP RATE: CW ONLY 256 CODES/BIT 128 CODES/BIT 64 CODES/BIT 32 CODES/BIT 08635-020 OUTPUT POWER (dBm) –10 10 OUTPUT POWER (dBm) 0 ADF7021-V 0.6 0.5 0.2 RSSI LEVEL (dBm) 0.3 –60 –80 –100 ACTUAL RF INPUT LEVEL –125 –120 –115 RF INPUT POWER (dBm) –110 –105 –140 –122.5 –112.5 –102.5 –92.5 –82.5 –72.5 –62.5 RF INPUT POWER (dBm) 08635-021 0 –130 –52.5 08635-023 –120 0.1 –42.5 Figure 26. Digital RSSI Readback Linearity Figure 23. 2FSK Sensitivity vs. VDD and Temperature at 868 MHz 0.6 80 DATA RATE = 1.2kbps fDEV = 2.4Hz RF FREQ = 460MHz IFBW = 9kHz 0.5 70 60 BLOCKING (dB) 0.4 BIT ERROR RATE RSSI READBACK LEVEL –40 –40°C, 2.3V –40°C, 3V –40°C, 3.6V +25°C, 2.3V +25°C, 3V +25°C, 3.6V +85°C, 2.3V +85°C, 3V +85°C, 3.6V 0.4 BIT ERROR RATE –20 DATA RATE = 1.2kbps fDEV = 2.4Hz RF FREQ = 868MHz IFBW = 9kHz –40°C, 2.3V –40°C, 3V –40°C, 3.6V +25°C, 2.3V +25°C, 3V +25°C, 3.6V +85°C, 2.3V +85°C, 3V +85°C, 3.6V 0.3 0.2 0.1 50 40 30 20 CALIBRATED UNCALIBRATED 10 BLOCKER FREQUENCY (MHz) Figure 24. 2FSK Sensitivity vs. VDD and Temperature at 460 MHz 80 ATTENUATION (dB) BLOCKING (dB) 70 60 50 40 30 20 10 –10 –5 0 5 10 FREQUENCY OFFSET (MHz) 15 20 08635-024 0 2.5 0 +90°C –2.5 –5.0 –7.5 –10.0 –12.5 –15.0 –17.5 –20.0 –22.5 –25.0 –27.5 –30.0 –32.5 –35.0 –37.5 90 92 –40°C 94 96 98 100 102 IF FREQUENCY (kHz) Figure 25. Wideband Interference Rejection (Modulated Carrier Is Swept 20 MHz Either Side of an 868 MHz Modulated GFSK 2.4 kHz/4.8 kbps Wanted Signal at the Sensitivity Point (−106.5 dBm); the Power Level of the Blocker Is Adjusted to Give a BER of 10−2; Interferer Is a GFSK PRBS15 4.8 kHz/2.4 kHz Signal) 104 106 108 110 08635-025 90 –15 460.15 Figure 27. Image Rejection, Uncalibrated vs. Calibrated 100 –10 –20 08635-080 460.10 460.05 460.00 459.95 –10 459.90 –105 459.85 –110 459.80 –120 –115 RF INPUT POWER (dBm) 459.70 –125 08635-022 0 –130 459.75 0 Figure 28. Variation of IF Filter Response with Temperature (IF_FILTER_BW = 9 kHz, Temperature Range Is −40°C to +90°C in 10° Steps) Rev. 0 | Page 19 of 60 ADF7021-V –70 –100 RF FREQ = 860MHz 2FSK MODULATION DATA RATE = 9.6kbps IFBW = 25kHz VDD = 3.0V TEMPERATURE = 25°C –104 –106 –108 DISCRIMINATOR BANDWIDTH = 2× FSK FREQUENCY DEVIATION –110 –112 –90 IP3 = –5dBm –100 2FSK MODULATION DATA RATE = 9.6kbps fDEV = 4kHz IFBW = 12.5kHz DEMOD = CORRELATOR SENSITIVITY @ BER = 10–3 IP3 = –9dBm IP3 = –3dBm IP3 = –20dBm –110 –114 –120 –116 HIGH MIXER LINEARITY –80 SENSITIVITY (dBm) DEFAULT MIXER LINEARITY IP3 = –13.5dBm IP3 = –24dBm DISCRIMINATOR BANDWIDTH = 1× FSK FREQUENCY DEVIATION 0 0.2 0.4 0.6 0.8 1.0 1.2 MODULATION INDEX –130 08635-026 –118 3, 72 10, 72 30, 72 (LOW GAIN MODE) (MEDIUM GAIN MODE) (HIGH GAIN MODE) LNA GAIN, FILTER GAIN Figure 31. 2FSK Receiver Sensitivity vs. LNA Gain/IF Filter Gain and Mixer Linearity Settings (Input IP3 at Each Setting Also Shown) Figure 29. 2FSK Sensitivity vs. Modulation Index and Correlator Discriminator Bandwidth 0 –1 THRESHOLD DETECTION –2 –4 –6 3FSK MODULATION VDD = 3.0V, TEMP = 25°C DATA RATE = 9.6kbps fDEV = 2.4kHz RF FREQ = 868MHz IFBW = 18.75kHz –7 –120 –118 –116 –114 –112 –110 –108 –106 –104 –102 –100 INPUT POWER (dBm) 08635-027 LOG BER VITERBI DETECTION –3 –5 08635-028 SENSITIVITY POINT (dBm) –102 Figure 30. 3FSK Receiver Sensitivity Using Viterbi Detection and Threshold Detection Rev. 0 | Page 20 of 60 ADF7021-V FREQUENCY SYNTHESIZER REFERENCE INPUT CLKOUT Divider and Buffer The on-board crystal oscillator circuitry (see Figure 32) can use a quartz crystal as the PLL reference. A quartz crystal with a frequency tolerance of ≤10 ppm for narrow-band applications is recommended. It is possible to use a quartz crystal with >10 ppm tolerance, but compensation for the frequency error of the crystal is necessary to comply with the absolute frequency error specifications of narrow-band regulations (for example, ARIB STD-T67 and ETSI EN 300 220). The CLKOUT circuit takes the reference clock signal from the oscillator section, shown in Figure 32, and supplies a divideddown, 50:50 mark/space signal to the CLKOUT pin. The CLKOUT signal is inverted with respect to the reference clock. An even divide from 2 to 30 is available; this divide number is set in Register 1, Bits[DB10:DB7]. On power-up, the CLKOUT defaults to divide-by-8. VDD The oscillator circuit is enabled by setting Bit DB12 in Register 1 high. It is enabled by default on power-up and is disabled by bringing CE low. Errors in the crystal can be corrected using the automatic frequency control (AFC) feature or by adjusting the fractional-N value (see the N Counter section). CLKOUT ENABLE BIT DIVIDER 1 TO 15 ÷2 CLKOUT 08635-031 OSC1 Figure 33. CLKOUT Stage OSC2 CP2 CP1 08635-030 OSC1 To disable CLKOUT, set the divide number to 0. The output buffer can drive a load of up to 20 pF with a 10% rise time at 4.8 MHz. Faster edges can result in some spurious feedthrough to the output. A series resistor (1 kΩ) can be used to slow the clock edges to reduce these spurs at the CLKOUT frequency. Figure 32. Crystal Oscillator Circuit on the ADF7021-V Two parallel resonant capacitors are required for oscillation at the correct frequency. Their values are dependent on the crystal specification. The resonant capacitors should be selected to ensure that the series value of capacitance added to the PCB track capacitance adds up to the specified load capacitance of the crystal, usually 12 pF to 20 pF. Track capacitance values vary from 2 pF to 5 pF, depending on board layout. When possible, choose capacitors that have a very low temperature coefficient to ensure stable frequency operation over all conditions. R Counter The 3-bit R counter divides the reference input frequency by an integer from 1 to 7. The divided-down signal is presented as the reference clock to the phase frequency detector (PFD). The divide ratio is set in Register 1, Bits[DB6:DB4]. Maximizing the PFD frequency reduces the N value. This reduces the noise multiplied at a rate of 20 log(N) to the output and reduces occurrences of spurious components. Register 1 defaults to R = 1 on power-up. Using a TCXO Reference PFD (Hz) = XTAL/R • • An oscillator with CMOS output levels can be applied to OSC2. The internal oscillator circuit should be disabled by setting Bit DB12 in Register 1 low. An oscillator with 0.8 V p-p levels can be ac-coupled through a 22 pF capacitor into OSC1. The internal oscillator circuit should be enabled by setting Bit DB12 in Register 1 high. Programmable Crystal Bias Current Bias current in the oscillator circuit can be configured from 20 μA to 35 μA by writing to the XTAL_BIAS bits (Register 1, Bits[DB14:DB13]). Increasing the bias current allows the crystal oscillator to power up faster. Loop Filter The loop filter integrates the current pulses from the charge pump to form a voltage that tunes the output of the VCO to the desired frequency. It also attenuates spurious levels generated by the PLL. A typical loop filter design is shown in Figure 34. CHARGE PUMP OUT VCO 08635-032 A single-ended reference (TCXO, VCXO, or OCXO) can also be used with the ADF7021-V. This is recommended for applications that have absolute frequency accuracy requirements of <10 ppm, such as applications requiring compliance with ARIB STD-T67 or ETSI EN 300 220. The following are two options for interfacing the ADF7021-V to an external reference oscillator. Figure 34. Typical Loop Filter Configuration The loop should be designed so that the loop bandwidth (LBW) is approximately 6 kHz. This provides a good compromise between in-band phase noise and out-of-band spurious rejection. Widening the LBW excessively reduces the time spent jumping between frequencies, but it can cause insufficient spurious attenuation. The loop filter design on the EVAL-ADF7021-VDBxZ should be used for optimum performance. Rev. 0 | Page 21 of 60 ADF7021-V The free design tool ADIsimSRD™ Design Studio can also be used to design loop filters for the ADF7021-V. See the ADIsimSRD Design Studio website (www.analog.com/adisimsrd) for details). N Counter The feedback divider in the ADF7021-V PLL consists of an 8-bit integer counter (set using Register 0, Bits[DB26:DB19]) and a 15-bit, Σ-Δ fractional-N divider (set using Register 0, Bits[DB18:DB4]). The integer counter is the standard pulseswallow type that is common in PLLs. It sets the minimum integer divide value to 23. The fractional divide value provides very fine resolution at the output, where the output frequency of the PLL is calculated as f OUT = XTAL × R FRACTIONAL _ N ⎞ ⎛ ⎜⎜ INTEGER _ N + ⎟⎟ 215 ⎝ ⎠ When RF_DIVIDE_BY_2 is enabled (see the Voltage Controlled Oscillator (VCO) section), this formula becomes f OUT FRACTIONAL _ N ⎞ XTAL ⎛ = × 0.5 × ⎜ INTEGER_N + ⎟ R 2 15 ⎝ ⎠ The serial interface operates from a regulator supply. Therefore, to write to the part, CE must be high and the regulator voltage must be stabilized. Regulator status (CREG4) can be monitored using the REGULATOR_READY signal from the MUXOUT pin. MUXOUT The MUXOUT pin allows access to various digital points in the ADF7021-V. The state of MUXOUT is controlled in Register 0, Bits[DB31:DB29]. REGULATOR_READY REGULATOR_READY is the default setting on MUXOUT after the transceiver is powered up. The power-up time of the regulator is typically 50 μs. Because the serial interface is powered from the regulator, the regulator must be at its nominal voltage before the ADF7021-V can be programmed. The regulator status can be monitored at MUXOUT. When the regulator ready signal on MUXOUT is high, programming of the ADF7021-V can begin. VDD REGULATOR_READY (DEFAULT) FILTER_CAL_COMPLETE The combination of INTEGER_N (maximum = 255) and FRACTIONAL_N (maximum = 32,768/32,768) gives a maximum N divider of 255 + 1. Therefore, the minimum usable PFD is RSSI_READY Tx_Rx MUX LOGIC_ZERO TRISTATE Maximum Required Output Frequency LOGIC_ONE (255 + 1) For example, when operating in the European 868 MHz to 870 MHz band, PFDMIN = 3.4 MHz. GND Figure 36. MUXOUT Circuit REFERENCE IN ÷R MUXOUT CONTROL PFD/ CHARGE PUMP FILTER_CAL_COMPLETE VCO MUXOUT can be set to FILTER_CAL_COMPLETE. This signal goes low for the duration of both a coarse IF filter calibration and a fine IF filter calibration. It can be used as an interrupt to a microcontroller to signal the end of the IF filter calibration. ÷N THIRD-ORDER Σ-Δ MODULATOR INTEGER_N 08635-033 FRACTIONAL_N DIGITAL_LOCK_DETECT Figure 35. Fractional-N PLL Voltage Regulators The ADF7021-V contains four regulators to supply stable voltages to the part. The nominal regulator voltage is 2.3 V. Regulator 1 requires a 3.9 Ω resistor and a 100 nF capacitor in series between CREG1 and ground, whereas the other regulators require a 100 nF capacitor connected between CREGx and ground. When CE is high, the regulators and other associated circuitry are powered on, drawing a total supply current of 2 mA. Bringing the CE pin low disables the regulators, reduces the supply current to less than 1 μA, and erases all values held in the registers. DIGITAL_LOCK_DETECT indicates when the PLL has locked. The lock detect circuit is located at the PFD. When the phase error on five consecutive cycles is less than 15 ns, lock detect is set high. Lock detect remains high until a 25 ns phase error is detected at the PFD. RSSI_READY MUXOUT can be set to RSSI_READY. This indicates that the internal analog RSSI has settled and that a digital RSSI readback can be performed. Tx_Rx Tx_Rx signifies whether the ADF7021-V is in transmit or receive mode. When in transmit mode, this signal is low. When in receive mode, this signal is high. It can be used to control an external Tx/Rx switch. Rev. 0 | Page 22 of 60 08635-034 PFD MIN (Hz) = DIGITAL_LOCK_DETECT ADF7021-V The VCO tuning voltage can be checked for a particular RF output frequency by measuring the voltage on the CPOUT pin when the part is fully powered up in transmit or receive mode. The VCO tuning range of the external VCO must be 0.2 V to 2 V. VOLTAGE CONTROLLED OSCILLATOR (VCO) To minimize feedthrough and spurious emissions, the external VCO must be chosen to operate at a minimum of twice the required RF frequency. The VCO frequency is divided by 2 inside the synthesizer loop, providing the required frequency for the transmitter and for the local oscillator (LO) of the receiver. For improved phase noise performance, an additional divide-by-2 can be enabled by setting the RF_DIVIDE_BY_2 bit (Bit DB18) in Register 1. The input impedance of the L2 pin is programmable and can be selected to have a high impedance value or 50 Ω impedance, depending on the VCO selected. The impedance of this pin can be set using the BUFFER_IMPEDANCE bit (Bit DB17) in Register 1. CHOOSING A VCO FOR BEST SYSTEM PERFORMANCE As an example, for 80 MHz operation, a 160 MHz external VCO could be used with the RF_DIVIDE_BY_2 bit disabled, or a 320 MHz VCO could be used with the RF_DIVIDE_BY_2 bit enabled to support operation in the 80 MHz band. Assuming that both VCOs have similar phase noise performance, the 320 MHz design using the additional divide-by-2 should result in improved transmit ACP, as well as improved ACR, blocking, and image rejection in the receiver. The interaction between the RF VCO frequency and the reference frequency can lead to fractional spur creation. When the synthesizer is in fractional mode (that is, the RF VCO and reference frequencies are not integer related), spurs can appear on the VCO output spectrum at an offset frequency that corresponds to the difference frequency between an integer multiple of the reference and the VCO frequency. The maximum VCO frequency of operation supported on the ADF7021-V is 1920 MHz, which results in a maximum RF channel frequency of 960 MHz using a 2× VCO or 480 MHz using a 4× VCO. These spurs are attenuated by the loop filter. They are more noticeable on channels close to integer multiples of the reference where the difference frequency may be inside the loop bandwidth (thus, the name integer boundary spurs). The occurrence of these spurs is rare because the integer frequencies are around multiples of the reference, which is typically >10 MHz. To avoid having very small or very large values in the fractional register, choose a suitable reference frequency. EXTERNAL COMPONENTS LOOP FILTER ÷R ÷2 PFD/CP MUX ÷N ADF7021-V SYNTH FREQUENCY ÷2 Figure 37. Voltage Controlled Oscillator (VCO) TO PA 08635-036 REF TCXO/XTAL VCO In addition to spurious considerations, the selection of a high performance VCO with very low phase noise is essential to minimize the ACP performance of the transmitter and to maximize the ACR and blocking resilience of the receiver. Rev. 0 | Page 23 of 60 ADF7021-V TRANSMITTER 1 RF OUTPUT STAGE 2 3 4 ... 8 ... 16 DATA BITS The power amplifier (PA) of the ADF7021-V is based on a single-ended, controlled current, open-drain amplifier that has been designed to deliver up to 13 dBm into a 50 Ω load at a maximum frequency of 960 MHz. PA RAMP 0 (NO RAMP) PA RAMP 1 (256 CODES PER BIT) PA RAMP 2 (128 CODES PER BIT) The PA output current and, consequently, the output power are programmable over a wide range. The PA configuration is shown in Figure 38. The output power is set using Register 2, Bits[DB18:DB13]. PA RAMP 3 (64 CODES PER BIT) PA RAMP 4 (32 CODES PER BIT) REGISTER 2, BITS[DB12:DB11] PA RAMP 5 (16 CODES PER BIT) 2 IDAC REGISTER 2, BITS[DB18:DB13] 08635-038 PA RAMP 6 (8 CODES PER BIT) 6 PA RAMP 7 (4 CODES PER BIT) Figure 39. PA Ramping Settings RFOUT PA Bias Currents REGISTER 2, BIT DB7 FROM VCO 08635-037 REGISTER 0, BIT DB27 RFGND Figure 38. PA Configuration The PA is equipped with overvoltage protection, which makes it robust in severe mismatch conditions. Depending on the application, users can design a matching network for the PA to exhibit optimum efficiency at the desired radiated output power level for a wide range of antennas, such as loop or monopole antennas. See the LNA/PA Matching section for more information. PA Ramping The PA_BIAS bits (Register 2, Bits[DB12:DB11]) facilitate an adjustment of the PA bias current to further extend the output power control range, if necessary. If this feature is not required, the default value of 9 μA is recommended. If output power greater than 10 dBm is required, a PA bias setting of 11 μA is recommended. The output stage is powered down by resetting Register 2, Bit DB7 to 0. MODULATION SCHEMES The ADF7021-V supports 2FSK, 3FSK, and 4FSK modulation. The implementation of these modulation schemes is shown in Figure 40. When the PA is switched on or off quickly, its changing input impedance momentarily disturbs the VCO output frequency. This process is called VCO pulling, and it manifests as spectral splatter or spurs in the output spectrum around the desired carrier frequency. Some radio emissions regulations place limits on these PA transient-induced spurs (for example, the ETSI EN 300 220 regulations). By gradually ramping the PA on and off, PA transient spurs are minimized. The ADF7021-V has built-in PA ramping configurability. As Figure 39 illustrates, there are eight ramp rate settings, defined as a certain number of PA setting codes per one data bit period. The PA steps through each of its 64 code levels but at different speeds for each setting. The ramp rate is set by configuring Bits[DB10:DB8] in Register 2. PFD/ CHARGE PUMP REF TO PA STAGE LOOP FILTER ÷2 VCO ÷N FRACTIONAL_N THIRD-ORDER Σ-Δ MODULATOR INTEGER_N Tx_FREQUENCY_ DEVIATION 2FSK GAUSSIAN OR RAISED COSINE FILTERING If the PA is enabled/disabled by the PA_ENABLE bit (Register 2, Bit DB7), it ramps up and down. If it is enabled/disabled by the Tx/Rx bit (Register 0, Bit DB27), it ramps up and turns hard off. Rev. 0 | Page 24 of 60 TxRxDATA MUX 3FSK 4FSK 1 – D2 PR SHAPING PRECODER 4FSK BIT SYMBOL MAPPER Figure 40. Transmit Modulation Implementation 08635-039 + ADF7021-V Setting the Transmit Data Rate Three-Level Frequency Shift Keying (3FSK) In all modulation modes except for oversampled 2FSK mode, an accurate clock is provided on the TxRxCLK pin to latch the data from the microcontroller into the transmit section at the required data rate. The exact frequency of this clock is defined by In three-level FSK modulation—3FSK, also known as modified duobinary FSK and as partial response maximum likelihood Class 4 (PRML4) signaling—the binary data (Logic 0 and Logic 1) is mapped onto three distinct frequencies: the carrier frequency (fC), the carrier frequency minus a deviation frequency (fC − fDEV), and the carrier frequency plus the deviation frequency (fC + fDEV). XTAL DEMOD_CLK_DIVIDE × CDR_CLK_DIVIDE ×32 where: XTAL is the crystal or TCXO frequency. DEMOD_CLK_DIVIDE is the divider that sets the demodulator clock rate (Register 3, Bits[DB9:DB6]). CDR_CLK_DIVIDE is the divider that sets the CDR clock rate (Register 3, Bits[DB17:DB10]). A Logic 0 is mapped to the carrier frequency, whereas a Logic 1 is mapped onto either the fC − fDEV frequency or the fC + fDEV frequency. 0 See the Register 3—Transmit/Receive Clock Register section for more programming information. fC – fDEV fC + fDEV Figure 41. 3FSK Symbol-to-Frequency Mapping Compared with 2FSK, this bit-to-frequency mapping results in a reduced transmission bandwidth because some energy is removed from the RF sidebands and transferred to the carrier frequency. At low modulation index, 3FSK improves the transmit spectral efficiency by up to 25% when compared with 2FSK. In all modulation modes, the deviation from the center frequency is set using the Tx_FREQUENCY_DEVIATION bits (Register 2, Bits[DB27:DB19]). The deviation from the center frequency in Hz is as follows: For direct RF output, PFD × Tx_FREQUENCY_DEVIATION 2 16 With RF_DIVIDE_BY_2 (Register 1, Bit DB18) enabled, PFD × Tx_FREQUENCY_DEVIATION The bit-to-symbol mapping for 3FSK is implemented using a linear convolutional encoder that also permits Viterbi detection to be used in the receiver. A block diagram of the transmit hardware used to realize this system is shown in Figure 42. The convolutional encoder polynomial used to implement the transmit spectral shaping is 216 P(D) = 1 − D2 where Tx_FREQUENCY_DEVIATION is a number from 1 to 511 (Register 2, Bits[DB27:DB19]). In 4FSK modulation, the four symbols (00, 01, 11, 10) are transmitted as ±3 × fDEV and ±1 × fDEV. Binary Frequency Shift Keying (2FSK) Binary frequency shift keying is implemented by setting the N value for the center frequency and then toggling it with the TxRxDATA line. The deviation from the center frequency is set using the Tx_FREQUENCY_DEVIATION bits (Register 2, Bits[DB27:DB19]). where: P is the convolutional encoder polynomial. D is the unit delay operator. A digital precoder with transfer function 1/P(D) implements an inverse modulo-2 operation of the 1 − D2 shaping filter in the transmitter. Tx DATA 0, 1 2FSK is selected by setting the MODULATION_SCHEME bits (Register 2, Bits[DB6:DB4]) to 000. Minimum shift keying (MSK) or Gaussian minimum shift keying (GMSK) is supported by selecting 2FSK modulation and using a modulation index of 0.5. A modulation index of 0.5 is set by configuring Register 2, Bits[DB27:DB19] for an fDEV = 0.25 × transmit data rate. Rev. 0 | Page 25 of 60 PRECODER 1/P(D) 0, 1 CONVOLUTIONAL ENCODER P(D) 0, +1, –1 fC fC + fDEV FSK MOD fC – fDEV CONTROL AND DATA FILTERING Figure 42. 3FSK Encoding TO N DIVIDER 08635-041 f DEV (Hz) = 0.5 × fC RF FREQUENCY Setting the FSK Transmit Deviation Frequency f DEV (Hz) = +1 –1 08635-040 DATA CLK = ADF7021-V The signal mapping of the input binary transmit data to the three-level convolutional output is shown in Table 9. The convolutional encoder restricts the maximum number of sequential +1s or −1s to two and delivers an equal number of +1s and −1s to the FSK modulator, thus ensuring equal spectral energy in both RF sidebands. Table 9. Three-Level Signal Mapping of the Convolutional Encoder TxDATA Precoder Output Encoder Output 1 1 0 0 1 0 1 1 0 0 0 1 1 1 0 1 0 1 1 0 +1 0 −1 +1 0 0 +1 0 0 −1 The inner deviation frequencies (+fDEV and −fDEV) are set using the Tx_FREQUENCY_DEVIATION bits (Bits[DB27:DB19] in Register 2). The outer deviation frequencies are automatically set to three times the inner deviation frequency. The transmit clock from Pin TxRxCLK is available after writing to Register 3 in the power-up sequence for receive mode. The MSB of the first symbol should be clocked into the ADF7021-V on the first transmit clock pulse from the ADF7021-V after writing to Register 3. See Figure 6 and Figure 7 for more timing information; see Figure 54 and Figure 55 for the power-up sequences. Oversampled 2FSK In oversampled 2FSK, there is no data clock from the TxRxCLK pin. Instead, the transmit data at the TxRxDATA pin is sampled at 32 times the programmed rate. Another property of this encoding scheme is that the transmitted symbol sequence is dc-free, which facilitates symbol detection and frequency measurement in the receiver. In addition, no code rate loss is associated with this three-level convolutional encoder; that is, the transmitted symbol rate is equal to the data rate presented at the transmit data input. Oversampled 2FSK is the only modulation mode that can be used with the UART mode interface for data transmission (see the Interfacing to a Microcontroller/DSP section for more information). 3FSK is selected by setting the MODULATION_SCHEME bits (Register 2, Bits[DB6:DB4]) to 010. It can also be used with raised cosine filtering to further increase the spectral efficiency of the transmit signal. Four-Level Frequency Shift Keying (4FSK) In 4FSK modulation, two bits per symbol spectral efficiency is realized by mapping consecutive input bit-pairs in the Tx data bit stream to one of four possible symbols (−3, −1, +1, +3). Thus, the transmitted symbol rate is half the input bit rate. These symbols are mapped to equally spaced discrete frequencies centered on the RF carrier at −3fDEV, −1fDEV, +1fDEV, and +3fDEV SPECTRAL SHAPING Gaussian or raised cosine filtering can be used to improve transmit spectral efficiency. The ADF7021-V supports Gaussian filtering (bandwidth time [BT] = 0.5) on 2FSK modulation. Raised cosine filtering can be used with 2FSK, 3FSK, or 4FSK modulation. The roll-off factor (alpha) of the raised cosine filter has programmable options of 0.5 and 0.7. Both the Gaussian and raised cosine filters are implemented using linear phase digital filter architectures that deliver precise control over the BT and alpha filter parameters, and guarantee a transmit spectrum that is very stable over temperature and supply variation. Gaussian Frequency Shift Keying (GFSK) where fDEV is programmed using the Tx_FREQUENCY_ DEVIATION bits (Bits[DB27:DB19] in Register 2) and is also equal to half the frequency spacing between adjacent symbols. Gaussian frequency shift keying reduces the bandwidth occupied by the transmitted spectrum by digitally prefiltering the transmit data. The BT product of the Gaussian filter used is 0.5. By minimizing the separation between symbol frequencies, 4FSK can have high spectral efficiency. The bit-to-symbol mapping for 4FSK is gray coded and is shown in Figure 43. Gaussian filtering can be used only with 2FSK modulation. GFSK is selected by setting Register 2, Bits[DB6:DB4] to 001. Tx DATA 0 0 0 1 1 0 1 Raised Cosine Filtering Raised cosine filtering provides digital prefiltering of the transmit data by using a raised cosine filter with a roll-off factor (alpha) of either 0.5 or 0.7. The alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7 (set Register 2, Bit DB30 to Logic 1). Raised cosine filtering can be used with 2FSK, 3FSK, and 4FSK modulation. 1 f +3fDEV +fDEV –fDEV Raised cosine filtering is enabled by setting Register 2, Bits[DB6:DB4] as shown in Table 10. –3fDEV t 08635-042 SYMBOL FREQUENCIES Figure 43. 4FSK Bit-to-Symbol Mapping Rev. 0 | Page 26 of 60 ADF7021-V The figures for latency in Table 11 assume that the positive TxRxCLK edge is used to sample data (default). If the TxRxCLK is inverted by setting Register 2, Bits[DB29:DB28], an additional 0.5 bit latency can be added to all values in Table 11. MODULATION AND FILTERING OPTIONS The various modulation and data filtering options for the ADF7021-V are described in Table 10. Table 10. Modulation and Filtering Options Modulation Binary FSK 2FSK MSK1 OQPSK with Half Sine Baseband Shaping2 GFSK GMSK3 RC2FSK Oversampled 2FSK Three-Level FSK 3FSK RC3FSK Four-Level FSK 4FSK RC4FSK Data Filtering Register 2, Bits[DB6:DB4] None None None 000 000 000 Gaussian Gaussian Raised cosine None 001 001 101 100 None Raised cosine 010 110 None Raised cosine 011 111 Table 11. Bit/Symbol Latency in Transmit Mode for Various Modulation Schemes Modulation 2FSK GFSK RC2FSK, alpha = 0.5 RC2FSK, alpha = 0.7 3FSK RC3FSK, alpha = 0.5 RC3FSK, alpha = 0.7 4FSK RC4FSK, alpha = 0.5 RC4FSK, alpha = 0.7 Latency 1 bit 4 bits 5 bits 4 bits 1 bit 5 bits 4 bits 1 symbol 5 symbols 4 symbols TEST PATTERN GENERATOR The ADF7021-V has a number of built-in test pattern generators that can be used to facilitate radio link setup or RF measurement. 2 A full list of the supported test patterns is shown in Table 12. The data rate for these test patterns is the programmed data rate set in Register 3. TRANSMIT LATENCY The PN9 sequence is suitable for test modulation when carrying out adjacent channel power (ACP) or occupied bandwidth measurements. 1 MSK is 2FSK modulation with a modulation index = 0.5. Offset quadrature phase shift keying (OQPSK) with half sine baseband shaping is spectrally equivalent to MSK. 3 GMSK is GFSK with a modulation index = 0.5. Transmit latency is the delay time from the sampling of a bit/symbol by the TxRxCLK signal to when that bit/symbol appears at the RF output. The latency without any data filtering is 1 bit. The addition of data filtering adds a further latency as indicated in Table 11. It is important that the ADF7021-V be left in transmit mode after the last data bit is sampled by the data clock to account for this latency. The ADF7021-V should stay in transmit mode for a time equal to the number of latency bit periods for the applied modulation scheme. This ensures that all of the data sampled by the TxRxCLK signal appears at RF. Table 12. Transmit Test Pattern Generator Options Test Pattern Normal Transmit carrier only Transmit +fDEV tone only Transmit −fDEV tone only Transmit 1010 pattern Transmit PN9 sequence Transmit SWD pattern repeatedly Rev. 0 | Page 27 of 60 Register 15, Bits[DB10:DB8] 000 001 010 011 100 101 110 ADF7021-V RECEIVER SECTION RF FRONT END The ADF7021-V is based on a fully integrated, low IF receiver architecture. The low IF architecture facilitates a very low external component count and does not suffer from powerline-induced interference problems. Figure 44 shows the structure of the receiver front end. The many programming options allow users to trade off sensitivity, linearity, and current consumption to best suit their application. To achieve a high level of resilience against spurious reception, the low noise amplifier (LNA) features a differential input. Switch SW2 shorts the LNA input when transmit mode is selected (Register 0, Bit DB27 = 0). This feature facilitates the design of a combined LNA/PA matching network, avoiding the need for an external Tx/Rx switch. See the LNA/PA Matching section for details on the design of the matching network. SW2 LNA LNA_GAIN (REG 9, BITS[DB21:DB20]) LNA/MIXER_ENABLE (REG 8, BIT DB6) For details on when it is necessary to perform a filter calibration, and in what applications to use either a coarse calibration or fine calibration, see the IF Filter Bandwidth Calibration section. RSSI/AGC LO The RSSI is implemented as a successive compression log amp following the baseband (BB) channel filtering. The log amp achieves ±3 dB log linearity. It also doubles as a limiter to convert the signal-to-digital levels for the FSK demodulator. The offset correction circuit uses the BBOS_CLK_DIVIDE bits (Bits DB5:DB4] in Register 3) and should be set between 1 MHz and 2 MHz. The RSSI level is converted for user readback and for digitally controlled AGC by an 80-level (7-bit) flash ADC. This level can be converted to input power in dBm. By default, the AGC is on when powered up in receive mode. MIXER_LINEARITY (REG 9, BIT DB28) 08635-043 LNA_BIAS (REG 9, BITS[DB27:DB26]) To compensate for manufacturing tolerances, the IF filter should be calibrated after power-up to ensure that the bandwidth and center frequency are correct. Coarse and fine calibration schemes are provided to offer a choice between fast calibration (coarse calibration) and high filter centering accuracy (fine calibration). Coarse calibration is enabled by setting Register 5, Bit DB4 high. Fine calibration is enabled by setting Register 6, Bit DB4 high. I (TO FILTER) Q (TO FILTER) LNA_MODE (REG 9, BIT DB25) IF Filter Bandwidth and Center Frequency Calibration Figure 44. RF Front End The LNA is followed by a quadrature downconversion mixer, which converts the RF signal to the IF frequency of 100 kHz. An important consideration is that the output frequency of the synthesizer must be programmed to a value 100 kHz below the center frequency of the received channel. The LNA has two basic operating modes: high gain/low noise mode and low gain/ low power mode. To switch between these two modes, use the LNA_MODE bit (Register 9, Bit DB25). The mixer is also configurable for either a low current mode or an enhanced linearity mode using the MIXER_LINEARITY bit (Register 9, Bit DB28). Based on the specific sensitivity and linearity requirements of the application, it is recommended that the LNA_MODE bit and the MIXER_LINEARITY bit be adjusted as shown in Table 14. The gain of the LNA is configured by the LNA_GAIN bits (Register 9, Bits[DB21:DB20]) and can be set by the user or by the automatic gain control (AGC) logic. IF FILTER IF Filter Settings Out-of-band interference is rejected by means of a fifth-order Butterworth polyphase IF filter centered on a frequency of 100 kHz. The bandwidth of the IF filter can be programmed to 9 kHz, 13.5 kHz, or 18.5 kHz in Register 4, Bits[DB31:DB30], and should be chosen as a compromise between interference rejection and attenuation of the desired signal. OFFSET CORRECTION 1 A IFWR A IFWR A IFWR LATCH IFWR FSK DEMOD CLK RSSI ADC R 08635-044 RFIN Tx/Rx SELECT (REG 0, BIT DB27) RFIN If the AGC loop is disabled, the gain of the IF filter can be set to one of three levels by using the FILTER_GAIN bits (Register 9, Bits[DB23:DB22]). The filter gain is adjusted automatically if the AGC loop is enabled. Figure 45. RSSI Block Diagram RSSI Thresholds When the RSSI is above AGC_HIGH_THRESHOLD (Register 9, Bits[DB17:DB11]), the gain is reduced. When the RSSI is below AGC_LOW_THRESHOLD (Register 9, Bits[DB10:DB4]), the gain is increased. The thresholds default to 70 (high threshold) and 30 (low threshold) on power-up in receive mode. A delay (set by AGC_CLK_DIVIDE in Register 3, Bits[DB31:DB26]) is programmed to allow for settling of the loop. A value of 33 is recommended to give an AGC update rate of 3 kHz. The user has the option of changing the two threshold values from the defaults of 70 and 30 (Register 9). The default AGC setup values should be adequate for most applications. The threshold values must be more than 30 apart for the AGC to operate correctly. Rev. 0 | Page 28 of 60 ADF7021-V Offset Correction Clock In Register 3, the user should set the BBOS_CLK_DIVIDE bits (Bits[DB5:DB4]) to give a baseband offset clock (BBOS CLK) frequency between 1 MHz and 2 MHz. BBOS CLK (Hz) = XTAL/(BBOS_CLK_DIVIDE) RSSI Formula (Converting to dBm) where BBOS_CLK_DIVIDE can be set to 4, 8, 16, or 32. The RSSI formula is AGC Information and Timing AGC is selected by default and operates by setting the appropriate LNA and filter gain settings for the measured RSSI level. To enter one of the LNA/mixer modes listed in Table 14, the user can disable AGC by writing to Register 9. After each gain change, the AGC loop waits for a programmed time to allow transients to settle. This AGC update rate is set according to AGC Update Rate (Hz) = Input Power (dBm) = (−130 dBm + (Readback Code + Gain Mode Correction)) × 0.5 where: Readback Code is given by Bit RV7 to Bit RV1 in the readback register (see Figure 57 and the Readback Format section). Gain Mode Correction is given by the values in Table 13. The LNA gain (LG2, LG1) and filter gain (FG2, FG1) values are also obtained from the readback register, as part of an RSSI readback. SEQ _ CLK _ DIVIDE (Hz) AGC _ CLK _ DIVIDE where: SEQ_CLK_DIVIDE = 100 kHz (Register 3, Bits[DB25:DB18]). AGC_CLK_DIVIDE is set by Register 3, Bits[DB31:DB26]. A value of 33 is recommended. It is recommended that AGC_CLK_DIVIDE be set to a value of 33, which allows a settling time of 333 μs for each gain change. By using the recommended setting for AGC_CLK_DIVIDE, the total AGC settling time is AGC Settling Time (sec) = The total AFC settling time depends on the number of AGC gain changes during reception of a packet. A total of five gain changes gives a worst-case AGC settling time of 5 × 333 μs. To allow for AGC settling, the preamble length should be adjusted accordingly. Number of AGC Gain Changes AGC Update Rate (Hz) Table 13. Gain Mode Correction LNA Gain (LG2, LG1) H (1, 0) M (0, 1) M (0, 1) M (0, 1) L (0, 0) Filter Gain (FG2, FG1) H (1, 0) H (1, 0) M (0, 1) L (0, 0) L (0, 0) Gain Mode Correction 0 24 38 58 86 An additional factor should be introduced to account for losses in the front-end-matching network/antenna. Table 14. LNA/Mixer Modes (Register 9 Settings) Receiver Mode High Sensitivity Mode (Default) Enhanced Linearity, High Gain Medium Gain Enhanced Linearity, Medium Gain Low Gain Enhanced Linearity, Low Gain LNA_MODE (Bit DB25) 0 LNA_GAIN (Bits[DB21:DB20]) 30 MIXER_LINEARITY (Bit DB28) 0 Sensitivity (2FSK, Data Rate = 4.8 kbps, fDEV = 4 kHz) (dBm) −116.5 Rx Current Consumption (mA) 20.1 Input IP3 (dBm) −24 0 30 1 −113 20.1 −20 1 1 10 10 0 1 −108 −102 17.9 17.9 −13.5 −9 1 1 3 3 0 1 −99 −91 17.9 17.9 −5 −3 Rev. 0 | Page 29 of 60 ADF7021-V DEMODULATION, DETECTION, AND CDR System Overview An overview of the demodulation, detection, and clock and data recovery (CDR) of the received signal on the ADF7021-V is shown in Figure 46. POST DEMOD FILTER LIMITERS I CORRELATOR DEMODULATOR Q MUX LINEAR DEMODULATOR The quadrature outputs of the IF filter are first limited and then fed to a digital frequency correlator that performs filtering and frequency discrimination of the 2FSK/3FSK/4FSK spectrum. For 2FSK modulation, data is recovered by comparing the output levels from two correlators. The performance of this frequency discriminator approximates that of a matched filter detector, which is known to provide optimum detection in the presence of additive white Gaussian noise (AWGN). This method of FSK demodulation provides approximately 3 dB to 4 dB better sensitivity than a linear demodulator. Linear Demodulator IF LIMITERS Q MUX FREQUENCY LINEAR DISCRIMINATOR 08635-045 VITERBI DETECTION 3FSK Following the demodulator, a digital postdemodulator filter removes excess noise from the demodulator signal output. Threshold/slicer detection is used for data recovery of 2FSK and 4FSK. Data recovery of 3FSK can be implemented using either threshold detection or Viterbi detection. An on-chip CDR PLL is used to resynchronize the received bit stream to a local clock. It outputs the retimed data and clock on the TxRxDATA and TxRxCLK pins, respectively. Correlator Demodulator The correlator demodulator can be used for 2FSK, 3FSK, and 4FSK demodulation. Figure 47 shows the operation of the correlator demodulator for 2FSK. FREQUENCY CORRELATOR DISCRIM BW I Figure 48. Block Diagram of Linear FSK Demodulator A digital frequency discriminator provides an output signal that is linearly proportional to the frequency of the limiter outputs. The discriminator output is filtered and averaged using a combined averaging filter and envelope detector. The demodulated 2FSK data from the postdemodulator filter is recovered by slicing against the output of the envelope detector, as shown in Figure 48. This method of demodulation corrects for frequency errors between the transmitter and receiver when the received spectrum is close to or within the IF bandwidth. This envelope detector output is also used for AFC readback and provides the frequency estimate for the AFC control loop. Postdemodulator Filter A second-order, digital low-pass filter removes excess noise from the demodulated bit stream at the output of the discriminator. The bandwidth of this postdemodulator filter is programmable and must be optimized for the user’s data rate and the received modulation type. If the bandwidth is too narrow, performance degrades due to intersymbol interference (ISI). If the bandwidth is too wide, excess noise degrades the performance of the receiver. The POST_DEMOD_BW bits (Register 4, Bits[DB29:DB20]) set the bandwidth of this filter. OUTPUT LEVELS: Q IF IF + fDEV REG 4, BITS[DB9:DB8] REG 4, BITS[DB19:DB10] Rx_INVERT DISCRIMINATOR_BW REG 4, BIT DB7 DOT_PRODUCT 08635-046 IF – fDEV RxCLK FREQUENCY READBACK AND AFC LOOP 2FSK = +1, –1 3FSK = +1, 0, –1 4FSK = +3, +1, –1, –3 LIMITERS 2FSK RxDATA REG 4, BITS[DB29:DB20] Figure 46. Overview of Demodulation, Detection, and CDR Process The quadrature outputs of the IF filter are first limited and then fed to either the correlator FSK demodulator or to the linear FSK demodulator. The correlator demodulator is used to demodulate 2FSK, 3FSK, and 4FSK. The linear demodulator is used for frequency measurement and is enabled when the AFC loop is active. The linear demodulator can also be used to demodulate 2FSK. + SLICER 2FSK 08635-047 CLOCK AND DATA RECOVERY LEVEL ENVELOPE DETECTOR TxRxDATA TxRxCLK I THRESHOLD DETECTION 2FSK/3FSK/4FSK POST DEMOD FILTER Figure 48 shows a block diagram of the linear demodulator. Figure 47. 2FSK Correlator FSK Demodulator Operation Rev. 0 | Page 30 of 60 ADF7021-V 2FSK Bit Slicer/Threshold Detection 2FSK demodulation can be implemented using the correlator FSK demodulator or the linear FSK demodulator. In both cases, threshold detection is used for data recovery at the output of the postdemodulator filter. The output signal levels of the correlator demodulator are always centered about 0. Therefore, the slicer threshold level can be fixed at 0, and the demodulator performance is independent of the run-length constraints of the transmit data bit stream. This results in robust data recovery that does not suffer from the classic baseline wander problems that exist in more traditional FSK demodulators. When the linear demodulator is used for 2FSK demodulation, the output of the envelope detector is used as the slicer threshold, and this output tracks frequency errors that are within the IF filter bandwidth. 3FSK and 4FSK Threshold Detection 4FSK demodulation is implemented using the correlator demodulator followed by the postdemodulator filter and threshold detection. The output of the postdemodulator filter is a four-level signal that represents the transmitted symbols (−3, −1, +1, +3). Threshold detection of 4FSK requires three threshold settings: one that is always fixed at 0 and two that are programmable and are symmetrically placed above and below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). 3FSK demodulation is implemented using the correlator demodulator, followed by a postdemodulator filter. The output of the postdemodulator filter is a three-level signal that represents the transmitted symbols (−1, 0, +1). Data recovery of 3FSK can be implemented using threshold detection or Viterbi detection. Threshold detection is implemented using two thresholds that are programmable and are symmetrically placed above and below 0 using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). 3FSK Viterbi Detection Viterbi detection of 3FSK operates on a four-state trellis and is implemented using two interleaved Viterbi detectors operating at half the symbol rate. The Viterbi detector is enabled by Register 13, Bit DB11. To facilitate different run-length constraints in the transmitted bit stream, the Viterbi path memory length is programmable in steps of 4 bits, 6 bits, 8 bits, or 32 bits by setting the VITERBI_ PATH_MEMORY bits (Register 13, Bits[DB14:DB13]). This value should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream. When used with Viterbi detection, the receiver sensitivity for 3FSK is typically 3 dB greater than that obtained using threshold detection. When the Viterbi detector is enabled, however, the receiver bit latency is increased by twice the Viterbi path memory length. Clock and Data Recovery (CDR) An oversampled digital clock and data recovery (CDR) PLL is used to resynchronize the received bit stream to a local clock in all modulation modes. The oversampled clock rate of the PLL (CDR CLK) must be set at 32 times the symbol rate (see the Register 3—Transmit/Receive Clock Register section). The maximum data/symbol rate tolerance of the CDR PLL is determined by the number of zero-crossing symbol transitions in the transmitted packet. For example, if using 2FSK with a 101010 preamble, a maximum tolerance of ±3.0% of the data rate is achieved. However, this tolerance is reduced during recovery of the remainder of the packet, where symbol transitions may not be guaranteed to occur at regular intervals. To maximize the data rate tolerance of the CDR, some form of encoding and/or data scrambling is recommended that guarantees a number of transitions at regular intervals. For example, using 2FSK with Manchester-encoded data achieves a data rate tolerance of ±2.0%. The CDR PLL is designed for fast acquisition of the recovered symbols during preamble and typically achieves bit synchronization within five-symbol transitions of preamble. In 4FSK modulation, the tolerance using the +3, −3, +3, −3 preamble is ±3% of the symbol rate (or ±1.5% of the data rate). However, this tolerance is reduced during recovery of the remainder of the packet, where symbol transitions may not be guaranteed to occur at regular intervals. To maximize the symbol/data rate tolerance of the CDR, the remainder of the 4FSK packet should be constructed so that the transmitted symbols retain close to dc-free properties by using data scrambling and/or by inserting specific dc-balancing symbols into the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols. In 3FSK modulation, the linear convolutional encoder scheme guarantees that the transmitted symbol sequence is dc-free, facilitating symbol detection. However, Tx data scrambling is recommended to limit the run length of 0 symbols in the transmit bit stream. Using 3FSK, the CDR data rate tolerance is typically ±0.5%. Rev. 0 | Page 31 of 60 ADF7021-V RECEIVER SETUP Table 17. Assignment of Correlator K Value for 4FSK Correlator Demodulator Setup K Even Odd To enable the correlator for various modulation modes, see Table 15. The linear demodulator can be used for 2FSK demodulation. To enable the linear demodulator, set the DEMOD_SCHEME bits (Register 4, Bits[DB6:DB4]) to 000. DEMOD_SCHEME (Register 4, Bits[DB6:DB4]) 001 010 011 Postdemodulator Filter Setup To optimize receiver sensitivity, the correlator bandwidth must be optimized for the specific deviation frequency and modulation used by the transmitter. The discriminator bandwidth is controlled by Register 4, Bits[DB19:DB10], and is defined as DISCRIMINATOR _ BW = POST _ DEMOD _ BW = 400 × 10 3 For 2FSK, ⎞ ⎟ ⎟ ⎠ For 3FSK, ⎛ 100 × 10 3 K = Round ⎜⎜ ⎝ 2 × f DEV ⎞ ⎟ ⎟ ⎠ where: Round is rounded to the nearest integer. Round4FSK is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is the frequency deviation used for the ±1 symbols (that is, the inner frequency deviations). To optimize the coefficients of the correlator, Register 4, Bit DB7 and Register 4, Bits[DB9:DB8] must also be assigned. The value of these bits depends on whether K is odd or even. These bits are assigned according to Table 16 and Table 17. Table 16. Assignment of Correlator K Value for 2FSK and 3FSK K/2 Even Odd N/A N/A (K + 1)/2 N/A N/A Even Odd DEMOD CLK where fCUTOFF is the target 3 dB bandwidth in Hz of the postdemodulator filter. Table 18. Postdemodulator Filter Bandwidth Settings for 2FSK/3FSK/4FSK Modulation Schemes Received Modulation 2FSK 3FSK 4FSK Postdemodulator Filter Bandwidth, fCUTOFF (Hz) 0.75 × data rate 1 × data rate 1.6 × symbol rate (0.8 × data rate) The Viterbi detector can be used for 3FSK data detection; it is activated by setting Register 13, Bit DB11, to Logic 1. For 4FSK, K Even Even Odd Odd 2 11 × π × f CUTOFF 3FSK Viterbi Detector Setup ⎞ ⎟ ⎟ ⎠ ⎛ 100 × 10 3 K = Round 4FSK ⎜⎜ ⎝ 4 × f DEV The 3 dB bandwidth of the postdemodulator filter should be set according to the received modulation type and data rate. The bandwidth is controlled by Register 4, Bits[DB29:DB20] and is given by (DEMOD CLK × K ) where: DEMOD CLK is as defined in the Register 3—Transmit/Receive Clock Register section. K is set for each modulation mode as follows: ⎛ 100 × 10 3 K = Round ⎜⎜ ⎝ f DEV Register 4, Bits[DB9:DB8] 00 00 Linear Demodulator Setup Table 15. Enabling the Correlator Demodulator Received Modulation 2FSK 3FSK 4FSK Register 4, Bit DB7 0 1 Register 4, Bit DB7 0 0 1 1 Register 4, Bits[DB9:DB8] 00 10 00 10 The Viterbi path memory length is programmable in steps of 4, 6, 8, or 32 bits (VITERBI_PATH_MEMORY, Register 13, Bits[DB14:DB13]). The path memory length should be set equal to or greater than the maximum number of consecutive 0s in the interleaved transmit bit stream. The Viterbi detector also uses threshold levels to implement the maximum likelihood detection algorithm. These thresholds are programmable via the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). These bits are assigned as follows: 3FSK/4FSK_SLICER_THRESHOLD = ⎛ Tx _ FREQUENCY _ DEVIATION × K 57 × ⎜ ⎜ 100 × 10 3 ⎝ ⎞ ⎟ ⎟ ⎠ where K is the value calculated for correlator discriminator bandwidth. 3FSK Threshold Detector Setup To activate threshold detection of 3FSK, Register 13, Bit DB11, should be set to Logic 0. The 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]) should be set as described in the 3FSK Viterbi Detector Setup section. Rev. 0 | Page 32 of 60 ADF7021-V 3FSK CDR Setup In 3FSK, a transmit preamble of at least 40 bits of continuous 1s is recommended to ensure a maximum number of symbol transitions for the CDR to acquire lock. 11001100…) can also be used, but result in a longer synchronization time of the received bit stream in the receiver. The preamble must allow enough bits for AGC settling of the receiver and CDR acquisition (see Table 20). The remaining fields that follow the preamble do not need to use dc-free coding. For these fields, the ADF7021-V can accommodate coding schemes with a run length of greater than eight bits without any performance degradation. Refer to the AN-915 Application Note for more information. The clock and data recovery for 3FSK requires a number of parameters in Register 13 to be set (see Table 19). 4FSK Threshold Detector Setup The threshold for the 4FSK detector is set using the 3FSK/4FSK_SLICER_THRESHOLD bits (Register 13, Bits[DB10:DB4]). The threshold should be set as follows: 4FSK Preamble and Data Coding The recommended preamble bit pattern for 4FSK is a repeating 00100010… bit sequence. This two-level sequence of repeating −3, +3, −3, +3 symbols is dc-free and maximizes the symbol timing performance and data recovery of the 4FSK preamble in the receiver. The minimum recommended length of the preamble is 32 bits (16 symbols). 3FSK/4FSK_SLICER_THRESHOLD = ⎛ 4FSK Outer Tx Deviation × K ⎞ ⎟ 78 × ⎜ 3 ⎜ ⎟ × 100 10 ⎝ ⎠ where K is the value calculated for correlator discriminator bandwidth. FSK DEMODULATOR OPTIMIZATION 2FSK Preamble The recommended preamble bit pattern for 2FSK, GFSK, and RC2FSK is a dc-free pattern (such as a 10101010… pattern). Preamble patterns with longer run-length constraints (such as The remainder of the 4FSK packet should be constructed so that the transmitted symbols retain close to a dc-free balance by using data scrambling and/or by inserting specific dc-balancing symbols in the transmitted bit stream at regular intervals, such as after every 8 or 16 symbols. Table 19. 3FSK CDR Settings Parameter (Register 13) PHASE_CORRECTION (Bit DB12) 3FSK_CDR_THRESHOLD (Bits[DB21:DB15]) 3FSK_PREAMBLE_TIME_VALIDATE (Bits[DB25:DB22]) Recommended Setting 1 Purpose Phase correction is on ⎛ Tx _ FREQUENCY _ DEVIATION × K ⎞ Sets CDR decision threshold levels 62 × ⎜ ⎜ ⎝ 100 × 10 3 where K is the value calculated for correlator discriminator bandwidth. 15 ⎟ ⎟ ⎠ Preamble detector time qualifier Table 20. Preamble Bit Length for 2FSK Modulation Demodulator Correlator (AFC off ) Mod index = 2 Mod index = 1 Mod index = 0.5 Linear (AFC off ) fDEV = 4.2 kHz fDEV = 2.2 kHz fDEV = 1.6 kHz Correlator (AFC on) Linear (AFC on) Correlator + bypass CDR (AFC off ) Sensitivity Degradation from Specifications Rx Frequency Error Tolerance (1% PER) Minimum Preamble (Bits) 0 dB 0 dB 0 dB ±30% × fDEV ±25% × fDEV ±20% × fDEV 16 16 16 3 dB 3 dB 3 dB 2 dB 3 dB 2 dB to 3 dB 4 ±0.5 × IFBW 1 ±0.5 × IFBW1 ±0.5 × IFBW1 AFC pull-in range 2 AFC pull-in range2 ±50% × fDEV 5 64 112 128 96 to 128 3 96 to 128 8 1 This value is generally true; however, some sensitivity degradation may occur close to the edge of the IF filter. Limited to ±0.5 × IFBW or AFC pull-in range, whichever is less. 3 Dependent on modulation index and fDEV. At higher modulation indexes (1.0 or greater) and higher fDEV (>4.0 kHz), the minimum preamble length is 96 bits. The minimum preamble length increases as the modulation index and fDEV are reduced. 4 Dependent on the performance of the symbol timing recovery module on the external microcontroller. 5 Depends on the pulse width mark/space ratio of Logic 1 to Logic 0 that the symbol timing recovery scheme on the external microcontroller can tolerate. In this mode, the mark/space ratio of the recovered bit stream increases with frequency error. In the absence of frequency error, the mark/space ratio is 50:50, that is, the width of a Logic 1 is the same as the width of a Logic 0. 2 Rev. 0 | Page 33 of 60 ADF7021-V Correlator Demodulator and Low Modulation Indexes Internal AFC The modulation index in 2FSK is defined as The ADF7021-V supports a real-time, internal, automatic frequency control loop. In this mode, an internal control loop automatically monitors the frequency error and adjusts the synthesizer-N divider using an internal proportional integral (PI) control loop. Modulation Index = 2 × f DEV Data Rate The receiver sensitivity performance and receiver frequency tolerance can be maximized at low modulation indexes by increasing the discriminator bandwidth of the correlator demodulator. For modulation indexes of less than 0.4, it is recommended that the correlator bandwidth be doubled by calculating K as follows: ⎛ 100 3 K = Round ⎜⎜ ⎝ 2 × f DEV The internal AFC control loop parameters are controlled in Register 10. The internal AFC loop is activated by setting Bit DB4 in Register 10 to 1. A scaling coefficient must also be entered, based on the crystal frequency in use. This is set up using Bits[DB16:DB5] in Register 10 and should be calculated as follows: ⎞ ⎟⎟ ⎠ The DISCRIMINATOR_BW value in Register 4 should be recalculated using the new K value. Figure 29 illustrates the improved sensitivity that can be achieved for 2FSK modulation, at low modulation indexes, by doubling the correlator bandwidth. AFC OPERATION The ADF7021-V also supports a real-time AFC loop that is used to remove frequency errors due to mismatches between the transmit and receive crystals/TCXOs. The AFC loop uses the linear frequency discriminator block to estimate frequency errors. The linear FSK discriminator output is filtered and averaged to remove the FSK frequency modulation using a combined averaging filter and envelope detector. In receive mode, the output of the envelope detector provides an estimate of the average IF frequency. The two methods of AFC supported on the ADF7021-V are external AFC and internal AFC. External AFC With external AFC, the user reads back the frequency information through the ADF7021-V serial port and applies a frequency correction value to the synthesizer-N divider. ⎛ 2 24 × 500 ⎞ ⎟ AFC _ SCALING _ FACTOR = Round ⎜ ⎜ XTAL ⎟ ⎝ ⎠ Maximum AFC Range The maximum frequency correction range of the AFC loop is programmable using Register 10, Bits[DB31:DB24]. The maximum AFC correction range is the difference in frequency between the upper and lower limits of the AFC tuning range. For example, if the maximum AFC correction range is set to 10 kHz, the AFC can adjust the receiver LO within the fLO ± 5 kHz range. However, when RF_DIVIDE_BY_2 (Register 1, Bit DB18) is enabled, the programmed range is halved. The user should account for this halving by doubling the programmed maximum AFC range. The recommended maximum AFC correction range should be ≤1.5 × IF filter bandwidth. If the maximum frequency correction range is set to be >1.5 × IF filter bandwidth, the attenuation of the IF filter can degrade the AFC loop sensitivity. The adjacent channel rejection (ACR) performance of the receiver can be degraded when AFC is enabled and the AFC correction range is close to or greater than the IF filter bandwidth. However, because the AFC correction range is programmable, the user can trade off AFC correction range and ACR performance of the receiver. The frequency information is obtained by reading the signed, 16-bit AFC readback value, as described in the Readback Format section, and by applying the following formula: Frequency Readback (Hz) = (AFC READBACK × DEMOD CLK)/218 Although the AFC readback value is a signed number, under normal operating conditions, it is positive. In the absence of frequency errors, the frequency readback value is equal to the IF frequency of 100 kHz. When AFC errors are removed using either the internal or external AFC, further improvement in receiver sensitivity can be obtained by reducing the IF filter bandwidth using the IF_FILTER_BW bits (Register 4, Bits[DB31:DB30]). Rev. 0 | Page 34 of 60 ADF7021-V AUTOMATIC SYNC WORD DETECTION (SWD) The ADF7021-V also supports automatic detection of the sync or ID fields. To activate this mode, the sync (or ID) word must be preprogrammed into the ADF7021-V. In receive mode, this preprogrammed word is compared to the received bit stream. When a valid match is identified, the external SWD pin is asserted by the ADF7021-V on the next Rx clock pulse. This feature can be used to alert the microprocessor that a valid channel has been detected. It relaxes the computational requirements of the microprocessor and reduces the overall power consumption. The SWD signal can also be used to frame the received packet by staying high for a preprogrammed number of bytes. The data packet length can be set in Register 12, Bits[DB15:DB8]. The SWD pin status can be configured by setting Bits[DB7:DB6] in Register 12. Bits[DB5:DB4] in Register 11 are used to set the length of the sync/ID word, which can be 12, 16, 20, or 24 bits long. A value of 24 bits is recommended to minimize false sync word detection in the receiver that can occur during recovery of the remainder of the packet or when a noise/no signal is present at the receiver input. The transmitter must transmit the sync byte MSB first, LSB last to ensure proper alignment in the receiver sync-byte-detection hardware. An error tolerance parameter can also be programmed that accepts a valid match when up to three bits of the word are incorrect. The error tolerance value is assigned in Register 11, Bits[DB7:DB6]. Rev. 0 | Page 35 of 60 ADF7021-V APPLICATIONS INFORMATION Lower Tone Frequency (kHz) = IF FILTER BANDWIDTH CALIBRATION The IF filter should be calibrated on every power-up in receive mode to correct for errors in the bandwidth and filter center frequency due to process variations. The automatic calibration requires no external intervention when it is initiated by a write to Register 5. Depending on numerous factors, such as IF filter bandwidth, received signal bandwidth, and temperature variation, the user must determine whether to carry out a coarse calibration or a fine calibration. The performance of both calibration methods is shown in Table 21. 1 Center Frequency Accuracy1 100 kHz ± 2.5 kHz 100 kHz ± 0.6 kHz Calibration Time (Typ) 200 μs 8.2 ms After calibration. Calibration Setup IF filter calibration is initiated by writing to Register 5 and setting the IF_CAL_COARSE bit (Bit DB4). This initiates a coarse filter calibration. If the IF_FINE_CAL bit (Register 6, Bit DB4) has already been set high, the coarse calibration is followed by a fine calibration; otherwise, the calibration ends. When initiated by writing to the part, calibration is performed automatically without user intervention. The calibration time is 200 μs for coarse calibration and 8.2 ms for fine calibration, during which time the ADF7021-V should not be accessed. The IF filter calibration logic requires that the IF_FILTER_DIVIDER bits (Register 5, Bits[DB13:DB5]) be set such that XTAL (Hz) IF _ FILTER _ DIVIDER Upper Tone Frequency (kHz) = XTAL IF_CAL_UPPER_TONE_DIVIDE × 2 It is recommended that the lower tone and the upper tone be set as shown in Table 22. Table 22. IF Filter Fine Calibration Tone Frequencies Table 21. IF Filter Calibration Specifications Filter Calibration Method Coarse Calibration Fine Calibration XTAL IF_CAL_LOWER_TONE_DIVIDE × 2 = 50 kHz IF Filter Bandwidth (kHz) 9 13.5 18.5 Lower Tone Frequency (kHz) 78.1 79.4 78.1 Upper Tone Frequency (kHz) 116.3 116.3 119 Because the filter attenuation is slightly asymmetrical, it is necessary to have a small offset in the filter center frequency to provide near equal rejection at the upper and lower adjacent channels. The calibration tones listed in Table 22 provide this small positive offset in the IF filter center frequency. In some applications, an offset may not be required, and the user may wish to center the IF filter at 100 kHz exactly. In this case, the user can alter the tone frequencies from those given in Table 22 to adjust the fine calibration result. The calibration algorithm adjusts the filter center frequency and measures the RSSI 10 times during the calibration. The time for an adjustment plus RSSI measurement is given by IF Tone Calibration Time = IF_CAL_DWELL_TIME SEQ CLK It is recommended that the IF tone calibration time be at least 800 μs. The total time for the IF filter fine calibration is given by The fine calibration uses two internally generated tones at certain offsets around the IF filter. The two tones are attenuated by the IF filter, and the level of this attenuation is measured using the RSSI. The filter center frequency is adjusted to allow equal attenuation of both tones. The attenuation of the two test tones is then remeasured. This process continues for a maximum of 10 RSSI measurements, at which point the calibration algorithm sets the IF filter center frequency to within 0.6 kHz of 100 kHz. The frequency of these tones is set in Register 6 by the IF_CAL_LOWER_TONE_DIVIDE bits (Bits[DB12:DB5]) and the IF_CAL_UPPER_TONE_DIVIDE bits (Bits[DB20:DB13]), as shown in the following equations. IF Filter Fine Calibration Time = IF Tone Calibration Time × 10 When to Use Coarse Calibration It is recommended that a coarse calibration be performed on every power-up in receive mode. This calibration typically takes 200 μs. The FILTER_CAL_COMPLETE signal from MUXOUT (set using Bits[DB31:DB29] in Register 0) can be used to monitor the filter calibration duration or to signal the end of calibration. The ADF7021-V should not be accessed during calibration. Rev. 0 | Page 36 of 60 ADF7021-V When to Use Fine Calibration LNA/PA MATCHING In cases where the receive signal bandwidth is very close to the bandwidth of the IF filter, it is recommended that a fine filter calibration be performed every time that the unit powers up in receive mode. The ADF7021-V exhibits optimum performance in terms of sensitivity, transmit power, and current consumption only if its RF input and output ports are properly matched to the antenna impedance. For cost-sensitive applications, the ADF7021-V is equipped with an internal Tx/Rx switch that facilitates the use of a simple, combined passive LNA/PA matching network. Alternatively, an external Tx/Rx switch such as the ADG919 can be used, which yields a slightly improved receiver sensitivity and lower transmitter power consumption. A fine calibration should be performed if OBW + Coarse Calibration Variation > IF_FILTER_BW where: OBW is the 99% occupied bandwidth of the transmit signal. Coarse Calibration Variation is 2.5 kHz. IF_FILTER_BW is set by Register 4, Bits[DB31:DB30]. Internal Tx/Rx Switch When to Use Single Fine Calibration In applications where the receiver powers up numerous times in a short period, it is necessary to perform fine calibration only once, on the initial power-up in receive mode. After the initial coarse calibration and fine calibration, the result of the fine calibration can be read back through the serial interface using the FILTER_CAL_READBACK result (see the Filter Bandwidth Calibration Readback section). On subsequent power-ups in receive mode, the filter is manually adjusted using the previous fine filter calibration result. This manual adjustment is performed using the IF_FILTER_ADJUST bits (Register 5, Bits[DB19:DB14]). Figure 49 shows the ADF7021-V in a configuration where the internal Tx/Rx switch is used with a combined LNA/PA matching network. This is the configuration used on the EVAL-ADF7021-VDBxZ evaluation board. For most applications, the slight performance degradation of 1 dB to 2 dB caused by the internal Tx/Rx switch is acceptable, allowing the user to take advantage of the cost-saving potential of this solution. The design of the combined matching network must compensate for the reactance presented by the networks in the Tx and the Rx paths, taking the state of the Tx/Rx switch into consideration. VBAT ADF7021-V C1 L1 RFOUT PA ANTENNA ZOPT_PA OPTIONAL BPF OR LPF ZIN_RFIN CA RFIN LA This method should only be used if the successive power-ups in receive mode are over a short duration, during which time there is little variation in temperature (<15°C). LNA RFIN ZIN_RFIN CB IF Filter Variation with Temperature When calibrated, the filter center frequency can vary with changes in temperature. If the ADF7021-V is used in an application where it remains in receive mode for a considerable length of time, the user must consider this variation of filter center frequency with temperature. This variation is typically 1 kHz per 20°C, which means that if a coarse filter calibration and fine filter calibration are performed at 25°C, the initial maximum error is ±0.5 kHz, and the maximum possible change in the filter center frequency over temperature (−40°C to +85°C) is ±3.25 kHz. This gives a total error of ±3.75 kHz. 08635-048 The FILTER_CAL_COMPLETE signal from MUXOUT (set by Register 0, Bits[DB31:DB29]) can be used to monitor the filter calibration duration or to signal the end of calibration. A coarse filter calibration is automatically performed prior to a fine filter calibration. Figure 49. ADF7021-V with Internal Tx/Rx Switch The procedure typically requires several iterations until an acceptable compromise is reached. The successful implementation of a combined LNA/PA matching network for the ADF7021-V is critically dependent on the availability of an accurate electrical model for the PCB. In this context, the use of a suitable CAD package is strongly recommended. To avoid this effort, a small form-factor reference design for the ADF7021-V is provided, including matching and harmonic filter components. The design is on a 4-layer PCB. Gerber files are available at www.analog.com. If the receive signal occupied bandwidth is considerably narrower than the IF filter bandwidth, the variation of filter center frequency over the operating temperature range may not be an issue. However, if the IF filter bandwidth is not wide enough to tolerate the variation with temperature, a periodic filter calibration can be performed or, alternatively, the on-chip temperature sensor can be used to determine when a filter calibration is necessary by monitoring for changes in temperature. Rev. 0 | Page 37 of 60 ADF7021-V External Tx/Rx Switch Figure 50 shows a configuration using an external Tx/Rx switch. This configuration allows independent optimization of the matching and filter network in the transmit and receive paths. Therefore, it is more flexible and less difficult to design than the configuration using the internal Tx/Rx switch. The PA is biased through Inductor L1, whereas C1 blocks dc current. Together, L1 and C1 form the matching network that transforms the source impedance into the optimum PA load impedance, ZOPT_PA. VBAT ADF7021-V ADG919 OPTIONAL LPF C1 L1 RFOUT PA ANTENNA ZOPT_PA ZIN_RFIN OPTIONAL CA BPF (SAW) RFIN LA LNA RFIN Rx/Tx – SELECT 08635-049 ZIN_RFIN CB Figure 50. ADF7021-V with External Tx/Rx Switch performance of the receiver is dependent on how well matched the I and Q signals are in amplitude and how well matched the quadrature is between them (that is, how close to 90° apart they are). The uncalibrated image rejection performance is approximately 29 dB (at 460 MHz). However, it is possible to improve this performance by as much as 20 dB by finding the optimum I/Q gain and phase adjust settings. Calibration Using Internal RF Source With the LNA powered off, an on-chip generated, low level RF tone is applied to the mixer inputs. The LO is adjusted to make the tone fall at the image frequency where it is attenuated by the image rejection of the IF filter. The power level of this tone is then measured using the RSSI readback. The I/Q gain and phase adjust DACs (Register 5, Bits[DB31:DB20]) are adjusted and the RSSI is remeasured. This process is repeated until the optimum values for the gain and phase adjust are found that provide the lowest RSSI readback level, thereby maximizing the image rejection performance of the receiver. Using the internal RF source, the RF frequencies that can be used for image calibration are programmable and are odd multiples of the reference frequency. Calibration Using External RF Source ZOPT_PA depends on various factors, such as the required output power, the frequency range, the supply voltage range, and the temperature range. Selecting an appropriate ZOPT_PA helps to minimize the Tx current consumption in the application. The AN-764 Application Note and the AN-859 Application Note contain a number of ZOPT_PA values for representative conditions. Under certain conditions, however, it is recommended that a suitable ZOPT_PA value be obtained by means of a load-pull measurement. IR calibration can also be implemented using an external RF source. The IR calibration procedure is the same as that used for the internal RF source, except that an RF tone is applied to the LNA input. Due to the differential LNA input, the LNA matching network must be designed to provide both a single-ended-to-differential conversion and a complex, conjugate impedance match. The network with the lowest component count that can satisfy these requirements is the configuration shown in Figure 50, consisting of two capacitors and one inductor. To enable the internal RF source, the IR_CAL_SOURCE_DRIVE_ LEVEL bits (Register 6, Bits[DB29:DB28]) should be set to the maximum level. The LNA should be set to its minimum gain setting, and the AGC should be disabled if the internal RF source is being used. Alternatively, an external RF source can be used. Depending on the antenna configuration, the user may need a harmonic filter at the PA output to satisfy the spurious emission requirement of the applicable government regulations. The harmonic filter can be implemented in various ways, for example, a discrete LC pi or T-stage filter. The immunity of the ADF7021-V to strong out-of-band interference can be improved by adding a band-pass filter in the Rx path. Alternatively, the ADF7021-V blocking performance can be improved by selecting one of the enhanced linearity modes, as described in Table 14. IMAGE REJECTION CALIBRATION The image channel in the ADF7021-V is 200 kHz below the desired signal. The polyphase filter rejects this image with an asymmetric frequency response. The image rejection (IR) Calibration Procedure and Setup The IR calibration algorithm available from Analog Devices, Inc., is based on a low complexity, 2D optimization algorithm that can be implemented in an external microprocessor or microcontroller. The magnitude of the phase adjust is set using the IR_PHASE_ ADJUST_MAG bits (Register 5, Bits[DB23:DB20]). This correction can be applied to either the I or Q channel, depending on the value of the IR_PHASE_ADJUST_DIRECTION bit (Register 5, Bit DB24). The magnitude of the I/Q gain is adjusted using the IR_GAIN_ ADJUST_MAG bits (Register 5, Bits[DB29:DB25]). This correction can be applied to either the I or Q channel, depending on the value of the IR_GAIN_ADJUST_I/Q bit (Register 5, Bit DB30), whereas the IR_GAIN_ADJUST_UP/DN bit (Register 5, Bit DB31) sets whether the gain adjustment defines a gain or an attenuation adjust. Rev. 0 | Page 38 of 60 ADF7021-V ADF7021-V RFIN LNA GAIN ADJUST RFIN MUX INTERNAL SIGNAL SOURCE POLYPHASE IF FILTER RSSI/ LOG AMP 7-BIT ADC PHASE ADJUST I Q FROM LO SERIAL INTERFACE 4 PHASE ADJUST REGISTER 5 4 GAIN ADJUST REGISTER 5 RSSI READBACK MICROCONTROLLER 08635-050 I/Q GAIN/PHASE ADJUST AND RSSI MEASUREMENT ALGORITHM Figure 51. Image Rejection Calibration Using the Internal Calibration Source and a Microcontroller PACKET STRUCTURE AND CODING The suggested packet structure to use with the ADF7021-V is shown in Figure 53. PREAMBLE SYNC WORD ID FIELD DATA FIELD CRC 08635-052 The calibration results are valid over changes in the ADF7021-V supply voltage. However, there is some variation with temperature. A typical plot of variation in image rejection over temperature after initial calibrations at −40°C, +25°C, and +85°C is shown in Figure 52. The internal temperature sensor on the ADF7021-V can be used to determine whether a new IR calibration is required. Figure 53. Typical Format of a Transmit Protocol 60 CAL AT +25°C See the Receiver Setup section for information about the required preamble structure and length for the various modulation schemes. 40 PROGRAMMING AFTER INITIAL POWER-UP CAL AT +85°C CAL AT –40°C 30 VDD = 3.0V IFBW = 25kHz 20 10 WANTED SIGNAL: RF FREQ = 430MHz MODULATION = 2FSK DATA RATE = 9.6kbps, DATA = PRBS9 fDEV = 4kHz LEVEL= –100dBm 0 –60 –40 –20 0 INTERFERER SIGNAL: RF FREQ = 429.8MHz MODULATION = 2FSK DATA RATE = 9.6kbps, DATA = PRBS11 fDEV = 4kHz 20 40 TEMPERATURE (°C) 60 80 100 08635-051 IMAGE REJECTION (dB) 50 Figure 52. Image Rejection vs. Temperature After Initial Calibrations at −40°C, +25°C, and +85°C Table 23 lists the minimum number of writes needed to set up the ADF7021-V in either Tx or Rx mode after CE is brought high for a minimum of 100 μs before programming any register. Additional registers can also be written to tailor the part to a particular application, such as setting up sync byte detection or enabling AFC. When going from Tx to Rx or vice versa, the user needs to toggle the Tx/Rx bit and write only to Register 0 to alter the LO by 100 kHz. Table 23. Minimum Register Writes Required for Tx/Rx Setup Mode Tx Rx Tx to Rx and Rx to Tx Rev. 0 | Page 39 of 60 Required Register Writes Reg 1, Reg 3, Reg 0, Reg 2 Reg 1, Reg 3, Reg 5, Reg 0, Reg 4 Reg 0 ADF7021-V The recommended programming sequences for transmit and receive are shown in Figure 54 and Figure 55, respectively. TCXO REFERENCE The difference in the power-up routine for a TCXO and XTAL reference is shown in these figures. POWER-DOWN CE LOW TURN ON EXTERNAL VCO AND ALLOW ADEQUATE SETTLING XTAL REFERENCE CE HIGH WAIT 50µs + 1ms (REGULATOR POWER-UP + TYPICAL XTAL SETTLING) CHECK FOR REGULATOR READY CE HIGH WAIT 50µs (REGULATOR POWER-UP) CHECK FOR REGULATOR READY WRITE TO REGISTER 1 WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS) WRITE TO REGISTER 0 (TURNS ON PLL) WAIT 40µs (TYPICAL PLL SETTLING) WRITE TO REGISTER 2 (TURNS ON PA) WAIT FOR PA TO RAMP UP (ONLY IF PA RAMP ENABLED) Tx MODE WAIT FOR Tx LATENCY NUMBER OF BITS (REFER TO TABLE 11) WRITE TO REGISTER 2 (TURNS OFF PA) WAIT FOR PA TO RAMP DOWN 08635-053 CE LOW POWER-DOWN OPTIONAL. ONLY NECESSARY IF PA RAMP-DOWN IS REQUIRED. Figure 54. Power-Up Sequence for Transmit Mode Rev. 0 | Page 40 of 60 ADF7021-V TCXO REFERENCE XTAL REFERENCE POWER-DOWN CE LOW TURN ON EXTERNAL VCO AND ALLOW ADEQUATE SETTLING CE HIGH WAIT 50µs + 1ms (REGULATOR POWER-UP + TYPICAL XTAL SETTLING) CHECK FOR REGULATOR READY CE HIGH WAIT 50µs (REGULATOR POWER-UP) CHECK FOR REGULATOR READY WRITE TO REGISTER 1 WRITE TO REGISTER 3 (TURNS ON Tx/Rx CLOCKS) WRITE TO REGISTER 6 (SETS UP IF FILTER FINE CALIBRATION) OPTIONAL: ONLY NECESSARY IF IF FILTER FINE CALIBRATION IS REQUIRED. WRITE TO REGISTER 5 (STARTS IF FILTER CALIBRATION) WAIT 0.2ms (COARSE CAL) OR WAIT 8.2ms (COARSE CALIBRATION + FINE CALIBRATION) WRITE TO REGISTER 11 (SET UP SWD) WRITE TO REGISTER 12 (ENABLE SWD) OPTIONAL: ONLY NECESSARY IF SWD IS REQUIRED. WRITE TO REGISTER 0 (TURNS ON PLL) WAIT 40µs (TYPICAL PLL SETTLING) WRITE TO REGISTER 4 (TURNS ON DEMOD) WRITE TO REGISTER 10 (TURNS ON AFC) OPTIONAL: ONLY NECESSARY IF AFC IS REQUIRED. Rx MODE 08635-054 CE LOW POWER-DOWN OPTIONAL. Figure 55. Power-Up Sequence for Receive Mode Rev. 0 | Page 41 of 60 ADF7021-V For recommended component values, see the ADF7021-V evaluation board data sheet and the AN-859 Application Note, accessible from the ADF7021-V product page. Follow the reference design schematic closely to ensure optimum performance in narrow-band applications. APPLICATIONS CIRCUIT The ADF7021-V requires very few external components for operation. Figure 56 shows the recommended application circuit. Note that the power supply decoupling and regulator capacitors are omitted for clarity. EXTERNAL VCO RFOUT LOOP FILTER VTUNE VDD TCXO REFERENCE RFOUT 5 RFGND 6 RFIN 37 38 39 OSC1 VDD3 OSC2 41 40 CREG3 42 CPOUT 43 44 L2 VDD 45 46 L1 47 SWD 33 VDD2 32 ADF7021-V ADCIN 30 RFIN 8 RLNA GND2 29 9 VDD4 SCLK 28 10 RSET SREAD 27 CREG4 SDATA SLE 26 25 CE TEST_A TO MICROCONTROLLER CONFIGURATION INTERFACE 24 23 FILT_Q FILT_Q GND4 22 21 20 GND4 19 FILT_I FILT_I MIX_Q RSET RESISTOR 18 13 RLNA RESISTOR 17 MIX_I GND4 MIX_Q 11 VDD CREG2 31 7 12 TO MICROCONTROLLER Tx/Rx SIGNAL INTERFACE CHIP ENABLE TO MICROCONTROLLER NOTES 1. PINS[13:18], PINS[20:21], AND PIN 23 ARE TEST PINS AND ARE NOT USED IN NORMAL OPERATION. Figure 56. Typical Application Circuit (Regulator Capacitors and Power Supply Decoupling Not Shown) Rev. 0 | Page 42 of 60 08635-055 4 CLKOUT 36 TxRxCLK 35 TxRxDATA 34 16 VDD VDD1 MIX_I T-STAGE LC FILTER 3 15 VDD VCOIN CREG1 14 ANTENNA CONNECTION 2 MUXOUT 1 MATCHING GND VDD GND1 CVCO 48 VDD ADF7021-V SERIAL INTERFACE RSSI Readback The serial interface allows the user to program the 16 32-bit registers using a 3-wire interface (SCLK, SDATA, and SLE). It consists of a level shifter, 32-bit shift register, and 16 latches. Signals should be CMOS compatible. The serial interface is powered by the regulator and, therefore, is inactive when CE is low. The format of the RSSI readback word is shown in Figure 57. It comprises the RSSI-level information (Bit RV7 to Bit RV1), the current filter gain (FG2, FG1), and the current LNA gain (LG2, LG1) setting. The filter and LNA gain are coded in accordance with the definitions in the Register 9—AGC Register section. For signal levels below −100 dBm, averaging the measured RSSI values improves accuracy. The input power can be calculated from the RSSI readback value as described in the RSSI/AGC section. Data is clocked into the register, MSB first, on the rising edge of each clock (SCLK). Data is transferred to one of 16 latches on the rising edge of SLE. The destination latch is determined by the value of the four control bits (C4 to C1); these bits are the four LSBs, DB3 to DB0, as shown in Figure 2. Data can also be read back on the SREAD pin. Readback with AFC or Linear Demodulation On To perform any readback with the AFC on, the AGC must first be locked. To lock the AGC, use the LOCK_THRESHOLD_MODE bits (Bits[DB5:DB4] in Register 12) for packet reception. The lock threshold mode locks the threshold of the envelope detector, as well as the AFC and AGC circuits. It can be set to lock on reception of a valid SWD and remain locked until it is released by a subsequent SPI command (LOCK_THRESHOLD_MODE = 1). It can also be set to lock on reception of a valid SWD for a specified number of bytes by setting LOCK_THRESHOLD_MODE = 2; or it can be locked at any time by setting LOCK_THRESHOLD_ MODE = 3. After the threshold is locked, a readback can be performed. The AGC/AFC lock is released by setting LOCK_THRESHOLD_MODE = 0. READBACK FORMAT The readback operation is initiated by writing a valid control word to the readback setup register and enabling the READBACK_ SELECT bit (Register 7, Bit DB8 = 1). The readback can begin after the control word has been latched with the SLE signal. SLE must be kept high while the data is being read out. Each active edge at the SCLK pin successively clocks the readback word out at the SREAD pin, MSB first (see Figure 57). The data appearing at the first clock cycle following the latch operation must be ignored. An extra clock cycle is needed after the 16th readback bit to return the SREAD pin to tristate. Therefore, 18 total clock cycles are needed for each readback. After the 18th clock cycle, SLE should be brought low. Battery Voltage/ADCIN/Temperature Sensor Readback AFC Readback The battery voltage is measured at Pin VDD4. The readback information is contained in Bit RV7 to Bit RV1. This also applies to the readback of the voltage at the ADCIN pin and the temperature sensor. From the readback information, the battery or ADCIN voltage can be determined as follows: The AFC readback is valid only during the reception of FSK signals with either the linear or correlator demodulator active. The AFC readback value is formatted as a signed, 16-bit integer comprising Bit RV16 to Bit RV1 and is scaled according to the following formula: VBATTERY = (BATTERY VOLTAGE READBACK)/21.1 FREQ RB (Hz) = (AFC READBACK × DEMOD CLK)/218 VADCIN = (ADCIN VOLTAGE READBACK)/42.1 In the absence of frequency errors, FREQ RB is equal to the IF frequency of 100 kHz. Note that, for the AFC readback to yield a valid result, the downconverted input signal must not fall outside the bandwidth of the analog IF filter. At low input signal levels, the variation in the readback value can be improved by averaging. The temperature can be calculated as follows: Temperature (°C) = −40 + [(68.4 − TEMP READBACK) × 9.32] READBACK VALUE DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 AFC READBACK RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 RSSI READBACK X X X X X LG2 LG1 FG2 FG1 RV7 RV6 RV5 RV4 RV3 RV2 RV1 BATTERY VOLTAGE/ADCIN/ TEMP. SENSOR READBACK X X X X X X X X X RV7 RV6 RV5 RV4 RV3 RV2 RV1 SILICON REVISION RV16 RV15 RV14 RV13 RV12 RV11 RV10 RV9 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 FILTER CAL READBACK 0 0 0 0 0 0 0 0 RV8 RV7 RV6 RV5 RV4 RV3 RV2 RV1 Figure 57. Readback Value Table Rev. 0 | Page 43 of 60 08635-056 READBACK MODE ADF7021-V Silicon Revision Readback UART Mode The silicon revision readback word is valid without setting any other registers. The silicon revision word is coded with four quartets in BCD format. The product code (PC) is coded with three quartets extending from Bit RV16 to Bit RV5. The revision code (RC) is coded with one quartet extending from Bit RV4 to Bit RV1. The product code for the ADF7021-V should read back as PC = 0x212. The current revision code should read as RC = 0x0. In UART mode, the TxRxCLK pin is configured to input transmit data in transmit mode. In receive mode, the receive data is available on the TxRxDATA pin, thus providing an asynchronous data interface. The UART mode can only be used with oversampled 2FSK modulation. Figure 59 shows a possible interface to a microcontroller using the UART mode of the ADF7021-V. To enable the UART interface mode, set Bit DB28 in Register 0 high. Figure 8 and Figure 9 show the relevant timing diagrams for UART mode. IF_FILTER_ADJUST = FILTER_CAL_READBACK − 128 The result should be programmed into Register 5, Bits[DB19:DB14] as described in the Register 5—IF Filter Setup Register section. INTERFACING TO A MICROCONTROLLER/DSP Standard Transmit/Receive Data Interface The standard transmit/receive signal and configuration interface to a microcontroller is shown in Figure 58. In transmit mode, the ADF7021-V provides the data clock on the TxRxCLK pin, and the TxRxDATA pin is used as the data input. The transmit data is clocked into the ADF7021-V on the rising edge of TxRxCLK. ADF7021-V TxRxDATA MOSI SCLOCK TxRxCLK SS GPIO GPIO P2.5 SLE P2.6 SDATA P2.7 SCLK SREAD SLE SDATA SCLK Figure 59. ADF7021-V (UART Mode) to Asynchronous Microcontroller Interface SPI Mode In SPI mode, the TxRxCLK pin is configured to input transmit data in transmit mode. In receive mode, the receive data is available on the TxRxDATA pin. The data clock in both transmit and receive modes is available on the CLKOUT pin. In transmit mode, data is clocked into the ADF7021-V on the rising edge of CLKOUT. In receive mode, the TxRxDATA data pin should be sampled by the microcontroller on the rising edge of CLKOUT. To enable SPI interface mode, set Bit DB28 in Register 0 high and set Bits[DB19:DB17] in Register 15 to 0x7. Figure 8 and Figure 9 show the relevant timing diagrams for SPI mode; Figure 60 shows the recommended interface to a microcontroller using the SPI mode of the ADF7021-V. MICROCONTROLLER SWD SREAD TxRxDATA SWD CE P2.4 RxDATA CE MISO SPI 08635-057 P3.7 P3.2/INT0 TxRxCLK ADF7021-V TxRxCLK MOSI TxRxDATA SCLK CLKOUT CE Figure 58. ADuC84x to ADF7021-V Connection Diagram SWD In receive mode, the ADF7021-V provides the synchronized data clock on the TxRxCLK pin. The received data is available on the TxRxDATA pin. The rising edge of TxRxCLK should be used to clock the receive data into the microcontroller. See Figure 4 and Figure 5 for the relevant timing diagrams. In 4FSK transmit mode, the MSB of the transmit symbol is clocked into the ADF7021-V on the first rising edge of the data clock from the TxRxCLK pin. In 4FSK receive mode, the MSB of the first payload symbol is clocked out on the first falling edge of the data clock after the SWD and should be clocked into the microcontroller on the following rising edge. See Figure 6 and Figure 7 for the relevant timing diagrams. SREAD GPIO SLE SDATA SCLK 08635-059 MISO UART TxDATA Figure 60. ADF7021-V (SPI Mode) to Microcontroller Interface ADSP-BF533 Interface The suggested method of interfacing to the Blackfin® ADSP-BF533 is shown in Figure 61. ADSP-BF533 SCK ADF7021-V SCLK MOSI SDATA MISO SREAD PF5 RSCLK1 DT1PRI SLE TxRxCLK TxRxDATA DR1PRI RFS1 PF6 SWD CE 08635-060 ADuC84x ADF7021-V MICROCONTROLLER The filter calibration readback word is contained in Bit RV8 to Bit RV1 (see Figure 57). This readback can be used for manual filter adjustment, thereby avoiding the need to do an IF filter calibration in some instances. The manual adjust value is programmed using Register 5, Bits[DB19:DB14]. To calculate the manual adjustment based on a filter calibration readback, use the following formula: 08635-058 Filter Bandwidth Calibration Readback Figure 61. ADSP-BF533 to ADF7021-V Connection Diagram Rev. 0 | Page 44 of 60 ADF7021-V M14 M13 ... M3 M2 M1 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 0 0 0 . . . 1 1 1 1 ... ... ... ... ... ... ... ... ... ... 0 0 0 . . . 1 1 1 1 0 0 1 . . . 0 0 1 1 0 1 0 . . . 0 1 0 1 UART_MODE 0 1 DISABLED ENABLED M3 M2 M1 MUXOUT 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 REGULATOR_READY (DEFAULT) FILTER_CAL_COMPLETE DIGITAL_LOCK_DETECT RSSI_READY Tx_Rx LOGIC_ZERO TRISTATE LOGIC_ONE N8 N7 N6 N5 N4 N3 N2 N1 INTEGER_N DIVIDE RATIO 0 0 . . . 1 0 0 . . . 1 0 0 . . . 1 1 1 . . . 1 0 1 . . . 1 1 0 . . . 1 1 0 . . . 0 1 0 . . . 1 23 24 . . . 253 1 1 1 1 1 1 1 0 254 1 1 1 1 1 1 1 1 255 DB1 DB0 FRACTIONAL_N DIVIDE RATIO 0 1 2 . . . 32,764 32,765 32,766 32,767 08635-061 U1 C1 (0) DB3 M15 TRANSMIT RECEIVE C2 (0) DB4 M1 C4 (0) Tx/Rx 0 1 DB2 DB5 DB7 M4 M2 DB8 M5 DB6 DB9 M3 DB10 DB12 M9 M6 DB13 M10 M7 DB14 M11 DB11 DB15 M12 M8 DB16 M13 DB20 N2 DB17 DB21 N3 M14 DB22 N4 DB18 DB23 N5 DB19 DB24 N6 N1 DB25 N7 M15 DB26 TR1 C3 (0) ADDRESS BITS FRACTIONAL_N N8 DB28 UART_MODE U1 Tx/Rx DB29 M1 INTEGER_N DB27 DB30 M2 MUXOUT TR1 DB31 M3 REGISTER 0—N REGISTER Figure 62. Register 0—N Register Map • • The RF output frequency is calculated as follows: For direct output, FRACTIONAL _ N ⎞ ⎛ RFOUT = PFD × ⎜ INTEGER _ N + ⎟ 215 ⎝ ⎠ With RF_DIVIDE_BY_2 (Register 1, Bit DB18) enabled, FRACTIONAL _ N ⎞ ⎛ RFOUT = PFD × 0.5 × ⎜ INTEGER _ N + ⎟ 215 ⎝ ⎠ • In UART/SPI mode, the TxRxCLK pin is used to input the transmitted data. The received data is available on the TxRxDATA pin. Rev. 0 | Page 45 of 60 In the MUXOUT map (Bits[DB31:DB29]), FILTER_CAL_ COMPLETE indicates when a coarse or coarse plus fine IF filter calibration has finished. DIGITAL_LOCK_DETECT indicates when the PLL has locked. RSSI_READY indicates that the RSSI signal has settled and an RSSI readback can be performed. Tx_Rx gives the status of Bit DB27 in this register, which can be used to control an external Tx/Rx switch. ADF7021-V DB6 DB5 DB4 R3 R2 R1 DB0 DB7 CL1 RF R_COUNTER R1 DIVIDE RATIO 1 1 0 2 . . . . . . 1 7 CLKOUT_ DIVIDE RATIO OFF 2 4 . . . 30 XTAL_ DOUBLER DISABLED ENABLED X1 XOSC_ENABLE 0 OFF 1 ON ICP (mA) 0.3 0.9 1.5 2.1 XB2 XB1 0 0 1 1 0 1 0 1 XTAL_BIAS 20µA 25µA 30µA 35µA 08635-062 RSET = 3.6kΩ CP2 CP1 0 0 0 1 1 0 1 1 DB1 DB8 CL2 D1 0 1 C1 (1) DB9 CL3 50Ω HIGH IMPEDANCE CL1 0 1 0 . . . 1 C2 (0) DB10 CL4 0 1 CL2 0 0 1 . . . 1 DB2 DB11 D1 BUFFER_ IMPEDANCE CL3 0 0 0 . . . 1 C3 (0) DB12 X1 VE1 CL4 0 0 0 . . . 1 DB3 DB13 XB1 OFF ON R2 0 1 . . . 1 C4 (0) XOSC_ ENABLE XTAL_ DOUBLER CP_ CURRENT DB14 DB19 RE1 XB2 DB20 RE2 DB15 DB21 RE3 DB16 DB22 RE4 CP1 R3 0 0 . . . 1 RFD1 RF_DIVIDE_BY_2 0 1 ADDRESS BITS R_COUNTER CP2 DB23 RE5 CLKOUT_ DIVIDE DB17 DB24 RE6 XTAL_ BIAS VE1 DB25 RE7 RESERVED RFD1 DB18 RF_DIVIDE_ BY_2 BUFFER_ IMPEDANCE REGISTER 1—OSCILLATOR REGISTER Figure 63. Register 1—Oscillator Register Map • The R_COUNTER and XTAL_DOUBLER relationship is as follows: If XTAL_DOUBLER = 0, PFD = • • XTAL R _ COUNTER If XTAL_DOUBLER = 1, PFD = XTAL × 2 R _ COUNTER Rev. 0 | Page 46 of 60 CLKOUT_DIVIDE is a divided-down and inverted version of the XTAL and is available on Pin 36 (CLKOUT). Set XOSC_ENABLE high when using an external crystal. If using an external oscillator (such as TCXO) with CMOS level outputs into Pin OSC2, set XOSC_ENABLE low. If using an external oscillator with a 0.8 V p-p clipped sine wave output into Pin OSC1, set XOSC_ENABLE high. ADF7021-V DI1 TxDATA_INVERT 0 0 1 1 0 1 0 1 NORMAL INVERT CLK INVERT DATA INV CLK AND DATA TFD9 ... 0 0 0 0 . 1 NRC1 R-COSINE_ALPHA 0 1 0.5 (DEFAULT) 0.7 0 0 1 1 . 1 0 1 0 1 . 1 0 1 0 1 5µA 7µA 9µA 11µA 0 1 PR2 PR1 PA_RAMP RATE 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 NO RAMP 256 CODES/BIT 128 CODES/BIT 64 CODES/BIT 32 CODES/BIT 16 CODES/BIT 8 CODES/BIT 4 CODES/BIT ... P2 P1 POWER_ AMPLIFIER 0 0 0 0 . . 1 0 0 0 0 . . 1 ... ... ... ... ... ... ... 0 0 1 1 . . 1 0 1 0 1 . . 1 0 (PA OFF) 1 (–16.0dBm) 2 3 . . 63 (+13dBm) DB6 DB5 DB4 DB3 DB2 DB1 DB0 S3 S2 S1 C4 (0) C3 (0) C2 (1) C1 (0) PA_ ENABLE DB7 DB8 OFF ON 0 0 0 0 1 1 1 1 P5 ADDRESS BITS MODULATION_ SCHEME PE1 PA_ENABLE PR3 P6 PE1 PR1 DB9 PR2 DB11 PA1 PA1 PA_BIAS 0 0 1 1 DB10 DB12 PA2 PA2 PA_RAMP PR3 DB13 DB14 P1 PA_BIAS P2 DB16 P4 DB15 DB17 P5 0 1 2 3 . 511 P3 DB18 P6 TFD1 DB19 TFD2 DB20 TFD3 DB21 TFD4 DB22 TFD3 TFD2 TFD1 fDEV ... ... ... ... ... ... 0 0 0 0 . 1 POWER_AMPLIFIER S3 S2 S1 MODULATION_SCHEME 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 2FSK GAUSSIAN 2FSK 3FSK 4FSK OVERSAMPLED 2FSK RAISED COSINE 2FSK RAISED COSINE 3FSK RAISED COSINE 4FSK 08635-063 DI2 TFD5 DB23 TFD6 DB24 TFD7 DB25 TFD8 DB26 DB28 DI1 Tx_FREQUENCY_DEVIATION TFD9 DB27 DB29 DI2 TxDATA_ INVERT NRC1 DB30 R-COSINE_ ALPHA REGISTER 2—TRANSMIT MODULATION REGISTER Figure 64. Register 2—Transmit Modulation Register Map • The 2FSK/3FSK/4FSK frequency deviation is expressed as follows: • For direct RF output, Frequency Deviation (Hz) = Tx_FREQUENCY_DEVIATION × PFD • 216 With RF_DIVIDE_BY_2 (Register 1, Bit DB18) enabled, Frequency Deviation (Hz) = 0.5 × Tx_FREQUENCY_DEVIATION × PFD 216 where: Tx_FREQUENCY_DEVIATION is set by Bits[DB27:DB19]. PFD is the PFD frequency. • In the case of 4FSK, there are tones at ±3 × the frequency deviation and at ±1 × the frequency deviation. Rev. 0 | Page 47 of 60 The power amplifier (PA) ramps at the programmed rate (Bits[DB10:DB8]) until it reaches its programmed level (Bits[DB18:DB13]). If the PA is enabled/disabled by the PA_ENABLE bit (Bit DB7), it ramps up and down. If it is enabled/disabled by the Tx/Rx bit (Register 0, Bit DB27), it ramps up and turns hard off. R-COSINE_ALPHA sets the roll-off factor (alpha) of the raised cosine data filter to either 0.5 or 0.7. The alpha is set to 0.5 by default, but the raised cosine filter bandwidth can be increased to provide less aggressive data filtering by using an alpha of 0.7. ADF7021-V GD5 GD4 GD3 GD2 GD1 AGC_CLK_DIVIDE 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 0 ... 1 0 1 ... 1 INVALID 1 ... 63 DB5 BK2 DB0 DB6 OK1 C1 (1) DB7 OK2 DB1 DB8 OK3 C2 (1) DB9 OK4 DB2 DB10 FS1 DB3 DB11 FS2 C3 (0) DB12 FS3 C4 (0) DB13 FS4 DB4 DB14 BK1 DB15 FS5 ADDRESS BITS SK3 SK2 SK1 SEQ_CLK_DIVIDE BK2 BK1 BBOS_CLK_DIVIDE 0 0 . 1 1 0 1 . 1 1 1 0 . 0 1 1 2 . 254 255 0 0 1 1 0 1 0 1 4 8 16 32 OK4 OK3 OK2 OK1 DEMOD_CLK_DIVIDE 0 0 ... 1 INVALID 1 ... 15 FS8 FS7 ... FS3 FS2 FS1 0 0 . 1 1 0 0 . 1 1 ... ... ... ... ... 0 0 . 1 1 0 1 . 1 1 1 0 . 0 1 0 0 ... 1 0 0 ... 1 0 1 ... 1 CDR_CLK_ DIVIDE 1 2 . 254 255 08635-064 GD6 FS6 ... ... ... ... ... ... DB16 0 0 . 1 1 DB17 SK7 0 0 . 1 1 FS7 DB22 SK5 DB18 DB23 SK6 SK8 FS8 DB24 SK7 SK1 DB25 SK8 DB19 DB26 GD1 DB20 DB27 GD2 SK2 DB28 GD3 DB21 DB29 GD4 SK3 DB30 GD5 DEMOD_CLK_ DIVIDE CDR_CLK_DIVIDE SK4 DB31 SEQ_CLK_DIVIDE GD6 AGC_CLK_DIVIDE BBOS_CLK_ DIVIDE REGISTER 3—TRANSMIT/RECEIVE CLOCK REGISTER Figure 65. Register 3—Transmit/Receive Clock Register Map • • Baseband offset clock frequency (BBOS CLK) must be greater than 1 MHz and less than 2 MHz, where BBOS CLK = (XTAL/BBOS_CLK_DIVIDE) • SEQ CLK = (XTAL/SEQ_CLK_DIVIDE) Set the demodulator clock (DEMOD CLK) such that 2 MHz ≤ DEMOD CLK ≤ 15 MHz, where • DEMOD CLK = (XTAL/DEMOD_CLK_DIVIDE) • The sequencer clock (SEQ CLK) supplies the clock to the digital receive block. It should be as close to 100 kHz as possible. For 2FSK/3FSK, the clock/data recovery frequency (CDR CLK) must be within 2% of (32 × data rate). For 4FSK, the CDR CLK must be within 2% of (32 × symbol rate). CDR CLK = (DEMOD CLK/CDR_CLK_DIVIDE) Rev. 0 | Page 48 of 60 The time allowed for each AGC step to settle is determined by the AGC update rate. It should be set close to 3 kHz. AGC Update Rate (Hz) = (SEQ CLK/AGC_CLK_DIVIDE) ADF7021-V 0 0 . . . . 1 . . . . . . . 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 1 . . . . 1 DB3 DB2 DB1 DB0 C2 (0) C1 (0) DB9 RI2 C3 (1) DB10 TD1 C4 (0) DB11 TD2 DB4 DB12 TD3 DS1 DB13 TD4 DB5 DB14 TD5 DOT_PRODUCT CROSS_PRODUCT DOT_PRODUCT NORMAL INVERT CLK INVERT DATA INVERT CLK/DATA 1 2 . . . . 1023 TD10 . TD6 TD5 TD4 TD3 TD2 TD1 DISCRIMINATOR_BW 0 0 . . . . 0 0 0 . . . . 1 0 0 . . . . 0 0 0 . . . . 1 0 1 . . . . 0 1 0 . . . . 0 1 2 . . . . 660 . . . . . . . DB6 DB15 TD6 DOT_PRODUCT 0 1 Rx_INVERT 1 0 . . . . 1 0 0 . . . . 1 DS2 DB16 TD7 DP1 DW6 DW5 DW4 DW3 DW2 DW1 POST_DEMOD_BW 0 0 . . . . 1 ADDRESS BITS DS3 DS2 DS1 DEMOD_SCHEME 0 0 0 0 1 1 1 1 2FSK LINEAR DEMODULATOR 2FSK CORRELATOR DEMODULATOR 3FSK DEMODULATOR 4FSK DEMODULATOR RESERVED RESERVED RESERVED RESERVED 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 08635-065 DW10 . 0 1 0 1 DS3 DB17 TD8 0 0 1 1 DB7 DB18 TD9 RI2 RI1 DP1 DB19 TD10 DW1 DB20 DW2 DB21 IF_FILTER _ IFB2 IFB1 BW 0 0 9kHz 0 1 13.5kHz 1 0 18.5kHz 1 1 INVALID DEMOD_ SCHEME DB8 Rx_ INVERT DISCRIMINATOR_BW DW3 DB22 DW4 DB23 DW5 DB24 DW6 DB25 DW7 DB26 DW8 DB27 DW9 DB28 DB30 IFB1 DW10 DB29 DB31 IFB2 POST_DEMOD_BW RI1 IF_FILTER_BW REGISTER 4—DEMODULATOR SETUP REGISTER Figure 66. Register 4—Demodulator Setup Register Map • where: Round is rounded to the nearest integer. Round4FSK is rounded to the nearest of the following integers: 32, 31, 28, 27, 24, 23, 20, 19, 16, 15, 12, 11, 8, 7, 4, 3. fDEV is the transmit frequency deviation in Hz. For 4FSK, fDEV is the frequency deviation used for the ±1 symbols (that is, the inner frequency deviations). To solve for DISCRIMINATOR_BW, (Bits[DB19:DB10]), use the following equation: ⎛ DEMOD CLK × K DISCRIMINATOR _ BW = ⎜ ⎜ 400 × 10 3 ⎝ ⎞ ⎟ ⎟ ⎠ where the maximum value = 660. For 2FSK, ⎛ 100 × 10 3 K = Round ⎜ ⎜ f DEV ⎝ ⎞ ⎟ ⎟ ⎠ • Rx_INVERT (Bits[DB9:DB8]) and DOT_PRODUCT (Bit DB7) must be set as indicated in Table 16 and Table 17. • POST_DEMOD_BW (Bits[DB29:DB20]) sets the bandwidth of the postdemodulator filter. To solve for POST_DEMOD_BW, use the following equation: For 3FSK, ⎛ 100 × 10 3 K = Round ⎜ ⎜ 2×f DEV ⎝ ⎞ ⎟ ⎟ ⎠ POST_DEMOD_BW = For 4FSK, K = Round 4 FSK ⎛ 100 × 10 3 ⎜ ⎜ 4×f DEV ⎝ 211 × π × f CUTOFF DEMOD CLK where fCUTOFF (the cutoff frequency of the postdemodulator filter) should typically be set equal to 0.75 × the data rate in 2FSK. In 3FSK, it should be set equal to the data rate, whereas in 4FSK, it should be set equal to 1.6 × the symbol rate. ⎞ ⎟ ⎟ ⎠ Rev. 0 | Page 49 of 60 ADF7021-V IF_CAL_COARSE DB2 DB1 DB0 C2 (0) C1 (1) DB3 C3 (1) DB4 CC1 IFD7 DB11 IFD8 DB12 IFD9 DB13 IFA1 DB14 IFA2 DB15 IFA3 DB16 IFA4 DB17 IFA5 DB18 IFA6 DB19 ADDRESS BITS C4 (0) DB20 PM1 DB5 DB21 PM2 IFD1 DB22 PM3 DB6 DB23 PM4 DB7 IR_PHASE_ DB24 ADJUST_DIRECTION PD1 IFD2 DB25 GM1 IFD3 DB26 GM2 DB8 DB27 GM3 IFD4 DB28 GM4 IF_FILTER_DIVIDER IF_FILTER_ADJUST DB9 DB29 GM5 IR_PHASE_ ADJUST_MAG IFD5 IR_GAIN_ ADJUST_I/Q DB30 GQ1 IR_GAIN_ ADJUST_MAG IFD6 DB10 IR_GAIN_ ADJUST_UP/DN DB31 GA1 REGISTER 5—IF FILTER SETUP REGISTER CC1 IF_CAL_COARSE 0 1 PM4 PM3 IR_PHASE_ PM2 PM1 ADJUST_MAG 0 0 0 . 1 0 0 0 . 1 0 0 1 . 1 0 1 2 ... 15 0 1 0 . 1 IFD9 . 0 0 . . . . 1 PD1 IR_PHASE_ADJUST_DIRECTION 0 1 0 0 0 . 1 0 0 0 . 1 GM3 IR_GAIN_ GM2 GM1 ADJUST_MAG 0 0 0 . 1 0 0 1 . 1 0 1 0 . 1 GQ1 IR_GAIN_ADJUST_I/Q 0 1 ADJUST I CH ADJUST Q CH GA1 IR_GAIN_ADJUST_UP/DN 0 1 GAIN ATTENUATE 0 1 2 ... 31 IFA6 IFA5 ... ... 0 0 ... 0 0 ... 0 0 ... .. .. ... 0 1 ... 1 0 ... 1 0 ... 1 0 ... 1 . ... 1 1 IF_FILTER_ IFD6 IFD5 IFD4 IFD3 IFD2 IFD1 DIVIDER 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 0 . . . . 1 0 1 . . . . 1 1 0 . . . . 1 1 2 . . . . 511 IFA2 IFA1 IF_FILTER_ADJUST 0 0 1 .. 1 0 0 1 . 1 0 1 0 .. 1 0 1 0 . 1 0 +1 +2 ... +31 0 –1 –2 ... –31 08635-066 GM5 GM4 ADJUST I CH ADJUST Q CH . . . . . . . DISABLED ENABLED Figure 67. Register 5—IF Filter Setup Register Map • • A coarse IF filter calibration is performed when the IF_CAL_COARSE bit (Bit DB4) is set. If the IF_FINE_ CAL bit (Register 6, Bit DB4) has been previously set, a fine IF filter calibration is automatically performed after the coarse calibration. Set IF_FILTER_DIVIDER such that XTAL = 50 kHz IF _ FILTER _ DIVIDER • • Rev. 0 | Page 50 of 60 IF_FILTER_ADJUST allows the IF fine filter calibration result to be programmed directly on subsequent receiver power-ups, thereby eliminating the need to redo a fine filter calibration in some instances. See the Filter Bandwidth Calibration Readback section for information about using the IF_FILTER_ADJUST bits. Bits[DB31:DB20] are used for image rejection calibration. See the Image Rejection Calibration section for information about how to program these parameters. ADF7021-V IF_FINE_ CAL DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 LT7 LT6 LT5 LT4 LT3 LT2 LT1 FC1 C4 (0) C3 (1) C2 (1) C1 (0) DB17 UT5 LT8 DB18 UT6 DB13 DB19 UT7 DB14 DB20 UT8 ADDRESS BITS UT1 DB21 CD1 IF_CAL_LOWER_TONE_DIVIDE UT2 DB22 CD2 DB15 DB23 CD3 UT3 DB24 CD4 DB16 DB25 CD5 UT4 DB26 CD6 IF_CAL_UPPER_TONE_DIVIDE DB27 IF_CAL_DWELL_TIME CD7 IRC2 DB29 IR_CAL_ SOURCE_ IRC1 DB28 DRIVE_LEVEL IRD1 DB30 IR_CAL_ SOURCE ÷2 REGISTER 6—IF FINE CALIBRATION SETUP REGISTER IRD1 IR_CAL_SOURCE ÷2 0 1 SOURCE ÷2 OFF SOURCE ÷2 ON UT8 UT7 ... 0 0 0 . . 0 IR_CAL_SOURCE_ IRC2 IRC1 DRIVE_LEVEL 0 0 OFF 0 1 LOW 1 0 MED 1 1 HIGH 0 0 0 . . 1 ... ... ... ... ... ... UT3 UT2 UT1 IF_CAL_UPPER_ TONE_DIVIDE 0 0 0 . . 1 0 1 1 . . 1 1 0 1 . . 1 1 2 3 . . 127 LT8 LT7 ... LT3 CD7 ... IF_CAL_ CD3 CD2 CD1 DWELL_TIME 0 0 0 . . 1 ... ... ... ... ... ... 0 0 0 . . 1 1 0 1 . . 1 1 2 3 . . 127 0 0 0 . . 1 ... ... ... ... ... ... 0 0 0 . . 1 IF_FINE_CAL 0 1 DISABLED ENABLED LT2 LT1 IF_CAL_LOWER_ TONE_DIVIDE 0 1 1 . . 1 1 0 1 . . 1 1 2 3 . . 255 08635-067 0 1 1 . . 1 0 0 0 . . 1 FC1 Figure 68. Register 6—IF Fine Calibration Setup Register Map • • A fine IF filter calibration is set by enabling the IF_FINE_ CAL bit (Bit DB4). A fine calibration is performed only when Register 5 is written to and Register 5, Bit DB4 is set. Lower Tone Frequency (kHz) = • XTAL IF_CAL_LOWER_TONE_DIVIDE × 2 IF Tone Calibration Time = IF Tone Calibration Time × 10 XTAL IF_CAL_UPPER_TONE_DIVIDE × 2 • It is recommended that the lower tone and the upper tone be set as shown in Table 24. Table 24. IF Filter Fine Calibration Tone Frequencies Lower Tone Frequency (kHz) 78.1 79.4 78.1 IF_CAL_DWELL_TIME SEQ CLK The total time for a fine IF filter calibration is Upper Tone Frequency (kHz) = IF Filter Bandwidth (kHz) 9 13.5 18.5 The IF tone calibration time is the amount of time that is spent at an IF calibration tone. It is dependent on the sequencer clock. It is recommended that the IF tone calibration time be at least 800 μs. Upper Tone Frequency (kHz) 116.3 116.3 119 Rev. 0 | Page 51 of 60 Bits[DB30:DB28] control the internal source for the image rejection (IR) calibration. The IR_CAL_SOURCE_DRIVE_ LEVEL bits (Bits[DB29:DB28]) set the drive strength of the source, whereas the IR_CAL_SOURCE ÷2 bit (Bit DB30) allows the frequency of the internal signal source to be divided by 2. ADF7021-V REGISTER 7—READBACK SETUP REGISTER READBACK_ SELECT CONTROL BITS ADC_ MODE DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 RB3 RB2 RB1 AD2 AD1 C4 (0) C3 (1) C2 (1) C1 (1) RB3 READBACK_SELECT AD2 AD1 ADC_MODE 0 1 0 0 1 1 DISABLED ENABLED RB2 RB1 READBACK MODE 0 1 0 1 MEASURE RSSI BATTERY VOLTAGE TEMP SENSOR TO EXTERNAL PIN AFC WORD ADC OUTPUT FILTER CAL SILICON REV 08635-068 0 0 1 1 0 1 0 1 Figure 69. Register 7—Readback Setup Register Map • • Readback of the measured RSSI value is valid only in Rx mode. Readback of the battery voltage, temperature sensor, or voltage at the external ADCIN pin is not valid in Rx mode. To read back the battery voltage, the temperature sensor, or the voltage at the external ADCIN pin in Tx mode, the user should first power up the ADC using Register 8, Bit DB8 because it is turned off by default in Tx mode to save power. • Rev. 0 | Page 52 of 60 For AFC readback, use the following equations (see the Readback Format section): FREQ RB (Hz) = (AFC READBACK × DEMOD CLK)/218 VBATTERY = BATTERY VOLTAGE READBACK/21.1 VADCIN = ADCIN VOLTAGE READBACK/42.1 Temperature (°C) = −40 + [(68.4 − TEMP READBACK) × 9.32] ADF7021-V Tx/Rx_SWITCH_ ENABLE LOG_AMP_ ENABLE DEMOD_ ENABLE ADC_ ENABLE FILTER_ ENABLE LNA/MIXER_ ENABLE RESERVED SYNTH_ ENABLE DB15 DB14 DB13 DB12 DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 CR1 RR2 RR1 PD7 SW1 LE1 PD6 PD5 PD4 PD3 RES PD1 COUNTER_ RESET PA_ENABLE_ Rx_MODE REGISTER 8—POWER-DOWN TEST REGISTER Rx_RESET CONTROL BITS DB3 DB1 DB0 C4 (1) C3 (0) C2 (0) C1 (0) CR1 COUNTER_RESET 0 1 DB2 NORMAL RESET PD1 SYNTH_ENABLE 0 1 SYNTH OFF SYNTH ON RR2 CDR_RESET 0 1 NORMAL RESET RR1 DEMOD_RESET NORMAL RESET 0 1 PD3 LNA/MIXER_ENABLE 0 1 LNA/MIXER OFF LNA/MIXER ON PD7 PA_ENABLE_Rx_MODE 0 1 PA OFF PA ON PD4 FILTER_ENABLE SW1 Tx/Rx_SWITCH_ENABLE 0 1 FILTER OFF FILTER ON DEFAULT (ON) OFF LE1 LOG_AMP_ENABLE 0 1 LOG AMP OFF LOG AMP ON PD6 DEMOD_ENABLE 0 1 DEMOD OFF DEMOD ON PD5 ADC_ENABLE 0 1 ADC OFF ADC ON 08635-069 0 1 Figure 70. Register 8—Power-Down Test Register Map It is not necessary to write to this register under normal operating conditions. For a combined LNA/PA matching network, Bit DB11 should always be set to 0, which enables the internal Tx/Rx switch. This is the power-up default condition. Rev. 0 | Page 53 of 60 ADF7021-V 0 1 0 0 1 1 LI2 LI1 LNA_BIAS 0 0 800µA (DEFAULT) FI1 FILTER_CURRENT 0 1 LOW HIGH 0 1 0 1 DB6 DB5 DB4 DB3 DB2 DB1 DB0 GL2 GL1 C4 (1) C3 (0) C2 (0) C1 (1) DB7 GL3 DB8 DB9 GL6 GL5 DB10 GL7 GL4 0 1 1 0 . . . 0 1 1 0 0 0 1 . . . 1 1 1 1 0 1 0 . . . 1 0 1 1 2 3 4 . . . 61 62 63 AGC_HIGH_ GH7 GH6 GH5 GH4 GH3 GH2 GH1 THRESHOLD 0 0 0 0 . . . 1 1 1 FG2 FG1 FILTER_GAIN 0 0 1 1 DB11 DB13 GH3 DEFAULT REDUCED GAIN 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 0 0 0 0 . . . 1 1 1 LM1 LNA_MODE 0 1 GH1 DB14 GH4 AUTO AGC MANUAL AGC FREEZE AGC RESERVED 0 1 0 1 DB12 DB15 GH5 AGC_LOW_ GL7 GL6 GL5 GL4 GL3 GL2 GL1 THRESHOLD GM2 GM1 AGC_MODE DEFAULT HIGH ADDRESS BITS AGC_LOW_THRESHOLD GH2 DB16 GH6 DB20 LG1 DB17 DB21 LG2 GH7 DB22 FG1 DB18 DB23 FG2 DB19 DB24 FI1 AGC_HIGH_THRESHOLD GM1 DB25 LM1 ML1 MIXER_LINEARITY AGC_ MODE GM2 DB26 LI1 FILTER_ CURRENT LNA_MODE DB27 LNA_ GAIN LI2 FILTER_ GAIN DB28 LNA_ BIAS ML1 MIXER_ LINEARITY REGISTER 9—AGC REGISTER 8 24 72 INVALID 0 0 0 0 . . . 0 0 0 0 0 0 0 . . . 0 0 1 0 0 0 0 . . . 1 1 0 0 0 0 1 . . . 1 1 0 0 1 1 0 . . . 1 1 0 1 0 1 0 . . . 0 1 0 1 2 3 4 . . . 78 79 80 LG2 LG1 LNA_GAIN 0 1 0 1 3 10 30 INVALID 08635-070 0 0 1 1 Figure 71. Register 9—AGC Register Map • • It is necessary to program this register only if AGC settings other than the defaults are required. In receive mode, AGC is set to automatic AGC by default on power-up. The default thresholds are AGC_LOW_ THRESHOLD = 30 and AGC_HIGH_THRESHOLD = 70. See the RSSI/AGC section for details. • • Rev. 0 | Page 54 of 60 AGC high and low threshold values must be more than 30 apart to ensure correct operation. An LNA gain of 30 is available only if LNA_MODE (Bit DB25) is set to 0. ADF7021-V MA8 ... MA3 MA2 MA1 MAX_AFC_RANGE 0 0 0 0 . . . 1 1 1 ... ... ... ... ... ... ... ... ... ... 0 0 0 1 . . . 1 1 1 0 1 1 0 . . . 0 1 1 1 0 1 0 . . . 1 0 1 DB7 DB6 DB5 M3 M2 M1 DB0 DB8 M4 C1 (0) DB9 M5 DB1 DB10 M6 DB2 DB11 M7 C2 (1) DB12 M8 C3 (0) DB13 M9 DB3 DB14 M10 C4 (1) DB15 M11 DB4 DB16 M12 AE1 DB17 KI1 ADDRESS BITS KI4 KI3 KI2 KI1 KI AE1 AFC_EN 0 0 . 1 0 0 . 1 0 0 . 1 0 1 . 1 2^0 2^1 ... 2^15 0 1 AFC OFF AFC ON 1 2 3 4 . . . 253 254 255 M12 ... M3 M2 M1 AFC_SCALING_ FACTOR 0 0 0 0 . . . 1 1 1 ... ... ... ... ... ... ... ... ... ... 0 0 0 1 . . . 1 1 1 0 1 1 0 . . . 0 1 1 1 0 1 0 . . . 1 0 1 1 2 3 4 . . . 4093 4094 4095 08635-071 2^0 2^1 ... 2^7 DB18 DB20 KI4 0 1 . 1 0 0 . 1 DB19 DB21 KP1 KP1 KP 0 0 . 1 AFC_SCALING_FACTOR KI2 DB22 KP2 KP3 KP2 KI3 DB23 DB26 MA3 KP3 DB27 MA4 DB24 DB28 MA5 DB25 DB29 MA6 KI MA1 DB30 MA7 KP MA2 DB31 MA8 MAX_AFC_RANGE AFC_EN REGISTER 10—AFC REGISTER Figure 72. Register 10—AFC Register Map • • The AFC_SCALING_FACTOR can be expressed as ⎛ 2 24 × 500 ⎞ ⎟⎟ AFC _ SCALING _ FACTOR = Round ⎜⎜ ⎝ XTAL ⎠ • • The settings for KI and KP affect the AFC settling time and AFC accuracy. The allowable range for each parameter is KI > 6 and KP < 7. The recommended settings for optimal AFC performance are KI = 11 and KP = 4. To trade off between AFC settling time and AFC accuracy, the KI and KP parameters can be adjusted from the recommended settings (staying within the allowable range) such that • AFC Correction Range = MAX_AFC_RANGE × 500 Hz Rev. 0 | Page 55 of 60 When RF_DIVIDE_BY_2 (Register 1, Bit DB18) is enabled, the programmed AFC correction range is halved. The user must account for this halving by doubling the programmed MAX_AFC_RANGE value. Signals that are within the AFC pull-in range but outside the IF filter bandwidth are attenuated by the IF filter. As a result, the signal can be below the sensitivity point of the receiver and, therefore, not detectable by the AFC. ADF7021-V DB0 C1 (1) DB6 MT1 DB1 DB7 MT2 C2 (1) DB8 SB1 DB2 DB9 SB2 DB3 DB10 SB3 C3 (0) DB11 SB4 C4 (1) DB12 SB5 DB4 DB13 SB6 CONTROL BITS PL1 DB14 SB7 PL2 DB15 SB8 DB5 MATCHING_ TOLERANCE DB16 SB9 SB10 DB17 SB11 DB18 SB12 DB19 SB13 DB20 SB14 DB21 SB15 DB22 SB16 DB23 SB17 DB24 SB18 DB25 SB19 DB26 SB20 DB27 SB21 DB28 SB22 DB29 SB23 DB30 SYNC_BYTE_SEQUENCE SB24 DB31 SYNC_BYTE_ LENGTH REGISTER 11—SYNC WORD DETECT REGISTER PL2 PL1 SYNC_BYTE_ LENGTH 0 0 1 1 0 1 0 1 12 BITS 16 BITS 20 BITS 24 BITS 0 0 1 1 0 1 0 1 ACCEPT 0 ERRORS ACCEPT 1 ERROR ACCEPT 2 ERRORS ACCEPT 3 ERRORS 08635-072 MATCHING_ MT2 MT1 TOLERANCE Figure 73. Register 11—Sync Word Detect Register Map DB2 DB1 DB0 C2 (0) C1 (0) DB7 IL2 C3 (1) DB8 DP1 DB3 DB9 DP2 C4 (1) DB10 DP3 DB4 DB11 DP4 LM1 DB12 DP5 DB5 DB13 DP6 LM2 DB14 DP7 CONTROL BITS DB6 DB15 DP8 DATA_PACKET_LENGTH IL1 SWD_MODE LOCK_ THRESHOLD_ MODE REGISTER 12—SWD/THRESHOLD SETUP REGISTER DPx DATA_PACKET_LENGTH 0 1 ... 255 INVALID 1 BYTE ... 255 BYTES ILx SWD_MODE 0 1 2 3 SWD PIN LOW SWD PIN HIGH AFTER NEXT SYNC WORD SWD PIN HIGH AFTER NEXT SYNC WORD FOR DATA PACKET LENGTH NUMBER OF BYTES SWD PIN HIGH 0 1 2 3 THRESHOLD FREE RUNNING LOCK THRESHOLD AFTER NEXT SYNC WORD LOCK THRESHOLD AFTER NEXT SYNC WORD FOR DATA PACKET LENGTH NUMBER OF BYTES LOCK THRESHOLD 08635-073 LMx LOCK_THRESHOLD_MODE Figure 74. Register 12—SWD/Threshold Setup Register Map Lock threshold locks the threshold of the envelope detector. This has the effect of locking the slicer in linear demodulation and locking the AFC and AGC loops when using linear or correlator demodulation. Rev. 0 | Page 56 of 60 ADF7021-V REGISTER 13—3FSK/4FSK DEMODULATION REGISTER VT1 0 0 1 1 . . 1 0 1 0 1 . . 1 OFF 1 2 3 . . 127 VM2 VM1 0 0 0 0 . . 1 0 0 0 0 . . 1 0 0 1 1 . . 1 0 1 0 1 . . 1 DB2 DB1 DB0 C2 (0) C1 (1) DB4 ST1 C3 (1) DB5 ST2 DB3 DB6 ST3 C4 (1) DB7 ST4 DB8 DB9 ST5 DB10 CONTROL BITS 3FSK_VITERBI_ VD1 DETECTOR 0 DISABLED 1 ENABLED PHASE_ PC1 CORRECTION 0 DISABLED 1 ENABLED VITERBI_PATH _ MEMORY 4 BITS 6 BITS 8 BITS 32 BITS ST7 ... ST3 ST2 ST1 3FSK/4FSK_SLICER_ THRESHOLD 0 0 0 0 . . 1 ... ... ... ... ... ... ... 0 0 0 0 . . 1 0 0 1 1 . . 1 0 1 0 1 . . 1 OFF 1 2 3 . . 127 3FSK_PREMABLE_ TIME_VALIDATE 0 1 2 3 . . 15 08635-074 PTV4 PTV3 PTV2 PTV1 0 1 0 1 ST6 DB12 PC1 VT2 0 0 0 0 . . 1 ST7 DB13 VM1 VT3 ... ... ... ... ... ... ... DB11 DB14 VM2 ... 0 0 0 0 . . 1 3FSK/4FSK_ SLICER_THRESHOLD VD1 DB15 VT7 3FSK_CDR_ THRESHOLD 0 0 1 1 PHASE_ CORRECTION 3FSK_VITERBI_ DETECTOR DB16 VT1 DB18 VT4 VT2 DB19 VT5 DB17 DB20 VT6 VT3 DB21 3FSK_CDR_THRESHOLD VT7 PTV1 DB22 PTV2 DB23 PTV4 DB25 PTV3 DB24 3FSK_PREAMBLE_ TIME_VALIDATE VITERBI_ PATH_ MEMORY See the Receiver Setup section for information about programming these settings. Figure 75. Register 13—3FSK/4FSK Demodulation Register Map Rev. 0 | Page 57 of 60 ADF7021-V EFx ED_LEAK_FACTOR ERx PULSE_EXTENSION 0 1 2 3 4 5 6 7 LEAKAGE = 2^–8 2^–9 2^–10 2^–11 2^–12 2^–13 2^–14 2^–15 0 1 2 3 ED_PEAK_RESPONSE 0 1 2 3 FULL RESPONSE TO PEAK 0.5 RESPONSE TO PEAK 0.25 RESPONSE TO PEAK 0.125 RESPONSE TO PEAK TEST_ TDAC_EN DB2 DB1 DB0 C2 (1) C1 (0) DB6 TO2 C3 (1) DB7 TO3 DB3 DB8 TO4 C4 (1) DB9 TO5 DB4 DB10 TO6 TE1 DB11 TO7 DB5 DB12 TO8 TO1 DB13 TO9 TO10 DB14 TO11 DB15 TO12 DB16 TO13 DB17 NO PULSE EXTENSION EXTENDED BY 1 EXTENDED BY 2 EXTENDED BY 3 ADDRESS BITS TGx TEST_DAC_GAIN TE1 TEST_TDAC_EN 0 1 ... 15 NO GAIN × 2^1 ... × 2^15 0 1 TEST DAC DISABLED TEST DAC ENABLED 08635-075 PEx TO14 DB18 TO15 DB19 DB21 DB23 TG3 TG1 DB24 TG4 TEST_DAC_OFFSET TO16 DB20 DB25 ER1 DB22 DB26 TG2 PULSE_ EXTENSION DB27 EF1 TEST_DAC_GAIN ER2 DB29 EF3 DB28 DB30 PE1 EF2 DB31 PE2 ED_LEAK_ FACTOR ED_PEAK_ RESPONSE REGISTER 14—TEST DAC REGISTER Figure 76. Register 14—Test DAC Register Map Whereas the correlators and filters are clocked by DEMOD CLK, the test DAC is clocked by CDR CLK. Note that although the test DAC functions in regular user mode, the best performance is achieved when CDR CLK is increased to or above the frequency of DEMOD CLK. The CDR block does not function when this condition exists. The demodulator tuning parameters, PULSE_EXTENSION, ED_LEAK_FACTOR, and ED_PEAK_RESPONSE, can be enabled only by setting Register 15, Bits[DB7:DB4] to 0x9. Using the On-Chip Test DAC The on-chip test DAC can be used to implement analog demodulation or to provide access for measurement of FSK demodulator output SNR or CNR. For detailed information about using the test DAC, see the AN-852 Application Note. The test DAC allows the postdemodulator filter output for both linear and correlator demodulators to be viewed externally. The test DAC also takes the 16-bit filter output and converts it to a high frequency, single-bit output using a second-order, error feedback Σ-Δ converter. The output can be viewed on the SWD pin. This signal, when filtered appropriately, can then be used to do the following: • • Programming Register 14 enables the test DAC. Both the linear and correlator demodulator outputs can be multiplexed into the DAC. Register 14 allows a fixed offset term to be removed from the signal (to remove the IF component in the linear demodulator case). It also has a signal gain term to allow the usage of the maximum dynamic range of the DAC. Monitor the signals at the FSK postdemodulator filter output. This allows the demodulator output SNR to be measured. Eye diagrams of the received bit stream can also be constructed to measure the received signal quality. Provide analog FM demodulation. Rev. 0 | Page 58 of 60 ADF7021-V 0 1 2 3 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 TM1 RT4 RT3 RT2 RT1 C4 (1) C3 (1) C2 (1) C1 (1) ADDRESS BITS TM2 Rx_TEST_ MODES DB10 DB17 CM1 Tx_TEST_ MODES TM3 DB18 CM2 DB11 DB19 CM3 DB12 DB20 PM1 SD1 DB21 PM2 SD2 DB22 PM3 DB13 DB23 PM4 SD3 DB24 AM1 DB14 DB25 AM2 Σ-Δ_TEST_ MODES PCx PFD/CP_TEST_MODES AUTO CAL OVERRIDE GAIN OVERRIDE BW OVERRIDE BW AND GAIN RD1 REG1_PD 0 1 NORMAL POWER-DOWN 0 1 2 3 4 5 6 7 DEFAULT, NO BLEED (+VE) CONSTANT BLEED (–VE) CONSTANT BLEED (–VE) PULSED BLEED (–VE) PULSE BLD, DELAY UP CP PUMP UP CP TRISTATE CP PUMP DN FH1 FORCE_LD_HIGH SDx Σ-Δ_TEST_MODES 0 1 NORMAL FORCE 0 1 2 3 4 5 6 7 DEFAULT, 3RD-ORDER Σ-Δ, NO DITHER 1ST-ORDER Σ-Δ 2ND-ORDER Σ-Δ DITHER TO FIRST STAGE DITHER TO SECOND STAGE DITHERTO THIRD STAGE DITHER × 8 DITHER × 32 AMx ANALOG_TEST_MODES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 BAND GAP VOLTAGE 40µA CURRENT FROM REG4 FILTER I CHANNEL: STAGE 1 FILTER I CHANNEL: STAGE 2 FILTER I CHANNEL: STAGE 1 FILTER Q CHANNEL: STAGE 1 FILTER Q CHANNEL: STAGE 2 FILTER Q CHANNEL: STAGE 1 ADC REFERENCE VOLTAGE BIAS CURRENT FROM RSSI 5µA FILTER COARSE CAL OSCILLATOR OUTPUT ANALOG RSSI ILCHANNE OFFSET LOOP +VE FBACK V (I CH) SUMMED OUTPUT OF RSSI RECTIFIER+ SUMMED OUTPUT OF RSSI RECTIFIER– BIAS CURRENT FROM BB FILTER TMx Tx_TEST_MODES 0 1 2 3 4 5 6 PMx PLL_TEST_MODES 0 1 2 3 4 5 6 7 8 9 10 11 12 NORMAL OPERATION R DIV N DIV RCNTR/2 ON MUXOUT NCNTR/2 ON MUXOUT ACNTR TO MUXOUT PFD PUMP UP TO MUXOUT PFD PUMP DNTO MUXOUT S DATA TO MUXOUT (OR SREAD) ANALOG LOCK DETECT ON MUXOUT END OF COARSE CAL ON MUXOUT END OF FINE CAL ON MUXOUT FORCE NEW PRESCALER CONFIG FOR ALL N TEST MUX SELECTS DATA LOCK DETECT PRECISION RESERVED 13 14 15 DB15 DB26 AM3 COx CAL_OVERRIDE PFD/CP_ TEST_MODES PC1 DB27 AM4 CLK_MUX PC2 DB28 FH1 PLL_TEST_ MODES DB16 DB29 RD1 ANALOG_TEST_ MODES PC3 REG1_PD FORCE_LD_ HIGH DB30 CO1 CAL_ OVERRIDE DB31 CO2 REGISTER 15—TEST MODE REGISTER NORMAL OPERATION Tx CARRIER ONLY Tx +fDEV TONE ONLY Tx –fDEV TONE ONLY Tx "1010" PATTERN Tx PN9 DATA SEQUENCE Tx SWD PATTERN REPEATEDLY RTx Rx_TEST_MODES 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 NORMAL SCLK, SDATA I,Q REVERSE I,Q I,Q TO TxRxCLK, TxRxDATA 3FSK SLICER ON TxRxDATA CORRELATOR SLICER ON TxRxDATA LINEAR SLICER ON TxRxDATA SDATA TO CDR ADDITIONAL FILTERING ON I,Q ENABLE REG 14 DEMOD PARAMETERS POWER DOWN DDT AND ED IN T/4 MODE ENVELOPE DETECTOR WATCHDOG DISABLED RESERVED PROHIBIT CAL ACTIVE FORCE CAL ACTIVE ENABLE DEMOD DURING CAL CMx CLK_MUX ON CLKOUT PIN NORMAL, NO OUTPUT DEMOD CLK CDR CLK SEQ CLK BB OFFSET CLK Σ-Δ CLK ADC CLK TxRxCLK 08635-076 0 1 2 3 4 5 6 7 Figure 77. Register 15—Test Mode Register Map • • Analog RSSI can be viewed on the TEST_A pin by setting ANALOG_TEST_MODES (Bits[DB27:DB24]) to 11. Tx_TEST_MODES can be used to enable modulation test. • Rev. 0 | Page 59 of 60 The CDR block can be bypassed by setting Rx_TEST_ MODES to 4, 5, or 6, depending on the demodulator used. ADF7021-V OUTLINE DIMENSIONS 7.00 BSC SQ 0.60 MAX 37 36 PIN 1 INDICATOR 25 24 13 12 0.25 MIN 5.50 REF 0.05 MAX 0.02 NOM 0.50 BSC 4.25 4.10 SQ 3.95 (BOTTOM VIEW) 0.80 MAX 0.65 TYP SEATING PLANE PIN 1 INDICATOR 1 EXPOSED PAD 6.75 BSC SQ 0.50 0.40 0.30 12° MAX 48 0.20 REF COPLANARITY 0.08 FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. COMPLIANT TO JEDEC STANDARDS MO-220-VKKD-2 042809-A TOP VIEW 1.00 0.85 0.80 0.30 0.23 0.18 0.60 MAX Figure 78. 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 7 mm × 7 mm Body, Very Thin Quad (CP-48-3) Dimensions shown in millimeters ORDERING GUIDE Model 1 ADF7021-VBCPZ ADF7021-VBCPZ-RL EVAL-ADF70XXMBZ2 EVAL-ADF7021-VDB1Z EVAL-ADF7021-VDB2Z 1 Temperature Range −40°C to +85°C −40°C to +85°C Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Evaluation Platform Mother Board 450 MHz to 470 MHz Daughter Board 868 MHz to 870 MHz Daughter Board Z = RoHS Compliant Part. ©2010 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D08635-0-4/10(0) Rev. 0 | Page 60 of 60 Package Option CP-48-3 CP-48-3