ON MC74HCT273A Octal d flip-flop with common clock and reset with lsttl-compatible input Datasheet

MC74HCT273A
Octal D Flip-Flop with
Common Clock and Reset
with LSTTL-Compatible
Inputs
http://onsemi.com
High−Performance Silicon−Gate CMOS
The MC74HCT273A may be used as a level converter for
interfacing TTL or NMOS outputs to High−Speed CMOS inputs.
The HCT273A is identical in pinout to the LS273.
This device consists of eight D flip−flops with common Clock and
Reset inputs. Each flip−flop is loaded with a low−to−high transition of
the Clock input. Reset is asynchronous and active low.
PDIP−20
N SUFFIX
CASE 738
1
SOIC−20W
DW SUFFIX
CASE 751D
Features
•
•
•
•
•
•
•
•
1
Output Drive Capability: 10 LSTTL Loads
TTL/NMOS Compatible Input Levels
Outputs Directly Interface to CMOS, NMOS and TTL
Operating Voltage Range: 4.5 V to 5.5 V
Low Input Current: 1.0 μA
In Compliance with the Requirements Defined by JEDEC Standard
No. 7 A
Chip Complexity: 284 FETs or 71 Equivalent Gates
These Devices are Pb−Free and are RoHS Compliant
D0
D1
D2
DATA
INPUTS
D3
D4
D5
D6
D7
CLOCK
RESET
3
2
4
5
7
6
8
9
13
12
14
15
17
16
18
19
11
1
PIN ASSIGNMENT
RESET
1
20
VCC
Q0
2
19
Q7
D0
3
18
D7
D1
4
17
D6
Q1
5
16
Q6
Q2
6
15
Q5
Q1
D2
7
14
D5
Q2
D3
8
13
D4
Q3
9
12
Q4
10
11
CLOCK
Q0
Q3
Q4
NONINVERTING
OUTPUTS
GND
Q5
FUNCTION TABLE
Q6
Inputs
Q7
PIN 20 = VCC
PIN 10 = GND
1
TSSOP−20
DT SUFFIX
CASE 948E
Figure 1. Logic Diagram
Output
Reset
Clock
D
Q
L
H
H
H
H
X
X
H
L
X
X
L
H
L
No Change
No Change
L
X = Don’t Care
Z = High Impedance
ORDERING INFORMATION
See detailed ordering, shipping information, and marking
information in the package dimensions section on page 5 of
this data sheet.
© Semiconductor Components Industries, LLC, 2011
May, 2011 − Rev. 11
1
Publication Order Number:
MC74HCT273A/D
MC74HCT273A
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MAXIMUM RATINGS
Symbol
Parameter
Value
Unit
– 0.5 to + 7.0
V
VCC
DC Supply Voltage (Referenced to GND)
Vin
DC Input Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Vout
DC Output Voltage (Referenced to GND)
– 0.5 to VCC + 0.5
V
Iin
DC Input Current, per Pin
± 20
mA
Iout
DC Output Current, per Pin
± 25
mA
ICC
DC Supply Current, VCC and GND Pins
± 50
mA
PD
Power Dissipation in Still Air
750
500
mW
Tstg
Storage Temperature
– 65 to + 150
_C
TL
Lead Temperature, 1 mm from Case for 10 Seconds
(SOIC or PDIP)
PDIP†
SOIC Package†
This device contains protection
circuitry to guard against damage
due to high static voltages or electric
fields. However, precautions must
be taken to avoid applications of any
voltage higher than maximum rated
voltages to this high−impedance circuit. For proper operation, Vin and
Vout should be constrained to the
range GND v (Vin or Vout) v VCC.
Unused inputs must always be
tied to an appropriate logic voltage
level (e.g., either GND or VCC).
Unused outputs must be left open.
_C
260
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above
the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions
may affect device reliability.
†Derating — Plastic DIP: – 10 mW/_C from 65_ to 125_C
SOIC Package: – 7 mW/_C from 65_ to 125_C
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RECOMMENDED OPERATING CONDITIONS
Symbol
VCC
Vin, Vout
Parameter
Min
Max
Unit
4.5
5.5
V
0
VCC
V
– 55
+ 125
_C
0
500
ns
DC Supply Voltage (Referenced to GND)
DC Input Voltage, Output Voltage (Referenced to GND)
TA
Operating Temperature, All Package Types
tr, tf
Input Rise and Fall Time (Figure 1)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Guaranteed Limit
Symbol
Parameter
Test Conditions
VCC
V
– 55 to
25_C
v 85_C
v 125_C
Unit
VIH
Minimum High−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
4.5
5.5
2.0
2.0
2.0
2.0
2.0
2.0
V
VIL
Maximum Low−Level Input
Voltage
Vout = 0.1 V or VCC – 0.1 V
|Iout| v 20 μA
4.5
5.5
0.8
0.8
0.8
0.8
0.8
0.8
V
VOH
Minimum High−Level Output
Voltage
Vin = VIH or VIL
|Iout| v 20 μA
4.5
5.5
4.4
5.4
4.4
5.4
4.4
5.4
V
Vin = VIH or VIL
|Iout| v 4.0 mA
4.5
3.98
3.84
3.7
Vin = VIH or VIL
|Iout| v 20 μA
4.5
5.5
0.1
0.1
0.1
0.1
0.1
0.1
Vin = VIH or VIL
|Iout| v 4.0 mA
4.5
0.26
0.33
0.4
VOL
Maximum Low−Level Output
Voltage
V
Iin
Maximum Input Leakage Current
Vin = VCC or GND
5.5
± 0.1
± 1.0
± 1.0
μA
ICC
Maximum Quiescent Supply
Current (per Package)
Vin = VCC or GND
Iout = 0 μA
5.5
4.0
40
160
μA
ΔICC
Additional Quiescent Supply
Current
Vin = 2.4 V, Any One Input
Vin = VCC or GND, Other Inputs
lout = 0 μA
http://onsemi.com
2
5.5
≥ −55_C
25_C to 125_C
2.9
2.4
mA
MC74HCT273A
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AC ELECTRICAL CHARACTERISTICS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
Symbol
Parameter
Fig.
– 55 to
25_C
v 85_C
v 125_C
Unit
fmax
Maximum Clock Frequency (50% Duty Cycle)
2, 5
30
24
20
MHz
tPLH,
tPHL
Maximum Propagation Delay, Clock to Q
2, 5
25
28
35
ns
tPHL
Maximum Propagation Delay, Reset to Q
25
28
35
ns
tTLH,
tTHL
Maximum Output Transition Time, Any Output
18
20
22
ns
2, 5
Typical @ 25°C, VCC = 5.0 V
CPD
30
Power Dissipation Capacitance (Per Gate)*
* Used to determine the no−load dynamic power consumption: P D = CPD VCC
2f
pF
+ ICC VCC .
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TIMING REQUIREMENTS (VCC = 5.0 V ± 10%, CL = 50 pF, Input tr = tf = 6.0 ns)
Guaranteed Limit
– 55 to 25_C
Symbol
Parameter
Fig.
Min
Max
v 85_C
Min
Max
v 125_C
Min
Max
Unit
tsu
Minimum Setup Time, Data to Clock
10
12
15
ns
th
Minimum Hold Time, Clock to Data
3.0
3.0
3.0
ns
trec
Minimum Recovery Time, Set or Reset Inactive to Clock
5.0
5.0
5.0
ns
tw
Minimum Pulse Width, Clock
12
15
18
ns
tw
Minimum Pulse Width, Set or Reset
12
15
18
ns
tr, tf
Maximum Input Rise and Fall Times
2
2
500
500
500
ns
SWITCHING WAVEFORMS
tf
tr
CLOCK
tw
2.7 V
1.3 V
0.3 V
tw
RESET
1.3 V
GND
GND
tPHL
1/fmax
tPLH
Q
3.0 V
3.0 V
tPHL
90%
1.3 V
10%
Q
1.3 V
trec
3.0 V
CLOCK
tTLH
1.3 V
tTHL
GND
Figure 2.
Figure 3.
http://onsemi.com
3
MC74HCT273A
SWITCHING WAVEFORMS
TEST POINT
OUTPUT
VALID
DEVICE
UNDER
TEST
3.0 V
DATA
1.3 V
GND
tsu
CL*
th
3.0 V
CLOCK
1.3 V
*Includes all probe and jig capacitance
GND
Figure 4.
Figure 5. Test Circuit
C
D0
3
DR
C
D1
4
DR
C
D2
7
DR
C
DATA
INPUTS
D3
8
DR
C
D4
13
DR
C
D5
14
DR
C
D6
D7
CLOCK
RESET
17
DR
C
18
DR
Q
Q
Q
Q
2
5
6
9
Q0
Q1
Q2
Q3
NONINVERTING
OUTPUTS
Q
Q
Q
Q
12
15
16
19
Q4
Q5
Q6
Q7
11
1
Figure 6. Expanded Logic Diagram
http://onsemi.com
4
MC74HCT273A
ORDERING INFORMATION
Package
Shipping†
MC74HCT273ANG
PDIP−20
(Pb−Free)
18 Units / Rail
MC74HCT273ADWG
SOIC−20
(Pb−Free)
38 Units / Rail
MC74HCT273ADWR2G
SOIC−20
(Pb−Free)
1000 / Tape & Reel
MC74HCT273ADTR2G
TSSOP−20*
2500 / Tape & Reel
Device
†For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging
Specifications Brochure, BRD8011/D.
*These packages are inherently Pb−Free.
MARKING DIAGRAMS
PDIP−20
SOIC−20W
20
TSSOP−20
20
20
HCT
273A
ALYWG
G
HCT273A
AWLYYWWG
MC74HCT273AN
AWLYYWWG
1
1
1
A
= Assembly Location
WL, L
= Wafer Lot
YY, Y
= Year
WW, W = Work Week
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
http://onsemi.com
5
MC74HCT273A
PACKAGE DIMENSIONS
PDIP−20
N SUFFIX
PLASTIC DIP PACKAGE
CASE 738−03
ISSUE E
−A−
20
11
1
10
NOTES:
1. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
2. CONTROLLING DIMENSION: INCH.
3. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
4. DIMENSION B DOES NOT INCLUDE MOLD
FLASH.
B
L
C
−T−
K
SEATING
PLANE
M
N
E
G
F
J
D
20 PL
20 PL
0.25 (0.010)
0.25 (0.010)
M
T A
M
T B
M
M
DIM
A
B
C
D
E
F
G
J
K
L
M
N
INCHES
MIN
MAX
1.010
1.070
0.240
0.260
0.150
0.180
0.015
0.022
0.050 BSC
0.050
0.070
0.100 BSC
0.008
0.015
0.110
0.140
0.300 BSC
0_
15 _
0.020
0.040
MILLIMETERS
MIN
MAX
25.66
27.17
6.10
6.60
3.81
4.57
0.39
0.55
1.27 BSC
1.27
1.77
2.54 BSC
0.21
0.38
2.80
3.55
7.62 BSC
0_
15_
0.51
1.01
SOIC−20W
DW SUFFIX
CASE 751D−05
ISSUE G
A
20
11
X 45 _
E
h
1
10
20X
B
B
0.25
M
T A
S
B
S
A
L
H
M
10X
0.25
NOTES:
1. DIMENSIONS ARE IN MILLIMETERS.
2. INTERPRET DIMENSIONS AND TOLERANCES
PER ASME Y14.5M, 1994.
3. DIMENSIONS D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE PROTRUSION
SHALL BE 0.13 TOTAL IN EXCESS OF B
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
q
B
M
D
18X
e
A1
SEATING
PLANE
C
T
http://onsemi.com
6
DIM
A
A1
B
C
D
E
e
H
h
L
q
MILLIMETERS
MIN
MAX
2.35
2.65
0.10
0.25
0.35
0.49
0.23
0.32
12.65
12.95
7.40
7.60
1.27 BSC
10.05
10.55
0.25
0.75
0.50
0.90
0_
7_
MC74HCT273A
PACKAGE DIMENSIONS
20X
0.15 (0.006) T U
2X
L
TSSOP−20
DT SUFFIX
CASE 948E−02
ISSUE C
K REF
0.10 (0.004)
S
L/2
20
M
T U
S
V
ÍÍÍÍ
ÍÍÍÍ
ÍÍÍÍ
S
J J1
11
B
−U−
PIN 1
IDENT
SECTION N−N
0.25 (0.010)
N
1
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION:
MILLIMETER.
3. DIMENSION A DOES NOT INCLUDE
MOLD FLASH, PROTRUSIONS OR GATE
BURRS. MOLD FLASH OR GATE BURRS
SHALL NOT EXCEED 0.15 (0.006) PER SIDE.
4. DIMENSION B DOES NOT INCLUDE
INTERLEAD FLASH OR PROTRUSION.
INTERLEAD FLASH OR PROTRUSION
SHALL NOT EXCEED 0.25 (0.010) PER SIDE.
5. DIMENSION K DOES NOT INCLUDE
DAMBAR PROTRUSION. ALLOWABLE
DAMBAR PROTRUSION SHALL BE 0.08
(0.003) TOTAL IN EXCESS OF THE K
DIMENSION AT MAXIMUM MATERIAL
CONDITION.
6. TERMINAL NUMBERS ARE SHOWN FOR
REFERENCE ONLY.
7. DIMENSION A AND B ARE TO BE
DETERMINED AT DATUM PLANE −W−.
K
K1
10
M
0.15 (0.006) T U
S
N
A
−V−
F
DETAIL E
−W−
C
G
D
H
0.100 (0.004)
−T− SEATING
DETAIL E
SOLDERING FOOTPRINT
PLANE
DIM
A
B
C
D
F
G
H
J
J1
K
K1
L
M
MILLIMETERS
MIN
MAX
6.40
6.60
4.30
4.50
--1.20
0.05
0.15
0.50
0.75
0.65 BSC
0.27
0.37
0.09
0.20
0.09
0.16
0.19
0.30
0.19
0.25
6.40 BSC
0_
8_
INCHES
MIN
MAX
0.252
0.260
0.169
0.177
--0.047
0.002
0.006
0.020
0.030
0.026 BSC
0.011
0.015
0.004
0.008
0.004
0.006
0.007
0.012
0.007
0.010
0.252 BSC
0_
8_
7.06
1
0.65
PITCH
16X
0.36
16X
1.26
DIMENSIONS: MILLIMETERS
ON Semiconductor and
are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice
to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
“Typical” parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All
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MC74HCT273A/D
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