Renesas HD74HC668 Synchronous up/down decade counter, synchronous up/down 4-bit binary counter Datasheet

HD74HC668, HD74HC669
Synchronous UP/Down Decade Counter
Synchronous Up/Down 4-bit binary Counter
REJ03D0638-0200
(Previous ADE-205-520)
Rev.2.00
Mar 30, 2006
Description
This synchronous presettable decade counter features an internal carry look-ahead for cascading in high-speed counting
applications. Synchronous operation is provided by having all flip-flops clocked simultaneously so that the outputs
change coincident with each other when so instructed by the count-enable inputs and internal gating. This mode of
operation helps eliminate the output counting spikes that are normally associated with asynchronous (ripple-clock)
counters.
A buffered clock input triggers the four master-slave flip-flops on the rising (positive going) edge of the clock
waveform. This counter is fully programmable; that is, the outputs may each be preset to either level. The load input
circuitry allows loading with the carry-enable output of cascaded counters. As loading is synchronous, setting up a low
level at the load input disables the counter and causes the outputs to agree with the data inputs after the next clock pulse.
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without additional
gating. Instrumental in accomplishing this function are two count enable inputs and a carry output. Both count enable
inputs (P and T) must be low to count. The direction of the count is determined by the level of the up/down input.
when the input is high, the counter counts up; when low, it counts down. Input T is fed forward to enable the carry
output. The carry output thus enabled will produce a low-level output pulse with a duration approximately equal to the
high portion of the QA output when counting up and approximately equal to the low portion of the QA output when
counting down. This low level overflow carry pulse can be used to enable successive cascaded stages. Transitions at
the enable P or T inputs are allowed regardless of the level of the clock input. All inputs are diode-clamped to minimize
transission-line effects, thereby simplifying system design. This counter features a fully independent clock circuit.
Changes at control inputs (enable P, Enable T, load, up/down) that will modify the operating mode have no effect until
clocking occurs. The function of the counter (whether enabled, disabled, loading, or counting) will be dictated solely
by the conditions meeting the stable setup and hold times.
Features
• High Speed Operation
• High Output Current: Fanout of 10 LSTTL Loads
• Wide Operating Voltage: VCC = 2 to 6 V
• Low Input Current: 1 µA max
• Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25°C)
• Ordering Information
Part Name
Package Type
HD74HC669P
DILP-16 pin
HD74HC669FPEL
SOP-16 pin (JEITA)
Package Code
(Previous Code)
PRDP0016AE-B
(DP-16FV)
PRSP0016DH-B
(FP-16DAV)
Package
Abbreviation
P
—
FP
EL (2,000 pcs/reel)
HD74HC668RPEL
PRSP0016DG-A
RP
SOP-16 pin (JEDEC)
(FP-16DNV)
HD74HC669RPEL
Note: Please consult the sales office for the above package availability.
Rev.2.00 Mar 30, 2006 page 1 of 10
Taping Abbreviation
(Quantity)
EL (1,000 pcs/reel)
HD74HC668, HD74HC669
Pin Arrangement
HD74HC668
U/D
1
16
VCC
CK
2
15
Ripple
carry
output
A
3
14
QA
B
4
13
QB
C
5
12
QC
D
6
11
QD
Enable P
7
10
Enable T
GND
8
9
Load
Data
inputs
Outputs
(Top view)
HD74HC669
U/D
1
16
VCC
CK
2
15
Ripple
carry
output
A
3
14
QA
B
4
13
QB
C
5
12
QC
D
6
11
QD
Enable P
7
10
Enable T
GND
8
9
Load
Data
inputs
Outputs
(Top view)
Rev.2.00 Mar 30, 2006 page 2 of 10
HD74HC668, HD74HC669
Logic Diagram
HD74HC668
T
U/D
IN
L
Q
CK
QA
Q
DA
Load
Enable P
T
Enable T
IN
L
Q
CK
QB
Q
DB
T
IN
DC
L
Q
CK
QC
Q
VCC
T
IN
L
Q
CK
QD
Q
DD
RCO
CK
HD74HC669
U/D
T
Q
IN
Q
T
Q
IN
Q
QA
DA
Load
Enable P
Enable T
QB
DB
T
Q
IN
Q
T
Q
IN
Q
QC
DC
QD
DD
RCO
VCC
CK
Rev.2.00 Mar 30, 2006 page 3 of 10
HD74HC668, HD74HC669
Timing Chart
HD74HC668
Load
A
B
Data
inputs
C
D
Clock
U/D
Enable P and T
QA
QB
QC
QD
Ripple
carry
output
7
8
9
0
Count up
Load
Rev.2.00 Mar 30, 2006 page 4 of 10
1
2
2
Inhibit
2
1
0
9
Count down
8
7
HD74HC668, HD74HC669
HD74HC669
Load
A
B
Data
inputs
C
D
Clock
U/D
P and T
QA
QB
QC
QD
Ripple
carry
output
13
14
15
0
1
Count up
2
2
2
1
0
Inhibit
15
14
13
Count down
Load
Absolute Maximum Ratings
Item
Supply voltage range
Symbol
VCC
Ratings
–0.5 to 7.0
Unit
V
Input / Output voltage
Input / Output diode current
VIN, VOUT
IIK, IOK
–0.5 to VCC +0.5
±20
V
mA
Output current
VCC, GND current
IO
ICC or IGND
±25
±50
mA
mA
PT
Tstg
500
–65 to +150
mW
°C
Power dissipation
Storage temperature
Note: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of
which may be realized at the same time.
Rev.2.00 Mar 30, 2006 page 5 of 10
HD74HC668, HD74HC669
Recommended Operating Conditions
Item
Symbol
Ratings
Unit
Supply voltage
Input / Output voltage
VCC
VIN, VOUT
2 to 6
0 to VCC
V
V
Operating temperature
Ta
–40 to 85
0 to 1000
°C
tr , tf
0 to 500
0 to 400
ns
Input rise / fall time
Note:
*1
Conditions
VCC = 2.0 V
VCC = 4.5 V
VCC = 6.0 V
1. This item guarantees maximum limit when one input switches.
Waveform: Refer to test circuit of switching characteristics.
Electrical Characteristics
Ta = 25°C
Item
Input voltage
Symbol VCC (V)
VIH
VIL
Output voltage
VOH
VOL
Ta = –40 to+85°C
2.0
Min
1.5
Typ
—
Max
—
Min
1.5
Max
—
4.5
6.0
3.15
4.2
—
—
—
—
3.15
4.2
—
—
2.0
4.5
—
—
—
—
0.5
1.35
—
—
0.5
1.35
6.0
2.0
—
1.9
—
2.0
1.8
—
—
1.9
1.8
—
4.5
6.0
4.4
5.9
4.5
6.0
—
—
4.4
5.9
—
—
4.5
6.0
4.18
5.68
—
—
—
—
4.13
5.63
—
—
2.0
4.5
—
—
0.0
0.0
0.1
0.1
—
—
0.1
0.1
6.0
4.5
—
—
0.0
—
0.1
0.26
—
—
0.1
0.33
—
—
—
—
0.26
±0.1
—
—
0.33
±1.0
—
—
4.0
—
40
Input current
Iin
6.0
6.0
Quiescent supply
current
ICC
6.0
Rev.2.00 Mar 30, 2006 page 6 of 10
Unit
Test Conditions
V
V
V
Vin = VIH or VIL IOH = –20 µA
IOH = –4 mA
IOH = –5.2 mA
V
Vin = VIH or VIL IOL = 20 µA
IOL = 4 mA
IOL = 5.2 mA
µA Vin = VCC or GND
µA
Vin = VCC or GND, Iout = 0 µA
HD74HC668, HD74HC669
Switching Characteristics (CL = 50 pF, Input tr = tf = 6 ns)
Ta = 25°C
Item
Symbol VCC (V)
Maximum clock
Frequency
fmax
Propagation delay
time
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
tPLH
tPHL
Pulse width
tw
Setup time
tsu
tsu
tsu
tsu
Hold time
th
Ta = –40 to +85°C
2.0
Min
—
Typ
—
Max
5
Min
—
Max
4
4.5
6.0
—
—
—
—
27
32
—
—
21
25
2.0
4.5
—
—
—
—
200
40
—
—
250
50
6.0
2.0
—
—
—
—
34
225
—
—
43
280
4.5
6.0
—
—
—
—
45
38
—
—
56
48
2.0
4.5
—
—
—
—
150
30
—
—
190
38
6.0
2.0
—
—
—
—
26
200
—
—
33
250
4.5
6.0
—
—
—
—
40
34
—
—
50
43
2.0
4.5
80
16
—
—
—
—
100
20
—
—
6.0
2.0
14
100
—
—
—
—
17
125
—
—
4.5
6.0
20
17
—
—
—
—
25
21
—
—
2.0
4.5
150
30
—
—
—
—
190
38
—
—
6.0
2.0
26
150
—
—
—
—
33
190
—
—
4.5
6.0
30
26
—
—
—
—
38
33
—
—
2.0
4.5
150
30
—
—
—
—
190
38
—
—
6.0
2.0
26
5
—
—
—
—
33
5
—
—
4.5
6.0
5
5
—
—
—
—
5
5
—
—
Output rise/fall
time
tTLH
tTHL
2.0
4.5
—
—
—
5
75
15
—
—
95
19
Input capacitance
Cin
6.0
—
—
—
—
5
13
10
—
—
16
10
Rev.2.00 Mar 30, 2006 page 7 of 10
Unit
Test Conditions
MHz
ns
Clock to Ripple carry out
ns
Clock to Q
ns
Enable T to Ripple carry out
ns
U/D to Ripple carry out
ns
ns
Data to Clock
ns
Enable P, T to Clock
ns
Loadk to Clock
ns
U/D to Clock
ns
ns
pF
HD74HC668, HD74HC669
Test Circuit
VCC
VCC
Output
U/D
Input
Input
Pulse Generator
Zout = 50 Ω
Output
Clock
See Function Table
Pulse Generator
Zout = 50 Ω
QA
A
Output
B
C
CL = 50 pF
QC
Output
D
Enable P
CL = 50 pF
QB
CL = 50 pF
QD
Load
Ripple
Enable T Carry
Output
CL = 50 pF
CL = 50 pF
Note : 1. CL includes probe and jig capacitance.
Rev.2.00 Mar 30, 2006 page 8 of 10
HD74HC668, HD74HC669
Package Dimensions
JEITA Package Code
P-DIP16-6.3x19.2-2.54
RENESAS Code
PRDP0016AE-B
Previous Code
DP-16FV
MASS[Typ.]
1.05g
D
9
E
16
1
8
b3
0.89
A1
A
Z
L
Reference
Symbol
θ
bp
e
e1
D
E
A
A1
bp
b3
c
θ
e
Z
L
c
e1
( Ni/Pd/Au plating )
JEITA Package Code
P-SOP16-5.5x10.06-1.27
RENESAS Code
PRSP0016DH-B
*1
Previous Code
FP-16DAV
Dimension in Millimeters
Min
Nom Max
7.62
19.2 20.32
6.3 7.4
5.06
0.51
0.40 0.48 0.56
1.30
0.19 0.25 0.31
0°
15°
2.29 2.54 2.79
1.12
2.54
MASS[Typ.]
0.24g
D
F
16
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
9
c
HE
*2
E
bp
Index mark
Terminal cross section
( Ni/Pd/Au plating )
1
Z
8
e
*3
bp
x
Reference
Symbol
M
A
L1
A1
θ
y
L
Detail F
Rev.2.00 Mar 30, 2006 page 9 of 10
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min Nom Max
10.06 10.5
5.50
0.00 0.10 0.20
2.20
0.34 0.40 0.46
0.15 0.20 0.25
0°
8°
7.50 7.80 8.00
1.27
0.12
0.15
0.80
0.50 0.70 0.90
1.15
HD74HC668, HD74HC669
JEITA Package Code
P-SOP16-3.95x9.9-1.27
RENESAS Code
PRSP0016DG-A
*1
Previous Code
FP-16DNV
MASS[Typ.]
0.15g
D
F
16
NOTE)
1. DIMENSIONS"*1 (Nom)"AND"*2"
DO NOT INCLUDE MOLD FLASH.
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
9
c
*2
Index mark
HE
E
bp
Terminal cross section
( Ni/Pd/Au plating )
1
Z
Reference
Symbol
8
e
*3
bp
x
M
A
L1
A1
θ
L
y
Detail F
Rev.2.00 Mar 30, 2006 page 10 of 10
D
E
A2
A1
A
bp
b1
c
c1
θ
HE
e
x
y
Z
L
L1
Dimension in Millimeters
Min Nom Max
9.90 10.30
3.95
0.10 0.14 0.25
1.75
0.34 0.40 0.46
0.15 0.20 0.25
0°
8°
5.80 6.10 6.20
1.27
0.25
0.15
0.635
0.40 0.60 1.27
1.08
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