AD EVAL-ADN2805EBZ 1.25 gbps clock and data recovery ic Datasheet

1.25 Gbps Clock and Data Recovery IC
ADN2805
FEATURES
GENERAL DESCRIPTION
Locks to 1.25 Gbps NRZ serial data input
Patented clock recovery architecture
No reference clock required
Loss-of-lock indicator
I2C interface to access optional features
Single-supply operation: 3.3 V
Low power: 390 mW typical
5 mm × 5 mm 32-lead LFCSP, Pb free
The ADN2805 provides the receiver functions of quantization
and clock and data recovery for 1.25 Gbps. The ADN2805
automatically locks to all data rates without the need for an
external reference clock or programming. All SONET jitter
requirements are met, including jitter transfer, jitter generation,
and jitter tolerance.
All specifications are specified for −40°C to +85°C ambient
temperature, unless otherwise noted. The ADN2805 is available
in a compact 5 mm × 5 mm 32-lead LFCSP.
APPLICATIONS
GbE line card
FUNCTIONAL BLOCK DIAGRAM
REFCLKP/REFCLKN
(OPTIONAL)
LOL
CF1
CF2
FREQUENCY
DETECT
LOOP
FILTER
PHASE
DETECT
LOOP
FILTER
VCC
VEE
PIN
NIN
BUFFER
PHASE
SHIFTER
VCO
VREF
DATA
RE-TIMING
DATAOUTP/
DATAOUTN
CLKOUTP/
CLKOUTN
ADN2805
07121-001
2
2
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2008 Analog Devices, Inc. All rights reserved.
ADN2805
TABLE OF CONTENTS
Features .............................................................................................. 1
Theory of Operation ...................................................................... 10
Applications ....................................................................................... 1
Functional Description .................................................................. 12
General Description ......................................................................... 1
Frequency Acquisition ............................................................... 12
Functional Block Diagram .............................................................. 1
Input Buffer ................................................................................. 12
Revision History ............................................................................... 2
Lock Detector Operation .......................................................... 12
Specifications..................................................................................... 3
SQUELCH Mode........................................................................ 13
Jitter Specifications ....................................................................... 3
System Reset ................................................................................ 13
Output and Timing Specifications ............................................. 4
I2C Interface ................................................................................ 13
Absolute Maximum Ratings............................................................ 6
Applications Information .............................................................. 14
Thermal Characteristics .............................................................. 6
PCB Design Guidelines ............................................................. 14
ESD Caution .................................................................................. 6
Outline Dimensions ....................................................................... 16
Pin Configuration and Function Descriptions ............................. 7
Ordering Guide .......................................................................... 16
2
I C Interface Timing and Internal Register Description ............. 8
REVISION HISTORY
1/08—Revision 0: Initial Version
Rev. 0 | Page 2 of 16
ADN2805
SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 1.
Parameter
QUANTIZER—DC CHARACTERISTICS
Input Voltage Range
Peak-to-Peak Differential Input
Input Common-Mode Level
QUANTIZER—AC CHARACTERISTICS
Data Rate
S11
Input Resistance
Input Capacitance
LOSS-OF-LOCK (LOL) DETECT
VCO Frequency Error for LOL Assert
VCO Frequency Error for LOL Deassert
LOL Response Time
ACQUISITION TIME
Lock-to-Data Mode
Optional Lock to REFCLK Mode
DATA RATE READBACK ACCURACY
Fine Readback
POWER SUPPLY
Power Supply Voltage
Power Supply Current
OPERATING TEMPERATURE RANGE
Conditions
Min
@ PIN or NIN, dc-coupled
PIN − NIN
DC-coupled
1.8
0.2
2.3
Typ
Max
Unit
2.5
2.8
2.0
2.8
V
V
V
1250
@ 2.5 GHz
Differential
−15
100
0.65
Mbps
dB
Ω
pF
With respect to nominal
With respect to nominal
1000
250
200
ppm
ppm
μs
GbE
1.5
20.0
ms
ms
In addition to REFCLK accuracy
3.0
3.3
118
Locked to 1.25 Gbps
−40
100
ppm
3.6
131
+85
V
mA
°C
JITTER SPECIFICATIONS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF = 0.47 μF, SLICEP = SLICEN = VEE, input data pattern: PRBS 223 − 1,
unless otherwise noted.
Table 2.
Parameter
PHASE-LOCKED LOOP CHARACTERISTICS
Jitter Peaking
Jitter Generation
Jitter Tolerance
Conditions
GbE, IEEE 802.3, 637 kHz
Rev. 0 | Page 3 of 16
Min
0.749
Typ
Max
Unit
0
0.001
0.02
0.03
0.003
0.04
dB
UI rms
UI p-p
UI p-p
ADN2805
OUTPUT AND TIMING SPECIFICATIONS
Table 3.
Parameter
LVDS OUTPUT CHARACTERISTICS
CLKOUTP/CLKOUTN, DATAOUTP/DATAOUTN
Differential Output Swing
Output Offset Voltage
Output Impedance
LVDS Outputs Timing
Rise Time
Fall Time
Setup Time
Hold Time
2
I C® INTERFACE DC CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input Current
Output Low Voltage
I2C INTERFACE TIMING
SCK Clock Frequency
SCK Pulse Width High
SCK Pulse Width Low
Start Condition Hold Time
Start Condition Setup Time
Data Setup Time
Data Hold Time
SCK/SDA Rise/Fall Time
Stop Condition Setup Time
Bus Free Time Between a Stop and a Start
REFCLK CHARACTERISTICS
Input Voltage Range
Input Low Voltage
Input High Voltage
Minimum Differential Input Drive
Reference Frequency
Required Accuracy
LVTTL DC INPUT CHARACTERISTICS
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
LVTTL DC OUTPUT CHARACTERISTICS
Output High Voltage
Output Low Voltage
1
Conditions
Min
Typ
Max
Unit
VOD (see Figure 3)
VOS (see Figure 3)
Differential
240
1125
300
1200
100
400
1275
mV
mV
Ω
115
115
400
400
220
220
440
440
ps
ps
ps
ps
0.3 VCC
+10.0
0.4
V
V
μA
V
20% to 80%
80% to 20%
TS (see Figure 2), GbE
TH (see Figure 2), GbE
LVCMOS
VIH
VIL
VIN = 0.1 VCC or VIN = 0.9 VCC
VOL, IOL = 3.0 mA
See Figure 10
360
360
0.7 VCC
−10.0
400
tHIGH
tLOW
tHD;STA
tSU;STA
tSU;DAT
tHD;DAT
tR/tF
tSU;STO
tBUF
Optional lock-to-REFCLK mode
@ REFCLKP or REFCLKN
VIL
VIH
600
1300
600
600
100
300
20 + 0.1 Cb 1
600
1300
300
0
VCC
100
10
160
100
VIH
VIL
IIH, VIN = 2.4 V
IIL, VIN = 0.4 V
2.0
VOH, IOH = −2.0 mA
VOL, IOL = 2.0 mA
2.4
0.8
5
−5
Cb = total capacitance of one bus line in pF. If mixed with high speed mode devices, faster fall times are allowed.
Rev. 0 | Page 4 of 16
0.4
kHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
V
mV p-p
MHz
ppm
V
V
μA
μA
V
V
ADN2805
Timing Characteristics
CLKOUTP
TH
07121-002
TS
DATAOUTP/
DATAOUTN
Figure 2. Output Timing
DIFFERENTIAL CLKOUTP/N, DATAOUTP/N
VOH
VOS
07121-003
|VOD|
VOL
Figure 3. Differential Output Specifications
5mA
RLOAD
100Ω
100Ω
VDIFF
SIMPLIFIED LVDS
OUTPUT STAGE
Figure 4. Differential Output Stage
Rev. 0 | Page 5 of 16
07121-004
5mA
ADN2805
ABSOLUTE MAXIMUM RATINGS
THERMAL CHARACTERISTICS
TA = TMIN to TMAX, VCC = VMIN to VMAX, VEE = 0 V, CF =
0.47 μF, SLICEP = SLICEN = VEE, unless otherwise noted.
Thermal Resistance
4-layer board with exposed paddle soldered to VEE.
Table 4.
Parameter
Supply Voltage (VCC)
Minimum Input Voltage (All Inputs)
Maximum Input Voltage (All Inputs)
Maximum Junction Temperature
Storage Temperature Range
Rating
4.2 V
VEE − 0.4 V
VCC + 0.4 V
125°C
−65°C to +150°C
Table 5. Thermal Resistance
Package Type
32-Lead LFCSP
ESD CAUTION
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Rev. 0 | Page 6 of 16
θJA
28
Unit
°C/W
ADN2805
32 TEST2
31 VCC
30 VEE
29 DATAOUTP
28 DATAOUTN
27 SQUELCH
26 CLKOUTP
25 CLKOUTN
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
PIN 1
INDIC ATOR
ADN2805*
TOP VIEW
(Not to Scale)
24 VCC
23 VEE
22 NC
21 SDA
20 SCK
19 SADDR5
18 VCC
17 VEE
* THERE IS AN EXPOSED PAD ON THE BOTTOM OF
THE PACKAGE THAT MUST BE CONNECTED TO GND.
07121-005
NC 9
REFCLKP 10
REFCLKN 11
VCC 12
VEE 13
CF2 14
CF1 15
LOL 16
TEST1 1
VCC 2
VREF 3
NIN 4
PIN 5
NC 6
NC 7
VEE 8
Figure 5. Pin Configuration
Table 6. Pin Function Descriptions
Pin No.
1
2
3
4
5
6, 7, 9, 22
8
10
11
12
13
14
15
16
17
18
19
20
21
23
24
25
26
27
28
29
30
31
32
Exposed Pad
1
Mnemonic
TEST1
VCC
VREF
NIN
PIN
NC
VEE
REFCLKP
REFCLKN
VCC
VEE
CF2
CF1
LOL
VEE
VCC
SADDR5
SCK
SDA
VEE
VCC
CLKOUTN
CLKOUTP
SQUELCH
DATAOUTN
DATAOUTP
VEE
VCC
TEST2
Pad
Type 1
P
AO
AI
AI
P
DI
DI
P
P
AO
AO
DO
P
P
DI
DI
DI
P
P
DO
DO
DI
DO
DO
P
P
P
Description
Connect to VCC.
Power for Limiting Amplifier, LOS.
Internal VREF Voltage. Decouple to GND with a 0.1 μF capacitor.
Differential Data Input. CML.
Differential Data Input. CML.
No Connect.
GND for Limiting Amplifier, LOS.
Differential REFCLK Input. 10 MHz to 160 MHz.
Differential REFCLK Input. 10 MHz to 160 MHz.
VCO Power.
VCO GND.
Frequency Loop Capacitor.
Frequency Loop Capacitor.
Loss-of-Lock Indicator. LVTTL active high.
FLL Detector GND.
FLL Detector Power.
Slave Address Bit 5.
I2C Clock Input.
I2C Data Input.
Output Buffer, I2C GND.
Output Buffer, I2C Power.
Differential Recovered Clock Output. LVDS.
Differential Recovered Clock Output. LVDS.
Disable Clock and Data Outputs. Active high. LVTTL.
Differential Recovered Data Output. LVDS.
Differential Recovered Data Output. LVDS.
Phase Detector, Phase Shifter GND.
Phase Detector, Phase Shifter Power.
Connect to VCC.
Connect to GND.
Type: P = power, AI = analog input, AO = analog output, DI = digital input, DO = digital output.
Rev. 0 | Page 7 of 16
ADN2805
I2C INTERFACE TIMING AND INTERNAL REGISTER DESCRIPTION
R/W
CTRL.
SLAVE ADDRESS [6...0]
A5
SET BY
PIN 19
0
0
0
0
0
X
07121-006
1
MSB = 1
0 = WR
1 = RD
S
SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR A(S) DATA A(S)
DATA A(S)
P
07121-007
Figure 6. Slave Address Configuration
Figure 7. I2C Write Data Transfer
SLAVE ADDR, LSB = 0 (WR) A(S) SUB ADDR
S = START BIT
A(S) = ACKNOWLEDGE BY SLAVE
A(S) S SLAVE ADDR, LSB = 1 (RD) A(S) DATA
A(M)
DATA A(M) P
P = STOP BIT
A(M) = LACK OF ACKNOWLEDGE BY MASTER
A(M) = ACKNOWLEDGE BY MASTER
07121-008
S
Figure 8. I2C Read Data Transfer
SDA
SLAVE ADDRESS
A6
SUB ADDRESS
A5
A7
STOP BIT
DATA
A0
D7
D0
SCK
S
WR
ACK
ACK
SLADDR[4...0]
ACK
SUB ADDR[6...1]
DATA[6...1]
Figure 9. I2C Data Transfer Timing
tF
tSU;DAT
tHD;STA
tBUF
SDA
tR
tR
tSU;STO
tF
tLOW
tHIGH
tHD;STA
S
tSU;STA
tHD;DAT
S
Figure 10. I2C Port Timing Diagram
Rev. 0 | Page 8 of 16
P
S
07121-010
SCK
P
07121-009
START BIT
ADN2805
Table 7. Internal Register Map 1, 2
Reg. Name
FREQ0
FREQ1
FREQ2
RATE
MISC
R/W
R
R
R
R
R
Address
0x0
0x1
0x2
0x3
0x4
D7
D6
D5
MSB
MSB
0
MSB
COARSE_RD[8] MSB
X
X
X
CTRLA
CTRLB
W
W
0x8
0x9
CTRLC
W
0x11
fREF Range
Config Reset
LOL
MISC[4]
0
0
1
2
D4
D3
D2
D1
Coarse Data Rate Readback
Static LOL
Data Rate
LOL
Status
Measure
Complete
Data Rate/DIV_fREF Ratio
0
System 0
Reset
Reset
MISC[2]
0
0
0
0
D0
LSB
LSB
LSB
COARSE_RD[1]
COARSE_RD[0]
(LSB)
X
Measure Data Rate
0
Lock to Reference
0
Squelch Mode
Output Boost
All writeable registers default to 0x00.
X = don’t care.
Table 8. Miscellaneous Register, MISC1
D7
X
1
D6
X
D5
X
Static LOL
D4
0 = waiting for next LOL
1 = static LOL until reset
LOL Status
D3
0 = locked
1 = acquiring
Data Rate Measurement Complete
D2
0 = measuring data rate
1 = measurement complete
D1
X
Coarse Rate Readback LSB
D0
COARSE_RD[0]
X = don’t care.
Table 9. Control Register, CTRLA 1
fREF Range
D7
0
0
1
1
1
D6
0
1
0
1
Data Rate/DIV_fREF Ratio
D5
D4
D3
D2
0
0
0
0
1
0
0
0
1
2
0
0
1
0
4
n
2n
1
0
0
0
256
10 MHz to 20 MHz
20 MHz to 40 MHz
40 MHz to 80 MHz
80 MHz to 160 MHz
Measure Data Rate
D1
Set to 1 to measure data rate
Lock to Reference
D0
0 = lock to input data
1 = lock to reference clock
Where DIV_fREF is the divided down reference referred to the 10 MHz to 20 MHz band.
Table 10. Control Register, CTRLB
Configure LOL
D7
0 = LOL pin normal operation
1 = LOL pin is static LOL
Reset MISC[4]
D6
Write a 1 followed by
0 to reset MISC[4]
System Reset
D5
Write a 1 followed by
0 to reset ADN2805
D4
Set to 0
Reset MISC[2]
D3
Write a 1 followed by
0 to reset MISC[2]
D2
Set to 0
D1
Set to 0
D0
Set to 0
Table 11. Control Register, CTRLC
D7
Set to 0
D6
Set to 0
D5
Set to 0
D4
Set to 0
D3
Set to 0
D2
Set to 0
Squelch Mode
D1
0 = SQUELCH DATAOUT and CLKOUT
1 = SQUELCH DATAOUT or CLKOUT
Rev. 0 | Page 9 of 16
Output Boost
D0
0 = default output swing
1 = boost output swing
ADN2805
THEORY OF OPERATION
Another view of the circuit is that the phase shifter implements
the zero required for frequency compensation of a second-order
phase-locked loop, and this zero is placed in the feedback path
and, thus, does not appear in the closed-loop transfer function.
Jitter peaking in a conventional second-order phase-locked loop
is caused by the presence of this zero in the closed-loop transfer
function. Because this circuit has no zero in the closed-loop
transfer, jitter peaking is minimized.
The delay and phase loops together simultaneously provide
wideband jitter accommodation and narrow-band jitter
filtering. The linearized block diagram in Figure 11 shows that
the jitter transfer function, Z(s)/X(s), is second-order low-pass,
providing excellent filtering. Note that the jitter transfer has no
zero, unlike an ordinary second-order phase-locked loop. This
means that the main PLL has virtually zero jitter peaking (see
Figure 12). This makes this circuit ideal for signal regenerator
applications where jitter peaking in a cascade of regenerators
can contribute to hazardous jitter accumulation.
The error transfer, e(s)/X(s), has the same high-pass form as an
ordinary phase-locked loop. This transfer function is free to be
optimized to give excellent wideband jitter accommodation
because the jitter transfer function, Z(s)/X(s), provides the
narrow-band jitter filtering.
INPUT
DATA
e(s)
X(s)
d/sc
o/s
1/n
Z(s)
RECOVERED
CLOCK
d = PHASE DETECTOR GAIN
o = VCO GAIN
c = LOOP INTEGRATOR
psh = PHASE SHIFTER GAIN
n = DIVIDE RATIO
JITTER TRANSFER FUNCTION
Z(s)
1
=
cn
n psh
X(s)
s2
+s
+1
do
o
TRACKING ERROR TRANSFER FUNCTION
07121-011
e(s)
s2
=
d psh do
X(s)
s2 + s
+
c
cn
Figure 11. ADN2805 PLL/DLL Architecture
JITTER PEAKING
IN ORDINARY PLL
ADN2805
Z(s)
X(s)
o
n psh
d psh
c
FREQUENCY (kHz)
07121-012
The delay and phase loops together track the phase of the input
data signal. For example, when the clock lags input data, the
phase detector drives the VCO to a higher frequency and
increases the delay through the phase shifter; both of these
actions serve to reduce the phase error between the clock and
data. The faster clock picks up phase, while simultaneously, the
delayed data loses phase. Because the loop filter is an integrator,
the static phase error is driven to zero.
psh
JITTER GAIN (dB)
The ADN2805 is a delay- and phase-locked loop circuit for
clock recovery and data retiming from an NRZ encoded data
stream. The phase of the input data signal is tracked by two
separate feedback loops that share a common control voltage. A
high speed delay-locked loop path uses a voltage controlled
phase shifter to track the high frequency components of input
jitter. A separate phase control loop, comprised of the VCO,
tracks the low frequency components of input jitter. The initial
frequency of the VCO is set by yet a third loop, which compares
the VCO frequency with the input data frequency and sets the
coarse tuning voltage. The jitter tracking phase-locked loop
(PLL) controls the VCO by the fine-tuning control.
Figure 12. ADN2805 Jitter Response vs. Conventional PLL
The delay and phase loops contribute to overall jitter accommodation. At low frequencies of input jitter on the data signal,
the integrator in the loop filter provides high gain to track large
jitter amplitudes with small phase error. In this case, the VCO is
frequency modulated and jitter is tracked as in an ordinary
phase-locked loop. The amount of low frequency jitter that can
be tracked is a function of the VCO tuning range. A wider
tuning range gives larger accommodation of low frequency
jitter. The internal loop control voltage remains small for small
phase errors; therefore, the phase shifter remains close to the
center of its range and thus contributes little to the low
frequency jitter accommodation.
At medium jitter frequencies, the gain and tuning range of the
VCO are not large enough to track input jitter. In this case, the
VCO control voltage becomes large and saturates, and the VCO
frequency dwells at either one extreme of its tuning range or at
the other. The size of the VCO tuning range, therefore, has only
a small effect on the jitter accommodation. As such, the delaylocked loop control voltage is larger, and, consequently, the
phase shifter takes on the burden of tracking the input jitter.
The phase shifter range, in UI, can be seen as a broad plateau on
the jitter tolerance curve. The phase shifter has a minimum
range of 2 UI at all data rates.
Rev. 0 | Page 10 of 16
ADN2805
The gain of the loop integrator is small for high jitter
frequencies; therefore, larger phase differences are needed to
make the loop control voltage large enough to tune the range of
the phase shifter. Large phase errors at high jitter frequencies
cannot be tolerated. In this region, the gain of the integrator
determines the jitter accommodation. Because the gain of the
loop integrator declines linearly with frequency, jitter accommodation is lower with higher jitter frequency. At the highest
frequencies, the loop gain is very small, and little tuning of the
phase shifter can be expected. In this case, jitter accommodation is
determined by the eye opening of the input data, the static
phase error, and the residual loop jitter generation. The jitter
accommodation is roughly 0.5 UI in this region. The corner
frequency between the declining slope and the flat region is
the closed loop bandwidth of the delay-locked loop, which is
roughly 1.5 MHz at 1.25 Gbps.
Rev. 0 | Page 11 of 16
ADN2805
FUNCTIONAL DESCRIPTION
FREQUENCY ACQUISITION
When LOL deasserts, the FLL turns off. The PLL/DLL pulls in
the VCO frequency until the VCO frequency equals the data
frequency.
The frequency loop requires a single external capacitor between
CF1 and CF2, Pin 15 and Pin 14. A 0.47 μF ± 20%, X7R ceramic
chip capacitor with <10 nA leakage current is recommended.
Calculate the leakage current of the capacitor by dividing the
maximum voltage across the 0.47 μF capacitor, ~3 V, by the
insulation resistance of the capacitor. The insulation resistance
of the 0.47 μF capacitor should be greater than 300 MΩ.
INPUT BUFFER
The input buffer has differential inputs (PIN/NIN), which are
internally terminated with 50 Ω to an on-chip voltage reference
(VREF = 2.5 V typically). The minimum differential input level
required to achieve a BER of 10−10 is 200 mV p-p.
LOCK DETECTOR OPERATION
The lock detector on the ADN2805 has three modes of
operation: normal mode, REFCLK mode, and static LOL mode.
Normal Mode
In normal mode, the ADN2805 locks onto 1.25 Gbps NRZ data
without the use of a reference clock as an acquisition aid. In this
mode, the lock detector monitors the frequency difference
between the VCO and the input data frequency, and deasserts
the loss-of-lock signal, which appears on Pin 16 (LOL) when
the VCO is within 250 ppm of the data frequency. This enables
the DLL/PLL, which pulls the VCO frequency in the remaining
amount and acquires phase lock. When locked, if the input
frequency error exceeds 1000 ppm (0.1%), the loss-of-lock
signal reasserts and control returns to the frequency loop,
which begins a new frequency acquisition. The LOL pin
remains asserted until the VCO locks onto a valid input data
stream to within 250 ppm frequency error. This hysteresis is
shown in Figure 13.
LOL
1
–250
–1000
0
250
1000
fVCO ERROR
(ppm)
07121-013
The ADN2805 acquires frequency from the data at 1.25 Gbps.
The lock detector circuit compares the frequency of the VCO
and the frequency of the incoming data. When these frequencies differ by more than 1000 ppm, LOL asserts. This initiates a
frequency acquisition cycle. An on-chip frequency-locked loop
(FLL) forces the frequency of the VCO to be approximately
equal to the frequency of the incoming data. LOL is deasserted
once the VCO frequency is within 250 ppm of the data frequency.
Figure 13. Transfer Function of LOL
LOL Detector Operation Using a Reference Clock
In REFCLK mode, a reference clock is used as an acquisition aid
to lock the ADN2805 VCO. Lock-to-reference mode is enabled
by setting CTRLA[0] to 1. The user also needs to write to the
CTRLA[7:6] and CTRLA[5:2] bits to set the reference frequency
range and the divide ratio of the data rate with respect to the
reference frequency. In this mode, the lock detector monitors
the difference in frequency between the divided down VCO
and the divided down reference clock. The loss-of-lock signal,
which appears on Pin 16 (LOL), deasserts when the VCO is
within 250 ppm of the desired frequency. This enables the DLL/
PLL, which pulls the VCO frequency in the remaining amount
with respect to the input data and acquires phase lock. When
locked, if the input frequency error exceeds 1000 ppm (0.1%),
the loss-of-lock signal reasserts and control returns to the frequency loop, which reacquires with respect to the reference
clock. The LOL pin remains asserted until the VCO frequency
is within 250 ppm of the desired frequency. This hysteresis is
shown in Figure 13.
Static LOL Mode
The ADN2805 implements a static LOL feature to indicate
whether a loss-of-lock condition has ever occurred and remains
asserted, even if the ADN2805 regains lock, until the static LOL
bit is manually reset. The I2C register bit, MISC[4], is the static
LOL bit. If there is ever an occurrence of a loss-of-lock condition,
this bit internally asserts to Logic high. The MISC[4] bit remains
high even after the ADN2805 has reacquired lock to a new data
rate. This bit can be reset by writing a 1 followed by 0 to I2C
Register Bit CTRLB[6]. When reset, the MISC[4] bit remains
deasserted until another loss-of-lock condition occurs.
Writing a 1 to I2C Register Bit CTRLB[7] causes the LOL pin,
Pin 16, to become a static LOL indicator. In this mode, the LOL
pin mirrors the contents of the MISC[4] bit and has the functionality described in the previous paragraph.
The CTRLB[7] bit defaults to 0. In this mode, the LOL pin
operates in the normal operating mode, that is, it asserts only
when the ADN2805 is in acquisition mode and deasserts when
the ADN2805 reacquires lock.
Rev. 0 | Page 12 of 16
ADN2805
SQUELCH MODE
Two squelch modes are available with the ADN2805. The
SQUELCH DATAOUT and CLKOUT mode is selected when
CTRLC[1] = 0 (default mode). In this mode, when the SQUELCH
input, Pin 27, is driven to a TTL high state, both the clock and
data outputs are set to the zero state to suppress downstream processing. If the squelch function is not required, tie Pin 27 to VEE.
SQUELCH DATAOUT or CLKOUT mode is selected when
CTRLC[1] is 1. In this mode, when the SQUELCH input is
driven to a high state, the DATAOUTN/DATAOUTP pins
are squelched. When the SQUELCH input is driven to a low
state, the CLKOUT pins are squelched. This feature is especially
useful in repeater applications, where the recovered clock may
not be needed.
SYSTEM RESET
A frequency acquisition can be initiated by writing a 1 followed
by a 0 to the I2C Register Bit CTRLB[5]. This initiates a new
frequency acquisition while keeping the ADN2805 in the
operating mode that it was previously programmed to in
Register CTRL[A], Register CTRL[B], and Register CTRL[C].
I2C INTERFACE
The ADN2805 supports a 2-wire, I2C-compatible, serial bus
driving multiple peripherals. Two inputs, serial data (SDA) and
serial clock (SCK), carry information between any devices
connected to the bus. Each slave device is recognized by a
unique address. The ADN2805 has two possible 7-bit slave
addresses for both read and write operations. The MSB of the
7-bit slave address is factory programmed to 1. Bit 5 of the slave
address is set by Pin 19, SADDR5. Slave Address Bits[4:0] are
defaulted to all 0s. The slave address consists of the 7 MSBs of
an 8-bit word. The LSB of the word either sets a read or write
operation (see Figure 6). Logic 1 corresponds to a read
operation whereas Logic 0 corresponds to a write operation.
To control the device on the bus, the following protocol must be
followed. First, the master initiates a data transfer by establishing
a start condition, defined by a high-to-low transition on SDA
while SCK remains high. This indicates that an address/data
stream follows. All peripherals respond to the start condition
and shift the next eight bits (the 7-bit address and the R/W bit).
The bits are transferred from MSB to LSB. The peripheral that
recognizes the transmitted address responds by pulling the data
line low during the ninth clock pulse. This is known as an acknowledge bit. All other devices withdraw from the bus at this point
and maintain an idle condition. The idle condition is where the
device monitors the SDA and SCK lines waiting for the start
condition and correct transmitted address. The R/W bit determines the direction of the data. Logic 0 on the LSB of the first
byte means that the master writes information to the peripheral.
Logic 1 on the LSB of the first byte means that the master reads
information from the peripheral.
The ADN2805 acts as a standard slave device on the bus. The data
on the SDA pin is eight bits long, supporting the 7-bit addresses,
plus the R/W bit. The ADN2805 has eight subaddresses to enable
the user-accessible internal registers (see Table 7 through Table 11).
It, therefore, interprets the first byte as the device address and
the second byte as the starting subaddress. Auto-increment
mode is supported, allowing data to be read from or written to
the starting subaddress and each subsequent address without
manually addressing the subsequent subaddress. A data transfer is always terminated by a stop condition. The user can also
access any unique subaddress register on a one-by-one basis
without updating all registers.
Stop and start conditions can be detected at any stage of the
data transfer. If these conditions assert out of sequence with
normal read and write operations, they cause an immediate
jump to the idle condition. During a given SCK high period,
the user should issue one start condition, one stop condition,
or a single stop condition followed by a single start condition.
If an invalid subaddress is issued by the user, the ADN2805
does not issue an acknowledge and returns to the idle condition. If the user exceeds the highest subaddress while reading
back in auto-increment mode, the highest subaddress register
contents continue to be output until the master device issues a
no-acknowledge. This indicates the end of a read. In a no-acknowledge condition, the SDATA line is not pulled low on the ninth
pulse. See Figure 7 and Figure 8 for sample read and write data
transfers and Figure 9 for a more detailed timing diagram.
Rev. 0 | Page 13 of 16
ADN2805
APPLICATIONS INFORMATION
PCB DESIGN GUIDELINES
If connections to the supply and ground are made through vias,
the use of multiple vias in parallel helps to reduce series
inductance, especially on Pin 24, which supplies power to the
high speed CLKOUTP/CLKOUTN and DATAOUTP/
DATAOUTN output buffers. Refer to Figure 14 for the
recommended connections.
Proper RF PCB design techniques must be used for optimal
performance.
Power Supply Connections and Ground Planes
Use of one low impedance ground plane is recommended. To
reduce series inductance, solder the VEE pins directly to the
ground plane. If the ground plane is an internal plane and
connections to the ground plane are made through vias, multiple
vias can be used in parallel to reduce the series inductance,
especially on Pin 23, which is the ground return for the output
buffers. Connect the exposed pad to the ground plane using
plugged vias to prevent solder from leaking through the vias
during reflow.
By using adjacent power supply and ground planes, excellent
high frequency decoupling can be realized by using close
spacing between the planes. This capacitance is given by
CPLANE = 0.88ε r A/d (pF )
where:
εr is the dielectric constant of the PCB material.
A is the area of the overlap of power and ground planes (cm2).
d is the separation between planes (mm).
Use of a 22 μF electrolytic capacitor between VCC and VEE is
recommended at the location where the 3.3 V supply enters the
PCB. When using 0.1 μF and 1 nF ceramic chip capacitors,
place them between the IC power supply VCC and VEE, as
close as possible to the ADN2805 VCC pins.
For FR-4, εr = 4.4 mm and 0.25 mm spacing, C ~15 pF/cm2.
50Ω TRANSMISSION LINES
VCC
DATAOUTP
+
22µF
0.1µF
DATAOUTN
1nF
CLKOUTP
TEST2
VCC
VEE
DATAOUTP
DATAOUTN
SQUELCH
CLKOUTP
CLKOUTN
CLKOUTN
0.1µF
50Ω
32
31
30
29
28
27
26
25
REFCLKP
REFCLKN
NC
VCC
VEE
CF2
CF1
LOL
OPTICAL
TRANSCEIVER
MODULE
24
EXPOSED PAD 23
TIED OFF TO 22
VEE PLANE 21
20
WITH VIAS
19
18
17
0.1µF
I2C CONTROLLER
I2C CONTROLLER
VCC
0.1µF
µC
NC
50Ω
1nF
VCC
VEE
NC
SDA
SCK
SADDR5
VCC
VEE
1nF
VCC
0.1µF
1nF
0.47µF ±20%
>300MΩ INSULATION RESISTANCE
Figure 14. Typical Applications Circuit
Rev. 0 | Page 14 of 16
07121-014
1nF
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
0.1µF
TEST1
VCC
VREF
NIN
PIN
NC
NC
VEE
VCC
ADN2805
VCC
Use of 50 Ω transmission lines is required for all high frequency
input and output signals to minimize reflections: PIN, NIN,
CLKOUTP, CLKOUTN, DATAOUTP, and DATAOUTN (also
REFCLKP and REFCLKN, if a high frequency reference clock is
used, such as 155 MHz). It is also necessary for the PIN/NIN
input traces to be matched in length, and the CLKOUTP/
CLKOUTN and DATAOUTP/DATAOUTN output traces to be
matched in length to avoid skew between the differential traces.
ADN2805
50Ω
CIN
PIN
50Ω
CIN
NIN
TIA
50Ω
0.1µF
VREF
50Ω
3kΩ
2.5V
07121-015
Transmission Lines
Figure 15. AC-Coupled Input Configuration
The high speed inputs, PIN and NIN, are internally terminated
with 50 Ω to an internal reference voltage (see Figure 15).
A 0.1 μF is recommended between VREF, Pin 3, and GND to
provide an ac ground for the inputs.
Soldering Guidelines for Lead Frame Chip Scale Package
The lands on the 32-lead LFCSP are rectangular. The printed
circuit board (PCB) pad for these should be 0.1 mm longer than
the package land length and 0.05 mm wider than the package
land width. The land should be centered on the pad. This
ensures that the solder joint size is maximized. The bottom of
the chip scale package has a central exposed pad. The pad on
the PCB should be at least as large as this exposed pad. The user
must connect the exposed pad to VEE using plugged vias so
that solder does not leak through the vias during reflow. This
ensures a solid connection from the exposed pad to VEE.
As with any high speed mixed-signal design, take care to keep
all high speed digital traces away from sensitive analog nodes.
VCC
V1
CIN
V2
ADN2805
PIN
TIA
V1b
CIN V2b
50Ω
NIN
V1
1
2
COUT
+
50Ω
VREF
DATAOUTP
CDR
BUFFER
DATAOUTN
COUT
–
3
4
V1b
V2
VREF
V2b
VTH
VDIFF
NOTES:
1. DURING DATA PATTERNS WITH HIGH TRANSITION DENSITY, DIFFERENTIAL DC VOLTAGE AT V1 AND V2 IS ZERO.
2. WHEN THE OUTPUT OF THE TIA GOES TO CID, V1 AND V1b ARE DRIVEN TO DIFFERENT DC LEVELS. V2 AND V2b DISCHARGE TO THE
VREF LEVEL, WHICH EFFECTIVELY INTRODUCES A DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS.
3. WHEN THE BURST OF DATA STARTS AGAIN, THE DIFFERENTIAL DC OFFSET ACROSS THE AC COUPLING CAPACITORS IS APPLIED TO
THE INPUT LEVELS CAUSING A DC SHIFT IN THE DIFFERENTIAL INPUT. THIS SHIFT IS LARGE ENOUGH SUCH THAT ONE OF THE STATES,
EITHER HIGH OR LOW DEPENDING ON THE LEVELS OF V1AND V1b WHEN THE TIA WENT TO CID, IS CANCELED OUT. THE QUANTIZER
DOES NOT RECOGNIZE THIS AS A VALID STATE.
4. THE DC OFFSET SLOWLY DISCHARGES UNTIL THE DIFFERENTIAL INPUT VOLTAGE EXCEEDS THE SENSITIVITY OF THE ADN2805. THE
QUANTIZER CAN RECOGNIZE BOTH HIGH AND LOW STATES AT THIS POINT.
Figure 16. Example of Baseline Wander
Rev. 0 | Page 15 of 16
07121-016
VDIFF = V2 – V2b
VTH = ADN2805 QUANTIZER THRESHOLD
ADN2805
OUTLINE DIMENSIONS
0.60 MAX
5.00
BSC SQ
0.60 MAX
PIN 1
INDICATOR
TOP
VIEW
0.50
BSC
4.75
BSC SQ
0.50
0.40
0.30
32
1
3.25
3.10 SQ
2.95
EXPOSED
PAD
(BOTTOM VIEW)
17
16
9
8
0.25 MIN
3.50 REF
0.80 MAX
0.65 TYP
12° MAX
1.00
0.85
0.80
PIN 1
INDICATOR
25
24
0.05 MAX
0.02 NOM
SEATING
PLANE
0.30
0.23
0.18
0.20 REF
COPLANARITY
0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 17. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ]
5 mm × 5 mm Body, Very Thin Quad
(CP-32-2)
Dimensions shown in millimeters
ORDERING GUIDE
Model
ADN2805ACPZ 1
ADN2805ACPZ-500RL71
ADN2805ACPZ-RL71
EVAL-ADN2805EBZ1
1
Temperature Range
−40°C to +85°C
−40°C to +85°C
−40°C to +85°C
Package Description
32-Lead LFCSP_VQ
32-Lead LFCSP_VQ, Tape-Reel, 500 pieces
32-Lead LFCSP_VQ, Tape-Reel, 1,500 pieces
Evaluation Board
Package Option
CP-32-2
CP-32-2
CP-32-2
Z = RoHS Compliant Part.
Purchase of licensed I2C components of Analog Devices or one of its sublicensed Associated Companies conveys a license for the purchaser under the Philips I2C Patent
Rights to use these components in an I2C system, provided that the system conforms to the I2C Standard Specification as defined by Philips.
©2008 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D07121-0-1/08(0)
Rev. 0 | Page 16 of 16
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