HSP051-4N10 4-line ESD protection for high speed lines Datasheet − production data Benefits • High ESD protection level • High integration • Suitable for high density boards Complies with following standards • MIL-STD 883G Method 3015-7 Class 3B: – 8 kV µQFN 1.9x1 10L HSP051-4N10 • IEC 61000-4-2 level 4: – 8 kV (contact discharge) – 15 kV (air discharge) Figure 1. Functional schematic (top view) I/O 1 1 Internally 10 not connected I/O 2 2 9 GND 3 8 GND I/O 3 4 7 I/O 4 5 6 Applications The HSP051-4N10 is designed to protect against electrostatic discharge on sub micron technology circuits driving: • HDMI 1.4 and 2.0 • Digital video Interface • Display port Internally not connected • USB 3.0 and 3.1 • Serial ATA Features Description • Flow-through routing to keep signal integrity The HSP051-4N10 is a 4-channel ESD array with a rail to rail architecture designed specifically for the protection of high speed differential lines. • Ultralarge bandwidth: 10 GHz • Ultralow capacitance: – 0.2 pF (I/O to I/O) – 0.35 pF (I/O to GND) The ultralow variation of the capacitance ensures very low influence on signal-skew. The large bandwidth make it compatible with HDMI 2.0 4K/2K (=5.94 Gbps) and USB 3.1 (=10 Gbps) • Very Low dynamic resistance: 0.48 Ω • 100 Ω differential impedance The device is packaged in µQFN 1.9 mm x 1 mm with a 400 µm pitch. • Low leakage current: 100 nA at 25 °C • Extended operating junction temperature range: -40 °C to 150 °C • RoHS compliant July 2014 This is information on a product in full production. DocID025979 Rev1 1/11 www.st.com Characteristics 1 HSP051-4N10 Characteristics Table 1. Absolute maximum ratings Tamb = 25 °C Symbol Value Unit 8 25 kV Operating junction temperature range -40 to +150 °C Tstg Storage temperature range -65 to +150 °C TL Maximum lead temperature for soldering during 10 s 260 °C VPP Tj Parameter IEC 61000-4-2 contact discharge IEC 61000-4-2 air discharge Peak pulse voltage Table 2. Electrical characteristics Tamb = 25 °C Symbol Test conditions Min. Typ. Max. Unit VBR IR = 1 mA IRM VRM = 3.6 V VCL IPP = 1 A, 8/20 µs VCL IEC 61000-4-2, +8 kV contact (IPP = 16 A), measured at 30 ns Rd Dynamic resistance, pulse duration 100 ns CI/O - I/O 4.5 10 0.48 GND to I/O 0.96 F = 2.5 GHz to 9 GHz -3dB nA 10 V Ω 0.2 0.3 pF 0.4 0.55 pF 0.35 0.45 pF 10 Time domain reflectometry: tr = 200 ps (10 - 90%), Z0 = 100 Ω Figure 2. Leakage current versus junction temperature (typical values) IR (nA) 85 GHz 100 Ω 115 Figure 3. S21 attenuation measurement 0 100 100 V I/O to GND F = 200 MHz to 2.5 GHz Zdiff V 13 VI/O = 0 V, F = 200 MHz to 9 GHz CI/O - GND VI/O = 0 V fC 5.8 S21 (db) -0.5 VR = VRM = 3.6V -1 -1.5 10 -2 1 -2.5 Tj (°C) 25 50 75 100 125 150 F (Hz) -3 100k 1M 0V 2/11 DocID025979 Rev1 10M 3.6 V 100M 2.5 V 1G 10G HSP051-4N10 Characteristics Figure 4. Eye diagram - HDMI mask at 3.4 Gbps Figure 5. Eye diagram - HDMI mask at 3.4 Gbps per channel (without HSP051-4N10)(1) per channel(1) (with HSP051-4N10) 1. HDMI specification conditions. This information can be provided for other applications. Please contact your local ST office. Figure 6. Eye diagram - HDMI 2.0 mask at 5.94 Gbps per channel (without HSP051-4N10) Figure 7. Eye diagram - HDMI 2.0 mask at 5.94 Gbps per channel (with HSP051-4N10 Figure 8. Eye diagram - USB 3.0 mask at 5.0 Gbps per channel (without HSP051-4N10) Figure 9. Eye diagram - USB 3.0 mask at 5.0 Gbps per channel (with HSP051-4N10) DocID025979 Rev1 3/11 Characteristics HSP051-4N10 Figure 10. Eye diagram - USB 3.1 mask at 10.0 Gbps per channel (without HSP051-4N10) Figure 11. Eye diagram - USB 3.1 mask at 10.0 Gbps per channel (with HSP051-4N10) Figure 12. ESD response to IEC 61000-4-2 (+8 kV contact discharge) Figure 13. ESD response to IEC 61000-4-2 (-8 kV contact discharge) 50 V / Div 50 V / Div 1 2 3 4 VCL: Peak clamping voltage VCL :clamping voltage at 30 ns VCL :clamping voltage at 60 ns VCL :clamping voltage at 100 ns 4 -2 V 3 -5 V 1 184 V 1 -147 V 3 11 V 2 13 V 4 10 V 2 -13 V 1 2 3 4 VCL: Peak clamping voltage VCL :clamping voltage @ 30 ns VCL :clamping voltage @ 60 ns VCL :clamping voltage @ 100 ns 20 ns / Div 20 ns / Div Figure 14. TLP measurement (pulse duration 100 ns) IPP (A) 20 15 10 5 IO/GND GND/IO 0 0 2 4 6 8 10 12 14 16 18 20 22 VCL (V) 4/11 DocID025979 Rev1 Figure 15. TDR measurement HSP051-4N10 Package information • Epoxy meets UL94, V0 • Lead-free packages In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK® packages, depending on their level of environmental compliance. ECOPACK® specifications, grade definitions and product status are available at: www.st.com. ECOPACK® is an ST trademark. Figure 16. µQFN 1.9x1 10L dimension definitions E D Top view Bottom view e k D2 A b Side view E2 A1 2 Package information L2 DocID025979 Rev1 5/11 Package information HSP051-4N10 Table 3. µQFN 1.9x1 10L dimension values Dimensions Ref. Millimeters Min. Typ. Max. A 0.29 0.32 0.35 A1 0.00 0.02 0.05 b 0.15 0.20 0.25 D 1.85 1.90 1.95 D2 0.15 0.20 0.25 E 0.95 1.00 1.05 E2 0.88 0.93 0.98 e 0.40 k 0.21 L2 0.02 0.05 Figure 17. Footprint recommendations (dimensions in mm) 0,4 0,93 0,21 0,2 6/11 Figure 18. Marking 0,4 0,56 0,2 0.07 DocID025979 Rev1 HC HSP051-4N10 Package information Figure 19. µQFN 1.9x1 10L tape and reel specification DocID025979 Rev1 7/11 Recommendation on PCB assembly 3 HSP051-4N10 Recommendation on PCB assembly Figure 20. Recommended stencil window position 0,14 0,24 0,66 0,53 0,19 0,4 3.1 3.2 8/11 0,4 Solder paste 1. Use halide-free flux, qualification ROL0 according to ANSI/J-STD-004. 2. “No clean” solder paste recommended. 3. Offers a high tack force to resist component displacement during PCB movement. 4. Use solder paste with fine particles: powder particle size 20-45 µm. Placement 1. Manual positioning is not recommended. 2. It is recommended to use the lead recognition capabilities of the placement system, not the outline centering. 3. Standard tolerance of ± 0.05 mm is recommended. 4. 3.5 N placement force is recommended. Too much placement force can lead to squeezed out solder paste and cause solder joints to short. Too low placement force can lead to insufficient contact between package and solder paste that could cause open solder joints or badly centered packages. 5. To improve the package placement accuracy, a bottom side optical control should be performed with a high resolution tool. 6. For assembly, a perfect supporting of the PCB (all the more on flexible PCB) is recommended during solder paste printing, pick and place and reflow soldering by using optimized tools. DocID025979 Rev1 HSP051-4N10 3.3 Recommendation on PCB assembly PCB design 1. To control the solder paste amount, the closed via is recommended instead of open vias. 2. The position of tracks and open vias in the solder area should be well balanced. The symmetrical layout is recommended, in case any tilt phenomena caused by asymmetrical solder paste amount due to the solder flow away. Figure 21. Printed circuit board layout recommendations P 9LDWR *1' 9LDWR *1' )RRWSULQW SDG 3.4 3&%WUDFNV Reflow profile Figure 22. ST ECOPACK® recommended soldering reflow profile for PCB mounting 240-245 °C Temperature (°C) 250 -2 °C/s 2 - 3 °C/s 60 sec (90 max) 200 -3 °C/s 150 -6 °C/s 100 0.9 °C/s 50 Time (s) 0 Note: 30 60 90 120 150 180 210 240 270 300 Minimize air convection currents in the reflow oven to avoid component movement. Maximum soldering profile corresponds to the latest IPC/JEDEC J-STD-020. DocID025979 Rev1 9/11 Ordering information 4 HSP051-4N10 Ordering information Figure 23. Ordering information scheme HSP 05 1 - 4 N10 High speed line protection Breakdown voltage Version Number of lines Package µQFN-10L 1.9x1.0mm Table 4. Ordering information 5 Order code Marking Package Weight Base qty Delivery mode HSP051-4N10 HC µQFN-10L 1.61 mg 7000 Tape and reel Revision history Table 5. Document revision history 10/11 Date Revision 11-Jul-2014 1 Changes Initial release. DocID025979 Rev1 HSP051-4N10 IMPORTANT NOTICE – PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST’s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers’ products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document. © 2014 STMicroelectronics – All rights reserved DocID025979 Rev1 11/11