CY7C008V CY7C018V CY7C009V CY7C019V 3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM CY7C008V/009V CY7C018V/019V 3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM 3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM Features ■ True dual-ported memory cells which allow simultaneous access of the same memory location ■ 64 K × 8 organization (CY7C008) ■ 128 K × 8 organization (CY7C009) ■ 64 K × 9 organization (CY7C018) ■ 128 K × 9 organization (CY7C019) ■ 0.35-micron CMOS for optimum speed/power ■ High-speed access: 15/20/25 ns ■ Low operating power ❐ Active: ICC = 115 mA (typical) ❐ Standby: ISB3 = 10 A (typical) ■ Fully asynchronous operation ■ Automatic power-down ■ Expandable data bus to 16/18 bits or more using Master/Slave chip select when using more than one device ■ On-chip arbitration logic ■ Semaphores included to permit software handshaking between ports ■ INT flag for port-to-port communication ■ Dual chip enables ■ Pin select for Master or Slave ■ Commercial and industrial temperature ranges ■ Available in 100-pin TQFP ■ Pb-free packages available Logic Block Diagram R/WL R/WR CE0L CE1L CEL CE0R CE1R CER OEL OER [1] 8/9 8/9 I/O0L–I/O7/8L [2] A0L–A15/16L [2] 16/17 Address Decode True Dual-Ported RAM Array 16/17 Address Decode 16/17 [2] A0R–A15/16R 16/17 A0L–A15/16L CEL OEL R/WL SEML BUSYL INTL I/O Control I/O Control [1] I/O0R–I/O7/8R [2] A0R–A15/16R CER OER R/WR SEMR Interrupt Semaphore Arbitration [3] [3] BUSYR INTR M/S Notes 1. I/O0–I/O7 for ×8 devices; I/O0–I/O8 for ×9 devices. 2. A0–A15 for 64 K devices; A0–A16 for 128 K. 3. BUSY is an output in master mode and an input in slave mode. Cypress Semiconductor Corporation Document Number: 38-06044 Rev. *E • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised November 9, 2010 [+] Feedback CY7C008V/009V CY7C018V/019V Functional Description The CY7C008V/009V and CY7C018V/019V are low-power CMOS 64 K, 128 K × 8/9 dual-port static RAMs. Various arbitration schemes are included on the devices to handle situations when multiple processors access the same piece of data. Two ports are provided permitting independent, asynchronous access for reads and writes to any location in memory. The devices can be utilized as standalone 8/9-bit dual-port static RAMs or multiple devices can be combined in order to function as a 16/18-bit or wider master/slave dual-port static RAM. An M/S pin is provided for implementing 16/18-bit or wider memory applications without the need for separate master and slave devices or additional discrete logic. Application areas include interprocessor/multiprocessor designs, communications status buffering, and dual-port video/graphics memory. Document Number: 38-06044 Rev. *E Each port has independent control pins: chip enable (CE), read or write enable (R/W), and output enable (OE). Two flags are provided on each port (BUSY and INT). BUSY signals that the port is trying to access the same location currently being accessed by the other port. The interrupt flag (INT) permits communication between ports or systems by means of a mail box. The semaphores are used to pass a flag, or token, from one port to the other to indicate that a shared resource is in use. The semaphore logic is comprised of eight shared latches. Only one side can control the latch (semaphore) at any time. Control of a semaphore indicates that a shared resource is in use. An automatic power-down feature is controlled independently on each port by a chip select (CE) pin. The CY7C008V/009V and CY7C018V/019V are available in 100-pin Thin Quad Plastic Flatpacks (TQFP). Page 2 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Contents Pin Configurations ........................................................... 4 Selection Guide ................................................................ 5 Pin Definitions .................................................................. 6 Maximum Ratings ............................................................. 6 Operating Range ............................................................... 6 Electrical Characteristics ................................................. 7 Capacitance ...................................................................... 7 AC Test Loads and Waveforms ....................................... 8 Switching Characteristics ................................................ 8 Data Retention Mode ...................................................... 10 Timing .............................................................................. 10 Switching Waveforms .................................................... 11 Read Cycle No.1 (Either Port Address Access) ........ 11 Read Cycle No.2 (Either Port CE/OE Access) .......... 11 Read Cycle No. 3 (Either Port) .................................. 11 Write Cycle No. 1: R/W Controlled Timing ................ 12 Write Cycle No. 2: CE Controlled Timing .................. 12 Semaphore Read After Write Timing, Either Side ..... 13 Timing Diagram of Semaphore Contention ............... 13 Timing Diagram of Read with BUSY (M/S=HIGH) .... 14 Write Timing with Busy Input (M/S=LOW) ................. 14 Busy Timing Diagram No. 1 (CE Arbitration) ............. 15 Busy Timing Diagram No. 2 (Address Arbitration) .... 15 Document Number: 38-06044 Rev. *E Architecture .................................................................... 17 Functional Description ................................................... 17 Write Operation ......................................................... 17 Read Operation ......................................................... 17 Interrupts ................................................................... 17 Busy .......................................................................... 17 Master/Slave ............................................................. 17 Semaphore Operation ............................................... 17 Ordering Information ...................................................... 19 128 K × 8 3.3 V Asynchronous Dual-Port SRAM ...... 19 Ordering Code Definitions ......................................... 19 Package Diagram ............................................................ 20 Acronyms ........................................................................ 21 Document Conventions ................................................. 21 Units of Measure ....................................................... 21 Document History Page ................................................. 22 Sales, Solutions, and Legal Information ...................... 23 Worldwide Sales and Design Support ....................... 23 Products .................................................................... 23 PSoC Solutions ......................................................... 23 Page 3 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Pin Configurations NC NC A6R A5R A4R A3R A2R A1R A0R INTR M/S BUSYR GND BUSYL NC INTL A1L A0L A2L A3L A4L A5L A6L NC NC Figure 1. 100-pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R 65 A15R 64 A16R [4] 63 GND 62 NC 61 NC A15L 11 [4] A16L 12 VCC 13 NC 14 NC 15 NC 16 60 NC NC 17 59 NC CY7C009V (128 K × 8) CY7C008V (64 K × 8) CE0L 18 58 CE0R CE1L 19 57 CE1R SEML 20 56 SEMR R/WL 21 55 R/WR OEL 22 54 OER GND 23 53 GND NC 24 52 GND NC 25 51 NC NC NC NC I/O7R I/O6R I/O5R I/O4R I/O3R VCC I/O2R I/01R I/O0R VCC GND I/O0L I/O1L GND I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L NC GND 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Note 4. This pin is NC for CY7C008V. Document Number: 38-06044 Rev. *E Page 4 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V NC A6R A5R A4R A3R A2R A0R A1R INTR M/S BUSYR VCC GND GND BUSYL A0L INTL A2L A1L A3L A4L A5L A6L NC NC Figure 2. 100-pin TQFP (Top View) 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 NC 1 75 NC NC 2 74 NC A7L 3 73 A7R A8L 4 72 A8R A9L 5 71 A9R A10L 6 70 A10R A11L 7 69 A11R A12L 8 68 A12R A13L 9 67 A13R A14L 10 66 A14R 65 A15R 64 A16R [5] 63 GND 62 NC 61 NC A15L 11 [5] A16L 12 VCC 13 NC 14 NC 15 NC 16 60 NC NC 17 59 NC CY7C019V (128 K × 9) CY7C018V (64 K × 9) CE0L 18 58 CE0R CE1L 19 57 CE1R SEML 20 56 SEMR R/WL 21 55 R/WR OEL 22 54 OER GND 23 53 GND NC 24 52 GND NC 25 51 NC NC NC I/O8R I/O7R I/O6R I/O5R I/O4R VCC I/O3R I/O2R I/01R I/O0R GND VCC I/O0L GND I/O1L I/O2L I/O3L I/O4L I/O5L I/O6L I/O7L GND I/O8L 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Selection Guide CY7C018V/019V –15 CY7C018V/019V –20 CY7C018V/019V –25 Unit Maximum access time 15 20 25 ns Typical operating current 125 120 115 mA Typical standby current for ISB1 (both ports TTL level) 35 35 30 mA Typical standby current for ISB3 (both ports CMOS level) 10 10 10 A Note 5. This pin is NC for CY7C018V. Document Number: 38-06044 Rev. *E Page 5 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Pin Definitions Left Port Right Port Description CE0L, CE1L CER, CE1R Chip enable (CE is LOW when CE0VIL and CE1 VIH) R/WL R/WR Read/Write enable OEL OER Output enable A0L–A16L A0R–A16R Address (A0–A15 for 64 K devices and A0–A16 for 128 K devices) I/O0L–I/O8L I/O0R–I/O8R Data bus input/output (I/O0–I/O7 for ×8 devices and I/O0–I/O8 for ×9) SEML SEMR Semaphore enable INTL INTR Interrupt flag BUSYL BUSYR Busy flag M/S Master or slave select VCC Power GND Ground NC No Connect Maximum Ratings[6] Exceeding maximum ratings may shorten the useful life of the device. User guidelines are not tested. DC input voltage .................................. –0.5 V to VCC + 0.5 V Output current into outputs (LOW) .............................. 20 mA Static discharge voltage.......................................... > 1100 V Storage temperature ................................ –65 C to +150 C Latch-up current .................................................... > 200 mA Ambient temperature with power applied ........................................... –55 C to +125 C Operating Range Supply voltage to ground potential ...............–0.5 V to +4.6 V DC voltage applied to outputs in high Z State ......................... –0.5 V to VCC + 0.5 V Range Ambient Temperature VCC Commercial 0 C to +70 C 3.3 V ± 300 mV Industrial[7] –40 C to +85 C 3.3 V ± 300 mV Notes 6. The voltage on any input or I/O pin cannot exceed the power pin during power-up. 7. Industrial parts are available in CY7C009V and CY7C019V only. Document Number: 38-06044 Rev. *E Page 6 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Electrical Characteristics Over the Operating Range CY7C018V/019V Parameter Description –15 Min –20 Typ Max Unit Typ Max Min Typ Max – 2.4 – – 2.4 – – V 0.4 – 0.4 – 0.4 V VOH Output HIGH voltage (VCC = Min, IOH = –4.0 mA) 2.4 VOL Output LOW voltage (VCC = Min, IOH = +4.0 mA) – VIH Input HIGH voltage 2.2 – 2.2 – 2.2 – V VIL Input LOW voltage – 0.8 – 0.8 – 0.8 V IIX Input leakage current –5 5 –5 5 –5 5 A IOZ Output leakage current –10 10 –10 10 –10 10 A ICC Operating current (VCC = Max, IOUT = 0 mA) outputs disabled Commercial 185 – 120 175 – 165 mA 140 195 Standby current (both ports TTL level) CEL and CER VIH, f = fMAX Commercial 35 45 45 55 Standby current (one port TTL level) CEL | CER VIH, f = fMAX Commercial ISB1 ISB2 ISB3 ISB4 – – –25 Min 125 Industrial[8] Industrial – 35 [8] – 80 Industrial[8] 10 Standby current (one port CMOS level) CEL | CER VIH, f = fMAX[9] 75 Industrial[8] 120 – Standby current (both ports CMOS level) Commercial CEL and CER VCC 0.2 V, f = 0 Industrial[8] Commercial 50 250 – 105 – 75 110 85 120 10 250 10 250 70 95 80 105 115 – 30 mA 40 – 65 mA 95 – 10 mA mA 250 A A – 60 mA 80 – mA mA Capacitance[10] Parameter Description CIN Input capacitance COUT Output capacitance Test Conditions TA = 25 C, f = 1 MHz, VCC = 3.3 V Max Unit 10 pF 10 pF Notes 8. Industrial parts are available in CY7C009V and CY7C019V only. 9. fMAX = 1/tRC = All inputs cycling at f = 1/tRC (except output enable). f = 0 means no address or control lines change. This applies only to inputs at CMOS level standby ISB3. 10. Tested initially and after any design or process changes that may affect these parameters. Document Number: 38-06044 Rev. *E Page 7 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V AC Test Loads and Waveforms 3.3 V 3.3 V R1 = 590 C = 30 pF RTH = 250 OUTPUT OUTPUT R1 = 590 OUTPUT C = 30 pF R2 = 435 VTH = 1.4 V (a) Normal Load (Load 1) (c) Three-State Delay (Load 2) (Used for tLZ, tHZ, tHZWE, & tLZWE including scope and jig) (b) Thévenin Equivalent (Load 1) ALL INPUT PULSES 3.0 V 10% GND R2 = 435 C = 5 pF 90% 10% 90% 3 ns 3 ns Switching Characteristics Over the Operating Range[11] CY7C018V/019V Parameter Description –15 –20 –25 Unit Min Max Min Max Min Max READ CYCLE tRC Read cycle time 15 – 20 – 25 – ns tAA Address to data valid – 15 – 20 – 25 ns tOHA Output hold from address change 3 – 3 – 3 – ns tACE[12] CE LOW to data valid – 15 – 20 – 25 ns tDOE OE LOW to data valid – 10 – 12 – 13 ns tLZOE[13, 14, 15] OE LOW to low Z 3 – 3 – 3 – ns tHZOE[13, 14, 15] tLZCE[13, 14, 15] tHZCE[13, 14, 15] tPU[15] tPD[15] tABE[12] OE HIGH to high Z – 10 – 12 – 15 ns CE LOW to low Z 3 – 3 – 3 – ns CE HIGH to high Z – 10 – 12 – 15 ns CE LOW to power-up 0 – 0 – 0 – ns CE HIGH to power-down – 15 – 20 – 25 ns Byte enable access time – 15 – 20 – 25 ns Notes 11. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified IOI/IOH and 30 pF load capacitance. 12. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 13. At any given temperature and voltage condition for any given device, tHZCE is less than tLZCE and tHZOE is less than tLZOE. 14. Test conditions used are Load 2. 15. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. Document Number: 38-06044 Rev. *E Page 8 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Switching Characteristics Over the Operating Range[11] (continued) CY7C018V/019V Parameter Description –15 –20 –25 Unit Min Max Min Max Min Max 15 – 20 – 25 – WRITE CYCLE tWC Write cycle time tSCE[16] ns CE LOW to write end 12 – 16 – 20 – ns tAW Address valid to write end 12 – 16 – 20 – ns tHA Address hold from write end 0 – 0 – 0 – ns tSA[16] Address set-up to write start 0 – 0 – 0 – ns tPWE Write pulse width 12 – 17 – 22 – ns tSD Data set-up to write end 10 – 12 – 15 – ns tHD Data hold from write end 0 – 0 – 0 – ns tHZWE[17, 18] tLZWE[17, 18] tWDD[19] tDDD[19] R/W LOW to high Z – 10 – 12 – 15 ns R/W HIGH to low Z 3 – 3 – 3 – ns Write pulse to data delay – 30 – 40 – 50 ns Write data valid to read data valid – 25 – 30 – 35 ns [20] BUSY TIMING tBLA BUSY LOW from address match – 15 – 20 – 20 ns tBHA BUSY HIGH from address mismatch – 15 – 20 – 20 ns tBLC BUSY LOW from CE LOW – 15 – 20 – 20 ns tBHC BUSY HIGH from CE HIGH – 15 – 16 – 17 ns tPS Port set-up for priority 5 – 5 – 5 – ns tWB R/W HIGH after BUSY (Slave) 0 – 0 – 0 – ns tWH R/W HIGH after BUSY HIGH (Slave) 13 – 15 – 17 – ns tBDD[21] BUSY HIGH to data valid – 15 – 20 – 25 ns [20] INTERRUPT TIMING tINS INT set time – 15 – 20 – 20 ns tINR INT reset time – 15 – 20 – 20 ns SEMAPHORE TIMING tSOP SEM flag update pulse (OE or SEM) 10 – 10 – 12 – ns tSWRD SEM flag write to read time 5 – 5 – 5 – ns tSPS SEM flag contention window 5 – 5 – 5 – ns tSAA SEM address access time – 15 – 20 – 25 ns Notes 16. To access RAM, CE = L, UB = L, SEM = H. To access semaphore, CE = H and SEM = L. Either condition must be valid for the entire tSCE time. 17. Test conditions used are Load 2. 18. This parameter is guaranteed by design, but it is not production tested.For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 19. For information on port-to-port delay through RAM cells from writing port to reading port, refer to Read Timing with Busy waveform. 20. Test conditions used are Load 1. 21. tBDD is a calculated parameter and is the greater of tWDD–tPWE (actual) or tDDD–tSD (actual). Document Number: 38-06044 Rev. *E Page 9 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Data Retention Mode The CY7C008V/009V and CY7C018V/019V are designed with battery backup in mind. Data retention voltage and supply current are guaranteed over temperature. The following rules ensure data retention: 1. Chip enable (CE) must be held HIGH during data retention, within VCC to VCC – 0.2 V. 2. CE must be kept between VCC – 0.2 V and 70% of VCC during the power-up and power-down transitions. 3. The RAM can begin operation > tRC after VCC reaches the minimum operating voltage (3.0 V). Timing Data Retention Mode VCC 3.0 V VCC 2.0 V 3.0 V VCC to VCC – 0.2 V CE Parameter ICCDR1 Test Conditions[22] @ VCCDR = 2 V tRC V IH Max Unit 50 A Note 22. CE = VCC, Vin = GND to VCC, TA = 25C. This parameter is guaranteed but not tested. Document Number: 38-06044 Rev. *E Page 10 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Switching Waveforms Read Cycle No.1 (Either Port Address Access)[23, 24, 25] tRC ADDRESS tOHA DATA OUT tAA tOHA PREVIOUS DATA VALID DATA VALID Read Cycle No.2 (Either Port CE/OE Access)[23, 26, 27] tACE CE tDOE OE tHZCE tHZOE tLZOE DATA VALID DATA OUT tLZCE tPU tPD ICC CURRENT ISB Read Cycle No. 3 (Either Port)[23, 25, 26, 27] tRC ADDRESS tAA tOHA tLZCE tABE CE tHZCE tACE tLZCE DATA OUT Notes 23. R/W is HIGH for read cycles. 24. Device is continuously selected CE = VIL. This waveform cannot be used for semaphore reads. 25. OE = VIL. 26. Address valid prior to or coincident with CE transition LOW. 27. To access RAM, CE = VIL, SEM = VIH. To access semaphore, CE = VIH, SEM = VIL. Document Number: 38-06044 Rev. *E Page 11 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Write Cycle No. 1: R/W Controlled Timing[28, 29, 30, 31] tWC ADDRESS tHZOE [33] OE tAW CE [32] tPWE[31] tSA tHA R/W tHZWE[33] DATA OUT tLZWE NOTE 34 NOTE 34 tSD tHD DATA IN Write Cycle No. 2: CE Controlled Timing[28, 29, 30, 35] tWC ADDRESS tAW CE [32] tSA tSCE tHA R/W tSD tHD DATA IN Notes 28. R/W must be HIGH during all address transitions. 29. A write occurs during the overlap (tSCE or tPWE) of a LOW CE or SEM. 30. tHA is measured from the earlier of CE or R/W or (SEM or R/W) going HIGH at the end of write cycle. 31. If OE is LOW during a R/W controlled write cycle, the write pulse width must be the larger of tPWE or (tHZWE + tSD) to allow the I/O drivers to turn off and data to be placed on the bus for the required tSD. If OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified tPWE. 32. To access RAM, CE = VIL, SEM = VIH. 33. Transition is measured 500 mV from steady state with a 5 pF load (including scope and jig). This parameter is sampled and not 100% tested. 34. During this period, the I/O pins are in the output state, and input signals must not be applied. 35. If the CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the high-impedance state. Document Number: 38-06044 Rev. *E Page 12 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Semaphore Read After Write Timing, Either Side[36] tSAA A0–A2 VALID ADRESS VALID ADRESS tAW tACE tHA SEM tOHA tSCE tSOP tSD I/O 0 DATAIN VALID tSA tPWE DATAOUT VALID tHD R/W tSWRD tDOE tSOP OE WRITE CYCLE READ CYCLE Timing Diagram of Semaphore Contention[37, 38, 39] A0L–A2L MATCH R/WL SEML tSPS A0R–A2R MATCH R/WR SEMR Notes 36. CE = HIGH for the duration of the above timing (both write and read cycle). 37. I/O0R = I/O0L = LOW (request semaphore); CER = CEL = HIGH. 38. Semaphores are reset (available to both ports) at cycle start. 39. If tSPS is violated, the semaphore will definitely be obtained by one side or the other, but which side will get the semaphore is unpredictable. Document Number: 38-06044 Rev. *E Page 13 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Timing Diagram of Read with BUSY (M/S=HIGH)[40] tWC ADDRESSR MATCH tPWE R/WR tSD DATA INR tHD VALID tPS ADDRESSL MATCH tBLA tBHA BUSYL tBDD tDDD DATAOUTL VALID tWDD Write Timing with Busy Input (M/S=LOW) tPWE R/W BUSY tWB tWH Note 40. CEL = CER = LOW. Document Number: 38-06044 Rev. *E Page 14 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Busy Timing Diagram No. 1 (CE Arbitration)[41] CEL Valid First: ADDRESSL,R ADDRESS MATCH CEL tPS CER tBLC tBHC BUSYR CER Valid First: ADDRESSL,R ADDRESS MATCH CER tPS CEL tBLC tBHC BUSYL Busy Timing Diagram No. 2 (Address Arbitration)[41] Left Address Valid First: tRC or tWC ADDRESSL ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSR tBLA tBHA BUSYR Right Address Valid First: tRC or tWC ADDRESSR ADDRESS MATCH ADDRESS MISMATCH tPS ADDRESSL tBLA tBHA BUSYL Note 41. If tPS is violated, the busy signal will be asserted on one side or the other, but there is no guarantee to which side BUSY will be asserted. Document Number: 38-06044 Rev. *E Page 15 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Switching Waveforms (continued) Interrupt Timing Diagrams Left Side Sets INTR: ADDRESSL tWC WRITE FFFF (1FFFF for CY7C009V/19V) tHA[42] CEL R/WL INTR tINS [43] Right Side Clears INTR: tRC READ FFFF (1FFFF for CY7C009V/19V) ADDRESSR CER tINR [43] R/WR OER INTR Right Side Sets INTL: tWC ADDRESSR WRITE FFFE (1FFFF for CY7C009V/19V) tHA[42] CER R/WR INTL [43] tINS Right Side Clears INTL: tRC READ 1FFE (1FFFF for CY7C009V/19V) ADDRESSR CEL tINR[43] R/WL OEL INTL Notes 42. tHA depends on which enable pin (CEL or R/WL) is deasserted first. 43. tINS or tINR depends on which enable pin (CEL or R/WL) is asserted last. Document Number: 38-06044 Rev. *E Page 16 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Architecture The CY7C008V/009V and CY7C018V/019V consist of an array of 64 K and 128 K words of 8 and 9 bits each of dual-port RAM cells, I/O and address lines, and control signals (CE, OE, R/W). These control pins permit independent access for reads or writes to any location in memory. To handle simultaneous writes/reads to the same location, a BUSY pin is provided on each port. Two interrupt (INT) pins can be utilized for port-to-port communication. Two semaphore (SEM) control pins are used for allocating shared resources. With the M/S pin, the devices can function as a master (BUSY pins are outputs) or as a slave (BUSY pins are inputs). The devices also have an automatic power-down feature controlled by CE. Each port is provided with its own output enable control (OE), which allows data to be read from the device. Functional Description Write Operation Data must be set up for a duration of tSD before the rising edge of R/W in order to guarantee a valid write. A write operation is controlled by either the R/W pin (see Write Cycle No. 1 waveform) or the CE pin (see Write Cycle No. 2 waveform). Required inputs for non-contention operations are summarized in Table 1 on page 18. If a location is being written to by one port and the opposite port attempts to read that location, a port-to-port flowthrough delay must occur before the data is read on the output; otherwise the data read is not deterministic. Data will be valid on the port tDDD after the data is presented on the other port. Read Operation When reading the device, the user must assert both the OE and CE pins. Data will be available tACE after CE or tDOE after OE is asserted. If the user wishes to access a semaphore flag, then the SEM pin must be asserted instead of the CE pin, and OE must also be asserted. Interrupts The upper two memory locations may be used for message passing. The highest memory location (FFFF for the CY7C008/18, 1FFFF for the CY7C009/19) is the mailbox for the right port and the second-highest memory location (FFFE for the CY7C008/18, 1FFFE for the CY7C009/19) is the mailbox for the left port. When one port writes to the other port’s mailbox, an interrupt is generated to the owner. The interrupt is reset when the owner reads the contents of the mailbox. The message is user defined. Each port can read the other port’s mailbox without resetting the interrupt. The active state of the busy signal (to a port) prevents the port from setting the interrupt to the winning port. Also, an active busy to a port prevents that port from reading its own mailbox and, thus, resetting the interrupt to it. If an application does not require message passing, do not connect the interrupt pin to the processor’s interrupt request input pin. The operation of the interrupts and their interaction with Busy are summarized in Table 2 on page 18. Document Number: 38-06044 Rev. *E Busy The CY7C008V/009V and CY7C018V/019V provide on-chip arbitration to resolve simultaneous memory location access (contention). If both ports’ CEs are asserted and an address match occurs within tPS of each other, the busy logic will determine which port has access. If tPS is violated, one port will definitely gain permission to the location, but it is not predictable which port will get that permission. BUSY will be asserted tBLA after an address match or tBLC after CE is taken LOW. Master/Slave A M/S pin is provided in order to expand the word width by configuring the device as either a master or a slave. The BUSY output of the master is connected to the BUSY input of the slave. This will allow the device to interface to a master device with no external components. Writing to slave devices must be delayed until after the BUSY input has settled (tBLC or tBLA), otherwise, the slave chip may begin a write cycle during a contention situation. When tied HIGH, the M/S pin allows the device to be used as a master and, therefore, the BUSY line is an output. BUSY can then be used to send the arbitration outcome to a slave. Semaphore Operation The CY7C008V/009V and CY7C018V/019V provide eight semaphore latches, which are separate from the dual-port memory locations. Semaphores are used to reserve resources that are shared between the two ports.The state of the semaphore indicates that a resource is in use. For example, if the left port wants to request a given resource, it sets a latch by writing a zero to a semaphore location. The left port then verifies its success in setting the latch by reading it. After writing to the semaphore, SEM or OE must be deasserted for tSOP before attempting to read the semaphore. The semaphore value will be available tSWRD + tDOE after the rising edge of the semaphore write. If the left port was successful (reads a zero), it assumes control of the shared resource, otherwise (reads a one) it assumes the right port has control and continues to poll the semaphore. When the right side has relinquished control of the semaphore (by writing a one), the left side will succeed in gaining control of the semaphore. If the left side no longer requires the semaphore, a one is written to cancel its request. Semaphores are accessed by asserting SEM LOW. The SEM pin functions as a chip select for the semaphore latches (CE must remain HIGH during SEM LOW). A0–2 represents the semaphore address. OE and R/W are used in the same manner as a normal memory access. When writing or reading a semaphore, the other address pins have no effect. When writing to the semaphore, only I/O0 is used. If a zero is written to the left port of an available semaphore, a one will appear at the same semaphore address on the right port. That semaphore can now only be modified by the side showing zero (the left port in this case). If the left port now relinquishes control by writing a one to the semaphore, the semaphore will be set to one for both sides. However, if the right port had requested the semaphore (written a zero) while the left port had control, the right port would immediately own the semaphore as soon as the left port released it. Table 3 on page 18 shows sample semaphore operations. Page 17 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V When reading a semaphore, all data lines output the semaphore value. The read value is latched in an output register to prevent the semaphore from changing state during a write from the other port. If both ports attempt to access the semaphore within tSPS of each other, the semaphore will definitely be obtained by one side or the other, but there is no guarantee which side will control the semaphore. Table 1. Non-Contending Read/Write Inputs Outputs CE R/W OE SEM H X X H High Z Deselected: Power-down H H L L Data out Read data in semaphore flag X X H X High Z I/O lines disabled X L Data in Write into semaphore flag H L H Data out Read L L X H Data in Write L X X L H L I/O0–I/O8 Operation Not allowed Table 2. Interrupt Operation Example (assumes BUSYL = BUSYR = HIGH)[44] Left Port Function Right Port R/WL CEL OEL A0L–16L INTL R/WR CER OER A0R–16R INTR Set Right INTR Flag L L X FFFF (or 1FFFF) X X X X X L[46] Reset Right INTR Flag X X X X X X L L FFFF (or 1FFFF) H[45] Set Left INTL Flag X X X X L[45] L L X FFFE (or 1FFFE) X FFFE (or 1FFFE) H[46] X X X X X Reset Left INTL Flag X L L Table 3. Semaphore Operation Example Function I/O0–I/O8 Left I/O0–I/O8Right Status No action 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Right port writes 0 to semaphore 0 1 No change. Right side has no write access to semaphore Left port writes 1 to semaphore 1 0 Right port obtains semaphore token Left port writes 0 to semaphore 1 0 No change. Left port has no write access to semaphore Right port writes 1 to semaphore 0 1 Left port obtains semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Right port writes 0 to semaphore 1 0 Right port has semaphore token Right port writes 1 to semaphore 1 1 Semaphore free Left port writes 0 to semaphore 0 1 Left port has semaphore token Left port writes 1 to semaphore 1 1 Semaphore free Notes 44. A0L–16L and A0R–16R, 1FFFF/1FFFE for the CY7C009V/19V. 45. If BUSYR = L, then no change. 46. If BUSYL = L, then no change. Document Number: 38-06044 Rev. *E Page 18 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Ordering Information 128 K × 8 3.3 V Asynchronous Dual-Port SRAM Speed (ns) Package Name Ordering Code Package Type Operating Range 15 CY7C009V-15AXC A100 100-pin Pb-free Thin Quad Flat Pack Commercial 20 CY7C009V-20AXI A100 100-pin Pb-free Thin Quad Flat Pack Industrial 25 CY7C009V-25AXC A100 100-pin Pb-free Thin Quad Flat Pack Commercial Ordering Code Definitions CY 7 C 00 9 V - XX A X X Operating Range: X = C or I C = Commercial; I = Industrial Pb-free Package: A = (A100) 100-pin Thin Quad Flat Pack Speed Bin: XX = 15/20/25 3.3 V part 64 K / 128 K Dual Port Family 00 = ×8 Technology Code: C = CMOS Marketing Code: 7 = SRAM Company ID: CY = Cypress Document Number: 38-06044 Rev. *E Page 19 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Package Diagram Figure 3. 100-pin Thin Plastic Quad Flat Pack (TQFP) A100 51-85048 *D Document Number: 38-06044 Rev. *E Page 20 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Acronyms Document Conventions Acronym Description Units of Measure CMOS complementary metal oxide semiconductor CE chip enable ns nano seconds I/O input/output V Volts OE output enable µA micro Amperes SRAM static random access memory mA milli Amperes TQFP thin quad flat pack ms milli seconds TTL Transistor–transistor logic mV milli Volts WE write enable MHz Mega Hertz Document Number: 38-06044 Rev. *E Symbol Unit of Measure pF pico Farad W Watts °C degree Celcius Page 21 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Document History Page Document Title: CY7C008V/009V, CY7C018V/019V 3.3 V 64 K/128 K × 8/9 Dual-Port Static RAM Document Number: 38-06044 REV. ECN NO. Issue Date Orig. of Change Description of Change ** 110192 09/29/01 SZV Change from Spec number: 38-00669 to 38-06044 *A 113541 04/15/02 OOR Change pin 85 from BUSYL to BUSYR (pg. 3) *B 122294 12/27/02 RBI Power up requirements added to Maximum Ratings Information *C 393440 See ECN YIM Added Pb-Free Logo Added Pb-Free parts to ordering information: CY7C008V-25AXC, CY7C009V-15AXC, CY7C009V-20AXI, CY7C009V-25AXC, CY7C019V-15AXC, CY7C019V-20AXC, CY7C019V-20AXI, CY7C019V-25AXC *D 2896038 03/19/10 RAME Removed inactive parts from ordering information table Updated package diagram *E 3081242 11/09/2010 ADMU Added Ordering Code Definitions. Added Acronyms and Units of Measure. Minor edits and updated in new template. Document Number: 38-06044 Rev. *E Page 22 of 23 [+] Feedback CY7C008V/009V CY7C018V/019V Sales, Solutions, and Legal Information Worldwide Sales and Design Support Cypress maintains a worldwide network of offices, solution centers, manufacturer’s representatives, and distributors. To find the office closest to you, visit us at Cypress Locations. Products Automotive Clocks & Buffers Interface Lighting & Power Control PSoC Solutions cypress.com/go/automotive cypress.com/go/clocks psoc.cypress.com/solutions cypress.com/go/interface PSoC 1 | PSoC 3 | PSoC 5 cypress.com/go/powerpsoc cypress.com/go/plc Memory Optical & Image Sensing cypress.com/go/memory cypress.com/go/image PSoC Touch Sensing cypress.com/go/psoc cypress.com/go/touch USB Controllers Wireless/RF cypress.com/go/USB cypress.com/go/wireless © Cypress Semiconductor Corporation, 2001-2010. The information contained herein is subject to change without notice. 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Document Number: 38-06044 Rev. *E Revised November 9, 2010 Page 23 of 23 All products and company names mentioned in this document may be the trademarks of their respective holders. [+] Feedback