ALSC AS7C31026 5v/3.3v 64kx6 cmos sram Datasheet

May 2000
AS7C1026
AS7C31026
®
5V/3.3V 64K×16 CMOS SRAM
• Low power consumption: STANDBY
- 28 mW (AS7C1026) / max CMOS I/O
- 18 mW (AS7C31026) / max CMOS I/O
• 2.0V data retention
• Easy memory expansion with CE, OE inputs
• TTL-compatible, three-state I/O
• JEDEC standard packaging
- 44-pin 400 mil SOJ
- 44-pin 400 mil TSOP II
- 48-ball 6 mm × 8 mm CSP mBGA
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
Features
• AS7C1026 (5V version)
• AS7C31026 (3.3V version)
• Industrial and commercial versions
• Organization: 65,536 words x 16 bits
• Center power and ground pins for low noise
• High speed
- 10/12/15/20 ns address access time
- 5/6/8/10 ns output enable access time
• Low power consumption: ACTIVE
- 880 mW (AS7C1026) / max @ 12 ns
- 396 mW (AS7C31026) / max @ 12 ns
Logic block diagram
Pin arrangement
I/O
buffer
WE
UB
OE
LB
CE
64K × 16
Array
Control circuit
Column decoder
A8
A9
A10
A11
A12
A13
A14
A15
I/O0–I/O7
I/O8–I/O15
VCC
Row decoder
A1
A2
A3
A4
A5
A6
A7
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
A4
A3
A2
A1
A0
CE
I/O0
I/O1
I/O2
I/O3
VCC
GND
I/O4
I/O5
I/O6
I/O7
WE
A15
A14
A13
A12
NC
AS7C102
44-Pin SOJ, TSOP II (400 mil)
A0
A5
A6
A7
OE
UB
LB
I/O15
I/O14
I/O13
I/O12
GND
VCC
I/O11
I/O10
I/O9
I/O8
NC
A8
A9
A10
A11
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
48-CSP mini Ball-Grid-Array Package
1
2
3
4
5
OE
A0
A1
A2
A
LB
A3
A4 CE
B I/O8 UB
A6 I/O1
C I/O9 I/O10 A5
A7 I/O3
D VSS I/O11 NC
E VDD I/O12 NC
NC I/O4
F I/O14 I/O13 A14 A15 I/O5
G I/O15 NC A12 A13 WE
H NC
A8
A9 A10 A11
6
NC
I/O0
I/O2
VDD
VSS
I/O6
I/O7
NC
Selection guide
AS7C1026-12 AS7C1026-15 AS7C1026-20
AS7C31026-10 AS7C31026-12 AS7C31026-15 AS7C31026-20
Unit
Maximum address access time
10
12
15
20
ns
Maximum output enable access time
5
6
8
10
ns
AS7C1026
–
160
150
140
mA
AS7C31026
125
110
100
90
mA
AS7C1026
–
3
3
3
mA
AS7C31026
3
3
3
3
mA
Maximum operating current
Maximum CMOS standby current
Shaded areas indicate preliminary information.
DID 11-20011-A. 5/22/00
ALLIANCE SEMICONDUCTOR
1
Copyright ©1999 Alliance Semiconductor. All rights reserved.
AS7C1026
AS7C31026
®
Functional description
SRAM
The AS7C1026 and AS7C31026 are high-performance CMOS 1,048,576-bit Static Random Access Memory (SRAM) devices
organized as 65,536 words x 16 bits. They are designed for memory applications where fast data access, low power, and simple
interfacing are desired.
Equal address access and cycle times (tAA, tRC, tWC) of 10/12/15/20 ns with output enable access times (tOE) of 5/6/8/10 ns
are ideal for high-performance applications.
When CE is high the devices enter stanby mode. The AS7C1026 is guaranteed not to exceed 28 mW power consumption in
CMOS standby mode. The devices also offer 2.0V data retention.
A write cycle is accomplished by asserting write enable (WE) and chip enable (CE). Data on the input pins I/O0–I/O15 is
written on the rising edge of WE (write cycle 1) or CE (write cycle 2). To avoid bus contention, external devices should drive I/
O pins only after outputs have been disabled with output enable (OE) or write enable (WE).
A read cycle is accomplished by asserting output enable (OE) and chip enable (CE), with write enable (WE) high. the chips drive
I/O pins with the data word referenced by the input address. When either chip enable or output enable is inactive, or write
enable is active, output drivers stay in high-impedance mode.
The devices provide multiple center power and ground pins, and separate byte enable controls, allowing individual bytes to be
written and read. LB controls the lower bits, I/O0–I/O7, and UB controls the higher bits, I/O8–I/O15.
All chip inputs and outputs are TTL-compatible, and operation is from a single 5V supply (AS7C1026) or 3.3V supply
(AS7C31026). the device is packaged in common industry standard packages. Chip scale BGA packaging, easy to use in
manufacturing, provides the smallest possible footprint. This 48-ball JEDEC-registered package has a ball pitch of 0.75 mm and
external dimensions of 8 mm × 6 mm.
Absolute maximum ratings
Parameter
Symbol
Min
Max
Unit
AS7C1026
Vt1
–0.50
+7.0
V
AS7C31026
Vt1
–0.50
+5.0
V
Voltage on any pin relative to GND
Vt2
–0.50
VCC +0.50
V
Power dissipation
PD
–
1.0
W
Storage temperature (plastic)
Tstg
–65
+150
°C
Ambient temperature with VCC applied
Tbias
–55
+125
°C
DC current into outputs (low)
IOUT
–
20
mA
Voltage on VCC relative to GND
Note: Stresses greater than those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stre ss rating only and functional operation of the device at these or any other conditions outside those indicated in the operational sections of this spec ification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect reliability.
Truth table
2
CE
WE
OE
LB
UB
I/O0–I/O7
I/O8–I/O15
Mode
H
X
X
X
X
High Z
High Z
Standby (ISB), ISBI)
L
H
L
L
H
DOUT
High Z
Read I/O0–I/O7 (ICC)
L
H
L
H
L
High Z
DOUT
Read I/O8–I/O15 (ICC)
L
H
L
L
L
DOUT
DOUT
Read I/O0–I/O15 (ICC)
L
L
X
L
L
DIN
DIN
Write I/O0–I/O15 (ICC)
L
L
X
L
H
DIN
High Z
Write I/O0–I/O7 (ICC)
ALLIANCE SEMICONDUCTOR
DID 11-20011-A. 5/22/00
AS7C1026
AS7C31026
®
WE
OE
LB
UB
I/O0–I/O7
I/O8–I/O15
Mode
L
L
X
H
L
High Z
DIN
Write I/O8–I/O15 (ICC)
L
L
H
X
H
X
X
H
X
H
High Z
High Z
Output disable (ICC)
SRAM
SRAM
CE
Key: H = High, L = Low, X = don’t care.
Recommended operating conditions
Parameter
Device
Symbol
Min
Typ
Max
Unit
AS7C1026
VCC
4.5
5.0
5.5
V
AS7C31026 (–10)
VCC
3.15
3.3
3.6
V
AS7C31026 (12/15/20)
VCC
3.0
3.3
3.6
V
AS7C1026
VIH
2.2
–
VCC + 0.5
V
AS7C31026
VIH
2.0
–
VCC + 0.5
V
VIL
–0.5†
–
0.8
V
commercial
TA
0
–
70
°C
industrial
TA
–40
–
85
°C
Supply voltage
Input voltage
Ambient operating temperature
†V
IL min = –3.0V for pulse width less than t RC/2.
DC operating characteristics (over the operating range)
-10
Parameter
-12
-15
-20
Min Max Min Max Min Max
Test conditions
| ILI |
VCC = Max
VIN = GND to VCC
–
1
–
1
–
1
–
1
µA
Output leakage
| ILO |
current
VCC = Max
CE = VIH,
VOUT = GND to VCC
–
1
–
1
–
1
–
1
µA
Operating
power supply
current
VCC = Max, CE ≤ VIL
outputs open,
f = fMax = 1/tRC
AS7C1026
–
–
–
160
–
150
–
140 mA
ICC
AS7C31026
–
125
–
110
–
100
–
90
VCC = Max, CE ≤ VIL,
outputs open,
f = fMax = 1/tRC
AS7C1026
–
–
–
40
–
40
–
40
ISB
AS7C31026
–
25
–
25
–
25
–
25
VCC = Max, CE ≥ VCC–0.2V,
VIN ≤ GND + 0.2V or
VIN ≥ VCC–0.2V, f = 0
AS7C1026
–
–
–
10
–
10
–
10
ISB1
AS7C31026
–
10
–
10
–
10
–
10
VOL
IOL = 8 mA, VCC = Min
–
0.4
–
0.4
–
0.4
–
0.4
V
VOH
IOH = –4 mA, VCC = Min
2.4
–
2.4
–
2.4
–
2.4
–
V
Input leakage
current
Standby
power supply
current
Output
voltage
Device
Min Max Unit
Sym
mA
mA
mA
Shaded areas indicate preliminary information.
Capacitance (f = 1MHz, Ta = 25 °C, VCC = NOMINAL)
Parameter
Symbol
Signals
Test conditions
Input capacitance
CIN
A, CE, WE, OE, LB, UB
VIN = 0V
5
pF
I/O capacitance
CI/O
I/O
VIN = VOUT = 0V
7
pF
DID 11-20011-A. 5/22/00
ALLIANCE SEMICONDUCTOR
Max Unit
3
AS7C1026
AS7C31026
®
Read cycle (over the operating range)
-10
SRAM
Parameter
-12
-15
-20
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Read cycle time
tRC
10
–
12
–
15
–
20
–
ns
Address access time
tAA
–
10
–
12
–
15
–
20
ns
3
Chip enable (CE) access time
tACE
–
10
–
12
–
15
–
20
ns
3
Output enable (OE) access time
tOE
–
5
–
5
–
8
–
10
ns
Output hold from address change
tOH
4
–
4
–
4
–
4
–
ns
5
CE Low to output in low Z
tCLZ
0
–
0
–
0
–
0
–
ns
4, 5
CE High to output in high Z
tCHZ
–
6
–
6
–
6
–
8
ns
4, 5
OE Low to output in low Z
tOLZ
0
–
0
–
0
–
0
–
ns
4, 5
Byte select access time
tBA
–
5
–
6
–
8
–
10
ns
Byte select Low to low Z
tBLZ
0
–
0
–
0
–
0
–
ns
4,5
Byte select High to high Z
tBHZ
–
5
–
6
–
6
–
8
ns
4,5
OE High to output in high Z
tOHZ
–
5
–
6
–
6
–
8
ns
4, 5
Power up time
tPU
0
–
0
–
0
–
0
–
ns
4, 5
Power down time
tPD
–
10
–
12
–
15
–
20
ns
4, 5
Shaded areas indicate preliminary information.
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
Read waveform 1 (address controlled)
tRC
Address
Data OUT
tAA
tOH
Previous data valid
tOH
Data valid
Read waveform 2 (OE, CE, UB, LB controlled)
tRC
Address
tAA
OE
tOE
tOLZ
tOH
CE
tLZ
tOHZ
tHZ
tACE
LB, UB
tBLZ
DataIN
4
tBA
tBHZ
Data valid
ALLIANCE SEMICONDUCTOR
DID 11-20011-A. 5/22/00
AS7C1026
AS7C31026
®
Write cycle (over the operating range)
-10
Parameter
-12
-15
-20
Symbol Min Max Min Max Min Max Min Max
Unit
Notes
tWC
10
–
12
–
15
–
20
–
ns
Chip enable (CE) to write end
tCW
8
–
8
–
12
–
13
–
ns
Address setup to write end
tAW
8
–
9
–
10
–
12
–
ns
Address setup time
tAS
0
–
0
–
0
–
0
–
ns
Write pulse width
tWP
8
–
8
–
10
–
12
–
ns
Address hold from end of write
tAH
0
–
0
–
0
–
0
–
ns
Data valid to write end
tDW
5
–
6
–
8
–
10
–
ns
Data hold time
tDH
0
–
0
–
0
–
0
–
ns
5
Write enable to output in high Z
tWZ
–
6
–
6
–
6
–
8
ns
4, 5
Output active from write end
tOW
1
–
1
–
1
–
2
–
ns
4, 5
Byte select low to end of write
tBW
8
–
8
–
9
–
12
–
ns
SRAM
SRAM
Write cycle time
Shaded areas indicate preliminary information.
Write waveform 1 (WE controlled)
tWC
Address
tWR
tCW
CE
tBW
LB, UB
tAW
tAS
tWP
WE
tDW
Data IN
tDH
Data valid
tWZ
Data OUT
tOW
Data undefined
high Z
Write waveform 2 (CE controlled)
tWC
Address
tAS
tWR
tCW
CE
tAW
tBW
LB, UB
tWP
WE
tDH
tDW
Data valid
DataIN
tCLZ
Data OUT
DID 11-20011-A. 5/22/00
high Z
tWZ
Data undefined
ALLIANCE SEMICONDUCTOR
tOW
high Z
5
AS7C1026
AS7C31026
®
Data retention characteristics (over the operating range)
SRAM
Parameter
Symbol
VCC for data retention
VDR
Data retention current
ICCDR
Chip deselect to data retention time
tCDR
Operation recovery time
Test conditions
VCC = 2.0V
CE ≥ VCC–0.2V
VIN ≥ VCC–0.2V or
VIN ≤ 0.2V
tR
|ILI|
Input leakage current
Min
Max
Unit
2.0
–
V
–
500
µA
0
–
ns
tRC
–
ns
–
1
µA
Data retention waveform
Data retention mode
VCC
VDR ≥ 2.0V
VCC
VCC
tCDR
tR
VDR
VIH
CE
VIH
AC test conditions
-
Output load: see Figure B or Figure C, except as noted.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
Thevenin Equivalent:
168W
+1.728V (5V and 3.3V)
D OUT
+5V
+3.3V
480W
+3.0V
GND
D OUT
90%
10%
90%
2 ns
Figure A: Input pulse
255W
10%
320W
D OUT
C(14)
GND
Figure B: 5V Output load
255W
C(14)
GND
Figure C: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
14
6
During V CC power-up, a pull-up resistor to VCC on CE is required to meet ISB specification.
This parameter is sampled, but not 100% tested.
For test conditions, see AC Test Conditions, Figures A, B, and C.
These parameters are specified with C L = 5pF, as in Figures B or C. Transition is measured ± 500 mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
CE or WE must be High during address transitions. Either CE or WE asserting high terminates a write cycle.
All write cycle timings are referenced from the last valid address to the first transitioning address.
Not applicable.
2V data retention applies to commercial temperature range operation only.
C=30pF, except all high Z and low Z parameters where C=5pF.
ALLIANCE SEMICONDUCTOR
DID 11-20011-A. 5/22/00
AS7C1026
AS7C31026
®
Typical DC and AC characteristics
1.4
0.8
0.6
ISB
0.4
0.2
1.0
0.8
0.6
ISB
0.4
0.0
–55
MAX
1.4
Normalized access time
1.2
1.1
1.0
0.9
NOMINAL
Supply voltage (V)
Output sink current (mA)
Ta = 25° C
100
80
60
40
20
0
VCC
Output voltage (V)
DID 11-20011-A. 5/22/00
0.04
–10
35
80
125
Ambient temperature (°C)
-55
1.2
1.1
1.0
0.9
-10
35
80
125
Ambient temperature (°C)
Normalized supply current ICC
vs. cycle frequency 1/tRC, 1/tWC
1.4
VCC = VCC(NOMINAL)
Ta = 25° C
1.0
0.8
0.6
0.4
0.2
0.0
–10
35
80
125
Ambient temperature (°C)
0
Output sink current IOL
vs. output voltage VOL
120
30
Ta = 25° C
100
80
60
40
20
25
50
75
Cycle frequency (MHz)
100
Typical access time change ∆tAA
vs. output capacitive loading
35
VCC = VCC(NOMINAL)
VCC = VCC (NOMINAL)
25
20
15
10
5
0
0
0.2
VCC = VCC(NOMINAL)
1.3
140
VCC = VCC (NOMINAL)
120
1
1.2
0.8
–55
MAX
Output source current I OH
vs. output voltage VOH
140
5
1.4
Ta = 25° C
VCC = VCC(NOMINAL)
25
Normalized access time tAA
vs. ambient temperature T a
1.5
1.3
0.8
MIN
625
Normalized ICC
NOMINAL
Supply voltage (V)
Normalized access time tAA
vs. supply voltage VCC
1.5
Normalized access time
ICC
0.2
0.0
MIN
Output source current (mA)
Normalized ISB1 (log scale)
1.0
Normalized ICC, ISB
Normalized ICC, ISB
1.2
ICC
Normalized supply current ISB1
vs. ambient temperature Ta
SRAM
SRAM
1.2
Normalized supply current ICC, ISB
vs. ambient temperature T a
Change in tAA (ns)
1.4
Normalized supply current ICC, I SB
vs. supply voltage VCC
0
0
VCC
Output voltage (V)
ALLIANCE SEMICONDUCTOR
0
250
500
750
Capacitance (pF)
1000
7
AS7C1026
AS7C31026
®
Package dimensions
c
44434241403938 373635 343332 31 3029 2827 2625 24 23
44-pin TSOP II
SRAM
Min
(mm)
E He
44-pin TSOP II
A
Max
(mm)
1.2
A1
0.05
A2
0.95
1.05
b
0.30
0.45
c
0.127 (typical)
1 2 3 4 5 6 7 8 9 10 11121314 1516 1718 1920 21 22
D
A2
A
A1
l
0–5°
e
b
D
18.28
18.54
E
10.03
10.29
He
11.56
11.96
e
l
D
e
44-pin SOJ
E1 E2
Pin 1
c
B
A2
A
A1
b
8
Seating
Plane
E2
ALLIANCE SEMICONDUCTOR
A
A1
A2
B
b
c
D
E
E1
E2
e
0.80 (typical)
0.40
0.60
44-pin SOJ
400 mL
Min
Max
0.128
0.148
0.025
–
1.105
1.115
0.026
0.032
0.015
0.020
0.007
0.013
1.120
1.130
0.370 NOM
0.395
0.405
0.435
0.445
0.050 NOM
DID 11-20011-A. 5/22/00
AS7C1026
AS7C31026
®
48-ball FBGA
Bottom View
5
4
3
2
Ball #A1 index
Ball A1
1
SRAM
SRAM
6
Top View
A
B
C
D
SRAM DIE
C1
C
F
G
H
J
Elastomer
A
B
B1
Detail View
Side View
A
E2
D
E
E2
Y
E
Die
Die
E1
0.3/Tµp
Minimum
Typical
Maximum
A
–
0.75
–
B
5.90
8.00
8.10
B1
–
3.75
–
C
7.90
8.00
8.10
C1
–
5.25
–
D
–
0.35
–
E
–
–
1.20
E1
–
0.68
–
E2
0.22
0.25
0.27
Y
–
–
0.08
DID 11-20011-A. 5/22/00
Notes
1 Bump counts: 48 (8 row x 6 column).
2 Pitch: (x,y) = 0.75 mm x 0.75 mm (typ).
3 Units: millimeters.
4 All tolerance are +/- 0.050 unless otherwise
specified.
5 Typ: typical.
6 Y is coplanarity: 0.08 (max).
ALLIANCE SEMICONDUCTOR
9
AS7C1026
AS7C31026
®
Ordering codes
SRAM
Package \ Access time
Plastic SOJ, 400 mil
Volt/Temp
10 ns
12 ns
15 ns
20 ns
5V commercial
NA
AS7C1026-12JC
AS7C1026-15JC
AS7C1026-20JC
5V industrial
NA
AS7C1026-12JI
AS7C1026-15JI
AS7C1026-20JI
3.3V commercial AS7C31026-10JC AS7C31026-12JC AS7C31026-15JC AS7C31026-20JC
5V commercial
TSOP II, 18.4×10.2 mm
CSP BGA, 8×6 mm
NA
AS7C1026-12TC
AS7C1026-15TC
AS7C1026-20TC
3.3V commercial AS7C31026-10TC AS7C31026-12TC AS7C31026-15TC AS7C31026-20TC
3.3V industrial
NA
AS7C31026-12TI AS7C31026-15TI AS7C31026-20TI
5V commercial
NA
AS7C1026-12BC
AS7C1026-15BC
AS7C1026-20BC
3.3V commercial AS7C31026-10BC AS7C31026-12BC AS7C31026-15BC AS7C31026-20BC
3.3V industrial
NA
AS7C31026-12BI AS7C31026-15BI AS7C31026-20BI
NA: not available.
Part numbering system
AS7C
X
SRAM
prefix
Blank=5V CMOS
3=3.3V CMOS
10
1026
–XX
Device Access
number time
X
C
Package: J=SOJ 400 mil
T=TSOP type 2, 18.4 × 10.2 mm
B=CSP BGA, 8 × 6 mm
Temperature range,
C=Commercial: 0° C to 70° C
I=Industrial: -40° C to 85° C
ALLIANCE SEMICONDUCTOR
DID 11-20011-A. 5/22/00