Maxim DS1341 Low-current i2c rtcs for high-esr crystal Datasheet

19-4998; Rev 1; 12/10
Low-Current I2C RTCs for High-ESR Crystals
The DS1341/DS1342 low-current real-time clocks (RTCs)
are timekeeping devices that provide an extremely low
standby current, which permits longer life from a power
supply. The DS1341/DS1342 support high-ESR crystals,
which broaden the pool of usable crystals for the devices.
The DS1341 uses a 6pF crystal, while the DS1342 uses a
12.5pF crystal. These devices are accessed through an
I2C serial interface. Other features include two time-of-day
alarms, two interrupt outputs, a programmable squarewave output, and a serial bus timeout mechanism.
Features
S Low Timekeeping Current of 250nA (typ)
S Compatible with Crystal ESR Up to 100kI
S Use Crystals with CL = 6pF (DS1341) or
CL = 12.5pF (DS1342)
S +1.8V to +5.5V Operating Voltage Range
S Maintain Time Down to +1.15V (typ)
S Fast (400kHz) I2C Interface
S Bus Timeout for Lockup-Free Operation
The clock/calendar provides seconds, minutes, hours,
day, date, month, and year information. The date at the
end of the month is automatically adjusted for months
with fewer than 31 days, including corrections for leap
year. The clock operates in either 24hr or 12hr format
with an AM/PM indicator.
S RTC Counts Seconds, Minutes, Hours, Day, Date,
The DS1341/DS1342 also include an input for synchronization. When a reference clock (e.g., 60Hz power line or
GPS 1PPS) is present at the CLKIN pin and the enable
external clock input bit (ECLK) is set to 1, the DS1341/
DS1342 RTCs are frequency-locked to the external clock
and the clock accuracy is determined by the external
source. In case of external clock failure, the clock is
switched to the crystal oscillator.
S Two Time-of-Day Alarms with Two Interrupt
The devices are available in lead(Pb)-free/RoHScompliant, 8-pin FSOP or TDFN packages. The devices
support a -40NC to +85NC extended temperature range.
Ordering Information
PART
TEMP RANGE
PINPACKAGE
DS1341U+
-40NC to +85NC
8 FSOP
6
DS1341U+T&R
-40NC to +85NC
8 FSOP
6
DS1341T+*
-40NC to +85NC
8 TDFN-EP**
6
DS1341T+T&R*
-40NC to +85NC
8 TDFN-EP**
6
DS1342U+
-40NC to +85NC
8 FSOP
12.5
DS1342U+T&R
-40NC to +85NC
8 FSOP
12.5
DS1342T+*
-40NC to +85NC
8 TDFN-EP**
12.5
DS1342T+T&R*
-40NC to +85NC
8 TDFN-EP**
12.5
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*Future product—contact factory for availability.
**EP = Exposed pad.
OSC
CL (pF)
Month, and Year with Leap Year Compensation
Valid Through 2099
S External Clock Source for Synchronization Clock
Reference (e.g., 32kHz, 50Hz/60Hz Power Line,
GPS 1PPS)
Outputs
S Programmable Square-Wave Output
S Industrial Temperature Range
S Small, 8-Pin µSOP or TDFN Packages
Applications
Medical
Portable Instruments
Point of Sale (POS)
Portable Audio
Telematics
Automotive
Typical Operating Circuit
VCC
VCC
RPU
RPU
RPU
SCL
VCC
X1
SDA
CLKIN/INTA
CPU
SQW/INTB
X2
DS1341/DS1342
GND
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642,
or visit Maxim’s website at www.maxim-ic.com.
DS1341/DS1342
General Description
DS1341/DS1342
Low-Current I2C RTCs for High-ESR Crystals
ABSOLUTE MAXIMUM RATINGS
Voltage Range on Any Pin Relative to Ground.....-0.3V to +6.0V
Operating Temperature Range........................... -40NC to +85NC
Junction Temperature Maximum......................................+150NC
Storage Temperature Range............................. -55NC to +125NC
Lead Temperature (soldering, 10s).................................+260NC
Soldering Temperature (reflow).......................................+260NC
PACKAGE THERMAL CHARACTERISTICS (Note 1)
FSOP
Junction-to-Ambient Thermal Resistance (BJA)......206.3NC/W
Junction-to-Case Thermal Resistance (BJC)................42NC/W
TDFN
Junction-to-Ambient Thermal Resistance (BJA)...........41NC/W
Junction-to-Case Thermal Resistance (BJC)..................8NC/W
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a fourlayer board. For detailed information on package thermal considerations, refer to www.maxim-ic.com/thermal-tutorial.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
DC ELECTRICAL CHARACTERISTICS
(VCC = +1.8V to +5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Note 2)
PARAMETER
Operating Voltage Range
Minimum Timekeeping Voltage
Timekeeping Current: DS1341
CLKIN = GND or CLKIN = VCC
(Note 4)
SYMBOL
CONDITIONS
MIN
TYP
MAX
VCC
Full operation (Note 3)
1.8
5.5
VCCT
Timekeeping (Notes 3, 4)
1.3
5.5
VCCTMIN
TA = +25NC (Notes 3, 4)
1.15
1.3
VCC = +3.0V, EGFIL = 0, DOSF = 1
220
500
VCC = +5.5V
250
600
VCC = +3.0V, EGFIL = 1, DOSF = 0
280
560
VCC = +5.5V
320
700
VCC = +3.0V, EGFIL = 0, DOSF = 1
250
600
VCC = +5.5V
280
700
VCC = +3.0V, EGFIL = 1, DOSF = 0
310
660
VCC = +5.5V
350
800
ICCT
UNITS
V
V
nA
Timekeeping Current: DS1342
CLKIN = GND or CLKIN = VCC
(Note 4)
ICCT
Logic 1 Input
VIH
(Note 2)
0.7 x
VCC
VCC +
0.3
V
Logic 0 Input
VIL
(Note 2)
-0.3
0.3 x
VCC
V
Input Leakage
(SCL, CLKIN/INTA)
ILI
ECLK = 1, VIN = 0V to VCC
-0.1
+0.1
FA
Output Leakage
(CLKIN/INTA, SQW/INTB)
IO
ECLK = A1IE = A2IE = 0
-1.0
+1.0
FA
Output Logic 1
VOH = +1.0V (SQW /INTB)
IOH
VCC R 1.8V, INTCN = 0
-3.0
mA
VCC R 1.3V, INTCN = 0
-250
FA
Output Logic 0
VOL = +0.4V (SDA, CLKIN/INTA,
SQW/INTB)
IOL
VCC R 1.8V
3.0
mA
VCC R 1.3V (Note 5)
250
FA
2
nA
Low-Current I2C RTCs for High-ESR Crystals
DS1341/DS1342
AC ELECTRICAL CHARACTERISTICS
(VCC = +1.8V to +5.5V, TA = -40NC to +85NC, unless otherwise noted.) (Note 2, Figure 1)
PARAMETER
SYMBOL
SCL Clock Frequency
fSCL
Bus Free Time Between a STOP
and START Condition
tBUF
Hold Time (Repeated) START
Condition
tHD:STA
CONDITIONS
MIN
TYP
(Note 6)
(Note 7)
0.6
Fs
Fs
tLOW
1.3
tHIGH
0.6
(Notes 8, 9)
Data Setup Time
tSU:DAT
(Note 10)
Setup Time for a Repeated
START Condition
tSU:STA
kHz
Fs
High Period of SCL Clock
tHD:DAT
UNITS
400
1.3
Low Period of SCL Clock
Data Hold Time
MAX
Fs
0
0.9
Fs
100
ns
0.6
Fs
Rise Time of Both SDA and SCL
Signals
tR
(Note 11)
20 +
0.1CB
300
ns
Fall Time for Both SDA and SCL
Signals
tF
(Note 11)
20 +
0.1CB
300
ns
Setup Time for STOP Condition
tSU:STO
Capacitive Load for Each Bus
Line
CB
I/O Capacitance
CI/O
10
pF
SCL Spike Suppression
tSP
30
ns
Oscillator Stop Flag (OSF) Delay
Timeout Interval
0.6
Fs
(Note 11)
tOSF
(Note 12)
tTIMEOUT
(Note 13)
400
25
25
pF
100
ms
35
ms
MAX
UNITS
CRYSTAL PARAMETERS
PARAMETER
Nominal Frequency
Series Resistance
Load Capacitance
Note
Note
Note
Note
Note
Note
Note
Note
Note
SYMBOL
CONDITIONS
fO
MIN
TYP
32.768
ESR
CL
kHz
100
DS1341
6
DS1342
12.5
kI
pF
Limits at -40NC are guaranteed by design; not production tested.
Voltage referenced to ground.
Specified with I2C bus inactive. Oscillator operational, INTCN = 1, ECLK = 0.
Applies to CLKIN/INTA and SQW/INTB only.
The minimum SCL clock frequency is limited by the bus timeout feature, which resets the serial bus interface if SCL is
held low for tTIMEOUT.
7: After this period, the first clock pulse is generated.
8: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to the VIHMIN of the SCL signal) to bridge the undefined region of the falling edge of SCL.
9: The maximum tHD:DAT need only be met if the device does not stretch the low period (tLOW) of the SCL signal.
10: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT R to 250ns must then be
met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does
stretch the low period of the SCL signal, it must output the next data bit to the SDA line tRMAX + tSU:DAT = 1000 + 250 =
1250ns before the SCL line is released.
2:
3:
4:
5:
6:
3
DS1341/DS1342
Low-Current I2C RTCs for High-ESR Crystals
Note 11: CB is the total capacitance of one bus line, including all connected devices, in pF.
Note 12: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the voltage
range of 2.4V P VCC P VCCMAX.
Note 13: The DS1341/DS1342 can detect any single SCL clock held low longer than tTIMEOUTMIN. The devices’ I2C interface is
in reset state and can receive a new START condition when SCL is held low for at least tTIMEOUTMAX. Once the device
detects this condition, the SDA output is released. The oscillator must be running for this function to work.
SDA
tBUF
tF
tLOW
tSP
tHD:STA
SCL
tHD:STA
tHIGH
tR
tSU:STA
tHD:DAT
STOP
tSU:STO
tSU:DAT
START
REPEATED
START
NOTE: TIMING IS REFERENCED TO VILMAX AND VIHMIN.
Figure 1. Data Transfer on I2C Serial Bus
Functional Diagram
VCC
DS1341/DS1342
32.768kHz
P
8.192kHz
4.096kHz
X1
/4
/2
/32
128Hz
EXTSYNC
OSC-1Hz
MUX/
BUFFER
SQW/INTB
N
EXT-1Hz
DIVIDER
X2
CLKIN/INTA
CONTROL LOGIC
SCL
SDA
N
SERIAL BUS
INTERFACE AND
ADDRESS
REGISTER
ALARM AND
CONTROL REGISTERS
OSC-1Hz
4
CLOCK AND
CALENDAR REGISTERS
N
Low-Current I2C RTCs for High-ESR Crystals
CLKIN = GND, IOUT = 0mA
350
300
+85°C
+25°C
250
CLKIN = GND, IOUT = 0mA
500
SUPPLY CURRENT (nA)
400
SUPPLY CURRENT (nA)
550
DS1341/2 toc01
450
DS1341 ICCT SUPPLY CURRENT vs. SUPPLY VOLTAGE
(EGFIL = 1, DOSF = 0)
200
150
450
+85°C
400
350
+25°C
300
250
-40°C
100
2
1
3
-40°C
200
4
5
2
1
4
5
DS1342 ICCT SUPPLY CURRENT vs. SUPPLY VOLTAGE
(EGFIL = 0, DOSF = 1)
DS1342 ICCT SUPPLY CURRENT vs. SUPPLY VOLTAGE
(EGFIL = 1, DOSF = 0)
400
+85°C
+25°C
300
250
200
150
450
400
+25°C
+85°C
350
300
250
-40°C
100
-40°C
200
1
2
3
4
5
2
1
SUPPLY VOLTAGE (V)
0.5
DS1341/2 toc05
1.4
1.2
0.3
0.2
0.1
1.0
5
POWER-SUPPLY CURRENT
vs. SCL FREQUENCY
80
TA = +25°C, IOUT = 0mA
70
SUPPLY CURRENT (µA)
1.6
VCC = +1.8V, TA = +25°C
0.4
OUTPUT VOLTAGE (V)
1.8
4
SQW/INTB OUTPUT-VOLTAGE LOW
vs. OUTPUT CURRENT
DS1341/2 toc06
SQW/INTB OUTPUT-VOLTAGE HIGH
vs. OUTPUT CURRENT
VCC = +1.8V, TA = +25°C
3
SUPPLY VOLTAGE (V)
DS1341/2 toc07
350
CLKIN = GND, IOUT = 0mA
500
SUPPLY CURRENT (nA)
SUPPLY CURRENT (nA)
550
DS1341/2 toc03
CLKIN = GND, IOUT = 0mA
DS1341/2 toc04
SUPPLY VOLTAGE (V)
450
OUTPUT VOLTAGE (V)
3
SUPPLY VOLTAGE (V)
500
2.0
DS1341/2 toc02
DS1341 ICCT SUPPLY CURRENT vs. SUPPLY VOLTAGE
(EGFIL = 0, DOSF = 1)
60
50
6.0V
40
3.0V
30
5.0V
20
10
0.8
-10
-8
-6
-4
OUTPUT CURRENT (mA)
-2
0
1.8V
0
0
0
2
4
6
OUTPUT CURRENT (mA)
8
10
0
100
200
300
400
SCL FREQUENCY (kHz)
5
DS1341/DS1342
Typical Operating Characteristics
(TA = +25°C, unless otherwise noted.)
Low-Current I2C RTCs for High-ESR Crystals
2
CLKIN/INTA
3
GND
4
DS1341
DS1342
µSOP
8
VCC
7
SQW/INTB
6
SCL
5
SDA
SQW/
INTB
SCL
SDA
6
5
DS1341
DS1342
EP
+
1
2
3
4
GND
X2
+
7
CLKIN/
INTA
1
8
X2
X1
VCC
TOP VIEW
X1
DS1341/DS1342
Pin Configurations
TDFN
Pin Description
6
PIN
NAME
FUNCTION
1
X1
2
X2
Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is
designed for operation with a crystal having a specified load capacitance (CL) of 6pF (DS1341)
or 12.5pF (DS1342).
3
CLKIN/INTA
4
GND
Ground
5
SDA
Serial-Data Input/Output. SDA is the input/output pin for the I2C serial interface. The SDA pin is
open drain and requires an external pullup resistor.
6
SCL
Serial-Clock Input. SCL is used to synchronize data movement on the serial interface.
7
SQW/INTB
8
VCC
—
EP
Clock Input/Active-Low Interrupt Output. This I/O pin is used to output an alarm interrupt or
accept an external clock input to drive the RTC counter. In the output mode, this is an open
drain and requires an external pullup resistor. If not used, connect this pin to ground.
Square-Wave/Active-Low Interrupt Output. This pin is used to output a programmable square
wave or an alarm interrupt signal. This is a CMOS push-pull output and does not require an
external pullup resistor. If not used, this pin can be left unconnected.
DC Power Input. This pin should be decoupled using a 0.01FF or 0.1FF capacitor.
Exposed Pad (TDFN Only). Connect to GND or leave unconnected.
Low-Current I2C RTCs for High-ESR Crystals
The DS1341/DS1342 low-current RTCs are timekeeping
devices that consume an extremely low timekeeping current, which permits longer life from a power supply. The
clock/calendar provides seconds, minutes, hours, day,
date, month, and year information. The date at the end of
the month is automatically adjusted for months with fewer
than 31 days, including corrections for leap year through
2099. The clock operates in either a 24hr or 12hr format
with an AM/PM indicator.
The DS1341/DS1342 use an external 32.768kHz crystal. The oscillator circuit does not require any external
resistors or capacitors to operate. The devices support
a high-ESR crystal, which broadens the pool of usable
crystals for the device. The DS1342 uses a 12.5pF crystal. The DS1341 uses a 6pF crystal, which decreases
oscillator current draw, but is less commonly available
than the 12.5pF crystals.
The DS1341/DS1342 also accept an external clock
reference for synchronization. The external clock can
be a 32.768kHz, 50Hz, 60Hz, or 1Hz source. When the
enable oscillator bit (EOSC) is a 0, the DS1341/DS1342
use the oscillator for timekeeping. If the enable external
clock input bit (ECLK) is set to 1, the time base derived
from the oscillator is compared to the 1Hz signal that is
derived from the CLKIN signal. The conditioned signal
drives the RTC time and date counters. If the oscillator
is disabled and the CLKIN signal is absent, the time and
date values remain static, provided that VCC remains at
a valid level.
When the external clock is lost or when the frequency
differs more than Q0.8% from the crystal frequency, the
signal derived from the crystal oscillator drives the RTC
counter.
Oscillator Circuit
The DS1341/DS1342 use an external 32.768kHz crystal. The oscillator circuit does not require any external
resistors or capacitors to operate. The DS1341 includes
integrated capacitive loading for a 6pF CL crystal, and
the DS1342 includes integrated capacitive loading for a
12.5pF CL crystal. See the Crystal Parameters table for
the external crystal parameters. The Functional Diagram
shows a simplified schematic of the oscillator circuit. The
startup time is usually less than 1 second when using a
crystal with the specified characteristics.
Clock Accuracy
When running from the internal oscillator, the accuracy of
the clock is dependent upon the accuracy of the crystal
and the accuracy of the match between the capacitive
load of the oscillator circuit and the capacitive load for
which the crystal was trimmed. Additional error is added
by crystal frequency drift caused by temperature shifts.
External circuit noise coupled into the oscillator circuit
can result in the clock running fast. Figure 2 shows a
typical PCB layout for isolation of the crystal and oscillator from noise. Refer to Application Note 58: Crystal
Considerations with Dallas Real-Time Clocks for detailed
information.
LOCAL GROUND PLANE (LAYER 2)
X1
CRYSTAL
X2
When ECLK is set to 0, the RTC counter is always driven
with the signal derived from the crystal oscillator. When
the EOSC bit is a 1 and the external clock source is
selected, the RTC counter is always clocked by the signal from the CLKIN pin.
Address and data are transferred serially through an I2C
serial interface. Other features include two time-of-day
alarms, two interrupts, a programmable square-wave
output, and a bus timeout mechanism that resets the I2C
bus if it remains inactive for a minimum of tTIMEOUT.
Both devices are available in lead(Pb)-free/RoHScompliant, 8-pin FSOP or TDFN packages, and support
the -40NC to +85NC extended temperature range.
GND
NOTE: AVOID ROUTING SIGNALS IN THE CROSSHATCHED AREA (UPPER LEFT-HAND
QUADRANT) OF THE PACKAGE UNLESS THERE IS A GROUND PLANE BETWEEN THE
SIGNAL LINE AND THE PACKAGE.
Figure 2. Layout Example
7
DS1341/DS1342
Detailed Description
DS1341/DS1342
Low-Current I2C RTCs for High-ESR Crystals
External Synchronization
When an external clock reference is used, the input
from CLKIN/INTA is divided down to 1Hz by the divisor selected by the CLKSEL[2:1] bits. The 1Hz from the
divider (Ext-1Hz, see the Functional Diagram) is used to
correct the 1Hz that is derived from the 32.768kHz oscillator (Osc-1Hz). As Osc-1Hz drifts in relation to Ext-1Hz,
Osc-1Hz is digitally adjusted.
As shown in the Functional Diagram, the three highest
frequencies driving the SQW/INTB pin are derived from
the uncorrected oscillator, while the 1Hz output is derived
from the adjusted Osc-1Hz signal.
Conceptually, the circuit can be thought of as two 1Hz
signals, one derived from the internal oscillator and the
other derived from the external reference clock, with the
oscillator-derived 1Hz signal being locked to the 1Hz signal derived from the external reference clock. The edges
of the 1Hz signals do not need to be aligned with each
other. While the external clock source is present and
within tolerance, the Ext-1Hz and Osc-1Hz maintain their
existing lock, regardless of their edge alignment, with
periodic correction of the Osc‑1Hz signal. If the external
signal is lost and then regained sometime later, the signals relock with whatever new alignment exists (Figure 3).
The Ext-1Hz is used by the device as long as it is within
tolerance, which is about 0.8% of Osc-1Hz. While Ext1Hz is within tolerance, the skew between the two signals could shift until a change of approximately 7.8ms
accumulates, after which the Osc-1Hz signal is adjusted
(Figure 4). The adjustment is accomplished by digitally
adjusting the 32kHz oscillator divider chain.
If the difference between Ext-1Hz and Osc-1Hz is greater
than approximately 0.8%, Osc-1Hz runs unadjusted (see
Figure 3) and the loss of signal (LOS) is set, provided
OSC-1Hz
FROM OSCILLATOR
SKEW
SKEW
EXT-1Hz
FROM EXTERNAL REFERENCE
BREAK IN EXTERNAL REFERENCE SIGNAL
Figure 3. Loss and Reacquisition of External Reference Clock
OSC-1Hz
FROM OSCILLATOR
CURRENT LOCK
DRIFT AFTER N CYCLES
EXT-1Hz
FROM EXTERNAL REFERENCE
Figure 4. Drift and Adjustment of Internal 1Hz to External Reference Clock
8
SHIFTED BACK TO CURRENT LOCK
Low-Current I2C RTCs for High-ESR Crystals
Register Map
Table 1 shows the map for the DS1341/DS1342 registers. During a multibyte access, if the address pointer
reaches the end of the register space (0Fh), it wraps
around to location 00h. On either an I2C START or
address pointer incrementing to location 00h, the current
time is transferred to a second set of registers. The time
information is read from these secondary registers while
the clock continues to run. This eliminates the need to
reread the registers in case the main registers update
during a read.
I2C Interface
The I2C interface is guaranteed to operate when VCC is
between 1.8V and 5.5V and the EOSC bit is 0. The I2C
interface is accessible whenever VCC is at a valid level.
To prevent invalid device operation, the I2C interface
should not be accessed when VCC is below +1.8V.
If a microcontroller connected to the DS1341/DS1342
resets during I2C communications, it is possible that the
microcontroller and the DS1341/DS1342 could become
unsynchronized. When the microcontroller resets, the
DS1341/DS1342 I2C interface can be placed into a
known state by holding SCL low for tTIMEOUT. Doing so
limits the minimum frequency at which the I2C interface
can be operated. If data is being written to the device
Table 1. Register Map
ADDRESS
BIT 7
FUNCTION
RANGE
00h
0
10 Seconds
Seconds
Seconds
00–59
01h
0
10 Minutes
Minutes
Minutes
00–59
02h
0
12/24
AM/PM
10hr
10hr
Hours
1–12+AM/PM
00–23
03h
0
0
0
0
Day
1–7
04h
0
0
Date
Date
01–31
Month
Month/
Century
01–12 + Century
Year
Year
00–99
05h
CENT
BIT 6
BIT 5
BIT 3
0
BIT 2
BIT 1
BIT 0
Hour
0
10 Date
0
06h
BIT 4
10 MO
10 Year
Day
07h
A1M1
10 Seconds
Seconds
Alarm 1
Seconds
00–59
08h
A1M2
10 Minutes
Minutes
Alarm 1
Minutes
00–59
09h
A1M3
12/24
Hour
Alarm 1
Hours
1–12 + AM/PM
00–23
0Ah
A1M4
DY/DT
Day,
Date
Alarm 1 Day,
Alarm 1 Date
1–7
1–31
0Bh
A2M2
Minutes
Alarm 2
Minutes
00–59
0Ch
A2M3
12/24
Hour
Alarm 2
Hours
1–12 + AM/PM
00–23
0Dh
A2M4
DY/DT
Day,
Date
Alarm 2 Day,
Alarm 2 Date
1–7
1–31
0Eh
EOSC
0
A1IE
Control
—
A1F
Control/
Status
—
0Fh
OSF
AM/PM
10hr
10hr
10 Date
10 Minutes
DOSF
AM/PM
10hr
10hr
10 Date
EGFIL
LOS
RS2
RS1
CLKSEL2 CLKSEL1
INTCN
ECLK
A2IE
A2F
Note: Bits listed as 0 always read back as 0 and cannot be written to a 1.
9
DS1341/DS1342
the ECLK bit is set. The external clock reference must be
within the defined frequency tolerance prior to initializing
the LOS flag.
DS1341/DS1342
Low-Current I2C RTCs for High-ESR Crystals
when the interface timeout is exceeded, prior to the
acknowledge, the incomplete byte of data is not written.
Clock and Calendar (00h–06h)
The time and calendar information is obtained by reading the appropriate register bytes. The RTC registers are
illustrated in Table 1. The time and calendar are set or
initialized by writing the appropriate register bytes. The
contents of the time and calendar registers are in the
binary-coded decimal (BCD) format. The Day register
increments at midnight and rolls over from 7 to 1. Values
that correspond to the day-of-week are user-defined
but must be sequential (i.e., if 1 equals Sunday, then 2
equals Monday, and so on). The CENT bit in the Month
register toggles when the Years register rolls over from
99 to 00. Illogical time and date entries result in an undefined operation.
The DS1341/DS1342 can be run in either 12hr or 24hr
mode. Bit 6 of the Hours register is defined as the 12hr
or 24hr mode select bit. When high, the 12hr mode is
selected. In the 12hr mode, bit 5 is the AM/PM bit, with
a content of 1 being PM. In the 24hr mode, bit 5 is the
second bit of the 10hr field. The century bit (bit 7 of the
Month register) is toggled when the Years register increments from 99 to 00. On a power-on reset (POR), the
time and date are set to 00:00:00 00/01/01 and the Day
register is set to 01.
Alarms (07h–0Dh)
The DS1341/DS1342 contain two time-of-day/date
alarms. Alarm 1 can be set by writing to registers 07h–
0Ah. Alarm 2 can be set by writing to registers 0Bh–0Dh.
The alarms can be programmed to activate the CLKIN/
INTA or SQW/INTB outputs (see Table 5) on an alarm
match condition. Bit 7 of each of the time of day/date
alarm registers are mask bits. When all the mask bits for
each alarm are 0, an alarm only occurs when the values
in the timekeeping registers 00h–06h match the values
stored in the time of day/date alarm registers. The alarms
can also be programmed to repeat every second, minute, hour, day, or date. Tables 2 and 3 show the possible
alarm settings. Configurations not listed in the tables
result in illogical operation. POR values are undefined.
The DY/DT bits (bit 6 of the alarm day/date registers)
control whether the alarm value stored in bits 0 to 5 of
that register reflects the day of the week or the date of
the month. If DY/DT is written to 0, the alarm is the result
of a match with date of the month. If DY/DT is written to
1, the alarm is the result of a match with day of the week.
Table 2. Alarm 1 Mask Bits
DY/DT
ALARM 1 MASK BITS (BIT 7)
ALARM RATE
A1M4
A1M3
A1M2
A1M1
X
1
1
1
1
Alarm once per second.
X
1
1
1
0
Alarm when seconds match.
X
1
1
0
0
Alarm when minutes and seconds match.
X
1
0
0
0
Alarm when hours, minutes, and seconds match.
0
0
0
0
0
Alarm when date, hours, minutes, and seconds match.
1
0
0
0
0
Alarm when day, hours, minutes, and seconds match.
X = Don’t care.
Table 3. Alarm 2 Mask Bits
DY/DT
ALARM RATE
A2M3
A2M2
X
1
1
1
Alarm once per minute (00 second of every minute).
X
1
1
0
Alarm when minutes match.
X
1
0
0
Alarm when hours and minutes match.
0
0
0
0
Alarm when date, hours, and minutes match.
1
0
0
0
Alarm when day, hours, and minutes match.
X = Don’t care.
10
ALARM 2 MASK BITS (BIT 7)
A2M4
Low-Current I2C RTCs for High-ESR Crystals
Control Register (0Eh)
Bit 7: Enable Oscillator (EOSC). When the EOSC bit
is 0, the oscillator is enabled. When this bit is a 1, the
oscillator is disabled. This bit is cleared (0) when power
is first applied.
Bit 6: No Function
Bit 5: Enable Glitch Filter (EGFIL). When the EGFIL bit
is 1, the 5Fs glitch filter at the output of the crystal oscillator is enabled. The glitch filter is disabled when this bit
is 0. Disabling the glitch filter is useful in reducing power
consumption. This bit is cleared (0) when power is first
applied.
Bits 4 and 3: Rate Select (RS[2:1]). These bits control the frequency of the square-wave output when the
square wave has been enabled. Table 4 shows the
square-wave frequencies that can be selected with the
RS bits. These bits are both set to 1 (32.768kHz) when
power is first applied.
The 32.768kHz oscillator is the source of all square-wave
output frequencies. Frequencies above 1Hz are not conditioned by CLKIN. The 1Hz output is the 32.768kHz oscillator frequency, divided down to 1Hz and conditioned by
CLKIN, provided that the CLKIN frequency differs by no
more than Q0.8% from the crystal frequency. Cycle-tocycle jitter of the 1Hz square wave can be up to 2ms.
Bit 2: Interrupt Control (INTCN). This bit controls the
relationship between the two alarms and the interrupt
output pins. When the INTCN bit is 0, a square wave is
output on the SQW/INTB pin, and the state of the ECLK
bit determines the function of the CLKIN/INTA pin (see
Table 5). When the INTCN bit is 1 and the ECLK bit is a
0, a match between the timekeeping registers and the
alarm 1 registers activates the CLKIN/INTA pin (provided
that the alarm is enabled) and a match between the
timekeeping registers and the alarm 2 registers activates
the SQW/INTB pin (provided that the alarm is enabled).
When the INTCN bit is 1 and the ECLK bit is a 1, a match
between the timekeeping registers and the alarm 1
registers or a match between the timekeeping registers
and the alarm 2 registers activates the SQW/INTB pin
(provided that the alarm is enabled). This bit is cleared
(0) when power is first applied.
Bit 1: Alarm 2 Interrupt Enable (A2IE). When the A2IE
bit is 0, the alarm 2 interrupt function is disabled. When
the A2IE bit is 1, the alarm 2 interrupt function is enabled
and is routed to an output, based upon the steering
defined by the INTCN and ECLK bits, as noted in Table
5. Regardless of the state of A2IE, a match between
the timekeeping registers and the alarm 2 registers
(0Bh–0Dh) sets the alarm 2 flag bit (A2F). This bit is
cleared (0) when power is first applied.
Bit 0: Alarm 1 Interrupt Enable (A1IE). When the A1IE
bit is 0, the alarm 1 interrupt function is disabled. When
the A1IE bit is 1, the alarm 1 interrupt function is enabled
and is routed to an output, based upon the steering
defined by the INTCN and ECLK bits, as noted in Table
5. Regardless of the state of A1IE, a match between the
timekeeping registers and the alarm 1 registers (07h–
0Ah) sets the alarm 1 flag bit (A1F). This bit is cleared (0)
when power is first applied.
Control Register Bitmap (0Eh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
EOSC
0
0
EGFIL
RS2
RS1
INTCN
A2IE
A1IE
0
0
1
1
0
0
0
Table 4. SQW/INTB Output Settings
RS2
RS1
0
0
1
1
0
1
0
1
SQW/INTB
1Hz
4.098kHz
8.192kHz
32.768kHz
Table 5. Interrupt Output Routing
INTCN
ECLK
0
0
1
1
0
1
0
1
CLKIN/INTA
A1F + A2F
CLKIN Input
A1F
CLKIN Input
SQW/INTB
SQW
SQW
A2F
A1F + A2F
11
DS1341/DS1342
When the RTC register values match alarm register settings, the corresponding alarm flag bit (A1F or A2F) is
set to 1 in the Control/Status register. If the corresponding alarm interrupt enable bit (A1IE or A2IE) is also set
to 1 in the Control register, the alarm condition activates
the output(s) defined by the ECLK and INTCN bits (see
Table 5).
DS1341/DS1342
Low-Current I2C RTCs for High-ESR Crystals
Control/Status Register Bitmap (0Fh)
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
OSF
DOSF
LOS
CLKSEL2
CLKSEL1
ECLK
A2F
A1F
1
0
1
0
0
0
X
X
Control/Status Register (0Fh)
Bit 7: Oscillator Stop Flag (OSF). If the OSF bit is a 1,
that indicates the oscillator has stopped or was stopped
for some period of time, and could be used to judge
the validity of the clock and calendar data. This bit is
edge triggered and is set to 1 when the internal circuitry
senses the oscillator has transitioned from a normal run
state to a STOP condition. The following are examples of
conditions that can cause the OSF bit to be set:
1) Power is applied for the first time.
2) T
he voltage present on VCC is insufficient to support
oscillation.
3) The EOSC bit is turned off.
4) T
here are external influences on the crystal (e.g.,
noise, leakage, etc.).
This bit remains at 1 until written to 0. Attempting to write
OSF to 1 leaves the value unchanged.
Bit 6: Disable Oscillator Stop Flag (DOSF). This bit,
when set to 1, disables the sensing of the oscillator
conditions that would set the OSF bit. OSF remains
at 0 regardless of what happens to the oscillator.
This bit is cleared (0) when power is first applied.
Disabling the oscillator sensing is useful in reducing
power consumption.
Bit 5: Loss of Signal (LOS). This status bit indicates the
state of the CLKIN pin. The bit is set to 1 when the RTC
counter is no longer conditioned by the external clock.
This happens when ECLK = 0, or when the clock signal
at CLKIN stops toggling, or when the CLKIN frequency
differs more than Q0.8% from the selected input frequency. This bit remains at 1 until written to 0. Attempting
to write LOS to 1 leaves the value unchanged. Clearing
the LOS flag when the CLKIN frequency is invalid inhibits
subsequent detections of the input frequency deviation.
Bits 4 and 3: Select Clock Source (CLKSEL[2:1]).
These two register bits select the clock source to drive
the RTC counter. Table 6 lists the input frequencies that
can be selected. Upon power-up, the bits are cleared to
0 and the 1Hz rate is selected.
12
Table 6. Input Frequency Options
CLKSEL2
CLKSEL1
0
0
1
1
0
1
0
1
CLKIN/INTA
1Hz Input
50Hz Input
60Hz Input
32.768kHz Input
Bit 2: Enable External Clock Input (ECLK). This bit
controls the direction of the CLKIN/INTA pin (see Table
5). When the ECLK bit is 1, the CLKIN/INTA pin is an
input, with the expected input rate defined by the state
of CLKSEL2 and CLKSEL1 (see Table 6).
When the ECLK bit is 0, the CLKIN/INTA pin is an
interrupt output (see Table 5). If the INTCN bit is 0,
CLKIN/INTA contains the status of A1F (provided that
the A1IE bit is 1) or A2F (provided that the A2IE bit is 1).
If the INTCN bit is 1, CLKIN/INTA contains the status of
A1F (provided that the A1IE bit is 1).
This bit is set to 0 when power is first applied.
Bit 1: Alarm 2 Flag (A2F). A 1 in the alarm 2 flag bit
indicates that the time matched the alarm 2 registers.
This flag can be used to generate an interrupt on either
CLKIN/INTA or SQW/INTB depending on the status of
the INTCN bit in the Control register. If the INTCN bit is
set to 0 and A2F bit is a 1 (and A2IE bit is also 1), the
CLKIN/INTA pin goes low. If the INTCN bit is set to 1 and
A2F bit is 1 (and A2IE bit is also 1), the SQW/INTB pin
goes low. The A2F bit is cleared when written to 0. This
bit can only be written to 0. Attempting to write this bit to
1 leaves the value unchanged.
Bit 0: Alarm 1 Flag (A1F). A 1 in the alarm 1 flag bit
indicates that the time matched the alarm 1 registers. If
the A1IE bit is also 1, the CLKIN/INTA pin goes low. A1F
is cleared when written to 0. This bit can only be written
to 0. Attempting to write this bit to 1 leaves the value
unchanged.
Low-Current I2C RTCs for High-ESR Crystals
I2C Slave Address
The DS1341/DS1342s’ slave address byte is D0h. The
first byte sent to the device includes the device identifier
and the R/W bit (Figure 5). The device address sent by
the I2C master must match the address assigned to the
device.
I2C Definitions
The following terminology is commonly used to describe
I2C data transfers.
Master Device: The master device controls the slave
devices on the bus. The master device generates
SCL clock pulses and START and STOP conditions.
Slave Devices: Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy: Time between STOP and
START conditions when both SDA and SCL are
inactive and in their logic-high states. When the bus
is idle, it often initiates a low-power mode for slave
devices.
START Condition: A START condition is generated
by the master to initiate a new data transfer with a
slave. Transitioning SDA from high to low while SCL
remains high generates a START condition. See
Figure 1 for applicable timing.
STOP Condition: A STOP condition is generated
by the master to end a data transfer with a slave.
Transitioning SDA from low to high while SCL remains
high generates a STOP condition. See Figure 1 for
applicable timing.
Repeated START Condition: The master can use
a repeated START condition at the end of one data
transfer to indicate that it immediately initiates a new
data transfer following the current one. Repeated
STARTs are commonly used during read operations
to identify a specific memory address to begin a data
transfer. A repeated START condition is issued identically to a normal START condition. See Figure 1 for
applicable timing.
LSB
MSB
1
1
0
1
DEVICE
IDENTIFIER
Figure 5. Slave Address Byte
0
0
0
R/W
READ/
WRITE BIT
Bit Write: Transitions of SDA must occur during
the low state of SCL. The data on SDA must remain
valid and unchanged during the entire high pulse of
SCL plus the setup and hold time requirements (see
Figure 1). Data is shifted into the device during the
rising edge of the SCL.
Bit Read: At the end of a write operation, the master
must release the SDA bus line for the proper amount
of setup time (see Figure 1) before the next rising
edge of SCL during a bit read. The device shifts out
each bit of data on SDA at the falling edge of the
previous SCL pulse and the data bit is valid at the
rising edge of the current SCL pulse. Remember that
the master generates all SCL clock pulses including
when it is reading bits from the slave.
Acknowledge (ACK and NACK): An acknowledge
(ACK) or not acknowledge (NACK) is always the
ninth bit transmitted during a byte transfer. The
device receiving data (the master during a read or
the slave during a write operation) performs an ACK
by transmitting a 0 during the ninth bit. A device performs a NACK by transmitting a 1 during the ninth bit.
Timing for the ACK and NACK is identical to all other
bit writes. An ACK is the acknowledgment that the
device is properly receiving data. A NACK is used to
terminate a read sequence or as an indication that the
device is not receiving data.
Byte Write: A byte write consists of 8 bits of information transferred from the master to the slave (most
significant bit first) plus a 1-bit acknowledgment from
the slave to the master. The 8 bits transmitted by the
master are done according to the bit write definition
and the acknowledgment is read using the bit read
definition.
Byte Read: A byte read is an 8-bit information transfer
from the slave to the master plus a 1-bit ACK or NACK
from the master to the slave. The 8 bits of information
that are transferred (most significant bit first) from the
slave to the master are read by the master using the
bit read definition, and the master transmits an ACK
using the bit write definition to receive additional data
bytes. The master must NACK the last byte read to
terminate communication so the slave returns control
of SDA to the master.
Slave Address Byte: Each slave on the I2C bus
responds to a slave address byte sent immediately
following a START condition. The slave address byte
contains the slave address in the most significant 7
bits and the R/W bit in the least significant bit. The
13
DS1341/DS1342
I2C Serial Port Operation
DS1341/DS1342
Low-Current I2C RTCs for High-ESR Crystals
TYPICAL I2C WRITE TRANSACTION
MSB
START
1
LSB
1
0
1
0
0
0
R/W
MSB
SLAVE
ACK
b7
LSB
b6
READ/
WRITE
SLAVE
ADDRESS
b5
b4
b3
b2
b1
b0
MSB
SLAVE
ACK
b7
LSB
b6
b5
b4
REGISTER ADDRESS
b3
b2
b1
b0
SLAVE
ACK
STOP
DATA
EXAMPLE I2C TRANSACTIONS
D0h
A) SINGLE BYTE WRITE
-WRITE CONTROL REGISTER
TO 18h
START
B) SINGLE BYTE READ
-READ CONTROL REGISTER
START 1 1 0 1 0 0 0 0
11010000
D0h
0Eh
SLAVE
00001110
ACK
0Eh
SLAVE
SLAVE
00001110
ACK
ACK
D0h
C) MULTIBYTE WRITE
-WRITE DATE REGISTER
TO "02" AND MONTH
REGISTER TO "11"
D) MULTIBYTE READ
-READ ALARM 2 HOURS
AND DATE VALUES
START 1 1 0 1 0 0 0 0
00000100
SLAVE
ACK
00001100
SLAVE
ACK
STOP
D1h
REPEATED
START
DATA
11010001
02h
04h
SLAVE
ACK
D0h
START 1 1 0 1 0 0 0 0
18h
SLAVE
00011000
ACK
SLAVE
ACK
MASTER
NACK
STOP
11h
SLAVE
ACK
00000010
SLAVE
ACK
REPEATED
START
SLAVE
ACK
00010001
SLAVE
ACK
SLAVE
ACK
VALUE
D1h
0Ch
VALUE
11010001
STOP
DATA
DATA
MASTER
ACK
VALUE
MASTER
NACK
STOP
Figure 6. I2C Transactions
DS1341/DS1342s’ slave address is D0h and cannot
be modified by the user. When the R/W bit is 0 (such
as in D0h), the master is indicating it writes data to the
slave. If R/W = 1 (D1h in this case), the master is indicating it wants to read from the slave. If an incorrect
slave address is written, the DS1341/DS1342 assume
the master is communicating with another I2C device
and ignore the communication until the next START
condition is sent.
Memory Address: During an I2C write operation, the
master must transmit a memory address to identify
the memory location where the slave is to store the
data. The memory address is always the second byte
transmitted during a write operation following the
slave address byte.
I2C Communication
2
See Figure 6 for an I C communication example.
Writing a Single Byte to a Slave: The master must
generate a START condition, write the slave address
byte (R/W = 0), write the memory address, write
the byte of data, and generate a STOP condition.
Remember the master must read the slave’s acknowledgment during all byte write operations.
14
Writing Multiple Bytes to a Slave: To write multiple
bytes to a slave, the master generates a START condition, writes the slave address byte (R/W = 0), writes
the starting memory address, writes multiple data
bytes, and generates a STOP condition.
Reading a Single Byte from a Slave: Unlike the write
operation that uses the specified memory address
byte to define where the data is to be written, the read
operation occurs at the present value of the memory
address counter. To read a single byte from the slave,
the master generates a START condition, writes the
slave address byte with R/W = 1, reads the data byte
with a NACK to indicate the end of the transfer, and
generates a STOP condition. However, since requiring the master to keep track of the memory address
counter is impractical, use the method for manipulating the address counter for reads.
Manipulating the Address Counter for Reads: A
dummy write cycle can be used to force the address
counter to a particular value. To do this the master generates a START condition, writes the slave
address byte (R/W = 0), writes the memory address
where it desires to read, generates a repeated START
condition, writes the slave address byte (R/W = 1),
Low-Current I2C RTCs for High-ESR Crystals
Reading Multiple Bytes from a Slave: The read
operation can be used to read multiple bytes with a
single transfer. When reading bytes from the slave,
the master simply ACKs the data byte if it desires to
read another byte before terminating the transaction.
After the master reads the last byte it must NACK to
indicate the end of the transfer and then it generates
a STOP condition.
Using Open-Drain Outputs
The CLKIN/INTA output is open drain and, therefore,
requires an external pullup resistor to realize a logic-high
output level.
SDA and SCL Pullup Resistors
SDA is an open-drain output and requires an external
pullup resistor to realize a logic-high level.
Because the DS1341/DS1342 do not use clock cycle
stretching, a master using either an open-drain output
with a pullup resistor or CMOS output driver (push-pull)
could be used for SCL.
Chip Information
Bus Timeout
To avoid an unintended I2C interface timeout, SCL
should not be held low longer than tTIMEOUTMIN. The
I2C interface is in the reset state and can receive a
new START condition when SCL is held low for at least
tTIMEOUTMAX. When the device detects this condition,
SDA is released and allowed to be pulled high by the
external pullup resistor. For the timeout function to work,
the oscillator must be enabled and running.
Applications Information
Power-Supply Decoupling
To achieve the best results when using the DS1341/
DS1342, decouple the VCC power supply with a 0.01FF
and/or 0.1FF capacitor. Use a high-quality, ceramic, surface-mount capacitor if possible. Surface-mount components minimize lead inductance, which improves performance, and ceramic capacitors tend to have adequate
high-frequency response for decoupling applications.
SUBSTRATE CONNECTED TO GROUND
Package Information
For the latest package outline information and land patterns,
go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package
drawings may show a different suffix character, but the drawing
pertains to the package regardless of RoHS status.
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
8 FSOP
U8+1
21-0036
90-0092
8 TDFN-EP
T833+2
21-0137
90-0059
15
DS1341/DS1342
reads data with ACK or NACK as applicable, and
generates a STOP condition. See Figure 6 for a read
example using the repeated START condition to
specify the starting memory location.
Low-Current I2C RTCs for High-ESR Crystals
DS1341/DS1342
Revision History
REVISION
NUMBER
REVISION
DATE
0
10/09
Initial release
12/10
Removed future status from the DS1342 in the Ordering Information table; added
the Package Thermal Characteristics section; added the DS1342 ICCT parameter to
the DC Electrical Characteristics table; changed the ESR specification in the Crystal
Parameters table from 80kW (max) to 100kW (max) and removed 35kW typ; added
the TDFN package to the Ordering Information, Pin Configurations, Pin Description,
and Package Information; added the Typical Operating Characteristics section
1
DESCRIPTION
PAGES
CHANGED
—
1, 2, 3, 5,
6, 15
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied.
Maxim reserves the right to change the circuitry and specifications without notice at any time.
16
©
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2010 Maxim Integrated Products
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