FDG6318P Dual P-Channel, Digital FET General Description Features These dual P-Channel logic level enhancement mode MOSFET are produced using Fairchild Semiconductor’s advanced PowerTrench process that has been especially tailored to minimize on-state resistance. This device has been designed especially for low voltage applications as a replacement for bipolar digital transistors and small signal MOSFETS. • –0.5 A, –20 V. RDS(ON) = 780 mΩ @ VGS = –4.5 V RDS(ON) = 1200 mΩ @ VGS = –2.5 V • Very low level gate drive requirements allowing direct operation in 3V circuits (VGS(th) < 1.5V). • Compact industry standard SC70-6 surface mount package Applications • Battery management S G D S 1 or 4 6 or 3 D G 2 or 5 5 or 2 G D 3 or 6 4 or 1 S D G Pin 1 S SC70-6 The pinouts are symmetrical; pin 1 and pin 4 are interchangeable. Absolute Maximum Ratings Symbol TA=25oC unless otherwise noted Parameter Ratings Units VDSS Drain-Source Voltage –20 V VGSS Gate-Source Voltage ±12 V ID Drain Current –0.5 A – Continuous (Note 1) – Pulsed –1.8 PD Power Dissipation for Single Operation TJ, TSTG Operating and Storage Junction Temperature Range (Note 1) 0.3 W –55 to +150 °C 415 °C/W Thermal Characteristics Thermal Resistance, Junction-to-Ambient RθJA (Note 1) Package Marking and Ordering Information Device Marking Device Reel Size Tape width Quantity .38 FDG6318P 7’’ 8mm 3000 units 2003 Fairchild Semiconductor Corporation FDG6318P Rev C (W) FDG6318P January 2003 Symbol Parameter TA = 25°C unless otherwise noted Test Conditions Min Typ Max Units Off Characteristics BVDSS ID = –250 µA VGS = 0 V, ∆BVDSS ∆TJ IDSS Drain–Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current VDS = –16 V, VGS = 0 V –1 µA IGSS Gate–Body Leakage VGS = ±12 V, VDS = 0 V ±100 nA On Characteristics –20 ID = –250 µA, Referenced to 25°C V –10 mV/°C (Note 2) ID = –250 µA VGS(th) Gate Threshold Voltage VDS = VGS, ∆VGS(th) ∆TJ RDS(on) Gate Threshold Voltage Temperature Coefficient Static Drain–Source On–Resistance ID = –250 µA, Referenced to 25°C ID(on) On–State Drain Current VGS = –4.5 V, VGS = –2.5 V, VGS = –4.5 V, VGS = –4.5 V, gFS Forward Transconductance VDS = –5 V, –0.65 –1.2 –1.5 2 580 980 780 V mV/°C 780 1200 ID = –0.5 A ID = –0.4 A ID = –0.5 A, TJ=125°C VDS = –5 V ID = –0.5 A 1.1 S VDS = –10 V, V GS = 0 V, f = 1.0 MHz 83 pF 20 pF 11 pF VGS = 15 mV, f = 1.0 MHz 12.1 Ω VDD = –10 V, ID = 1 A, VGS = –4.5 V, RGEN = 6 Ω 6 12 ns 12 22 ns ns –1.8 mΩ A Dynamic Characteristics Ciss Input Capacitance Coss Output Capacitance Crss Reverse Transfer Capacitance RG Gate Resistance Switching Characteristics td(on) Turn–On Delay Time tr Turn–On Rise Time (Note 2) td(off) Turn–Off Delay Time 6 13 tf Turn–Off Fall Time 1 3 ns Qg Total Gate Charge 0.86 1.2 nC Qgs Gate–Source Charge Qgd Gate–Drain Charge VDS = –10 V, ID = –0.6 A, VGS = –4.5 V 0.22 nC 0.25 nC Drain–Source Diode Characteristics and Maximum Ratings IS Maximum Continuous Drain–Source Diode Forward Current VSD trr Drain–Source Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge VGS = 0 V, IS = –0.25 A(Note 2) IF = –0.5 A, diF/dt = 100 A/µs –0.83 –0.25 A –1.2 V 12.6 ns 2.52 nC Notes: 1. RθJA is the sum of the junction-to-case and case-to-ambient thermal resistance where the case thermal reference is defined as the solder mounting surface of the drain pins. RθJC is guaranteed by design while RθJA is determined by the user's board design. RθJA = 415°C/W when mounted on a minimum pad . 2. Pulse Test: Pulse Width < 300µs, Duty Cycle < 2.0% FDG6318P Rev C (W) FDG6318P Electrical Characteristics FDG6318P Typical Characteristics 1.8 1.75 -ID, DRAIN CURRENT (A) -4.5V RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE -3.5V VGS = -10.0V -3.0V -6.0V 1.2 -2.5V 0.6 -2.0V VGS = -3.5V 1.5 -4.0V -4.5V -5.0V 1.25 -6.0V -10.0V 1 0.75 0 0 0.5 1 1.5 2 2.5 0 3 0.4 Figure 1. On-Region Characteristics. 1.2 1.6 Figure 2. On-Resistance Variation with Drain Current and Gate Voltage. 1.8 1.4 ID = -0.5A VGS = -4.5V 1.3 RDS(ON), ON-RESISTANCE (OHM) RDS(ON), NORMALIZED DRAIN-SOURCE ON-RESISTANCE 0.8 -ID, DRAIN CURRENT (A) -VDS, DRAIN-SOURCE VOLTAGE (V) 1.2 1.1 1 0.9 0.8 0.7 -50 -25 0 25 50 75 100 ID = -0.25A 1.4 1 TA = 125oC 0.6 TA = 25oC 0.2 125 0 2 4 6 8 10 o TJ, JUNCTION TEMPERATURE ( C) -VGS, GATE TO SOURCE VOLTAGE (V) Figure 3. On-Resistance Variation with Temperature. Figure 4. On-Resistance Variation with Gate-to-Source Voltage. 10 -IS, REVERSE DRAIN CURRENT (A) 1.8 -ID, DRAIN CURRENT (A) VDS = -5V TA = -55oC 25oC 1.2 125oC 0.6 VGS = 0V 1 TA = 125oC 0.1 25oC 0.01 o -55 C 0.001 0.0001 0 0.5 1 1.5 2 2.5 3 -VGS, GATE TO SOURCE VOLTAGE (V) Figure 5. Transfer Characteristics. 3.5 0 0.2 0.4 0.6 0.8 1 1.2 1.4 -VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 6. Body Diode Forward Voltage Variation with Source Current and Temperature. FDG6318P Rev C (W) FDG6318P Typical Characteristics 120 ID = -0.5A f = 1MHz VGS = 0 V VDS = -5V 8 -10V 6 CAPACITANCE (pF) -VGS, GATE-SOURCE VOLTAGE (V) 10 -15V 4 80 Ciss 40 Coss 2 Crss 0 0 0 0.3 0.6 0.9 1.2 1.5 1.8 2.1 0 4 Qg, GATE CHARGE (nC) 8 12 16 Figure 7. Gate Charge Characteristics. Figure 8. Capacitance Characteristics. 30 10 SINGLE PULSE RθJA = 415oC/W RDS(ON) LIMIT 100µs 24 TA = 25oC 1ms POWER (W) 1 10ms 100ms 1s DC VGS = -4.5V SINGLE PULSE RθJA = 415oC/W 0.1 18 12 6 o TA = 25 C 0.01 0.1 1 10 0 0.0001 100 0.001 0.01 -VDS, DRAIN-SOURCE VOLTAGE (V) 0.1 1 10 100 SINGLE PULSE TIME (SEC) Figure 9. Maximum Safe Operating Area. r(t), NORMALIZED EFFECTIVE TRANSIENT THERMAL RESISTANCE -ID, DRAIN CURRENT (A) 20 -VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 10. Single Pulse Maximum Power Dissipation. 1 D = 0.5 RθJA(t) = r(t) * RθJA RθJA = 415 °C/W 0.2 0.1 0.1 P(pk) 0.05 t1 0.02 t2 0.01 0.01 TJ - TA = P * RθJA(t) Duty Cycle, D = t1 / t2 SINGLE PULSE 0.001 0.0001 0.001 0.01 0.1 1 10 100 t1, TIME (sec) Figure 11. Transient Thermal Response Curve. Thermal characterization performed using the conditions described in Note 1. Transient thermal response will change depending on the circuit board design. FDG6318P Rev C (W) TRADEMARKS The following are registered and unregistered trademarks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx FACT ActiveArray FACT Quiet Series Bottomless FASTâ CoolFET FASTr CROSSVOLT FRFET DOME GlobalOptoisolator EcoSPARK GTO E2CMOSTM HiSeC EnSignaTM I2C Across the board. Around the world. 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A critical component is any component of a life 1. Life support devices or systems are devices or support device or system whose failure to perform can systems which, (a) are intended for surgical implant into be reasonably expected to cause the failure of the life the body, or (b) support or sustain life, or (c) whose support device or system, or to affect its safety or failure to perform when properly used in accordance with instructions for use provided in the labeling, can be effectiveness. reasonably expected to result in significant injury to the user. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Product Status Definition Advance Information Formative or In Design This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. Preliminary First Production This datasheet contains preliminary data, and supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. No Identification Needed Full Production This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice in order to improve design. Obsolete Not In Production This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I2