Rohm BD9536FV-E2 2ch switching regulator for desktop pc Datasheet

High Performance Regulators for PCs
2ch Switching Regulator
for Desktop PC
BD9536FV
No.10030EAT35
●Description
BD9536FV is a 2ch switching regulator controller that can generate low output voltages (0.7V to 5.5V) from a wide input
voltage range (7.5V to 15V). High efficiency for the switching regulator can be achieved due to its internal N-MOSFET power
3
TM
transistor. The IC also incorporates a new technology called H Reg , a Rohm proprietary control method which facilitates
ultra-high transient response against changes in load. For protection and ease of use, the IC also incorporates soft start,
variable frequency, and short circuit protection with timer latch functions. This switching regulator is specially designed for
DRAM and power supplies for graphics chips.
●Features
3
TM
1) 2ch H Reg DC/DC converter controller
2) Thermal Shut down (TSD), Under-Voltage Lock-Out (UVLO),
Adjustable Over Current Protection (OCP): detected FET Ron,
Over Voltage Protection (OVP), Short Circuit Protection (SCP) built-in
3) Soft start function to minimize rush current during startup
4) Adjustable switching frequency (f = 200 kHz – 600 kHz)
5) SSOP-B28 Package
6) Built-in 5V power supply for FET driver
7) Integrated bootstrap diode
●Applications
LCD, Game Consoles, Desktop PCs
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© 2010 ROHM Co., Ltd. All rights reserved.
1/18
2010.07 - Rev.A
Technical Note
BD9536FV
●Maximum Absolute Ratings (Ta=25℃)
Parameter
Symbol
Ratings
Unit
Input Voltage
VIN
16 *1
V
BOOT Voltage
BOOT1/2
23 *1
V
BOOT1-SW1, BOOT2-SW2
7 *1
V
HG1-SW1, HG2-SW2
7 *1
V
LG1/2
5VReg
V
VOUT1/2
7 *1
V
Output Feedback Voltage
FB1/2
5VReg
V
FS Voltage
FS1/2
5VReg
V
5VReg Voltage
5VReg
7 *1
V
Current Limit Setting Voltage
ILIM1/2
5VReg
V
Logic Input Voltage
EN1/2, CTL1/2
7 *1
V
Power dissipation 1
Pd1
0.8 *2
W
Power dissipation 2
Pd2
1.06 *3
W
Operating Temperature Range
Topr
-20～+100
℃
Storage Temperature Range
Tstg
-55～+150
℃
Tjmax
+150
℃
BOOT-SW Voltage
HG-SW Voltage
LG Voltage
Output Voltage
Junction Temperature
*1 Not to exceed Pd.
*2 Reduced by 6.4mW for each increase in Ta of 1℃ over 25℃ (when not mounted on a heat radiation board )
*3 Reduced by 8.5mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 70.0mm×70mm×1.6mm Glass-epoxy PCB.)
●Operating Conditions (Ta=25℃)
Parameter
Ratings
Symbol
Min.
Max.
Unit
Input voltage
VIN
7.5
15
V
BOOT voltage
BOOT1/2
4.5
20
V
SW1/2
-0.7
15
V
BOOT-SW voltage
BOOT1-SW1, BOOT2-SW2
4.5
5.5
V
Logic Input Voltage
EN1/2, CTL1/2
0
5.5
V
Output Voltage
VOUT1/2
0.7
5.5
V
MIN ON Time
tonmin
-
100
ns
SW Voltage
★ This product should not be used in a radioactive environment.
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© 2010 ROHM Co., Ltd. All rights reserved.
2/18
2010.07 - Rev.A
Technical Note
BD9536FV
●Electrical Characteristics (Unless otherwise noted, Ta=25℃, VCC=5V, VIN=12V, VEN1=VEN2=3V, VOUT1=VOUT2=1.8V, RFS=75kΩ)
Limits
Symbol
Unit
Parameter
Condition
Min.
Typ.
Max.
[General]
VIN Bias Current
IIN
-
1.6
2.5
mA
VIN Standby Current
IIN_stb
-
0
10
µA
EN Low Voltage 1,2
VEN_low1,2
GND
-
0.3
V
EN High Voltage 1,2
VEN_high1,2
2.2
-
5.5
V
EN Bias Current 1,2
IEN1,2
-
14
20
µA
5Vreg_stb
-
-
0.1
V
5VReg
4.8
5.0
5.2
V
IReg
50
-
-
mA
5VReg Threshold Voltage
5VReg_UVLO
3.75
4.20
4.65
V
5VReg Hysteresis Voltage
d5VReg_UVLO
100
160
220
mV
FB_OVP1,2
0.75
0.85
0.95
V
ton1
480
600
720
ns
MAX ON Time 1
Tonmax1
3.0
4.0
5.0
µs
MIN OFF Time 1
Toffmin1
600
900
-
ns
Ton2
480
600
720
ns
VEN1=VEN2=0V
[5V Linear Regulator]
5VReg Standby Voltage
5VReg Output Voltage
Maximum Current
VEN1=VEN2=0V
VIN=7.5V to 15V
Ireg=0mA to 10mA
[Under-Voltage Lock-Out]
5VReg:Sweep up
5VReg:Sweep down
[OVP Block]
FB Threshold Voltage 1,2
3
[H REG
TM
Control Block]
ON Time1
ON Time 2
RFS1=75kΩ
RFS2=75kΩ
MAX ON Time 2
Tonmax2
3.0
4.0
5.0
µs
MIN OFF Time 2
Toffmin2
600
900
-
ns
RHGhon1,2
-
3.0
6.0
Ω
RHGlon1,2
-
2.0
4.0
Ω
RLGhon1,2
-
2.0
4.0
Ω
RLGlon1,2
-
0.5
1.0
Ω
Vilim11,2
80
100
120
mV
RILIM=100k
VReIlim11,2
80
100
120
mV
RILIM=100k
FB1 threshold Voltage 1
FB1-1
0.615
0.625
0.635
V
CTL1/2=0V or 3V
FB1 threshold Voltage 2
FB1-2
0.640
0.650
0.660
V
CTL1=0V, CTL2=3V
FB1 threshold Voltage 3
FB1-3
0.590
0.600
0.610
V
CTL1=3V, CTL2=0V
FB2
0.640
0.650
0.660
V
[FET Block]
HG High side
ON Resistance 1,2
HG Low side
ON Resistance 1,2
LG High side
ON Resistance 1,2
LG Low side
ON Resistance 1,2
[Over Current Protection Block]
Current Limit
Threshold Voltage1_1,2
Reverse Current
Limit Threshold Voltage 1_1,2
[Output Voltage Detection Block]
FB2 threshold Voltage
CTL Low Voltage 1,2
VCTL_low1,2
GND
-
0.5
V
CTL High Voltage 1,2
VCTL_high1,2
VCC-0.5
-
VCC
V
IFB
-1
-
1
µA
IVOUT
5
10
-
mA
FB1/2 Input Current
VOUT Discharge Current
VOUT=1V, EN=0V
[SCP Block]
Threshold Voltage 1,2
Vthscp1,2
REF1/2× REF1/2× REF1/2×
0.70
0.80
0.90
1
2
3
V
Charge Current (SCP)
ISCP
Charge Current (OVP)
IOVP
4
8
12
µA
Delay Setting Voltage
VSCP
1.05
1.2
1.35
V
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© 2010 ROHM Co., Ltd. All rights reserved.
3/18
µA
2010.07 - Rev.A
Technical Note
BD9536FV
●Block Diagram
VIN
6
VOUT1
FS1
21
VIN
20
5VReg
5VReg
TSD
Thermal
Protection
VOUT1
BOOT1
2
27
5V
5VReg
VIN
EN1/UVLO
BG
26
TM
H Reg
Controller
Block
4
R
Driver
OCP Circuit
Q
S
VOUT1
HG1
25
3
REF 1
VIN
SW1
5VReg
SW1
24
LG1
+
5VReg
-
3
FB1
22
OVP
UVLO
ILIM1
SCP
TSD
0.85
FB1
VCC
Logic Input
EN1 28
EN2 15
CTL1 1
VOUT2
Reference
Block
+
-
0.85
FB 2
FB1
SCP
EN2
OVP2
REF1
REF 1× 0.8
+ REF 2× 0.8
- FB 2
OVP
DAC
ILIM1
EN1
Delay
UVLO
8
5VReg
+
VIN
16
13
VIN
3
17
TM
H Reg
Controller
Block
11
R
18
Driver
Q
S
OCP
Circuit
SW2
+
FB2
7
GND
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© 2010 ROHM Co., Ltd. All rights reserved.
UVLO
ILIM2
SCP
TSD
BOOT2
HG2
VOUT2
SW2
5VReg
5VReg
19
-
12
PGND
5
SCP
BG
EN2/UVLO
BG
REF2
OVP1
CTL2 14
VOUT2
23
+
LG2
OVP
9
ILIM2
FS2
4/18
10
PGND
2010.07 - Rev.A
Technical Note
BD9536FV
●Pin Configuration
CTL1
28 EN1
1
27 BOOT1
VOUT1 2
FB1 3
26 HG1
REF1 4
25 SW1
ILIM1 5
24 LG1
FS1 6
23 PGND
BD9536FV
22 VCC
GND
7
SCP
8
21 VIN
FS2
9
20 5Vreg
ILIM2 10
19 LG2
REF2 11
18 SW2
FB2 12
17 HG2
VOUT2 13
16 BOOT2
CTL2 14
●Pin Function
PIN
PIN
No. name
1
2
CTL1
15 EN2
PIN Function
PIN
No.
PIN
name
1ch Output Voltage Setting Control Pin 1
:See P13/17
15
EN2
VOUT1 Output Voltage Sence Pin 1
3
FB1
4
16
PIN Function
Enable Input Pin 2
(0～0.3V:OFF, 2.2～5.5V:ON)
BOOT2 HG Driver Power Supply Pin 2
Output Voltage Feedback Pin 1
17
HG2
High side FET Gate Driver Pin 2
REF1
Reference Voltage Pin 1 /
Soft Start Time Setting Pin 1
(0.625V±25mV select) :See P13/17
18
SW2
High side FET Source Pin 2
5
ILIM1
1ch OCP Setting Pin
19
LG2
Low side FET Gate Driver Pin 2
6
FS1
Switching Frequency Adjustable Pin 1
20
5VReg
7
GND
Sense GND
21
VIN
Battery Voltage Sense Pin
8
SCP
Timer Latch Delay time Setting Pin
for short circuit protection
22
VCC
Power Supply Input Pin
9
FS2
Switching Frequency Adjustable Pin 2
23
PGND
10
ILIM2
2ch OCP Setting Pin
24
LG1
Low side FET Gate Driver Pin 1
11
REF2
Reference Voltage Pin 2 /
Soft Start Time Setting Pin 2(0.65V)
25
SW1
High side FET Source Pin 1
12
FB2
Output Voltage Feedback Pin 2
26
HG1
High side FET Gate Driver Pin 1
13
14
VOUT2 Output Voltage Sense Pin 2
CTL2
27
1ch Output Voltage Setting Control Pin 2
:See P13/17
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5/18
28
Reference Voltage Inside IC
(5V Voltage / always ON)
Power GND
BOOT1 HG Driver Power Supply Pin 1
EN1
Enable Input Pin 1
(0～0.3V:OFF, 2.2～5.5V:ON)
2010.07 - Rev.A
Technical Note
BD9536FV
●Reference Data
VOUT1
(50mV/div)
REF1
(50mV/div)
CTL1
(5V/div)
CTL2
(5V/div)
VOUT1
(50mV/div)
VOUT1
(50mV/div)
REF1
(50mV/div)
REF1
(50mV/div)
CTL1
(5V/div)
CTL1
(5V/div)
CTL2
(5V/div)
CTL2
(5V/div)
(100µs/div)
(100µs/div)
VOUT1
(50mV/div)
REF1
(50mV/div)
(100µs/div)
Fig.2 DAC switch 2
Fig.1 DAC switch1
Fig.3 DAC switch 3
EN1
(5V/div)
EN2
(5V/div)
VOUT1
(1V/div)
VOUT2
(1V/div)
REF1
(500mV/div)
REF2
(500mV/div)
CTL1
(5V/div)
CTL2
(5V/div)
(100µs/div)
Fig.4 DAC switch 4
VOUT2
(1V/div)
VOUT1
(1V/div)
VOUT1
(1V/div)
HG1
(10V/div)
HG1
(10V/div)
HG2
(10V/div)
HG2
(10V/div)
VOUT2
(1V/div)
VOUT1
(1V/div)
EN2
(5V/div)
EN1
(5V/div)
(20ms/div)
(500ms/div)
(20ms/div)
Fig.7 VOUT1 SCP function
Fig.9 VOUT1 VOUT2 SCP function
Fig.8 VOUT2 SCP function
VOUT1
(200mV/div)
VOUT2
(50mV/div)
VOUT1
(200mV/div)
HG1/LG1
(10V/div)
HG1/LG1
(10V/div)
IOUT1
(5A/div)
IOUT1
(5A/div)
HG2/LG2
(10V/div)
IOUT2
(5A/div)
(20µs/div)
(20µs/div)
Fig.10 VOUT1transient response
Fig.11 VOUT1 transient response
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Fig.6 EN startup (REF2)
Fig.5 EN startup (REF1)
VOUT2
(1V/div)
© 2010 ROHM Co., Ltd. All rights reserved.
(200µs/div)
(200µs/div)
6/18
(10µs/div)
Fig.12 VOUT2 transient response
2010.07 - Rev.A
Technical Note
BD9536FV
2.0
10
9
VOUT2
(50mV/div)
8
1.5
HG2/LG2
(10V/div)
6
IIN [mA]
IIN [μA]
7
5
1.0
4
3
0.5
2
IOUT2
(5A/div)
1
0.0
0
(10µs/div)
-10
Fig.13 VOUT2 transient response
10
30
50
Ta [℃]
70
90
-10
100
Fig.14 Ta vs IIN (standby)
6.0
10
30
50
Ta [℃]
70
90 100
Fig.15 Ta vs IIN (active)
0.90
0.60
0.88
0.56
0.86
0.52
FB1 [V]
FB [V]
VREG5V [V]
5.5
5.0
0.84
0.48
0.82
0.44
4.5
4.0
0.40
0.80
-10
10
30
50
Ta [℃]
70
90
100
-10
30
50
Ta [℃]
70
90
-10
100
0.60
1.5
0.56
1.4
0.52
50
Ta [℃]
90 100
70
-90
SW[mV]
SCP [V]
30
-80
1.3
0.48
10
Fig.18 Ta vs SCP threshold (1ch)
Fig.17 Ta vs OVP threshold
Fig.16 Ta vs VREG5V
FB2 [V]
10
1.2
-100
-110
0.44
1.1
0.40
30
50
Ta [℃]
70
100
90 100
-10
90
90
80
80
70
70
Efficiency [%]
100
50
40
30
50
Ta [℃]
70
90
100
20
10
10
0.01
0.1
IOUT [A]
1
Fig.22 efficiency (1ch)
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© 2010 ROHM Co., Ltd. All rights reserved.
10
0.001
90 100
70
REF2
0.62
REF1
0.58
0.54
0.50
0
0.001
50
Ta [℃]
0.66
40
30
30
0.70
50
20
10
Fig.21 Ta vs OCP threshold
60
30
0
-10
Fig.20 Ta vs delay setting voltage
100
60
10
REF[V]
10
Fig.19 Ta vs SCP threshold (2ch)
Efficiency [%]
-120
1.0
-10
0.01
0.1
IOUT [A]
1
Fig.23 efficiency (2ch)
7/18
10
-10
10
30
50
Ta [℃]
70
90 100
Fig.24 Ta vs REF
2010.07 - Rev.A
Technical Note
BD9536FV
●Evaluation Board Circuit
GND
VIN
21
12V
R1
VIN
C1
20
BD9536FV
SSOP-B28
HG1
22
5V
Vcc
SW1
C3
LG1
EN1
28
SW1
R3
PGND
EN1
C4
5
VOUT1
FB1
ILIM1
FS1
R4
SCP
4
REF1
5V
EN2
C5
BOOT2
HG2
15
SW2
EN2
R5
R6
SW2
C6
10
1
Logic Input
14
Logic Input
11
GND
PGND1 PGND2
VIN
BOOT1
5VReg
C2
R2
PGND
U1
LG2
ILIM2
27
26
HG1
R7
C8
M1
SW1
25
1.8V/6A
L1
LG1
24
C12
C11
M2
R11
D1
23
R12
R13
2
FB2
FS2
REF 2
C16
C17
C14
6
8
R8
VIN
16 C9
17
R9
C10
HG2
M3
SW2
18
C19
C18
1.2V/12A
L2
LG2
19
M4
D2
R14
R15
R16
CTL2
C15
3
CTL1
VOUT2
C13
13
C20
C22
C23
C24
C21
12
9
FS
C7
GND
7
●Evaluation Board Parts List
Designation
Value
R10
Part No.
Company
Designation
Value
Part No.
Company
MCR03 series
ROHM
C10
0.1µF
KYOCERA
R1
0Ω
R2
10Ω
MCR03 series
ROHM
C11
0.1µF
KYOCERA
R3
1kΩ
MCR03 series
ROHM
C12
10µF
KYOCERA
R4
100kΩ
MCR03 series
ROHM
C13
330pF
KYOCERA
R5
1kΩ
MCR03 series
ROHM
C14
100pF
KYOCERA
R6
100kΩ
MCR03 series
ROHM
C15
330µF
R7
0Ω
MCR03 series
ROHM
C16
0.1µF
KYOCERA
R8
68kΩ
MCR03 series
ROHM
C17
-
KYOCERA
OS-CON
SANYO
R9
0Ω
MCR03 series
ROHM
C18
10µF
KYOCERA
R10
58kΩ
MCR03 series
ROHM
C19
10µF
KYOCERA
R11
-
MCR03 series
ROHM
C20
330pF
KYOCERA
R12
11.5kΩ
MCR03 series
ROHM
C21
100pF
R13
6.5kΩ
MCR03 series
ROHM
C22
330µF
R14
-
MCR03 series
ROHM
C23
0.1µF
KYOCERA
R15
6.5kΩ
MCR03 series
ROHM
C24
-
KYOCERA
R16
6.5kΩ
MCR03 series
ROHM
D1
KYOCERA
SPCAP
Panasonic
RB083L-20
ROHM
RB083L-20
ROHM
B966AS
TOKO
C1
1µF
KYOCERA
D2
C2
10µF
KYOCERA
L1
3.9µH
C3
0.1µF
KYOCERA
L2
1.6µH
962BS
TOKO
C4
33pF
KYOCERA
M1
SH8K4 (Q1)
ROHM
C5
0.01µF
KYOCERA
M2
SH8K4 (Q2)
ROHM
C6
33pF
KYOCERA
M3
RSS100N03
ROHM
C7
0.01µF
KYOCERA
M4
RSS100N03
ROHM
C8
0.1µF
KYOCERA
U1
BD9536FV
ROHM
C9
0.01µF
KYOCERA
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8/18
-
2010.07 - Rev.A
Technical Note
BD9536FV
●Pin Descriptions
・EN1 (28 Pin) / EN2 (15 Pin)
When the input voltage on the EN pin reaches at least 2.2 V, the switching regulator becomes active. At voltages less
than 0.3 V, the switching regulator becomes inactive, and the input current drops to 10 µA or less. Thus the IC can be
controlled from 2.5 V, 3.3 V or 5 V power supplies.
・5VReg (20 Pin)
5.0 V reference voltage output pin. If at least 2.2 V is supplied to either the EN1 or EN2 pin, the reference output is
switched on. This pin supplies 5.0 V at up to 50 mA. Inserting a 10 µF capacitor (with a X5R or X7R rating) between the
5VReg and GND pins is recommended.
・ILIM1 (5 Pin) / ILIM2 (10 Pin)
The IC monitors the voltage between the SW pin and PGND pin as a control for the output current protection (OCP)
mechanism. The voltage at which OCP engages is determined by the resistance value connected to the ILIM pin. This
also allows for compatibility with FETs of various RON values.
・VIN (21 pin)
The IC determines the duty cycles internally based upon the input voltage on this pin. Therefore, variations in voltage on
this pin can lead to highly unstable operation. This pin also acts as the voltage input to the internal switching regulator
block, and is sensitive to the impedance of the power supply. Attaching a bypass capacitor or RC filter on this pin as
appropriate for the application is recommended.
・FS1 (6 Pin) / FS2 (9 Pin)
This pin is used to adjust the switching frequency via an external resistor. The frequency range is from 200 kHz to 600
kHz.
・BOOT1 (27 pin) / BOOT2 (16 pin)
This pin supplies voltage used for driving the high-side FET. Maximum absolute ratings are 23V from GND and 5.5V from
SW. BOOT voltage swings between VIN + 5VReg and 5VReg during active operation.
・HG1 (26 pin) / HG2 (17 pin)
This pin supplies voltage used for driving the gate of the high-side FET. This voltage swings between BOOT and SW.
High-speed gate driving for the high side FET can be achieved due to its low on-resistance (3 Ω when HG = high, 2 Ω
when HG = low) of the driver.
・SW1 (25 pin) / SW2 (18 pin)
This pin acts as the source connection to the high-side FET. Maximum absolute rating is 16V from GND. SW voltage
swings between VIN and GND.
・LG1 (24 pin) / LG2 (19 pin)
This pin supplies voltage used for driving the gate of the low-side FET. This voltage swings between VDD and PGND.
High-speed gate driving for the low-side FET can be achieved due to its low on-resistance (2 Ω when LG = high, 0.5 Ω
when LG = low) of the driver.
・PGND (23 pin)
This pin acts as the ground connection to the source of the low-side FET.
・GND (7 pin)
This is the ground pin for all internal analog and digital power supplies.
・SCP (8 pin)
This pin allows for adjustment of the latch timer used for short circuit protection. When voltage on this pin drops lower
than 80% of REF, the output will switch off and remain latched after the specified time interval. When the UVLO circuit
becomes active, or when EN is pulled low, the timer-latching function is disabled.
・VOUT1 (2 pin) / VOUT2 (13 pin)
This is the output voltage sense pin; this pin features an integrated discharge FET used to discharge the output capacitor
when status is set to OFF.
・FB1 (3 pin) / FB2 (12 pin)
This is the output feedback pin. While channel 2 internal reference voltages is fixed at 0.650V, channel 1 internal
reference voltage is adjustable depending on the input conditions of the CTL1 and CTL2 pins.
・REF1 (4 pin) / REF2 (11 pin)
This is the reference/adjustment pin for soft start time. Output rise time is determined by the RC time constant of the IC’s
internal resistance (50kΩ typ.) and an external capacitor.
・Vcc (22 pin)
This is the power supply pin for all internal circuitry. This pin can be supplied directly by a 5V source, or via an RC filter
(10 Ω, 0.01 µF) from the 5VReg pin.
・CTL1 (1 pin) / CTL2 (14 pin)
These pins allow for the adjustment of the internal voltage reference (REF1) for channel 1. The pins recognize a logic HI
at VCC-0.5 V or above and logic LO at 0.5 V or below. Refer to the voltage adjustment table for REF1 on page 13.
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9/18
2010.07 - Rev.A
Technical Note
BD9536FV
●Explanation of Operation
3
The BD9536FV is a 2ch switching regulator controller incorporating ROHM’s proprietary H Reg CONTROLLA control system.
When VOUT drops due to a rapid load change, the system quickly restores VOUT by extending the TON time interval.
3
TM
H Reg control
(Normal operation)
FB
When FB falls below the threshold voltage (REF), a drop
3
is detected, activating the H REG CONTROLLA system.
REF
tON=
HG
REF
1
×
VIN
f
[sec]・・・(1)
HG output is determined by the formula above.
LG
(VOUT drops due to a rapid load change)
FB
When FB (VOUT) drops due to a rapid load change, and
the voltage remains below REF after the programmed
tON time interval has elapsed, the system quickly
restores VOUT by extending the tON time, improving
transient response.
REF
Io
TON+α
HG
LG
●Timing Chart
・Soft Start Function
Soft start is utilized when the EN pin is set high. Current
control takes effect at startup, enabling a moderate
“ramping start” on the output voltage. Soft start timing
and input current are determined via formula (2) and (3)
below.
EN
TSS(ON)
Soft start time:
REF
Tss(ON)= 50kΩ×Css [sec] ・・・(2)
VOUT
Rush current:
IIN =
IIN
Co×VOUT
Tss
[A] ・・・(3)
(Css: Soft start capacitor; Co: Output capacitor)
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10/18
2010.07 - Rev.A
Technical Note
BD9536FV
●Timing Chart
・Over current protection circuit
tON
tON
tON
tON
During normal operation, when VOUT falls below REF,
HG switches high during for the period of time tON (P8).
However, if the current through the inductor exceeds the
ILIMIT threshold, HG will switch off.
After the MAX ON TIME period elapses, HG switches
high again if the output voltage is lower than the
specified voltage level, and if IL is lower than the ILIMIT
level.
HG
LG
IL
・Timer Latch Type Short Circuit Protection
REF×0.8
Short protection engages when output falls to or below
REF x 0.8. When the programmed time period elapses,
output is latched off to prevent damage to the IC. Output
voltage can be restored either by reconnecting the EN pin
or disabling UVLO. Short circuit protection time is
determined via formula (4) below.
FB
TSCP
Delay setting voltage
1.2V
SCP
Short protection time setting
Tscp=
EN/UVLO
1.2(V)×CSCP
2 µA(typ)
[sec] ・・・(4)
・Output Over Voltage Protection
When output voltage rises to or above REF x 1.2, output
over-voltage protection engages after the set time TSCP/8
has elapsed. During this protection period, the low-side
FET opens completely for maximum reduction of output
voltage (LG = high, HG = low). Output voltage can be
restored either by reconnecting the EN pin or disabling
UVLO.
REF×1.2
VOUT
HG
LG
Switching
SCP
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Delay setting voltage
1.2V
11/18
2010.07 - Rev.A
Technical Note
BD9536FV
●External Component Selection
1. Inductor (L) selection
The inductance value has a major influence on output ripple current.
As formula (5) below indicates, the greater the inductance or
switching frequency, the lower the ripple current.
ΔIL
ΔIL=
VIN
L×VIN×f
[A]・・・(5)
The proper output ripple current setting is about 30% of maximum
output current.
IL
HG
(VIN-VOUT)×VOUT
VOUT
SW
ΔIL=0.3×IOUTmax. [A]・・・(6)
L
Co
LG
L=
(VIN-VOUT)×VOUT
ΔIL×VIN×f
[H]・・・(7)
(ΔIL: output ripple current; f: switch frequency)
Output Ripple Current
※Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease
system efficiency. When selecting an inductor, be sure to allow enough margin to assure that peak current does not
exceed the inductor’s rated current value.
※To minimize possible inductor damage and maximize efficiency, choose a inductor with a low (DCR, ACR) resistance.
2. Output Capacitor (CO) Selection
VIN
HG
VOUT
SW
L
When determining a proper output capacitor, be sure to factor in the equivalent
series resistance and equivalent series inductance required to set the output ripple
voltage to 20mV or more. Also, make sure the capacitor’s voltage rating is high
enough for the set output voltage (including ripple).
Output ripple voltage is determined as in formula (8) below.
ESR
LG
ESL
Co
ΔVOUT=ΔIL×ESR+ESL×ΔIL/TON・・・(8)
(ΔIL: Output ripple current; ESR: CO equivalent series resistance,
ESL: equivalent series inductance)
Output Capacitor
Also, give due consideration to the conditions in formula (9) below for output capacitance, bearing in mind that output rise
time must be established within the soft start time frame:
Tss: Soft start time
TSS×(Limit-IOUT)
Co≦
Limit: Over current detection
・・・(9)
VOUT
IOUT : Output current
Note: an improper output capacitor may cause startup malfunctions.
3. Input Capacitor (Cin) Selection
In order to prevent transient spikes in voltage, the input capacitor selected must
have a low enough ESR resistance to fully support a large ripple current on the
output. The formula for ripple current IRMS is given in equation (10) below:
VIN
Cin
HG
VOUT
SW
L
Co
LG
VOUT (VIN-VOUT)
[A]・・・(10)
VIN
IOUT
Where VIN=2×VOUT, IRMS =
2
IRMS = IOUT ×
Input Capacitor
A low-ESR capacitor is recommended to reduce ESR loss and maximize efficiency.
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12/18
2010.07 - Rev.A
Technical Note
BD9536FV
4. MOSFET Selection
Main MOSFET power dissipation is computed as follows:
VIN
Pmain = PRON + PGATE + PTRAN
main switch
=
VOUT
2
VOUT ×RON×IOUT2+Qg(Hi)×f×5VReg+ VIN ×Crss×IOUT×f
VIN
IDRIVE
・・・(11)
L
(Ron: On-resistance of FET; Qg: FET gate capacitance;
f: Switching frequency; Crss: FET inverse transfers function;
IDRIVE: Gate peak current)
Co
synchronous switch
Synchronous MOSFET power dissipation is computed as follows:
Psyn = PRON + PGATE
=
VIN-VOUT
VIN
×RON×IOUT2+5VReg×f×VDD
・・・(12)
Qg loss is also incurred as internal power dissipation in the IC:
= PIC(DRIVE) = Qg(Hi)×f + Qg(Low)×f
×(VIN-5VReg) ・・・(13)
For example:
If Qg(Hi) = 20nq, Qg(Low) = 50nq, f = 300kHz,
PIC(DRIVE) =
20n×300k +50n×300k
×(12-5)
= 0.147W
5. Determining Detection Resistance
The over-current protection function is controlled via the voltage detected
between the SW and PGND pins – i.e., the ON-resistance of the
synchronous FET. The current limit value is determined by formula (14)
below:
VIN
L
VOUT
SW
ILIM=
10k
RILIM ×RON
[A]・・・(14)
Co
RILIM
PGND
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© 2010 ROHM Co., Ltd. All rights reserved.
(RILIM: Resistance for setting over-current protection limit,
RON: Low side FET on-resistance)
13/18
2010.07 - Rev.A
Technical Note
BD9536FV
6. Setting frequency
【1,2ch】
The on-time (TON) at steady state is determined by
the resistance value connected to the FS pin.
However, the actual SW rise/fall time is influenced by
the gate capacitance and switching speed of the
external MOSFET, thereby increasing TON. The
frequency is determined by the following formula after
TON, input current and the REF voltage are fixed.
2500
from top VIN=7.5V
12V
15V
2000
Freq =
Ton[ns]
1500
1000
0
50
100
150
200
VIN×TON
250
RFS [kΩ]
7. Output Voltage Setting
The IC will try to maintain output voltage such that VREF≒VFB.
However, the actual output voltage will also reflect the average ripple voltage value.
The output voltage is set via a resistive voltage divider between the output and the FB pin.
is given in (16) below:
Output voltage=
REF
R1+R2
R2
× REF +
H3 RegTM
CONTROLLA
1
2
R
・・・(15)
Consequently, the actual overall frequency becomes
lower than the value obtained by the formula above.
TON is also influenced by “dead time,” which occurs
when the output current approaches the 0A range in
continuous mode; frequency in this output range will
also be lower than the set oscillation frequency.
It is recommended to check the steady-state frequency
while pulling a large current (but without saturating the
output inductor).
500
0
VOUT
The formula for output voltage
×ΔIL×ESR・・・(16)
V IN
Q
Output voltage
Driver
S
ESR
Circuit
FB
R1
C
1
Radd(for Low Ripple)
R2
Cadd (for Low Ripple)
It is recommended that R1 and C1 be connected in parallel to the FB pin.
In low output ripple applications (ΔV < 20 mV), add Radd and Cadd as shown in the above application circuit.
For value settings, refer to the tool provided separately.
REF2 voltage is fixed at 0.65 V; however, REF1 voltage can be adjusted via the CTL1 and CTL2 pins.
REF1 voltage setting table
CTL1
CTL2
REF1
L
L
0.625V
H
L
0.600V
L
H
0.650V
H
H
0.625V
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14/18
2010.07 - Rev.A
Technical Note
BD9536FV
●I/O Equivalent Circuits
16pin, 27pin (BOOT1/2)
HG
SW
15pin, 28pin (EN1/2)
6pin, 9pin (FS1/2)
20pin (5VReg)
1pin 14pin(CTL 1/2)
5VReg
4pin, 11pin (REF 1/2)
BOOT 1/2
26pin, 17pin (HG1/2)
BOOT
25pin, 18pin (SW1/2)
24pin, 19pin (LG1/2)
BOOT
BOOT
VDD
HG
100KΩ
300KΩ
SW
300K
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15/18
2010.07 - Rev.A
Technical Note
BD9536FV
●Operation Notes
1) Absolute Maximum Ratings
Use of the IC in excess of absolute maximum ratings (such as the input voltage or operating temperature range) may
result in damage to the IC. Assumptions should not be made regarding the state of the IC (e.g., short mode or open mode)
when such damage is suffered. If operational values are expected to exceed the maximum ratings for the device, consider
adding protective circuitry (such as fuses) to eliminate the risk of damaging the IC.
2) Power Supply Polarity
Connecting the power supply in reverse polarity can cause damage to the IC. Take precautions when connecting the
power supply lines. An external power diode can be added.
3) Power Supply Lines
In order to minimize noise, PCB layout should be designed such that separate, low-impedance power lines are routed to
the digital and analog blocks. Additionally, a coupling capacitor should be inserted between all power input pins and the
ground terminal. If electrolytic capacitors are used, keep in mind that their capacitance characteristics are reduced at low
temperatures.
4) GND voltage
The potential of the GND pin must be the minimum potential in the system in all operating conditions.
5) Thermal design
Use a thermal design that allows for a sufficient margin for power dissipation (Pd) under actual operating conditions.
6) Inter-pin Shorts and Mounting Errors
Use caution when orienting and positioning the IC for mounting on printed circuit boards. Improper mounting may result in
damage to the IC. Shorts between output pins or between output pins and the power supply and GND pins caused by poor
soldering or foreign objects may result in damage to the IC.
7) Operation in Strong Electromagnetic Fields
Using this product in strong electromagnetic fields may cause IC malfunction. Caution should be exercised in applications
where strong electromagnetic fields may be present.
8) ASO - Area of Safe Operation
When using the IC, ensure that operating conditions do not exceed absolute maximum ratings or ASO of the output
transistors.
9) Thermal shutdown (TSD) circuit
The IC incorporates a built-in thermal shutdown circuit, which is designed to turn the IC off completely in the event of
thermal overload. It is not designed to protect the IC from damage or guarantee its operation. ICs should not be used
after this function has activated, or in applications where the operation of this circuit is assumed.
TSD ON Temp. [°C] (typ.)
Hysteresis Temp. [°C] (typ.)
BD9536FV
175
15
10) Testing on application boards
When testing the IC on an application board, connecting a capacitor directly to a low-impedance pin may subject the IC to
stress. Always discharge capacitors completely after each process or step. The IC’s power supply should always be
turned off completely before connecting or removing it from a jig or fixture during the evaluation process. To prevent
damage from static discharge, ground the IC during assembly and use similar precautions during transport and storage.
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16/18
2010.07 - Rev.A
Technical Note
BD9536FV
11) Regarding input pins of the IC
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them isolated.
PN junctions are formed at the intersection of these P layers with the N layers of other elements, creating parasitic diodes
and/or transistors. For example (refer to the figure below):
・When GND > Pin A and GND > Pin B, the PN junction operates as a parasitic diode
・When GND > Pin B, the PN junction operates as a parasitic transistor
Parasitic diodes occur inevitably in the structure of the IC, and the operation of these parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, conditions that cause these diodes to
operate, such as applying a voltage lower than the GND voltage to an input pin (and thus to the P substrate) should be
avoided.
Resistor
Transistor (NPN)
Pin A
Pin B
B
C
Pin B
E
Pin A
N P
+
N
P
P
N
+
N
P
Parasitic
element
P substrate
Parasitic element
B
N
P+
P
C
+
N
P substrate
E
Parasitic
element
Other adjacent elements
GND
GND
Parasitic element
GND
GND
Example of IC structure
12) Ground Wiring Pattern
When using both small-signal and large-current GND traces, the two ground traces should be routed separately but
connected to a single ground potential within the application in order to avoid variations in the small-signal ground caused
by large currents. Also ensure that the GND traces of external components do not cause variations on GND voltage.
●Power Dissipation
1.2
Mounted on board
70mm×70mm×1.6mm glass-epoxy PCB
θj-a=117.6℃/W
1.06W
Power Dissipation
Pd （W)
1
0.8W
0.8
Only IC
θj-a=156.3℃/W
0.6
100℃
0.4
0.2
0
0
25
50
75
100
125
150
Temperature Atmosphere Ta(℃)
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17/18
2010.07 - Rev.A
Technical Note
BD9536FV
●Ordering part number
B
D
9
Part No.
5
3
6
F
Part No.
V
-
Package
F: SSSOP-B28
E
2
Packaging and forming specification
E2: Embossed tape and reel
SSOP-B28
Tape
Embossed carrier tape
28
Quantity
2000pcs
15
Direction
of feed
0.3Min.
5.6 ± 0.2
7.6 ± 0.3
<Tape and Reel information>
10 ± 0.2
(MAX 10.35 include BURR)
The direction is the 1pin of product is at the upper left when you hold
( reel on the left hand and you pull out the tape on the right hand
)
14
0.15 ± 0.1
0.1
1.15 ± 0.1
1
E2
0.1
0.65
0.22 ± 0.1
1pin
Reel
(Unit : mm)
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18/18
Direction of feed
∗ Order quantity needs to be multiple of the minimum quantity.
2010.07 - Rev.A
Notice
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specified herein is subject to change for improvement without notice.
The content specified herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specifications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specified in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specified herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specified in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, office-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specified in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, fire or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, fire control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuelcontroller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specified herein that may
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More detail product informations and catalogs are available, please contact us.
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R1010A