Power Architecture® 32-bit MCU Fact Sheet Qorivva MPC5554 Family For engine management applications Target Applications • Multipoint fuel injection control • Electronically controlled transmissions • Direct diesel injection • Gasoline direct injection • Avionics • High-end motion control • Military • Heavy industries Overview The Qorivva MPC5554 32-bit embedded controller built on Power Architecture® technology is ideal for any application that requires complex, real-time control. It offers system performance of up to five times that of its MPC500 predecessors while providing the reliability and familiarity of Power Architecture technology. The Qorivva MPC5554 MCU helps you face the dual pressures of controlling costs while designing for increasingly complex applications. This high-performance MCU delivers more on-chip functionality than the MPC500 family, the largest amount of embedded flash offered from Freescale to date, enhanced timer systems and a peripheral set specifically tailored for automotive and industrial applications. The Qorivva MPC5554 MCU also offers a migration path from the market-leading MPC500 family of 32-bit MCUs, facilitating reuse of legacy software architectures. MPC5554: Qorivva MCU for Powertrain MPC5554: Qorivva 32-bit32-bit MCU for Powertrain ApplicationsApplications JTAG GPIO NEXUS 2x CAN 3x DSPI 32-ch. eTPU 1x 40-ch. ADC 2x eSCI 19 KB SRAM 24-ch. eMIOS 32-ch. DMA 1 MB Flash 64 KB SRAM SPE e200z6 MMU 16-bit External Bus The e200z6 Core Input/Output Development Support • High-performance 132 MHz 32-bit • 40-ch. dual enhanced queued analog- A comprehensive suite of hardware Book E-compliant core built on Power to-digital converter (eQADC)—up to and software development tools for the Architecture technology 12-bit resolution and up to 1.25 ms Qorivva MPC5554 MCU is available to conversions, six queues with triggering help simplify and speed system design. and DMA support Development support is available through • Memory management unit (MMU) with 32-entry fully associative translation lookaside buffer • Signal processing extension (SPE): DSP, SIMD and floating point capabilities Memory • 2 MB of embedded flash memory with error correction coding (ECC) and read while write capability • 64 KB on-chip static RAM with ECC • 32 KB of cache (with line locking) that can be configured as additional RAM System • Two enhanced time processor units (eTPUs) with 64 input/output (I/O) channels and 19 KB of designated SRAM • 64-ch. enhanced direct memory access controller • Interrupt controller capable of handling 308 selectable-priority interrupt sources • Frequency modulated phase-locked loop • Four deserial serial peripheral interface (DSPI) modules—16 bits wide up to six chip selects each • Three controller area network (CAN) modules with 64 buffers each • Two enhanced serial communication interface (eSCI) modules • 24-ch. enhanced multiple I/O system (EMIOS) with unified channels Benefits Excellent System Performance Cost Effectiveness Integrates more functionality on chip. evaluation kits to offer a uniquely catered outof-box experience. Committed to you for the long run, Freescale understands your top priority: design higher performance products in less time and at a reduced total cost. The Qorivva MPC55xx family enables you to buy as much, or as little and resources already invested in the Power Architecture instruction set architecture won’t be wasted. Functions previously performed in external analog hardware have been moved into software. • Nexus IEEE-ISTO 5001™ Class 3+ Scalability and Compatibility +125 ºC Software and iSYSTEM both provide individual path from the MPC500 family means time requirements through intelligent subsystems. • Optional temperature range: –55 ºC to CodeWarrior compiler offering, Green Hills product development goals. Its migration Supports multiple protocols and customer • Temperature range: –40 ºC to +125 ºC standard evaluation kit that comes with the features and upgraded interrupt control. • MPC500-compatible external bus interface • 416-pin PBGA package specific development tools. In addition to the performance as you need to help meet your Flexibility 1.5 V core environments, as well as more advanced or Architecture core includes integrated DSP management • 5/3.3 V IO, 5 V ADC, 3.3/1.8 V bus, providing compilers, debuggers, simulation Book E superscalar compliant with the Power to assist in electromagnetic interference multicore debug capabilities leading independent tool vendors, Core- and platform-based architecture enables simple derivative development. Leverages past engineering investments and existing knowledge of Power Architecture technology to create a solid migration path for MPC500 users. Ease of Use 5 V interfaces to allow use of legacy sensor and I/O systems. For more information about the MPC5554 or the MPC55xx family, visit freescale.com/Qorivva Freescale, the Freescale logo and Qorivva are trademarks of Freescale Semiconductor, Inc., Reg. U.S. Pat. & Tm. Off. The Power Architecture and Power.org word marks and the Power and Power.org logos and related marks are trademarks and service marks licensed by Power.org. All other product or service names are the property of their respective owners. © 2005, 2008, 2010, 2012 Freescale Semiconductor, Inc. Document Number: MPC5554FAMFS REV 3