Renesas H8S/2668 16-bit single-chip microcomputer Datasheet

REJ09B0281-0300
The revision list can be viewed directly by
clicking the title page.
The revision list summarizes the locations of
revisions and additions. Details should always
be checked by referring to the relevant text.
16
H8S/2668 Group, H8S/2667 F-ZTAT
Hardware Manual
Renesas 16-Bit Single-Chip Microcomputer
H8S Family/H8S/2600 Series
H8S/2667
Rev. 3.00
Revision Date: Feb 22, 2006
HD64F2667
Keep safety first in your circuit designs!
1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and
more reliable, but there is always the possibility that trouble may occur with them. Trouble with
semiconductors may lead to personal injury, fire or property damage.
Remember to give due consideration to safety when making your circuit designs, with appropriate
measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or
(iii) prevention against any malfunction or mishap.
Notes regarding these materials
1. These materials are intended as a reference to assist our customers in the selection of the Renesas
Technology Corp. product best suited to the customer's application; they do not convey any license
under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or
a third party.
2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any thirdparty's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or
circuit application examples contained in these materials.
3. All information contained in these materials, including product data, diagrams, charts, programs and
algorithms represents information on products at the time of publication of these materials, and are
subject to change by Renesas Technology Corp. without notice due to product improvements or
other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or
an authorized Renesas Technology Corp. product distributor for the latest product information
before purchasing a product listed herein.
The information described here may contain technical inaccuracies or typographical errors.
Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising
from these inaccuracies or errors.
Please also pay attention to information published by Renesas Technology Corp. by various means,
including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com).
4. When using any or all of the information contained in these materials, including product data,
diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total
system before making a final decision on the applicability of the information and products. Renesas
Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the
information contained herein.
5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or
system that is used under circumstances in which human life is potentially at stake. Please contact
Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when
considering the use of a product contained herein for any specific purposes, such as apparatus or
systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use.
6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in
whole or in part these materials.
7. If these products or technologies are subject to the Japanese export control restrictions, they must
be exported under a license from the Japanese government and cannot be imported into a country
other than the approved destination.
Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the
country of destination is prohibited.
8. Please contact Renesas Technology Corp. for further details on these materials or the products
contained therein.
Rev. 3.00 Feb 22, 2006 page ii of xl
General Precautions on Handling of Product
1. Treatment of NC Pins
Note: Do not connect anything to the NC pins.
The NC (not connected) pins are either not connected to any of the internal circuitry or are
used as test pins or to reduce noise. If something is connected to the NC pins, the
operation of the LSI is not guaranteed.
2. Treatment of Unused Input Pins
Note: Fix all unused input pins to high or low level.
Generally, the input pins of CMOS products are high-impedance input pins. If unused pins
are in their open states, intermediate levels are induced by noise in the vicinity, a passthrough current flows internally, and a malfunction may occur.
3. Processing before Initialization
Note: When power is first supplied, the product’s state is undefined.
The states of internal circuits are undefined until full power is supplied throughout the
chip and a low level is input on the reset pin. During the period where the states are
undefined, the register settings and the output state of each pin are also undefined. Design
your system so that it does not malfunction because of processing while it is in this
undefined state. For those products which have a reset function, reset the LSI immediately
after the power supply has been turned on.
4. Prohibition of Access to Undefined or Reserved Addresses
Note: Access to undefined or reserved addresses is prohibited.
The undefined or reserved addresses may be used to expand functions, or test registers
may have been be allocated to these addresses. Do not access these registers; the system’s
operation is not guaranteed if they are accessed.
Rev. 3.00 Feb 22, 2006 page iii of xl
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Main Revisions in This Edition
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
5. Contents
6. Overview
7. Description of Functional Modules
•
CPU and System-Control Modules
•
On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
8. List of Registers
9. Electrical Characteristics
10. Appendix
11. Index
Rev. 3.00 Feb 22, 2006 page iv of xl
Preface
The H8S/2668 Group are microcomputers (MCU) made up of the H8S/2600 CPU employing
Renesas’ original architecture as their cores, and the peripheral functions required to configure a
system.
The H8S/2600 CPU has an internal 32-bit configuration, sixteen 16-bit general registers, and a
simple and optimized instruction set for high-speed operation. The H8S/2600 CPU can handle a
16-Mbyte linear address space.
This LSI is equipped with data transfer controller (DTC) bus masters, ROM and RAM memory, a
16-bit timer pulse unit (TPU), a programmable pulse generator (PPG), an 8-bit timer (TMR), a
watchdog timer (WDT), a serial communication interface (SCI and IrDA), a 10-bit A/D converter,
an 8-bit D/A converter, and I/O ports as on-chip peripheral modules required for system
configuration.
A high functionality bus controller is also provided, enabling fast and easy connection of DRAM,
SDRAM and other kinds of memory.
A single-power flash memory (F-ZTAT*) version and masked ROM version are available for
this LSI's ROM. The F-ZTAT version provides flexibility as it can be reprogrammed in no time to
cope with all situations from the early stages of mass production to full-scale mass production.
This is particularly applicable to application devices with specifications that will most probably
change.
This manual describes this LSI's hardware.
Note: * F-ZTAT is a trademark of Renesas Technology Corp.
Target Users: This manual was written for users who will be using this LSI in the design of
application systems. Target users are expected to understand the fundamentals of
electrical circuits, logical circuits, and microcomputers.
Objective:
This manual was written to explain the hardware functions and electrical
characteristics of this LSI to the target users.
Refer to the H8S/2600 Series, H8S/2000 Series Programming Manual for a
detailed description of the instruction set.
Notes on reading this manual:
In order to understand the overall functions of the chip
Read the manual according to the contents. This manual can be roughly categorized into parts
on the CPU, system control functions, peripheral functions and electrical characteristics.
Rev. 3.00 Feb 22, 2006 page v of xl
In order to understand the details of the CPU's functions
Read the H8S/2600 Series, H8S/2000 Series Programming Manual.
In order to understand the details of a register when its name is known
Read the index that is the final part of the manual to find the page number of the entry on the
register. The addresses, bits, and initial values of the registers are summarized in section 20,
List of Registers.
Examples:
Related Manuals:
Register name:
The following notation is used for cases when the same or a
similar function, e.g. 16-bit timer pulse unit or serial
communication, is implemented on more than one channel:
XXX_N (XXX is the register name and N is the channel
number)
Bit order:
The MSB is on the left and the LSB is on the right.
Number notation:
Binary is B'xxxx, hexadecimal is H'xxxx, decimal is xxxx.
Signal notation:
An overbar is added to a low-active signal: xxxx
The latest versions of all related manuals are available from our web site.
Please ensure you have the latest versions of all documents you require.
http://www.renesas.com
H8S/2668 Group manuals:
Document Title
Document No.
H8S/2668 Group Hardware Manual
This manual
H8S/2600 Series, H8S/2000 Series Programming Manual
REJ09B139
User's manuals for development tools:
Document Title
Document No.
H8S, H8/300 Series C/C++ Compiler, Assembler, Optimizing Linkage Editor
User's Manual
REJ10B0058
H8S, H8/300 Series Simulator/Debugger User's Manual
ADE-702-037
H8S, H8/300 Series High-performance Embedded Workshop,
High-performance Debugging Interface Tutorial
ADE-702-231
High-performance Embedded Workshop User's Manual
ADE-702-201
Rev. 3.00 Feb 22, 2006 page vi of xl
Main Revisions in This Edition
Item
Page
Revision (See Manual for Details)
All
—
All references to Hitachi, Hitachi, Ltd., Hitachi Semiconductors,
and other Hitachi brand names changed to Renesas
Technology Corp. Designation for categories changed from
“series” to “group”
5.6.5 DTC Activation
by Interrupt
95
Figure title amended
7.8.3 DTCE Bit
Setting
171
Description of “DMAC Transfer End Interrupt” deleted
Section 8 I/O Port
174
Table 8.1 amended
Figure 5.6 DTC and
Interrupt Controller
Table 8.1 Port
Functions
Port
Description
Port General I/O port
1 also functioning
as PPG outputs,
and TPU I/Os
Modes
1 and 5
Modes
2 and 6
Mode 7
Mode 4
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2
EXPE = 1
EXPE = 0
Input/
Output
Type
Schmitttriggered
input
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
Port General I/O port
2 also functioning
as PPG outputs,
TPU I/Os, and
interrupt inputs
P27/PO7/TIOCB5
P26/PO6/TIOCA5
Schmitttriggered
input
P25/PO5/TIOCB4
P24/PO4/TIOCA4
P23/PO3/TIOCD3
P22/PO2/TIOCC3
P21/PO1/TIOCB3
P20/PO0/TIOCA3
Port General I/O port
3 also functioning
as SCI I/Os
P35/SCK1
P34/SCK0
P33/RxD1
Opendrain
output
enable
P32/RxD0/IrRxD
P31/TxD1
P30/TxD0/IrTxD
Rev. 3.00 Feb 22, 2006 page vii of xl
Item
Page
Revision (See Manual for Details)
Section 8 I/O Port
175
Table 8.1 amended
Table 8.1 Port
Functions
Port
Description
Port General I/O port
5 also functioning
as interrupt inputs,
A/D converter
analog inputs, and
D/A converter
analog outputs
General I/O port
also functioning
as interrupt inputs,
A/D converter
analog inputs, and
SCI I/Os
Modes
1 and 5
Modes
2 and 6
Mode 7
Mode 4
EXPE = 1
EXPE = 0
P57/AN15/DA3/IRQ7
Input/
Output
Type
Schmitttriggered
input
when
used as
IRQ input
P56/AN14/DA2/IRQ6
P55/AN13/IRQ5
P54/AN12/IRQ4
P53/ADTRG/IRQ3
Schmitttriggered
input
when
used as
IRQ input
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
P65/TMO1
Port General I/O port
6 also functioning
P64/TMO0
as interrupt inputs,
P63/TMCI1
and TMR I/Os
P62/TMCI0
P61/TMRI1
P60/TMRI0
Port General I/O port
7
P75
P75
P75
P74
P74
P74
P73
P73
P73
P72
P72
P72
P71
P71
P71
P70
P70
P70
Port General I/O port
P85/IRQ5
8 as interrupt inputs P84/IRQ4
P85/IRQ5
P85/IRQ5
P84/IRQ4
P84/IRQ4
P83/IRQ3
P83/IRQ3
P83/IRQ3
P82/IRQ2
P82/IRQ2
P82/IRQ2
P81/IRQ1
P81/IRQ1
P81/IRQ1
P80/IRQ0
P80/IRQ0
P80/IRQ0
176
Port
Description
Port General I/O port
A also functioning
as address
outputs
Modes
1 and 5
Modes
2 and 6
Mode 7
Mode 4
EXPE = 1
PA7/A23
PA7/A23 PA7/A23
PA7
PA6/A22
PA6/A22 PA6/A22
PA6
PA5/A21
PA5/A21 PA5/A21
PA5
A20
PA4/A20 PA4/A20
PA4
A19
PA3/A19 PA3/A19
PA3
A18
PA2/A18 PA2/A18
PA2
A17
PA1/A17 PA1/A17
PA1
A16
PA0/A16 PA0/A16
PA0
177
Port
Description
Port General I/O port
H also functioning
as interrupt inputs
and bus control
I/Os
Rev. 3.00 Feb 22, 2006 page viii of xl
EXPE = 0
Modes
1 and 5
Modes
2 and 6
EXPE = 1
Input/
Output
Type
Built-in
input pullup MOS
Opendrain
output
enable
Mode 7
Mode 4
Schmitttriggered
input
when
used as
IRQ input
EXPE = 0
PH3/CS7/(IRQ7)
PH3/CS7/(IRQ7)
PH3/(IRQ7)
PH2/CS6/(IRQ6)
PH2/CS6/(IRQ6)
PH2/(IRQ6)
PH1/CS5
PH1/CS5
PH1
PH0/CS4
PH0/CS4
PH0
Input/
Output
Type
Schmitttriggered
input
when
used as
IRQ input
Item
Page
Revision (See Manual for Details)
9.3.9 Timer
Synchronous Register
(TSYR)
288
Bit 7 and 6 initial value amended
13.3.7 Serial Status
Register (SSR)
406
(Before)  → (After) 0
Normal Serial Communication Interface Mode (When SMIF in
SCMR is 0)
Bit 2 Clearing condition amended
• When the DTC is activated by a TXI interrupt and writes data
to TDR
13.3.9 Bit Rate
Register (BRR)
411
Table 13.2 amended
Mode
Bit Rate
Error
Table13.2
Relationships between
N Setting in BRR and
Bit Rate B
Smart Card
Interface Mode
14.3.2 A/D
477
Control/Status Register
(ADCSR)
Bit 7 Clearing condition amended
18.5.1 Notes on
Clock Pulse Generator
540
Description amended
Section 19 PowerDown Mode
544
EXDMAC and DMAC description deleted from table 19.1
566
Table amended
B=
φ × 106
{ B × S × 2φ × 10× (N + 1) – 1} × 100
6
S × 22n+1 × (N + 1)
Error (%) =
2n+1
• When the DTC is activated by an ADI interrupt and ADDR is
read
Note that the frequency of φ will be changed when setting
SCKCR or PLLCR while executing the external bus cycle with
the Write-data-buffer function.
Table 19.1 Operating
Mode
20.2 Register Bits
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MRA
SM1
SM0
DM1
DM0
MD1
MD0
DTS
Sz
DTC*7
SAR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MRB
CHNE
DISEL
CHNS
—
—
—
—
—
DAR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRA
CRB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
Rev. 3.00 Feb 22, 2006 page ix of xl
Item
Page
Revision (See Manual for Details)
20.2 Register Bits
567
Table amended
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
ITSR
—
—
—
—
—
—
—
—
INt
ITS7
ITS6
ITS5
ITS4
ITS3
ITS2
ITS1
ITS0
—
—
—
—
—
—
—
—
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PFCR2
—
—
—
—
ASOE
LWROE
—
—
PORT
SSIER
568
569
Description amended
BROMCRH, BROMCRL, DRAMCR, DRACCR, REFCR,
RTCNT, and RTCOR deleted from table
7
BCR (Before) ICIS2* → (After) ICIS2
570
Table amended
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
DTCERA
DTCEA7
DTCEA6
DTCEA5
DTCEA4
DTCEA3
DTCEA2
DTCEA1
DTCEA0
DTC
DTCERB
—
—
—
—
—
—
—
—
DTCERC
—
DTCEC6
DTCEC5
DTCEC4
DTCEC3
DTCEC2
DTCEC1
DTCEC0
DTCERD
DTCED7
DTCED6
DTCED5
DTCED4
DTCED3
DTCED2
DTCED1
DTCED0
DTCEE0
DTCERE
DTCEE7
DTCEE6
—
—
DTCEE3
DTCEE2
DTCEE1
DTCERF
—
—
—
—
DTCEF3
DTCEF2
DTCEF1
DTCEF0
DTCERG
DTCEG7
DTCEG6
—
—
—
—
—
—
DTVEC0
DTVECR
SWDTE
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
INTCR
—
—
INTM1
INTM0
NMIEG
—
—
—
IER
—
—
—
—
—
—
—
—
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
ISR
—
—
—
—
—
—
—
—
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
NDRH*
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
NDRL*1
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
NDRH*
—
—
—
—
NDR11
NDR10
NDR9
NDR8
NDRL*1
—
—
—
—
NDR3
NDR2
NDR1
NDR0
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
C/A/
GM*2
CHR/
3
BLK*
PE
O/E
STOP/
4
BCP1*
MP/
BRR_2
Bit7
Bit6
Bit5
Bit4
Bit3
SCR_2
TIE
RIE
TE
RE
MPIE
TDR_2
Bit7
Bit6
Bit5
Bit4
SSR_2
TDRE
RDRF
ORER
FER/
6
ERS*
RDR_2
Bit7
Bit6
Bit5
SCMR_2
—
—
—
1
1
572
SMR_2
Rev. 3.00 Feb 22, 2006 page x of xl
INT
PPG
Bit 1
Bit 0
Module
CKS1
CKS0
SCI_2,
Bit2
Bit1
Bit0
TEIE
CKE1
CKE0
Bit3
Bit2
Bit1
Bit0
PER
TEND
MPB
MPBT
Bit4
Bit3
Bit2
Bit1
Bit0
—
SDIR
SINV
—
SMIF
BCP0*
5
Smart card
interface_2
Item
Page
Revision (See Manual for Details)
20.2 Register Bits
573
Table amended
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
ADDRH
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
A/D
AD1
AD0
—
—
—
—
—
—
ADF
ADIE
ADST
—
CH3
CH2
CH1
CH0
ADCSR
574
ADCR
TRGS1
TRGS0
SCANE
SCANS
CKS1
CH3
—
—
DADR0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
FLMCR1
—
SWE
ESU
PSU
EV
PV
E
P
FLASH
FLMCR2
FLER
—
—
—
—
—
—
—
EBR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EBR2
—
—
EB13
EB12
EB11
EB10
EB9
EB8
D/A
(F-ZTAT
version )
575
Notes amended
Notes: 1. If the PCR setting specifies the same output trigger
for pulse output group 2 and pulse output group 3, the address
is H'FF4C. If the triggers are different, the NDRH address
corresponding to pulse output group 2 is H'FF4E and the NDRH
address corresponding to pulse output group 3 is H'FF4C. In
like manner, if the PCR setting specifies the same output trigger
for pulse output group 0 and pulse output group 1, the address
is H'FF4D. If the triggers are different, the NDRH address
corresponding to pulse output group 0 is H'FF4F and the NDRH
address corresponding to pulse output group 1 is H'FF4D.
2. Functions as C/A for SCI use, ...
3. Functions as CHR for SCI use, ...
4. Functions as STOP for SCI use, ...
5. Functions as MP for SCI use, ...
6. Functions as FER for SCI use, ...
7. Loaded in on-chip RAM. The bus width is 32 bits when the
DTC accesses this area as register information, and 16 bits
otherwise.
20.3 Register Stated
in Each Operating
Mode
576
578
582
Note *1 deleted
1
(Before) SEMR* → (After) SEMR
1
(Before) RAMER* → (After) RAMER
(Before) FLMCR1* → (After) FLMCR1
1
(Before) FLMCR2* → (After) FLMCR2
1
(Before) EBR1* → (After) EBR1
1
(Before) EBR2* → (After) EBR2
1
Rev. 3.00 Feb 22, 2006 page xi of xl
Item
Page
Revision (See Manual for Details)
21.1.6 Flash Memory
Characteristics
607
Table 21.12 amended
Table 21.12 Flash
Memory Characteristics
Item
Symbol
Min
Typ
Max
Programming time*1 *2 *4
tP
—
10
200
ms/
128 bytes
Erase time*1 *3 *6
tE
—
50
1000
ms/
128 bytes
Rewrite times
NWEC
100*1
10000*2 —
Times
Data retention time*3
tDRP
10
—
—
Years
Programming Wait time after SWE bit
setting*1
x
1
—
—
µs
Rev. 3.00 Feb 22, 2006 page xii of xl
Unit
Test
Conditions
Contents
Section 1 Overview .............................................................................................................
1.1
1.2
1.3
1
Features ............................................................................................................................. 1
Block Diagram .................................................................................................................. 2
Pin Description.................................................................................................................. 3
1.3.1 Pin Arrangement .................................................................................................. 3
1.3.2 Pin Arrangement in Each Operating Mode.......................................................... 4
1.3.3 Pin Functions ....................................................................................................... 10
Section 2 CPU ...................................................................................................................... 15
2.1
2.2
2.3
2.4
2.5
2.6
2.7
Features .............................................................................................................................
2.1.1 Differences between H8S/2600 CPU and H8S/2000 CPU ..................................
2.1.2 Differences from H8/300 CPU ............................................................................
2.1.3 Differences from H8/300H CPU..........................................................................
CPU Operating Modes ......................................................................................................
2.2.1 Normal Mode.......................................................................................................
2.2.2 Advanced Mode...................................................................................................
Address Space...................................................................................................................
Registers............................................................................................................................
2.4.1 General Registers .................................................................................................
2.4.2 Program Counter (PC) .........................................................................................
2.4.3 Extended Register (EXR) ....................................................................................
2.4.4 Condition-Code Register (CCR) ..........................................................................
2.4.5 Multiply-Accumulate Register (MAC) ................................................................
2.4.6 Initial Values of CPU Internal Registers..............................................................
Data Formats.....................................................................................................................
2.5.1 General Register Data Formats ............................................................................
2.5.2 Memory Data Formats .........................................................................................
Instruction Set ...................................................................................................................
2.6.1 Table of Instructions Classified by Function .......................................................
2.6.2 Basic Instruction Formats ....................................................................................
Addressing Modes and Effective Address Calculation .....................................................
2.7.1 Register Direct—Rn.............................................................................................
2.7.2 Register Indirect—@ERn ....................................................................................
2.7.3 Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)..............
2.7.4 Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn ..
2.7.5 Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32....................................
2.7.6 Immediate—#xx:8, #xx:16, or #xx:32 .................................................................
15
16
16
17
18
18
20
22
23
24
25
25
26
27
27
27
28
30
31
32
41
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43
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44
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2.8
2.9
2.7.7 Program-Counter Relative—@(d:8, PC) or @(d:16, PC)....................................
2.7.8 Memory Indirect—@@aa:8 ................................................................................
2.7.9 Effective Address Calculation .............................................................................
Processing States...............................................................................................................
Usage Note........................................................................................................................
2.9.1 Usage Notes on Bit-wise Operation Instructions .................................................
44
45
46
48
49
49
Section 3 MCU Operating Modes .................................................................................. 51
3.1
3.2
3.3
3.4
Operating Mode Selection ................................................................................................
Register Descriptions ........................................................................................................
3.2.1 Mode Control Register (MDCR) .........................................................................
3.2.2 System Control Register (SYSCR) ......................................................................
Operating Mode Descriptions ...........................................................................................
3.3.1 Mode 1 .................................................................................................................
3.3.2 Mode 2 .................................................................................................................
3.3.3 Mode 3 .................................................................................................................
3.3.4 Mode 4 .................................................................................................................
3.3.5 Mode 5 .................................................................................................................
3.3.6 Mode 6 .................................................................................................................
3.3.7 Mode 7 .................................................................................................................
3.3.8 Pin Functions .......................................................................................................
Memory Map in Each Operating Mode ............................................................................
51
52
52
52
54
54
54
54
54
55
55
55
56
57
Section 4 Exception Handling ......................................................................................... 59
4.1
4.2
4.3
4.4
4.5
4.6
4.7
4.8
Exception Handling Types and Priority ............................................................................
Exception Sources and Exception Vector Table ...............................................................
Reset..................................................................................................................................
4.3.1 Reset exception handling .....................................................................................
4.3.2 Interrupts after Reset............................................................................................
4.3.3 On-Chip Peripheral Functions after Reset Release ..............................................
Traces................................................................................................................................
Interrupts ...........................................................................................................................
Trap Instruction.................................................................................................................
Stack Status after Exception Handling..............................................................................
Usage Note........................................................................................................................
59
59
61
62
63
64
64
65
66
67
68
Section 5 Interrupt Controller .......................................................................................... 69
5.1
5.2
5.3
Features .............................................................................................................................
Input/Output Pins ..............................................................................................................
Register Descriptions ........................................................................................................
5.3.1 Interrupt Control Register (INTCR).....................................................................
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71
71
72
5.4
5.5
5.6
5.7
5.3.2 Interrupt Priority Registers A to K (IPRA to IPRK) ............................................
5.3.3 IRQ Enable Register (IER) ..................................................................................
5.3.4 IRQ Sense Control Registers (ISCR) ...................................................................
5.3.5 IRQ Status Register (ISR)....................................................................................
5.3.6 IRQ Pin Select Register (ITSR) ...........................................................................
5.3.7 Software Standby Release IRQ Enable Register (SSIER) ...................................
Interrupt Sources...............................................................................................................
5.4.1 External Interrupts ...............................................................................................
5.4.2 Internal Interrupts.................................................................................................
Interrupt Exception Handling Vector Table......................................................................
Interrupt Control Modes and Interrupt Operation .............................................................
5.6.1 Interrupt Control Mode 0 .....................................................................................
5.6.2 Interrupt Control Mode 2 .....................................................................................
5.6.3 Interrupt Exception Handling Sequence ..............................................................
5.6.4 Interrupt Response Times ....................................................................................
5.6.5 DTC Activation by Interrupt................................................................................
Usage Notes ......................................................................................................................
5.7.1 Contention between Interrupt Generation and Disabling.....................................
5.7.2 Instructions that Disable Interrupts ......................................................................
5.7.3 Times when Interrupts are Disabled ....................................................................
5.7.4 Interrupts during Execution of EEPMOV Instruction..........................................
5.7.5 Change of IRQ Pin Select Register (ITSR) Setting .............................................
5.7.6 Note on IRQ Status Register (ISR) ......................................................................
73
75
76
79
80
81
81
81
82
83
87
87
89
91
93
94
96
96
97
97
98
98
98
Section 6 Bus Controller (BSC) ...................................................................................... 99
6.1
6.2
6.3
6.4
Features .............................................................................................................................
Input/Output Pins ..............................................................................................................
Register Descriptions ........................................................................................................
6.3.1 Bus Width Control Register (ABWCR)...............................................................
6.3.2 Access State Control Register (ASTCR) .............................................................
6.3.3 Wait Control Registers AH, AL, BH, and BL
(WTCRAH, WTCRAL, WTCRBH, and WTCRBL)...........................................
6.3.4 Read Strobe Timing Control Register (RDNCR) ................................................
6.3.5 CS Assertion Period Control Registers H, L (CSACRH, CSACRL)...................
6.3.6 Bus Control Register (BCR) ................................................................................
6.3.7 Refresh Timer Counter (RTCNT)........................................................................
6.3.8 Refresh Time Constant Register (RTCOR) .........................................................
Bus Control .......................................................................................................................
6.4.1 Area Division .......................................................................................................
6.4.2 Bus Specifications................................................................................................
6.4.3 Memory Interfaces ...............................................................................................
99
101
102
102
103
103
108
110
112
114
114
114
114
116
118
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6.4.4 Chip Select Signals ..............................................................................................
Basic Bus Interface ...........................................................................................................
6.5.1 Data Size and Data Alignment.............................................................................
6.5.2 Valid Strobes........................................................................................................
6.5.3 Basic Timing........................................................................................................
6.5.4 Wait Control ........................................................................................................
6.5.5 Read Strobe (RD) Timing ....................................................................................
6.5.6 Extension of Chip Select (CS) Assertion Period..................................................
6.6 Idle Cycle ..........................................................................................................................
6.6.1 Operation .............................................................................................................
6.6.2 Pin States in Idle Cycle ........................................................................................
6.7 Write Data Buffer Function ..............................................................................................
6.8 Bus Release.......................................................................................................................
6.8.1 Operation .............................................................................................................
6.8.2 Pin States in External Bus Released State............................................................
6.8.3 Transition Timing ................................................................................................
6.9 Bus Arbitration..................................................................................................................
6.9.1 Operation .............................................................................................................
6.9.2 Bus Transfer Timing ............................................................................................
6.10 Bus Controller Operation in Reset ....................................................................................
6.11 Usage Notes ......................................................................................................................
6.11.1 External Bus Release Function and All-Module-Clocks-Stopped Mode.............
6.11.2 External Bus Release Function and Software Standby ........................................
6.11.3 BREQO Output Timing .......................................................................................
6.5
119
120
120
121
122
130
132
132
134
134
137
138
139
139
140
141
142
142
142
143
143
143
143
144
Section 7 Data Transfer Controller (DTC) ................................................................... 145
7.1
7.2
7.3
7.4
7.5
Features .............................................................................................................................
Register Descriptions ........................................................................................................
7.2.1 DTC Mode Register A (MRA) ............................................................................
7.2.2 DTC Mode Register B (MRB).............................................................................
7.2.3 DTC Source Address Register (SAR)..................................................................
7.2.4 DTC Destination Address Register (DAR)..........................................................
7.2.5 DTC Transfer Count Register A (CRA) ..............................................................
7.2.6 DTC Transfer Count Register B (CRB)...............................................................
7.2.7 DTC Enable Registers A to H (DTCERA to DTCERH) .....................................
7.2.8 DTC Vector Register (DTVECR)........................................................................
Activation Sources ............................................................................................................
Location of Register Information and DTC Vector Table ................................................
Operation ..........................................................................................................................
7.5.1 Normal Mode.......................................................................................................
7.5.2 Repeat Mode ........................................................................................................
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146
147
149
149
149
150
150
150
151
152
153
156
159
160
7.6
7.7
7.8
7.5.3 Block Transfer Mode ...........................................................................................
7.5.4 Chain Transfer .....................................................................................................
7.5.5 Interrupt Sources..................................................................................................
7.5.6 Operation Timing.................................................................................................
7.5.7 Number of DTC Execution States........................................................................
Procedures for Using DTC................................................................................................
7.6.1 Activation by Interrupt.........................................................................................
7.6.2 Activation by Software ........................................................................................
Examples of Use of the DTC ............................................................................................
7.7.1 Normal Mode.......................................................................................................
7.7.2 Chain Transfer .....................................................................................................
7.7.3 Chain Transfer when Counter = 0........................................................................
7.7.4 Software Activation .............................................................................................
Usage Notes ......................................................................................................................
7.8.1 Module Stop Mode Setting ..................................................................................
7.8.2 On-Chip RAM .....................................................................................................
7.8.3 DTCE Bit Setting.................................................................................................
161
162
163
163
164
166
166
166
167
167
167
168
170
171
171
171
171
Section 8 I/O Ports .............................................................................................................. 173
8.1
8.2
8.3
8.4
8.5
Port 1.................................................................................................................................
8.1.1 Port 1 Data Direction Register (P1DDR).............................................................
8.1.2 Port 1 Data Register (P1DR)................................................................................
8.1.3 Port 1 Register (PORT1)......................................................................................
8.1.4 Pin Functions .......................................................................................................
Port 2.................................................................................................................................
8.2.1 Port 2 Data Direction Register (P2DDR).............................................................
8.2.2 Port 2 Data Register (P2DR)................................................................................
8.2.3 Port 2 Register (PORT2)......................................................................................
8.2.4 Pin Functions .......................................................................................................
Port 3.................................................................................................................................
8.3.1 Port 3 Data Direction Register (P3DDR).............................................................
8.3.2 Port 3 Data Register (P3DR)................................................................................
8.3.3 Port 3 Register (PORT3)......................................................................................
8.3.4 Port 3 Open Drain Control Register (P3ODR).....................................................
8.3.5 Port Function Control Register 2 (PFCR2) ..........................................................
8.3.6 Pin Functions .......................................................................................................
Port 4.................................................................................................................................
8.4.1 Port 4 Register (PORT4)......................................................................................
Port 5.................................................................................................................................
8.5.1 Port 5 Data Direction Register (P5DDR).............................................................
8.5.2 Port 5 Data Register (P5DR)................................................................................
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178
179
179
180
188
188
189
189
190
198
198
199
199
200
200
201
203
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204
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8.5.3 Port 5 Register (PORT5)......................................................................................
8.5.4 Pin Functions .......................................................................................................
8.6 Port 6.................................................................................................................................
8.6.1 Port 6 Data Direction Register (P6DDR).............................................................
8.6.2 Port 6 Data Register (P6DR)................................................................................
8.6.3 Port 6 Register (PORT6)......................................................................................
8.6.4 Pin Functions .......................................................................................................
8.7 Port 7.................................................................................................................................
8.7.1 Port 7 Data Direction Register (P7DDR).............................................................
8.7.2 Port 7 Data Register (P7DR)................................................................................
8.7.3 Port 7 Register (PORT7)......................................................................................
8.8 Port 8.................................................................................................................................
8.8.1 Port 8 Data Direction Register (P8DDR).............................................................
8.8.2 Port 8 Data Register (P8DR)................................................................................
8.8.3 Port 8 Register (PORT8)......................................................................................
8.8.4 Pin Functions .......................................................................................................
8.9 Port A................................................................................................................................
8.9.1 Port A Data Direction Register (PADDR) ...........................................................
8.9.2 Port A Data Register (PADR) ..............................................................................
8.9.3 Port A Register (PORTA) ....................................................................................
8.9.4 Port A Pull-Up MOS Control Register (PAPCR) ................................................
8.9.5 Port A Open Drain Control Register (PAODR)...................................................
8.9.6 Port Function Control Register 1 (PFCR1) ..........................................................
8.9.7 Pin Functions .......................................................................................................
8.9.8 Port A Input Pull-Up MOS States........................................................................
8.10 Port B ................................................................................................................................
8.10.1 Port B Data Direction Register (PBDDR)............................................................
8.10.2 Port B Data Register (PBDR) ..............................................................................
8.10.3 Port B Register (PORTB) ....................................................................................
8.10.4 Port B Pull-Up MOS Control Register (PBPCR).................................................
8.10.5 Pin Functions .......................................................................................................
8.10.6 Port B Input Pull-Up MOS States ........................................................................
8.11 Port C ................................................................................................................................
8.11.1 Port C Data Direction Register (PCDDR)............................................................
8.11.2 Port C Data Register (PCDR) ..............................................................................
8.11.3 Port C Register (PORTC) ....................................................................................
8.11.4 Port C Pull-Up MOS Control Register (PCPCR).................................................
8.11.5 Pin Functions .......................................................................................................
8.11.6 Port C Input Pull-Up MOS States ........................................................................
8.12 Port D................................................................................................................................
8.12.1 Port D Data Direction Register (PDDDR) ...........................................................
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205
208
208
209
209
210
212
212
213
213
214
214
215
215
216
217
218
219
219
220
220
220
222
222
223
223
224
224
225
225
226
226
227
227
228
228
229
229
230
230
8.13
8.14
8.15
8.16
8.12.2 Port D Data Register (PDDR) ..............................................................................
8.12.3 Port D Register (PORTD) ....................................................................................
8.12.4 Port D Pull-up Control Register (PDPCR)...........................................................
8.12.5 Pin Functions .......................................................................................................
8.12.6 Port D Input Pull-Up MOS States........................................................................
Port E ................................................................................................................................
8.13.1 Port E Data Direction Register (PEDDR) ............................................................
8.13.2 Port E Data Register (PEDR)...............................................................................
8.13.3 Port E Register (PORTE).....................................................................................
8.13.4 Port E Pull-up Control Register (PEPCR)............................................................
8.13.5 Pin Functions .......................................................................................................
8.13.6 Port E Input Pull-Up MOS States ........................................................................
Port F.................................................................................................................................
8.14.1 Port F Data Direction Register (PFDDR) ............................................................
8.14.2 Port F Data Register (PFDR) ...............................................................................
8.14.3 Port F Register (PORTF) .....................................................................................
8.14.4 Pin Functions .......................................................................................................
Port G................................................................................................................................
8.15.1 Port G Data Direction Register (PGDDR) ...........................................................
8.15.2 Port G Data Register (PGDR) ..............................................................................
8.15.3 Port G Register (PORTG) ....................................................................................
8.15.4 Port Function Control Register 0 (PFCR0) ..........................................................
8.15.5 Pin Functions .......................................................................................................
Port H................................................................................................................................
8.16.1 Port H Data Direction Register (PHDDR) ...........................................................
8.16.2 Port H Data Register (PHDR) ..............................................................................
8.16.3 Port H Register (PORTH) ....................................................................................
8.16.4 Pin Functions .......................................................................................................
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231
232
232
233
234
234
235
235
236
236
237
237
238
239
239
240
242
242
244
244
245
245
247
247
248
248
249
Section 9 16-Bit Timer Pulse Unit (TPU) .................................................................... 251
9.1
9.2
9.3
Features .............................................................................................................................
Input/Output Pins ..............................................................................................................
Register Descriptions ........................................................................................................
9.3.1 Timer Control Register (TCR) .............................................................................
9.3.2 Timer Mode Register (TMDR) ............................................................................
9.3.3 Timer I/O Control Register (TIOR) .....................................................................
9.3.4 Timer Interrupt Enable Register (TIER) ..............................................................
9.3.5 Timer Status Register (TSR)................................................................................
9.3.6 Timer Counter (TCNT)........................................................................................
9.3.7 Timer General Register (TGR) ............................................................................
9.3.8 Timer Start Register (TSTR)................................................................................
251
255
256
258
263
265
282
284
287
287
287
Rev. 3.00 Feb 22, 2006 page xix of xl
9.4
9.5
9.6
9.7
9.8
9.9
9.3.9 Timer Synchronous Register (TSYR) ..................................................................
Operation ..........................................................................................................................
9.4.1 Basic Functions....................................................................................................
9.4.2 Synchronous Operation........................................................................................
9.4.3 Buffer Operation ..................................................................................................
9.4.4 Cascaded Operation .............................................................................................
9.4.5 PWM Modes ........................................................................................................
9.4.6 Phase Counting Mode ..........................................................................................
Interrupt Sources...............................................................................................................
DTC Activation.................................................................................................................
A/D Converter Activation .................................................................................................
Operation Timing..............................................................................................................
9.8.1 Input/Output Timing ............................................................................................
9.8.2 Interrupt Signal Timing........................................................................................
Usage Notes ......................................................................................................................
9.9.1 Module Stop Mode Setting ..................................................................................
9.9.2 Input Clock Restrictions ......................................................................................
9.9.3 Caution on Cycle Setting .....................................................................................
9.9.4 Contention between TCNT Write and Clear Operations .....................................
9.9.5 Contention between TCNT Write and Increment Operations..............................
9.9.6 Contention between TGR Write and Compare Match .........................................
9.9.7 Contention between Buffer Register Write and Compare Match ........................
9.9.8 Contention between TGR Read and Input Capture..............................................
9.9.9 Contention between TGR Write and Input Capture.............................................
9.9.10 Contention between Buffer Register Write and Input Capture ............................
9.9.11 Contention between Overflow/Underflow and Counter Clearing........................
9.9.12 Contention between TCNT Write and Overflow/Underflow...............................
9.9.13 Multiplexing of I/O Pins ......................................................................................
9.9.14 Interrupts and Module Stop Mode .......................................................................
288
289
289
294
297
300
302
307
313
315
315
316
316
320
324
324
324
325
325
326
327
328
329
330
331
332
333
333
333
Section 10 Programmable Pulse Generator (PPG) .................................................... 335
10.1 Features .............................................................................................................................
10.2 Input/Output Pins ..............................................................................................................
10.3 Register Descriptions ........................................................................................................
10.3.1 Next Data Enable Registers H, L (NDERH, NDERL).........................................
10.3.2 Output Data Registers H, L (PODRH, PODRL)..................................................
10.3.3 Next Data Registers H, L (NDRH, NDRL) .........................................................
10.3.4 PPG Output Control Register (PCR)....................................................................
10.3.5 PPG Output Mode Register (PMR)......................................................................
10.4 Operation ..........................................................................................................................
10.4.1 Output Timing......................................................................................................
Rev. 3.00 Feb 22, 2006 page xx of xl
335
337
337
338
339
339
342
343
345
346
10.4.2
10.4.3
10.4.4
10.4.5
10.4.6
Sample Setup Procedure for Normal Pulse Output..............................................
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)..........
Non-Overlapping Pulse Output............................................................................
Sample Setup Procedure for Non-Overlapping Pulse Output ..............................
Example of Non-Overlapping Pulse Output
(Example of Four-Phase Complementary Non-Overlapping Output)..................
10.4.7 Inverted Pulse Output ..........................................................................................
10.4.8 Pulse Output Triggered by Input Capture ............................................................
10.5 Usage Notes ......................................................................................................................
10.5.1 Module Stop Mode Setting ..................................................................................
10.5.2 Operation of Pulse Output Pins............................................................................
347
348
349
351
352
354
355
355
355
355
Section 11 8-Bit Timers (TMR) ...................................................................................... 357
11.1 Features .............................................................................................................................
11.2 Input/Output Pins ..............................................................................................................
11.3 Register Descriptions ........................................................................................................
11.3.1 Timer Counter (TCNT)........................................................................................
11.3.2 Time Constant Register A (TCORA)...................................................................
11.3.3 Time Constant Register B (TCORB) ...................................................................
11.3.4 Timer Control Register (TCR) .............................................................................
11.3.5 Timer Control/Status Register (TCSR) ................................................................
11.4 Operation ..........................................................................................................................
11.4.1 Pulse Output.........................................................................................................
11.5 Operation Timing..............................................................................................................
11.5.1 TCNT Incrementation Timing .............................................................................
11.5.2 Timing of CMFA and CMFB Setting when Compare-Match Occurs .................
11.5.3 Timing of Timer Output when Compare-Match Occurs......................................
11.5.4 Timing of Compare Match Clear .........................................................................
11.5.5 Timing of TCNT External Reset..........................................................................
11.5.6 Timing of Overflow Flag (OVF) Setting .............................................................
11.6 Operation with Cascaded Connection ...............................................................................
11.6.1 16-Bit Counter Mode ...........................................................................................
11.6.2 Compare Match Count Mode...............................................................................
11.7 Interrupt Sources...............................................................................................................
11.7.1 Interrupt Sources and DTC Activation ................................................................
11.7.2 A/D Converter Activation....................................................................................
11.8 Usage Notes ......................................................................................................................
11.8.1 Contention between TCNT Write and Clear........................................................
11.8.2 Contention between TCNT Write and Increment ................................................
11.8.3 Contention between TCOR Write and Compare Match ......................................
11.8.4 Contention between Compare Matches A and B .................................................
357
359
359
360
360
360
361
363
367
367
368
368
369
369
370
370
371
372
372
372
373
373
373
374
374
375
376
377
Rev. 3.00 Feb 22, 2006 page xxi of xl
11.8.5 Switching of Internal Clocks and TCNT Operation............................................. 377
11.8.6 Mode Setting with Cascaded Connection ............................................................ 379
11.8.7 Interrupts in Module Stop Mode.......................................................................... 379
Section 12 Watchdog Timer .............................................................................................
12.1 Features .............................................................................................................................
12.2 Input/Output Pin................................................................................................................
12.3 Register Descriptions ........................................................................................................
12.3.1 Timer Counter (TCNT)........................................................................................
12.3.2 Timer Control/Status Register (TCSR) ................................................................
12.3.3 Reset Control/Status Register (RSTCSR) ............................................................
12.4 Operation ..........................................................................................................................
12.4.1 Watchdog Timer Mode ........................................................................................
12.4.2 Interval Timer Mode ............................................................................................
12.5 Interrupt Source ................................................................................................................
12.6 Usage Notes ......................................................................................................................
12.6.1 Notes on Register Access.....................................................................................
12.6.2 Contention between Timer Counter (TCNT) Write and Increment .....................
12.6.3 Changing Value of CKS2 to CKS0......................................................................
12.6.4 Switching between Watchdog Timer Mode and Interval Timer Mode................
12.6.5 Internal Reset in Watchdog Timer Mode.............................................................
12.6.6 System Reset by WDTOVF Signal......................................................................
381
381
382
383
383
383
385
386
386
387
388
389
389
390
390
391
391
391
Section 13 Serial Communication Interface (SCI, IrDA) ........................................
13.1 Features .............................................................................................................................
13.2 Input/Output Pins ..............................................................................................................
13.3 Register Descriptions ........................................................................................................
13.3.1 Receive Shift Register (RSR) ..............................................................................
13.3.2 Receive Data Register (RDR) ..............................................................................
13.3.3 Transmit Data Register (TDR).............................................................................
13.3.4 Transmit Shift Register (TSR) .............................................................................
13.3.5 Serial Mode Register (SMR)................................................................................
13.3.6 Serial Control Register (SCR)..............................................................................
13.3.7 Serial Status Register (SSR) ................................................................................
13.3.8 Smart Card Mode Register (SCMR) ....................................................................
13.3.9 Bit Rate Register (BRR) ......................................................................................
13.3.10 IrDA Control Register (IrCR) ..............................................................................
13.3.11 Serial Extension Mode Register (SEMR) ............................................................
13.4 Operation in Asynchronous Mode ....................................................................................
13.4.1 Data Transfer Format...........................................................................................
393
393
396
397
398
398
398
398
398
402
405
410
411
420
421
423
423
Rev. 3.00 Feb 22, 2006 page xxii of xl
13.5
13.6
13.7
13.8
13.9
13.10
13.4.2 Receive Data Sampling Timing and Reception Margin
in Asynchronous Mode ........................................................................................
13.4.3 Clock....................................................................................................................
13.4.4 SCI Initialization (Asynchronous Mode) .............................................................
13.4.5 Data Transmission (Asynchronous Mode)...........................................................
13.4.6 Serial Data Reception (Asynchronous Mode)......................................................
Multiprocessor Communication Function.........................................................................
13.5.1 Multiprocessor Serial Data Transmission ............................................................
13.5.2 Multiprocessor Serial Data Reception .................................................................
Operation in Clocked Synchronous Mode ........................................................................
13.6.1 Clock....................................................................................................................
13.6.2 SCI Initialization (Clocked Synchronous Mode) .................................................
13.6.3 Serial Data Transmission (Clocked Synchronous Mode) ....................................
13.6.4 Serial Data Reception (Clocked Synchronous Mode)..........................................
13.6.5 Simultaneous Serial Data Transmission and Reception
(Clocked Synchronous Mode) .............................................................................
Operation in Smart Card Interface Mode..........................................................................
13.7.1 Pin Connection Example......................................................................................
13.7.2 Data Format (Except for Block Transfer Mode)..................................................
13.7.3 Block Transfer Mode ...........................................................................................
13.7.4 Receive Data Sampling Timing and Reception Margin.......................................
13.7.5 Initialization .........................................................................................................
13.7.6 Data Transmission (Except for Block Transfer Mode) ........................................
13.7.7 Serial Data Reception (Except for Block Transfer Mode) ...................................
13.7.8 Clock Output Control...........................................................................................
IrDA Operation .................................................................................................................
Interrupt Sources...............................................................................................................
13.9.1 Interrupts in Normal Serial Communication Interface Mode ..............................
13.9.2 Interrupts in Smart Card Interface Mode .............................................................
Usage Notes ......................................................................................................................
13.10.1 Module Stop Mode Setting ..................................................................................
13.10.2 Break Detection and Processing ..........................................................................
13.10.3 Mark State and Break Sending.............................................................................
13.10.4 Receive Error Flags and Transmit Operations
(Clocked Synchronous Mode Only) ....................................................................
13.10.5 Relation between Writes to TDR and the TDRE Flag .........................................
13.10.6 Restrictions on Use of DTC .................................................................................
13.10.7 Operation in Case of Mode Transition.................................................................
425
426
427
428
430
434
435
437
440
440
441
442
445
447
449
449
450
451
451
453
454
457
459
460
464
464
465
466
466
466
466
466
467
467
468
Section 14 A/D Converter ................................................................................................. 473
14.1 Features ............................................................................................................................. 473
Rev. 3.00 Feb 22, 2006 page xxiii of xl
14.2 Input/Output Pins ..............................................................................................................
14.3 Register Descriptions ........................................................................................................
14.3.1 A/D Data Registers A to H (ADDRA to ADDRH)..............................................
14.3.2 A/D Control/Status Register (ADCSR) ...............................................................
14.3.3 A/D Control Register (ADCR) ............................................................................
14.4 Operation ..........................................................................................................................
14.4.1 Single Mode.........................................................................................................
14.4.2 Scan Mode ...........................................................................................................
14.4.3 Input Sampling and A/D Conversion Time .........................................................
14.4.4 External Trigger Input Timing.............................................................................
14.5 Interrupt Source ................................................................................................................
14.6 A/D Conversion Accuracy Definitions .............................................................................
14.7 Usage Notes ......................................................................................................................
14.7.1 Module Stop Mode Setting ..................................................................................
14.7.2 Permissible Signal Source Impedance .................................................................
14.7.3 Influences on Absolute Precision.........................................................................
14.7.4 Setting Range of Analog Power Supply and Other Pins ......................................
14.7.5 Notes on Board Design ........................................................................................
14.7.6 Notes on Noise Countermeasures ........................................................................
474
475
476
477
479
480
480
480
481
483
484
484
486
486
486
487
487
487
488
Section 15 D/A Converter ................................................................................................. 491
15.1 Features .............................................................................................................................
15.2 Input/Output Pins ..............................................................................................................
15.3 Register Descriptions ........................................................................................................
15.3.1 D/A Data Registers 0 to 3 (DADR0 to DADR3) .................................................
15.3.2 D/A Control Registers 01 and 23 (DACR01, DACR23) .....................................
15.4 Operation ..........................................................................................................................
15.5 Usage Notes ......................................................................................................................
15.5.1 Setting for Module Stop Mode.............................................................................
15.5.2 D/A Output Hold Function in Software Standby Mode.......................................
491
493
493
493
494
497
498
498
498
Section 16 RAM .................................................................................................................. 499
Section 17 Flash Memory (F-ZTAT Version) ............................................................ 501
17.1
17.2
17.3
17.4
17.5
Features .............................................................................................................................
Mode Transitions ..............................................................................................................
Block Configuration..........................................................................................................
Input/Output Pins ..............................................................................................................
Register Descriptions ........................................................................................................
17.5.1 Flash Memory Control Register 1 (FLMCR1).....................................................
17.5.2 Flash Memory Control Register 2 (FLMCR2).....................................................
Rev. 3.00 Feb 22, 2006 page xxiv of xl
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502
506
508
508
508
510
17.5.3 Erase Block Register 1 (EBR1) ...........................................................................
17.5.4 Erase Block Register 2 (EBR2) ...........................................................................
17.5.5 RAM Emulation Register (RAMER)...................................................................
On-Board Programming Modes........................................................................................
17.6.1 Boot Mode ...........................................................................................................
17.6.2 User Program Mode.............................................................................................
Flash Memory Emulation in RAM ...................................................................................
Flash Memory Programming/Erasing ...............................................................................
17.8.1 Program/Program-Verify .....................................................................................
17.8.2 Erase/Erase-Verify...............................................................................................
17.8.3 Interrupt Handling when Programming/Erasing Flash Memory..........................
Program/Erase Protection .................................................................................................
17.9.1 Hardware Protection ............................................................................................
17.9.2 Software Protection..............................................................................................
17.9.3 Error Protection....................................................................................................
Programmer Mode ............................................................................................................
Power-Down States for Flash Memory.............................................................................
Usage Notes ......................................................................................................................
511
512
513
515
515
518
519
521
522
524
524
526
526
526
526
527
527
528
Section 18 Clock Pulse Generator ..................................................................................
18.1 Register Descriptions ........................................................................................................
18.1.1 System Clock Control Register (SCKCR) ...........................................................
18.1.2 PLL Control Register (PLLCR) ...........................................................................
18.2 Oscillator...........................................................................................................................
18.2.1 Connecting a Crystal resonator ............................................................................
18.2.2 External Clock Input ............................................................................................
18.3 PLL Circuit .......................................................................................................................
18.4 Frequency Divider ............................................................................................................
18.5 Usage Notes ......................................................................................................................
18.5.1 Notes on Clock Pulse Generator ..........................................................................
18.5.2 Notes on Resonator ..............................................................................................
18.5.3 Notes on Board Designs.......................................................................................
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533
534
535
536
536
537
539
539
540
540
540
541
17.6
17.7
17.8
17.9
17.10
17.11
17.12
Section 19 Power-Down Modes ...................................................................................... 543
19.1 Register Descriptions ........................................................................................................
19.1.1 Standby Control Register (SBYCR) ....................................................................
19.1.2 Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)....................
19.2 Operation ..........................................................................................................................
19.2.1 Clock Division Mode...........................................................................................
19.2.2 Sleep Mode ..........................................................................................................
19.2.3 Software Standby Mode.......................................................................................
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549
549
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550
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19.2.4 Hardware Standby Mode .....................................................................................
19.2.5 Module Stop Mode ..............................................................................................
19.2.6 All-Module-Clocks-Stop Mode ...........................................................................
19.3 φ Clock Output Control.....................................................................................................
19.4 Usage Notes ......................................................................................................................
19.4.1 I/O Port Status......................................................................................................
19.4.2 Current Dissipation during Oscillation Stabilization Standby Period..................
19.4.3 DTC Module Stop................................................................................................
19.4.4 On-Chip Peripheral Module Interrupts ................................................................
19.4.5 Writing to MSTPCR ............................................................................................
552
553
554
554
555
555
555
555
555
555
Section 20 List of Registers .............................................................................................. 557
20.1 Register Addresses (Address Order) ................................................................................. 558
20.2 Register Bits...................................................................................................................... 566
20.3 Register States in Each Operating Mode........................................................................... 576
Section 21 Electrical Characteristics.............................................................................. 585
21.1 Electrical Characteristics of F-ZTAT Version (H8S/2667) ..............................................
21.1.1 Absolute Maximum Ratings ................................................................................
21.1.2 DC Characteristics ...............................................................................................
21.1.3 AC Characteristics ...............................................................................................
21.1.4 A/D Conversion Characteristics...........................................................................
21.1.5 D/A Conversion Characteristics...........................................................................
21.1.6 Flash Memory Characteristics .............................................................................
585
585
586
589
606
606
607
Appendix .................................................................................................................................. 609
A.
B.
C.
I/O Port States in Each Pin State....................................................................................... 609
Product Lineup.................................................................................................................. 616
Package Dimensions ......................................................................................................... 617
Index .......................................................................................................................................... 619
Rev. 3.00 Feb 22, 2006 page xxvi of xl
Figures
Section 1 Overview
Figure 1.1
Internal Block Diagram........................................................................................
Figure 1.2
Pin Arrangement ..................................................................................................
2
3
Section 2 CPU
Figure 2.1
Exception Vector Table (Normal Mode) .............................................................
Figure 2.2
Stack Structure in Normal Mode .........................................................................
Figure 2.3
Exception Vector Table (Advanced Mode) .........................................................
Figure 2.4
Stack Structure in Advanced Mode......................................................................
Figure 2.5
Memory Map .......................................................................................................
Figure 2.6
CPU Registers......................................................................................................
Figure 2.7
Usage of General Registers..................................................................................
Figure 2.8
Stack.....................................................................................................................
Figure 2.9
General Register Data Formats (1) ......................................................................
Figure 2.9
General Register Data Formats (2) ......................................................................
Figure 2.10 Memory Data Formats .........................................................................................
Figure 2.11 Instruction Formats (Examples)...........................................................................
Figure 2.12 Branch Address Specification in Memory Indirect Mode....................................
Figure 2.13 State Transitions...................................................................................................
19
19
20
21
22
23
24
25
28
29
30
42
45
49
Section 3 MCU Operating Modes
Figure 3.1
Memory Map (1).................................................................................................. 57
Figure 3.1
Memory Map (2).................................................................................................. 58
Section 4 Exception Handling
Figure 4.1
Reset Sequence (Advanced Mode with On-chip ROM Enabled) ........................
Figure 4.2
Reset Sequence (Advanced Mode with On-chip ROM Disabled) .......................
Figure 4.3
Stack Status after Exception Handling.................................................................
Figure 4.4
Operation when SP Value Is Odd ........................................................................
Section 5 Interrupt Controller
Figure 5.1
Block Diagram of Interrupt Controller ................................................................
Figure 5.2
Block Diagram of Interrupts IRQ7 to IRQ0.........................................................
Figure 5.3
Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0 .................................................................................
Figure 5.4
Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2 .................................................................................
Figure 5.5
Interrupt Exception Handling...............................................................................
62
63
67
68
70
82
88
90
92
Rev. 3.00 Feb 22, 2006 page xxvii of xl
Figure 5.6
Figure 5.7
DTC and Interrupt Controller .............................................................................. 95
Contention between Interrupt Generation and Disabling..................................... 97
Section 6 Bus Controller (BSC)
Figure 6.1
Block Diagram of Bus Controller ........................................................................
Figure 6.2
Read Strobe Negation Timing (Example of 3-State Access Space).....................
Figure 6.3
CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0) .............................................
Figure 6.4
Area Divisions .....................................................................................................
Figure 6.5
CSn Signal Output Timing (n = 0 to 7)................................................................
Figure 6.6
Access Sizes and Data Alignment Control (8-Bit Access Space) ........................
Figure 6.7
Access Sizes and Data Alignment Control (16-bit Access Space).......................
Figure 6.8
Bus Timing for 8-Bit, 2-State Access Space........................................................
Figure 6.9
Bus Timing for 8-Bit, 3-State Access Space........................................................
Figure 6.10 Bus Timing for 16-Bit, 2-State Access Space (Even Address Byte Access) .......
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space (Odd Address Byte Access).........
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space (Word Access) .............................
Figure 6.13 Bus Timing for 16-Bit, 3-State Access Space (Even Address Byte Access) .......
Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space (Odd Address Byte Access).........
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space (Word Access) .............................
Figure 6.16 Example of Wait State Insertion Timing..............................................................
Figure 6.17 Example of Read Strobe Timing..........................................................................
Figure 6.18 Example of Timing when Chip Select Assertion Period Is Extended..................
Figure 6.19 Example of Idle Cycle Operation (Consecutive Reads in Different Areas).........
Figure 6.20 Example of Idle Cycle Operation (Write after Read)...........................................
Figure 6.21 Example of Idle Cycle Operation (Read after Write)...........................................
Figure 6.22 Relationship between Chip Select (CS) and Read (RD) ......................................
Figure 6.23 Example of Timing when Write Data Buffer Function Is Used...........................
Figure 6.24 Bus Released State Transition Timing .................................................................
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115
119
120
121
122
123
124
125
126
127
128
129
131
132
133
134
135
136
137
138
141
Section 7 Data Transfer Controller (DTC)
Figure 7.1
Block Diagram of DTC........................................................................................
Figure 7.2
Block Diagram of DTC Activation Source Control.............................................
Figure 7.3
Correspondence between DTC Vector Address and Register Information..........
Figure 7.4
Flowchart of DTC Operation ...............................................................................
Figure 7.5
Memory Mapping in Normal Mode.....................................................................
Figure 7.6
Memory Mapping in Repeat Mode ......................................................................
Figure 7.7
Memory Mapping in Block Transfer Mode .........................................................
Figure 7.8
Operation of Chain Transfer ................................................................................
Figure 7.9
DTC Operation Timing (Example in Normal Mode or Repeat Mode) ................
146
152
153
157
159
160
161
162
163
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100
109
Figure 7.10
Figure 7.11
Figure 7.12
DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2) ........................................................................................... 164
DTC Operation Timing (Example of Chain Transfer) ......................................... 164
Chain Transfer when Counter = 0........................................................................ 169
Section 9 16-Bit Timer Pulse Unit (TPU)
Figure 9.1
Block Diagram of TPU ........................................................................................
Figure 9.2
Example of Counter Operation Setting Procedure...............................................
Figure 9.3
Free-Running Counter Operation.........................................................................
Figure 9.4
Periodic Counter Operation .................................................................................
Figure 9.5
Example of Setting Procedure for Waveform Output by Compare Match ..........
Figure 9.6
Example of 0 Output/1 Output Operation ............................................................
Figure 9.7
Example of Toggle Output Operation..................................................................
Figure 9.8
Example of Setting Procedure for Input Capture Operation ................................
Figure 9.9
Example of Input Capture Operation ...................................................................
Figure 9.10 Example of Synchronous Operation Setting Procedure .......................................
Figure 9.11 Example of Synchronous Operation ....................................................................
Figure 9.12 Compare Match Buffer Operation .......................................................................
Figure 9.13 Input Capture Buffer Operation ...........................................................................
Figure 9.14 Example of Buffer Operation Setting Procedure .................................................
Figure 9.15 Example of Buffer Operation (1) .........................................................................
Figure 9.16 Example of Buffer Operation (2) .........................................................................
Figure 9.17 Cascaded Operation Setting Procedure................................................................
Figure 9.18 Example of Cascaded Operation (1) ....................................................................
Figure 9.19 Example of Cascaded Operation (2) ....................................................................
Figure 9.20 Example of PWM Mode Setting Procedure.........................................................
Figure 9.21 Example of PWM Mode Operation (1)................................................................
Figure 9.22 Example of PWM Mode Operation (2)................................................................
Figure 9.23 Example of PWM Mode Operation (3)................................................................
Figure 9.24 Example of Phase Counting Mode Setting Procedure .........................................
Figure 9.25 Example of Phase Counting Mode 1 Operation...................................................
Figure 9.26 Example of Phase Counting Mode 2 Operation...................................................
Figure 9.27 Example of Phase Counting Mode 3 Operation...................................................
Figure 9.28 Example of Phase Counting Mode 4 Operation...................................................
Figure 9.29 Phase Counting Mode Application Example .......................................................
Figure 9.30 Count Timing in Internal Clock Operation ..........................................................
Figure 9.31 Count Timing in External Clock Operation .........................................................
Figure 9.32 Output Compare Output Timing ..........................................................................
Figure 9.33 Input Capture Input Signal Timing ......................................................................
Figure 9.34 Counter Clear Timing (Compare Match) .............................................................
Figure 9.35 Counter Clear Timing (Input Capture).................................................................
254
289
290
291
291
292
292
293
294
295
296
297
298
298
299
300
301
301
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310
311
313
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316
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317
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318
Rev. 3.00 Feb 22, 2006 page xxix of xl
Figure 9.36
Figure 9.37
Figure 9.38
Figure 9.39
Figure 9.40
Figure 9.41
Figure 9.42
Figure 9.43
Figure 9.44
Figure 9.45
Figure 9.46
Figure 9.47
Figure 9.48
Figure 9.49
Figure 9.50
Figure 9.51
Figure 9.52
Figure 9.53
Buffer Operation Timing (Compare Match) ........................................................
Buffer Operation Timing (Input Capture)............................................................
TGI Interrupt Timing (Compare Match)..............................................................
TGI Interrupt Timing (Input Capture)..................................................................
TCIV Interrupt Setting Timing ............................................................................
TCIU Interrupt Setting Timing ............................................................................
Timing for Status Flag Clearing by CPU .............................................................
Timing for Status Flag Clearing by DTC Activation ...........................................
Phase Difference, Overlap, and Pulse Width in Phase Counting Mode...............
Contention between TCNT Write and Clear Operations .....................................
Contention between TCNT Write and Increment Operations..............................
Contention between TGR Write and Compare Match .........................................
Contention between Buffer Register Write and Compare Match ........................
Contention between TGR Read and Input Capture..............................................
Contention between TGR Write and Input Capture.............................................
Contention between Buffer Register Write and Input Capture ............................
Contention between Overflow and Counter Clearing ..........................................
Contention between TCNT Write and Overflow .................................................
319
319
320
321
322
322
323
323
324
325
326
327
328
329
330
331
332
333
Section 10 Programmable Pulse Generator (PPG)
Figure 10.1 Block Diagram of PPG ........................................................................................
Figure 10.2 Overview Diagram of PPG ..................................................................................
Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)..............................
Figure 10.4 Setup Procedure for Normal Pulse Output (Example) .........................................
Figure 10.5 Normal Pulse Output Example (Five-Phase Pulse Output)..................................
Figure 10.6 Non-Overlapping Pulse Output............................................................................
Figure 10.7 Non-Overlapping Operation and NDR Write Timing..........................................
Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example) .........................
Figure 10.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary) ............
Figure 10.10 Inverted Pulse Output (Example).........................................................................
Figure 10.11 Pulse Output Triggered by Input Capture (Example) ..........................................
336
345
346
347
348
349
350
351
352
354
355
Section 11 8-Bit Timers (TMR)
Figure 11.1 Block Diagram of 8-Bit Timer Module ...............................................................
Figure 11.2 Example of Pulse Output .....................................................................................
Figure 11.3 Count Timing for Internal Clock Input ................................................................
Figure 11.4 Count Timing for External Clock Input ...............................................................
Figure 11.5 Timing of CMF Setting........................................................................................
Figure 11.6 Timing of Timer Output.......................................................................................
Figure 11.7 Timing of Compare Match Clear .........................................................................
Figure 11.8 Timing of Clearance by External Reset ...............................................................
358
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368
368
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370
370
Rev. 3.00 Feb 22, 2006 page xxx of xl
Figure 11.9
Figure 11.10
Figure 11.11
Figure 11.12
Timing of OVF Setting ........................................................................................
Contention between TCNT Write and Clear........................................................
Contention between TCNT Write and Increment ................................................
Contention between TCOR Write and Compare Match ......................................
371
374
375
376
Section 12 Watchdog Timer
Figure 12.1 Block Diagram of WDT.......................................................................................
Figure 12.2 Operation in Watchdog Timer Mode ...................................................................
Figure 12.3 Operation in Interval Timer Mode .......................................................................
Figure 12.4
Writing to TCNT, TCSR, and RSTCSR .............................................................
Figure 12.5 Contention between TCNT Write and Increment ................................................
Figure 12.6 Circuit for System Reset by WDTOVF Signal (Example) ..................................
382
387
388
389
390
391
Section 13 Serial Communication Interface (SCI, IrDA)
Figure 13.1 Block Diagram of SCI .........................................................................................
Figure 13.2 Data Format in Asynchronous Communication (Example with 8-Bit Data,
Parity, Two Stop Bits)..........................................................................................
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode.....................................
Figure 13.4 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode) .........................................................................................
Figure 13.5 Sample SCI Initialization Flowchart....................................................................
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit).................................................
Figure 13.7 Sample Serial Transmission Flowchart................................................................
Figure 13.8 Example of SCI Operation in Reception (Example with 8-Bit Data, Parity,
One Stop Bit) .......................................................................................................
Figure 13.9 Sample Serial Reception Data Flowchart (1).......................................................
Figure 13.9 Sample Serial Reception Data Flowchart (2).......................................................
Figure 13.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A) .........................................
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart.......................................
Figure 13.12 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit) .......................................................................
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1) ......................................
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2) ......................................
Figure 13.14 Data Format in Clocked Synchronous Communication (For LSB-First).............
Figure 13.15 Sample SCI Initialization Flowchart....................................................................
Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode.................
Figure 13.17 Sample Serial Transmission Flowchart................................................................
Figure 13.18 Example of SCI Operation in Reception..............................................................
Figure 13.19 Sample Serial Reception Flowchart .....................................................................
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423
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439
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446
Rev. 3.00 Feb 22, 2006 page xxxi of xl
Figure 13.20
Figure 13.21
Figure 13.22
Figure 13.23
Figure 13.24
Figure 13.25
Figure 13.26
Figure 13.27
Figure 13.28
Figure 13.29
Figure 13.30
Figure 13.31
Figure 13.32
Figure 13.33
Figure 13.34
Figure 13.35
Figure 13.36
Figure 13.37
Figure 13.38
Figure 13.39
Sample Flowchart of Simultaneous Serial Transmit and Receive Operations .....
Schematic Diagram of Smart Card Interface Pin Connections ............................
Normal Smart Card Interface Data Format ..........................................................
Direct Convention (SDIR = SINV = O/E = 0).....................................................
Inverse Convention (SDIR = SINV = O/E = 1) ...................................................
Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Bit Rate).............................................................
Retransfer Operation in SCI Transmit Mode .......................................................
TEND Flag Generation Timing in Transmission Operation ................................
Example of Transmission Processing Flow .........................................................
Retransfer Operation in SCI Receive Mode.........................................................
Example of Reception Processing Flow...............................................................
Timing for Fixing Clock Output Level ................................................................
Clock Halt and Restart Procedure........................................................................
Block Diagram of IrDA .......................................................................................
IrDA Transmit/Receive Operations .....................................................................
Example of Synchronous Transmission Using DTC ...........................................
Sample Flowchart for Mode Transition during Transmission .............................
Port Pin States during Mode Transition (Internal Clock, Asynchronous
Transmission).......................................................................................................
Port Pin States during Mode Transition (Internal Clock, Synchronous
Transmission).......................................................................................................
Sample Flowchart for Mode Transition during Reception...................................
Section 14 A/D Converter
Figure 14.1 Block Diagram of A/D Converter ........................................................................
Figure 14.2 A/D Conversion Timing.......................................................................................
Figure 14.3 External Trigger Input Timing .............................................................................
Figure 14.4 A/D Conversion Accuracy Definitions ................................................................
Figure 14.5 A/D Conversion Accuracy Definitions ................................................................
Figure 14.6 Example of Analog Input Circuit.........................................................................
Figure 14.7 Example of Analog Input Protection Circuit........................................................
Figure 14.8 Analog Input Pin Equivalent Circuit....................................................................
448
449
450
450
451
452
455
455
456
457
458
459
460
461
462
467
469
470
470
471
474
482
483
485
485
486
488
489
Section 15 D/A Converter
Figure 15.1 Block Diagram of D/A Converter ........................................................................ 492
Figure 15.2 Example of D/A Converter Operation ................................................................. 498
Section 17 Flash Memory (F-ZTAT Version)
Figure 17.1
Block Diagram of Flash Memory ....................................................................... 502
Figure 17.2 Flash Memory State Transitions .......................................................................... 503
Rev. 3.00 Feb 22, 2006 page xxxii of xl
Figure 17.3
Figure 17.4
Figure 17.5
Figure 17.6
Figure 17.7
Figure 17.8
Figure 17.9
Figure 17.10
Figure 17.11
Figure 17.12
Boot Mode ...........................................................................................................
User Program Mode.............................................................................................
384-Kbyte Flash Memory Block Configuration (Modes 3, 4, and 7) ..................
Programming/Erasing Flowchart Example in User Program Mode.....................
Flowchart for Flash Memory Emulation in RAM................................................
Example of RAM Overlap Operation ..................................................................
Program/Program-Verify Flowchart ....................................................................
Erase/Erase-Verify Flowchart..............................................................................
Power-On/Off Timing..........................................................................................
Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode) ..........................
Section 18 Clock Pulse Generator
Figure 18.1 Block Diagram of Clock Pulse Generator............................................................
Figure 18.2 Connection of Crystal Resonator (Example) .......................................................
Figure 18.3 Crystal Resonator Equivalent Circuit...................................................................
Figure 18.4 External Clock Input (Examples).........................................................................
Figure 18.5 External Clock Input Timing ...............................................................................
Figure 18.6 Note on Oscillator Board Design .........................................................................
Figure 18.7 Recommended External Circuitry for PLL Circuit ..............................................
504
505
507
518
519
521
523
525
530
531
533
536
536
537
538
541
541
Section 19 Power-Down Modes
Figure 19.1 Mode Transitions ................................................................................................. 545
Figure 19.2 Software Standby Mode Application Example .................................................... 552
Figure 19.3 Hardware Standby Mode Timing......................................................................... 553
Section 21 Electrical Characteristics
Figure 21.1 Output Load Circuit .............................................................................................
Figure 21.2 System Clock Timing ..........................................................................................
Figure 21.3(1) Oscillation Stabilization Timing ..........................................................................
Figure 21.3(2) Oscillation Stabilization Timing ..........................................................................
Figure 21.4 Reset Input Timing ..............................................................................................
Figure 21.5 Interrupt Input Timing .........................................................................................
Figure 21.6 Basic Bus Timing: Two-State Access..................................................................
Figure 21.7 Basic Bus Timing: Three-State Access................................................................
Figure 21.8 Basic Bus Timing: Three-State Access, One Wait...............................................
Figure 21.9 Basic Bus Timing: Two-State Access (CS Assertion Period Extended)..............
Figure 21.10 Basic Bus Timing: Three-State Access (CS Assertion Period Extended)............
Figure 21.11 External Bus Release Timing...............................................................................
Figure 21.12 External Bus Request Output Timing ..................................................................
Figure 21.13 I/O Port Input/Output Timing ..............................................................................
589
590
591
591
592
593
596
597
598
599
600
601
601
603
Rev. 3.00 Feb 22, 2006 page xxxiii of xl
Figure 21.14
Figure 21.15
Figure 21.16
Figure 21.17
Figure 21.18
Figure 21.19
Figure 21.20
Figure 21.21
Figure 21.22
Figure 21.23
Appendix
Figure C.1
PPG Output Timing .............................................................................................
TPU Input/Output Timing....................................................................................
TPU Clock Input Timing .....................................................................................
8-Bit Timer Output Timing..................................................................................
8-Bit Timer Clock Input Timing ..........................................................................
8-Bit Timer Reset Input Timing...........................................................................
WDT Output Timing............................................................................................
SCK Clock Input Timing .....................................................................................
SCI Input/Output Timing: Synchronous Mode....................................................
A/D Converter External Trigger Input Timing ....................................................
603
603
604
604
604
604
605
605
605
605
Package Dimensions (FP-144H) ............................................................................ 617
Rev. 3.00 Feb 22, 2006 page xxxiv of xl
Tables
Section 1 Overview
Table 1.1
Pin Arrangement in Each Operating Mode ............................................................ 4
Table 1.2
Pin Functions.......................................................................................................... 10
Section 2 CPU
Table 2.1
Instruction Classification........................................................................................
Table 2.2
Operation Notation.................................................................................................
Table 2.3
Data Transfer Instructions ......................................................................................
Table 2.4
Arithmetic Operations Instructions (1)...................................................................
Table 2.4
Arithmetic Operations Instructions (2)...................................................................
Table 2.5
Logic Operations Instructions ................................................................................
Table 2.6
Shift Instructions ....................................................................................................
Table 2.7
Bit Manipulation Instructions (1) ...........................................................................
Table 2.7
Bit Manipulation Instructions (2) ...........................................................................
Table 2.8
Branch Instructions ................................................................................................
Table 2.9
System Control Instructions ...................................................................................
Table 2.10 Block Data Transfer Instructions ...........................................................................
Table 2.11 Addressing Modes..................................................................................................
Table 2.12 Absolute Address Access Ranges ..........................................................................
31
32
33
34
35
36
36
37
38
39
40
41
42
44
Section 3 MCU Operating Modes
Table 3.1
MCU Operating Mode Selection............................................................................ 51
Table 3.2
Pin Functions in Each Operating Mode.................................................................. 56
Section 4 Exception Handling
Table 4.1
Exception Types and Priority .................................................................................
Table 4.2
Exception Handling Vector Table ..........................................................................
Table 4.3
Status of CCR and EXR after Trace Exception Handling ......................................
Table 4.4
Status of CCR and EXR after Trap Instruction Exception Handling .....................
59
60
64
66
Section 5 Interrupt Controller
Table 5.1
Pin Configuration ................................................................................................... 71
Table 5.2
Interrupt Sources, Vector Addresses, and Interrupt Priorities ................................ 83
Table 5.3
Interrupt Control Modes......................................................................................... 87
Table 5.4
Interrupt Response Times....................................................................................... 93
Table 5.5
Number of States in Interrupt Handling Routine Execution Statuses..................... 94
Rev. 3.00 Feb 22, 2006 page xxxv of xl
Section 6 Bus Controller (BSC)
Table 6.1
Pin Configuration ................................................................................................... 101
Table 6.2
Bus Specifications for Each Area (Basic Bus Interface) ........................................ 117
Table 6.3
Data Buses Used and Valid Strobes ....................................................................... 121
Table 6.4
Pin States in Idle Cycle .......................................................................................... 137
Table 6.5
Pin States in Bus Released State ............................................................................ 140
Section 7 Data Transfer Controller (DTC)
Table 7.1
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs ................
Table 7.2
Chain Transfer Conditions .....................................................................................
Table 7.3
Register Function in Normal Mode........................................................................
Table 7.4
Register Function in Repeat Mode .........................................................................
Table 7.5
Register Function in Block Transfer Mode ............................................................
Table 7.6
DTC Execution Status ............................................................................................
Table 7.7
Number of States Required for Each Execution Status ..........................................
154
158
159
160
161
165
165
Section 8 I/O Ports
Table 8.1
Port Functions ........................................................................................................
Table 8.2
Input Pull-Up MOS States (Port A)........................................................................
Table 8.3
Input Pull-Up MOS States (Port B)........................................................................
Table 8.4
Input Pull-Up MOS States (Port C)........................................................................
Table 8.5
Input Pull-Up MOS States (Port D)........................................................................
Table 8.6
Input Pull-Up MOS States (Port E) ........................................................................
174
223
226
229
233
237
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.1
TPU Functions........................................................................................................ 252
Table 9.2
Pin Configuration ................................................................................................... 255
Table 9.3
CCLR2 to CCLR0 (Channels 0 and 3)................................................................... 259
Table 9.4
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5).......................................................... 259
Table 9.5
TPSC2 to TPSC0 (Channel 0)................................................................................ 260
Table 9.6
TPSC2 to TPSC0 (Channel 1)................................................................................ 260
Table 9.7
TPSC2 to TPSC0 (Channel 2)................................................................................ 261
Table 9.8
TPSC2 to TPSC0 (Channel 3)................................................................................ 261
Table 9.9
TPSC2 to TPSC0 (Channel 4)................................................................................ 262
Table 9.10 TPSC2 to TPSC0 (Channel 5)................................................................................ 262
Table 9.11 MD3 to MD0.......................................................................................................... 264
Table 9.12 TIORH_0................................................................................................................ 266
Table 9.13 TIORL_0 ................................................................................................................ 267
Table 9.14 TIOR_1 .................................................................................................................. 268
Table 9.15 TIOR_2 .................................................................................................................. 269
Table 9.16 TIORH_3................................................................................................................ 270
Rev. 3.00 Feb 22, 2006 page xxxvi of xl
Table 9.17
Table 9.18
Table 9.19
Table 9.20
Table 9.21
Table 9.22
Table 9.23
Table 9.24
Table 9.25
Table 9.26
Table 9.27
Table 9.28
Table 9.29
Table 9.30
Table 9.31
Table 9.32
Table 9.33
Table 9.34
Table 9.35
Table 9.36
TIORL_3 ................................................................................................................
TIOR_4 ..................................................................................................................
TIOR_5 ..................................................................................................................
TIORH_0................................................................................................................
TIORL_0 ................................................................................................................
TIOR_1 ..................................................................................................................
TIOR_2 ..................................................................................................................
TIORH_3................................................................................................................
TIORL_3 ................................................................................................................
TIOR_4 ..................................................................................................................
TIOR_5 ..................................................................................................................
Register Combinations in Buffer Operation...........................................................
Cascaded Combinations .........................................................................................
PWM Output Registers and Output Pins................................................................
Clock Input Pins in Phase Counting Mode.............................................................
Up/Down-Count Conditions in Phase Counting Mode 1 .......................................
Up/Down-Count Conditions in Phase Counting Mode 2 .......................................
Up/Down-Count Conditions in Phase Counting Mode 3 .......................................
Up/Down-Count Conditions in Phase Counting Mode 4 .......................................
TPU Interrupts........................................................................................................
271
272
273
274
275
276
277
278
279
280
281
297
300
303
307
308
309
310
311
314
Section 10 Programmable Pulse Generator (PPG)
Table 10.1 Pin Configuration ................................................................................................... 337
Section 11 8-Bit Timers (TMR)
Table 11.1 Pin Configuration ...................................................................................................
Table 11.2 Clock Input to TCNT and Count Condition ...........................................................
Table 11.3 8-Bit Timer Interrupt Sources ................................................................................
Table 11.4 Timer Output Priorities ..........................................................................................
Table 11.5 Switching of Internal Clock and TCNT Operation ................................................
359
362
373
377
378
Section 12 Watchdog Timer
Table 12.1 Pin Configuration ................................................................................................... 382
Table 12.2 WDT Interrupt Source............................................................................................ 388
Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.1 Pin Configuration ...................................................................................................
Table 13.2 Relationships between N Setting in BRR and Bit Rate B ......................................
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1).............................
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2).............................
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3).............................
396
411
412
413
414
Rev. 3.00 Feb 22, 2006 page xxxvii of xl
Table 13.3
Table 13.4
Table 13.5
Table 13.6
Table 13.7
Table 13.8
BRR Settings for Various Bit Rates (Asynchronous Mode) (4).............................
Maximum Bit Rate for Each Frequency (Asynchronous Mode)............................
Maximum Bit Rate with External Clock Input (Asynchronous Mode)..................
BRR Settings for Various Bit Rates (Clocked Synchronous Mode) ......................
Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)......
Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(when n = 0 and S = 372) .......................................................................................
Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372) .......................................................................................................
Serial Transfer Formats (Asynchronous Mode) .....................................................
SSR Status Flags and Receive Data Handling........................................................
Settings of Bits IrCKS2 to IrCKS0 ........................................................................
SCI Interrupt Sources .............................................................................................
SCI Interrupt Sources .............................................................................................
419
424
431
463
464
465
Section 14 A/D Converter
Table 14.1 A/D Converter Pin Configuration ..........................................................................
Table 14.2 Analog Input Channels and Corresponding ADDR Registers................................
Table 14.3 A/D Conversion Time (Single Mode) ....................................................................
Table 14.4 A/D Conversion Time (Scan Mode).......................................................................
Table 14.5 A/D Converter Interrupt Source .............................................................................
Table 14.6 Analog Pin Specifications ......................................................................................
475
476
482
483
484
489
Table 13.9
Table 13.10
Table 13.11
Table 13.12
Table 13.13
Table 13.14
415
416
416
417
418
419
Section 15 D/A Converter
Table 15.1 Pin Configuration ................................................................................................... 493
Table 15.2 Control of D/A Conversion .................................................................................... 495
Table 15.3 Control of D/A Conversion .................................................................................... 497
Section 17 Flash Memory (F-ZTAT Version)
Table 17.1 Differences between Boot Mode and User Program Mode.................................... 503
Table 17.2 Pin Configuration ................................................................................................... 508
Table 17.3 Erase Blocks........................................................................................................... 513
Table 17.4 Setting On-Board Programming Modes................................................................. 515
Table 17.5 Boot Mode Operation............................................................................................. 517
Table 17.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is
Possible .................................................................................................................. 518
Table 17.7 Flash Memory Operating States ............................................................................. 527
Section 18 Clock Pulse Generator
Table 18.1 Damping Resistance Value .................................................................................... 536
Table 18.2 Crystal Resonator Characteristics........................................................................... 537
Rev. 3.00 Feb 22, 2006 page xxxviii of xl
Table 18.3
External Clock Input Conditions ............................................................................ 538
Section 19 Power-Down Modes
Table 19.1 Operating Modes .................................................................................................... 544
Table 19.2 Oscillation Stabilization Time Settings .................................................................. 551
Table 19.3 φ Pin State in Each Processing State ...................................................................... 554
Section 21
Table 21.1
Table 21.2
Table 21.3
Table 21.4
Table 21.5
Table 21.6
Table 21.7
Table 21.8
Table 21.9
Table 21.10
Table 21.11
Table 21.12
Electrical Characteristics
Absolute Maximum Ratings...................................................................................
DC Characteristics (1) ............................................................................................
DC Characteristics (2) ............................................................................................
Permissible Output Currents ..................................................................................
Clock Timing .........................................................................................................
Control Signal Timing............................................................................................
Bus Timing (1) .......................................................................................................
Bus Timing (2) .......................................................................................................
Timing of On-Chip Peripheral Modules.................................................................
A/D Conversion Characteristics .............................................................................
D/A Conversion Characteristics .............................................................................
Flash Memory Characteristics................................................................................
585
586
587
588
590
592
594
595
602
606
606
607
Rev. 3.00 Feb 22, 2006 page xxxix of xl
Rev. 3.00 Feb 22, 2006 page xl of xl
Section 1 Overview
Section 1 Overview
1.1
Features
• High-speed H8S/2600 central processing unit with an internal 16-bit architecture
Upward-compatible with H8/300 and H8/300H CPUs on an object level
Sixteen 16-bit general registers
69 basic instructions
• Various peripheral functions
Data transfer controller (DTC)
16-bit timer-pulse unit (TPU)
Programmable pulse generator (PPG)
8-bit timer (TMR)
Watchdog timer (WDT)
Asynchronous or clocked synchronous serial communication interface (SCI)
10-bit A/D converter
8-bit D/A converter
Clock pulse generator
• On-chip memory
ROM Type
Model
ROM
RAM
Flash memory version
HD64F2667
384 kbytes
16 kbytes
• General I/O ports
I/O pins: 103
Input-only pins: 12
• Supports various power-down states
• Compact package
Package
(Code)
Body Size
Pin Pitch
LQFP-144
FP-144H
22.0 × 22.0 mm
0.5 mm
Rev. 3.00 Feb 22, 2006 page 1 of 624
REJ09B0281-0300
Section 1 Overview
Port A
Port B
Port C
ROM
PB7/A15
PB6/A14
PB5/A13
PB4/A12
PB3 / A11
PB2/A10
PB1/A9
PB0/A8
PC7/A7
PC6/A6
PC5/A5
PC4/A4
PC3/A3
PC2/A2
PC1/A1
PC0/A0
Port 3
Port 6
DTC
PA7/A23
PA6/A22
PA5/A21
PA4/A20
PA3/A19
PA2/A18
PA1/A17
PA0/A16
P35/SCK1
P34/SCK0
P33/RxD1
P32/RxD0/IrRxD
P31/TxD1
P30/TxD0/IrTxD
Port 5
Port G
P65/TMO1
P64/TMO0
P63/TMCI1
P62/TMCI0
P61/TMRI1
P60/TMRI0
Interrupt controller
Peripheral address bus
Port F
PG6/BREQ
PG5/BACK
PG4/BREQO
PG3/CS3
PG2/CS2
PG1/CS1
PG0/CS0
Bus controller
Internal data bus
H8S/2600 CPU
Clock
pulse
generator
Peripheral data bus
PE7/D7
PE6/D6
PE5/D5
PE4/D4
PE3/D3
PE2/D2
PE1/D1
PE0/D0
Port E
PLL
PF7/φ
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2
PF1
PF0/WAIT
P57/AN15/DA3/IRQ7
P56/AN14/DA2/IRQ6
P55/AN13/IRQ5
P54/AN12/IRQ4
P53/ADTRG//IRQ3
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
WDT
RAM
TMR × 2 channels
SCI × 3 channels
TPU × 6 channels
8-bit D/A converter
PPG
Port 8
Port 4
Port 7
Port H
P75
P74
P73
P72
P71
P70
PH3/CS7/(IRQ7)
PH2/CS6/(IRQ6)
PH1/CS5
PH0/CS4
P20 / PO0 / TIOCA3
P21 / PO1 / TIOCB3
P22 / PO2 / TIOCC3
P23 / PO3 / TIOCD3
P24 / PO4 / TIOCA4
P25 / PO5 / TIOCB4
P26 / PO6 / TIOCA5
P27 / PO7 / TIOCB5
Port 2
P10/ PO8 / TIOCA0
P11 / PO9 / TIOCB0
P12 / PO10 / TIOCC0 / TCLKA
P13 / PO11 /TIOCD0 / TCLKB
P14 / PO12 / TIOCA1
P15 / PO13 / TIOCB1 / TCLKC
P16 / PO14 / TIOCA2
P17 / PO15 / TIOCB2 / TCLKD
Port 1
P47 / AN7 / DA1
P46 / AN6 / DA0
P45 / AN5
P44 / AN4
P43 / AN3
P42 / AN2
P41 / AN1
P40 / AN0
10-bit A/D converter
Vref
AVcc
AVss
P85/(IRQ5)
P84/(IRQ4)
P83/(IRQ3)
P82/(IRQ2)
P81/(IRQ1)
P80/(IRQ0)
Port D
Internal address bus
MD2
MD1
MD0
EXTAL
XTAL
STBY
RES
WDTOVF
NMI
PD7/D15
PD6/D14
PD5/D13
PD4/D12
PD3/D11
PD2/D10
PD1/D9
PD0/D8
Block Diagram
Vcc
Vcc
Vcc
Vcc
Vcc
PLLVcc
PLLVss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
Vss
1.2
Figure 1.1 Internal Block Diagram
Rev. 3.00 Feb 22, 2006 page 2 of 624
REJ09B0281-0300
Section 1 Overview
Pin Description
1.3.1
Pin Arrangement
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
FP-144H
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
PD7 / D15
PE0 / D0
PE1 / D1
PE2 / D2
PE3 / D3
Vcc
PE4 / D4
PE5 / D5
PE6 / D6
PE7 / D7
Vss
P61/TMRI1
P60/TMRI0
P27/ PO7 / TIOCB5
P26/ PO6 / TIOCA5
P25/ PO5/TIOCB4
P24/ PO4/TIOCA4
P23/ PO3/TIOCD3
P22/ PO2/TIOCC3
P21/PO1/TIOCB3
P20/PO0/TIOCA3
P17/ PO15/TIOCB2 /TCLKD
P16/PO14/TIOCA2
P15/ PO13/TIOCB1 /TCLKC
P14/PO12/TIOCA1
Vss
P13/ PO11/TIOCD0 /TCLKB
P12/ PO10/TIOCC0 /TCLKA
P11/ PO9/TIOCB0
P10/ PO8/TIOCA0
P75
P74
P73
Vcc
NMI
WDTOVF
MD2
P83 /(IRQ3)
P84 /(IRQ4)
P85 /(IRQ5)
Vcc
PC0/A0
PC1/A1
PC2/A2
PC3/A3
PC4/A4
PC5/A5
Vss
PC6/A6
PC7/A7
PB0/A8
PB1/A9
PB2/A10
PB3/A11
Vss
PB4/A12
PB5/A13
PB6/A14
PB7/A15
PA0/A16
PA1/A17
Vss
PA2/A18
PA3/A19
PA4/A20
PA5/A21
PA6/A22
PA7/A23
NC*
P70
P71
P72
P52/SCK2/IRQ2
P53/ADTRG/IRQ3
PH2/CS6/(IRQ6)
PH3/CS7/(IRQ7)
PG4 / BREQO
PG5 /BACK
PG6 /BREQ
Vcc
P40 / AN0
P41 / AN1
P42 / AN2
P43 / AN3
Vref
AVcc
P44 / AN4
P45 / AN5
P46 / AN6 / DA0
P47 / AN7 / DA1
P54 / AN12/IRQ4
P55 / AN13/IRQ5
P56 / AN14/DA2/IRQ6
P57 / AN15/DA3/IRQ7
AVss
NC*
P35 / SCK1
P34 / SCK0
P33 / RxD1
Vss
P32 / RxD0/IrRxD
P31 / TxD1
P30 / TxD0/IrTxD
P80 / (IRQ0)
P81 / (IRQ1)
P82/(IRQ2)
MD0
MD1
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
P51/RxD2/IRQ1
P50/TxD2/IRQ0
PH1/CS5
PH0/CS4
PG3/CS3
PG2/CS2
PG1/CS1
PG0/CS0
STBY
Vss
XTAL
EXTAL
Vcc
PF7/φ
PLLVcc
RES
PLLVss
PF6/AS
PF5/RD
PF4/HWR
PF3/LWR
PF2
PF1
PF0/WAIT
P65/TMO1
P64/TMO0
P63/TMCI1
P62/TMCI0
PD0/D8
PD1/D9
PD2/D10
PD3/D11
Vss
PD4/D12
PD5/D13
PD6/D14
1.3
Note: * An NC pin should be unconnected.
Figure 1.2 Pin Arrangement
Rev. 3.00 Feb 22, 2006 page 3 of 624
REJ09B0281-0300
Section 1 Overview
1.3.2
Pin Arrangement in Each Operating Mode
Table 1.1
Pin Arrangement in Each Operating Mode
Pin Name
Mode 7
Modes 1
and 5
Modes 2
and 6
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
1
MD2
MD2
MD2
MD2
MD2
Vss
2
P83/(IRQ3)
P83/(IRQ3)
P83/(IRQ3)
P83/(IRQ3)
P83/(IRQ3)
NC
3
P84/(IRQ4)
P84/(IRQ4)
P84/(IRQ4)
P84/(IRQ4)
P84/(IRQ4)
NC
4
P85/(IRQ5)
P85/(IRQ5)
P85/(IRQ5)
P85/(IRQ5)
P85/(IRQ5)
NC
5
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
6
A0
A0
PC0/A0
PC0/A0
PC0
A0
7
A1
A1
PC1/A1
PC1/A1
PC1
A1
8
A2
A2
PC2/A2
PC2/A2
PC2
A2
Pin
No.
9
A3
A3
PC3/A3
PC3/A3
PC3
A3
10
A4
A4
PC4/A4
PC4/A4
PC4
A4
11
A5
A5
PC5/A5
PC5/A5
PC5
A5
12
Vss
Vss
Vss
Vss
Vss
Vss
13
A6
A6
PC6/A6
PC6/A6
PC6
A6
14
A7
A7
PC7/A7
PC7/A7
PC7
A7
15
A8
A8
PB0/A8
PB0/A8
PB0
A8
16
A9
A9
PB1/A9
PB1/A9
PB1
A9
17
A10
A10
PB2/A10
PB2/A10
PB2
A10
18
A11
A11
PB3/A11
PB3/A11
PB3
A11
19
Vss
Vss
Vss
Vss
Vss
Vss
20
A12
A12
PB4/A12
PB4/A12
PB4
A12
21
A13
A13
PB5/A13
PB5/A13
PB5
A13
22
A14
A14
PB6/A14
PB6/A14
PB6
A14
23
A15
A15
PB7/A15
PB7/A15
PB7
A15
24
A16
A16
PA0/A16
PA0/A16
PA0
A16
25
A17
A17
PA1/A17
PA1/A17
PA1
A17
26
Vss
Vss
Vss
Vss
Vss
Vss
27
A18
A18
PA2/A18
PA2/A18
PA2
A18
28
A19
A19
PA3/A19
PA3/A19
PA3
NC
Rev. 3.00 Feb 22, 2006 page 4 of 624
REJ09B0281-0300
Section 1 Overview
Pin Name
Pin
No.
Modes 1
and 5
Modes 2
and 6
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
29
A20
A20
PA4/A20
PA4/A20
PA4
NC
30
PA5/A21
PA5/A21
PA5/A21
PA5/A21
PA5
NC
31
PA6/A22
PA6/A22
PA6/A22
PA6/A22
PA6
NC
32
PA7/A23
PA7/A23
PA7/A23
PA7/A23
PA7
NC
33
NC
NC
NC
NC
NC
NC
34
P70
P70
P70
P70
P70
NC
35
P71
P71
P71
P71
P71
NC
36
P72
P72
P72
P72
P72
NC
37
WDTOVF
WDTOVF
WDTOVF
WDTOVF
WDTOVF
NC
38
NMI
NMI
NMI
NMI
NMI
Vcc
39
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
40
P73
P73
P73
P73
P73
NC
41
P74
P74
P74
P74
P74
NC
42
P75
P75
P75
P75
P75
NC
43
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
P10/PO8/
TIOCA0
NC
44
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
P11/PO9/
TIOCB0
NC
45
P12/PO10/
TIOCC0/
TCLKA
P12/PO10/
TIOCC0/
TCLKA
P12/PO10/
TIOCC0/
TCLKA
P12/PO10/
TIOCC0/
TCLKA
P12/PO10/
TIOCC0/
TCLKA
NC
46
P13/PO11/
TIOCD0/
TCLKB
P13/PO11/
TIOCD0/
TCLKB
P13/PO11/
TIOCD0/
TCLKB
P13/PO11/
TIOCD0/
TCLKB
P13/PO11/
TIOCD0/
TCLKB
NC
47
Vss
Vss
Vss
Vss
Vss
Vss
48
P14/PO12/
TIOCA1
P14/PO12/
TIOCA1
P14/PO12/
TIOCA1
P14/PO12/
TIOCA1
P14/PO12/
TIOCA1
NC
49
P15/PO13/
TIOCB1/
TCLKC
P15/PO13/
TIOCB1/
TCLKC
P15/PO13/
TIOCB1/
TCLKC
P15/PO13/
TIOCB1/
TCLKC
P15/PO13/
TIOCB1/
TCLKC
NC
50
P16/PO14/
TIOCA2
P16/PO14/
TIOCA2
P16/PO14/
TIOCA2
P16/PO14/
TIOCA2
P16/PO14/
TIOCA2
NC
51
P17/PO15/
TIOCB2/
TCLKD
P17/PO15/
TIOCB2/
TCLKD
P17/PO15/
TIOCB2/
TCLKD
P17/PO15/
TIOCB2/
TCLKD
P17/PO15/
TIOCB2/
TCLKD
NC
Mode 7
Rev. 3.00 Feb 22, 2006 page 5 of 624
REJ09B0281-0300
Section 1 Overview
Pin Name
Mode 7
Flash Memory
Programmer
Mode
Pin
No.
Modes 1
and 5
Modes 2
and 6
Mode 4
EXPE = 1
EXPE = 0
52
P20/PO0/
TIOCA3
P20/PO0/
TIOCA3
P20/PO0/
TIOCA3
P20/PO0/
TIOCA3
P20/PO0/
TIOCA3
NC
53
P21/PO1/
TIOCB3
P21/PO1/
TIOCB3
P21/PO1/
TIOCB3
P21/PO1/
TIOCB3
P21/PO1/
TIOCB3
NC
54
P22/PO2/
TIOCC3
P22/PO2/
TIOCC3
P22/PO2/
TIOCC3
P22/PO2/
TIOCC3
P22/PO2/
TIOCC3
OE
55
P23/PO3/
TIOCD3
P23/PO3/
TIOCD3
P23/PO3/
TIOCD3
P23/PO3/
TIOCD3
P23/PO3/
TIOCD3
CE
56
P24/PO4/
TIOCA4
P24/PO4/
TIOCA4
P24/PO4/
TIOCA4
P24/PO4/
TIOCA4
P24/PO4/
TIOCA4
WE
57
P25/PO5/
TIOCB4
P25/PO5/
TIOCB4
P25/PO5/
TIOCB4
P25/PO5/
TIOCB4
P25/PO5/
TIOCB4
Vss
58
P26/PO6/
TIOCA5
P26/PO6/
TIOCA5
P26/PO6/
TIOCA5
P26/PO6/
TIOCA5
P26/PO6/
TIOCA5
NC
59
P27/PO7/
TIOCB5
P27/PO7/
TIOCB5
P27/PO7/
TIOCB5
P27/PO7/
TIOCB5
P27/PO7/
TIOCB5
NC
60
P60/TMRI0
P60/TMRI0
P60/TMRI0
P60/TMRI0
P60/TMRI0
NC
61
P61/TMRI1
P61/TMRI1
P61/TMRI1
P61/TMRI1
P61/TMRI1
NC
62
Vss
Vss
Vss
Vss
Vss
Vss
63
D7
PE7/D7
PE7/D7
PE7/D7
PE7
NC
64
D6
PE6/D6
PE6/D6
PE6/D6
PE6
NC
65
D5
PE5/D5
PE5/D5
PE5/D5
PE5
NC
66
D4
PE4/D4
PE4/D4
PE4/D4
PE4
NC
67
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
68
D3
PE3/D3
PE3/D3
PE3/D3
PE3
NC
69
D2
PE2/D2
PE2/D2
PE2/D2
PE2
NC
70
D1
PE1/D1
PE1/D1
PE1/D1
PE1
NC
71
D0
PE0/D0
PE0/D0
PE0/D0
PE0
NC
72
D15
D15
D15
D15
PD7
I/O7
73
D14
D14
D14
D14
PD6
I/O6
74
D13
D13
D13
D13
PD5
I/O5
75
D12
D12
D12
D12
PD4
I/O4
76
Vss
Vss
Vss
Vss
Vss
Vss
Rev. 3.00 Feb 22, 2006 page 6 of 624
REJ09B0281-0300
Section 1 Overview
Pin Name
Pin
No.
Modes 1
and 5
Modes 2
and 6
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
77
D11
D11
D11
D11
PD3
I/O3
78
D10
D10
D10
D10
PD2
I/O2
79
D9
D9
D9
D9
PD1
I/O1
80
D8
D8
D8
D8
PD0
I/O0
81
P62/TMCI0
P62/TMCI0
P62/TMCI0
P62/TMCI0
P62/TMCI0
NC
82
P63/TMCI1
P63/TMCI1
P63/TMCI1
P63/TMCI1
P63/TMCI1
NC
83
P64/TMO0
P64/TMO0
P64/TMO0
P64/TMO0
P64/TMO0
NC
84
P65/TMO1
P65/TMO1
P65/TMO1
P65/TMO1
P65/TMO1
NC
85
PF0/WAIT
PF0/WAIT
PF0/WAIT
PF0/WAIT
PF0
NC
86
PF1
PF1
PF1
PF1
PF1
NC
87
PF2
PF2
PF2
PF2
PF2
NC
88
PF3/LWR
PF3/LWR
PF3/LWR
PF3/LWR
PF3
NC
89
HWR
HWR
HWR
HWR
PF4
NC
90
RD
RD
RD
RD
PF5
NC
91
PF6/AS
PF6/AS
PF6/AS
PF6/AS
PF6
NC
92
PLLVss
PLLVss
PLLVss
PLLVss
PLLVss
Vss
93
RES
RES
RES
RES
RES
RES
94
PLLVcc
PLLVcc
PLLVcc
PLLVcc
PLLVcc
Vcc
Mode 7
95
PF7/φ
PF7/φ
PF7/φ
PF7/φ
PF7/φ
NC
96
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
97
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
EXTAL
98
XTAL
XTAL
XTAL
XTAL
XTAL
XTAL
99
Vss
Vss
Vss
Vss
Vss
Vss
100
STBY
STBY
STBY
STBY
STBY
Vcc
101
PG0/CS0
PG0/CS0
PG0/CS0
PG0/CS0
PG0
NC
102
PG1/CS1
PG1/CS1
PG1/CS1
PG1/CS1
PG1
NC
103
PG2/CS2
PG2/CS2
PG2/CS2
PG2/CS2
PG2
NC
104
PG3/CS3
PG3/CS3
PG3/CS3
PG3/CS3
PG3
NC
105
PH0/CS4
PH0/CS4
PH0/CS4
PH0/CS4
PH0
NC
106
PH1/CS5
PH1/CS5
PH1/CS5
PH1/CS5
PH1
NC
Rev. 3.00 Feb 22, 2006 page 7 of 624
REJ09B0281-0300
Section 1 Overview
Pin Name
Mode 7
Flash Memory
Programmer
Mode
Pin
No.
Modes 1
and 5
Modes 2
and 6
Mode 4
EXPE = 1
EXPE = 0
107
P50/TxD2/
IRQ0
P50/TxD2/
IRQ0
P50/TxD2/
IRQ0
P50/TxD2/
IRQ0
P50/TxD2/
IRQ0
Vss
108
P51/RxD2/
IRQ1
P51/RxD2/
IRQ1
P51/RxD2/
IRQ1
P51/RxD2/
IRQ1
P51/RxD2/
IRQ1
Vss
109
P52/SCK2/
IRQ2
P52/SCK2/
IRQ2
P52/SCK2/
IRQ2
P52/SCK2/
IRQ2
P52/SCK2/
IRQ2
Vcc
110
P53/ADTRG/
IRQ3
P53/ADTRG/
IRQ3
P53/ADTRG/
IRQ3
P53/ADTRG/
IRQ3
P53/ADTRG/
IRQ3
NC
111
PH2/CS6/
(IRQ6)
PH2/CS6/
(IRQ6)
PH2/CS6/
(IRQ6)
PH2/CS6/
(IRQ6)
PH2/(IRQ6)
NC
112
PH3/CS7/
(IRQ7)
PH3/CS7/
(IRQ7)
PH3/CS7/
(IRQ7)
PH3/CS7/
(IRQ7)
PH3/(IRQ7)
NC
113
PG4/BREQO
PG4/BREQO
PG4/BREQO
PG4/BREQO
PG4
NC
114
PG5/BACK
PG5/BACK
PG5/BACK
PG5/BACK
PG5
NC
115
PG6/BREQ
PG6/BREQ
PG6/BREQ
PG6/BREQ
PG6
NC
116
Vcc
Vcc
Vcc
Vcc
Vcc
Vcc
117
P40/AN0
P40/AN0
P40/AN0
P40/AN0
P40/AN0
NC
118
P41/AN1
P41/AN1
P41/AN1
P41/AN1
P41/AN1
NC
119
P42/AN2
P42/AN2
P42/AN2
P42/AN2
P42/AN2
NC
120
P43/AN3
P43/AN3
P43/AN3
P43/AN3
P43/AN3
NC
121
Vref
Vref
Vref
Vref
Vref
NC
122
AVcc
AVcc
AVcc
AVcc
AVcc
Vcc
123
P44/AN4
P44/AN4
P44/AN4
P44/AN4
P44/AN4
NC
124
P45/AN5
P45/AN5
P45/AN5
P45/AN5
P45/AN5
NC
125
P46/AN6/DA0
P46/AN6/DA0
P46/AN6/DA0
P46/AN6/DA0
P46/AN6/DA0
NC
126
P47/AN7/DA1
P47/AN7/DA1
P47/AN7/DA1
P47/AN7/DA1
P47/AN7/DA1
NC
127
P54/AN12/
IRQ4
P54/AN12/
IRQ4
P54/AN12/
IRQ4
P54/AN12/
IRQ4
P54/AN12/
IRQ4
NC
128
P55/AN13/
IRQ5
P55/AN13/
IRQ5
P55/AN13/
IRQ5
P55/AN13/
IRQ5
P55/AN13/
IRQ5
NC
129
P56/AN14/
DA2/IRQ6
P56/AN14/
DA2/IRQ6
P56/AN14/
DA2/IRQ6
P56/AN14/
DA2/IRQ6
P56/AN14/
DA2/IRQ6
NC
130
P57/AN15/
DA3/IRQ7
P57/AN15/
DA3/IRQ7
P57/AN15/
DA3/IRQ7
P57/AN15/
DA3/IRQ7
P57/AN15/
DA3/IRQ7
NC
Rev. 3.00 Feb 22, 2006 page 8 of 624
REJ09B0281-0300
Section 1 Overview
Pin Name
Pin
No.
Modes 1
and 5
Modes 2
and 6
Mode 4
EXPE = 1
EXPE = 0
Flash Memory
Programmer
Mode
131
AVss
AVss
AVss
AVss
AVss
Vss
132
NC
NC
NC
NC
NC
NC
133
P35/SCK1
P35/SCK1
P35/SCK1
P35/SCK1
P35/SCK1
NC
134
P34/SCK0
P34/SCK0
P34/SCK0
P34/SCK0
P34/SCK0
NC
135
P33/RxD1
P33/RxD1
P33/RxD1
P33/RxD1
P33/RxD1
NC
136
Vss
Vss
Vss
Vss
Vss
Vss
137
P32/RxD0/
IrRxD
P32/RxD0/
IrRxD
P32/RxD0/
IrRxD
P32/RxD0/
IrRxD
P32/RxD0/
IrRxD
Vcc
138
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
P31/TxD1
NC
139
P30/TxD0/
IrTxD
P30/TxD0/
IrTxD
P30/TxD0/
IrTxD
P30/TxD0/
IrTxD
P30/TxD0/
IrTxD
NC
140
P80/(IRQ0)
P80/(IRQ0)
P80/(IRQ0)
P80/(IRQ0)
P80/(IRQ0)
NC
141
P81/(IRQ1)
P81/(IRQ1)
P81/(IRQ1)
P81/(IRQ1)
P81/(IRQ1)
NC
Mode 7
142
P82/(IRQ2)
P82/(IRQ2)
P82/(IRQ2)
P82/(IRQ2)
P82/(IRQ2)
NC
143
MD0
MD0
MD0
MD0
MD0
Vss
144
MD1
MD1
MD1
MD1
MD1
Vss
Rev. 3.00 Feb 22, 2006 page 9 of 624
REJ09B0281-0300
Section 1 Overview
1.3.3
Pin Functions
Table 1.2
Pin Functions
Type
Symbol
Power
VCC
Pin No.
FP-144H
I/O
Function
5, 39, 67,
96, 116
Input
For connection to the power supply. All VCC
pins should be connected to the system
power supply.
VSS
12, 19, 26,
47, 76, 99,
136
Input
For connection to ground. All VSS pins should
be connected to the system power supply
(0 V).
PLLVCC
94
Input
Power supply pin for the on-chip PLL
oscillator.
PLLVSS
92
Input
Ground pin for the on-chip PLL oscillator.
XTAL
98
Input
For connection to a crystal oscillator. See
section 18, Clock Pulse Generator for typical
connection diagrams for a crystal oscillator
and external clock input.
EXTAL
97
Input
For connection to a crystal oscillator. The
EXTAL pin can also input an external clock.
See section 18, Clock Pulse Generator for
typical connection diagrams for a crystal
oscillator and external clock input.
φ
95
Output
Supplies the system clock to external
devices.
Operating
mode control
MD2
MD1
MD0
1, 144, 143
Input
These pins set the operating mode. These
pins should not be changed while the MCU is
operating.
System
control
RES
93
Input
When this pin is driven low, the chip is reset.
STBY
100
Input
When this pin is driven low, a transition is
made to hardware standby mode.
BREQ
115
Input
Requests chip to release the bus to an
external bus master.
BREQO
113
Output
External bus request signal used when an
internal bus master accesses external space
when the external bus is released.
BACK
114
Output
Indicates that the bus has been released to
an external bus master.
Clock
Rev. 3.00 Feb 22, 2006 page 10 of 624
REJ09B0281-0300
Section 1 Overview
Pin No.
FP-144H
I/O
Function
32 to 27,
25 to 20,
18 to 13,
11 to 6
Output
These pins output an address.
D15 to D0
72 to 75,
77 to 80,
63 to 66,
68 to 71
Input/
output
These pins constitute a bidirectional data
bus.
CS7 to
CS0
112, 111,
106 to 101
Output
Signals that select division areas 7 to 0 in the
external address space.
AS
91
Output
When this pin is low, it indicates that address
output on the address bus is valid.
RD
90
Output
When this pin is low, it indicates that the
external address space is being read.
HWR
89
Output
Strobe signal indicating that external address
space is to be written, and the upper half
(D15 to D8) of the data bus is enabled.
Type
Symbol
Address bus
A23 to A0
Data bus
Bus control
Write enable signal for DRAM interface
space.
Interrupt
signals
LWR
88
Output
Strobe signal indicating that external address
space is to be written, and the lower half (D7
to D0) of the data bus is enabled.
WAIT
85
Input
Requests insertion of a wait state in the bus
cycle when accessing external 3-state
address space.
NMI
38
Input
Nonmaskable interrupt request pin. Fix high
when not used.
IRQ7 to
IRQ0
130 to 127,
110 to 107
Input
These pins request a maskable interrupt.
(IRQ7) to
(IRQ0)
112, 111,
4 to 2,
142 to 140
The input pins of DREQn and (DREQn) are
selected by the IRQ pin select register
(ITSR) of the interrupt controller. (n = 0 to 7)
Rev. 3.00 Feb 22, 2006 page 11 of 624
REJ09B0281-0300
Section 1 Overview
Pin No.
FP-144H
I/O
Function
45, 46, 49,
51
Input
External clock input pins.
TIOCA0
TIOCB0
TIOCC0
TIOCD0
43, 44, 45,
46
Input/
output
TGRA_0 to TGRD_0 input capture
input/output compare output/PWM output
pins.
TIOCA1
TIOCB1
48, 49
Input/
output
TGRA_1 and TGRB_1 input capture
input/output compare output/PWM output
pins.
TIOCA2
TIOCB2
50, 51
Input/
output
TGRA_2 and TGRB_2 input capture
input/output compare output/PWM output
pins.
TIOCA3
TIOCB3
TIOCC3
TIOCD3
52, 53, 54,
55
Input/
output
TGRA_3 to TGRD_3 input capture
input/output compare output/PWM output
pins.
TIOCA4
TIOCB4
56, 57
Input/
output
TGRA_4 and TGRB_4 input capture
input/output compare output/PWM output
pins.
TIOCA5,
TIOCB5
58, 59
Input/
output
TGRA_5 and TGRB_5 input capture
input/output compare output/PWM output
pins.
Programmable PO15 to
pulse
PO0
generator
(PPG)
51 to 48,
46 to 43,
59 to 52
Output
Pulse output pins.
8-bit timer
TMO0
TMO1
83, 84
Output
Waveform output pins with output compare
function.
TMCI0
TMCI1
81, 82
Input
External event input pins.
TMRI0
TMRI1
60, 61
Input
Counter reset input pins.
WDTOVF
37
Output
Counter overflow signal output pin in
watchdog timer mode.
Type
Symbol
16-bit timer
pulse unit
(TPU)
TCLKA
TCLKB
TCLKC
TCLKD
Watchdog
timer (WDT)
Rev. 3.00 Feb 22, 2006 page 12 of 624
REJ09B0281-0300
Section 1 Overview
Function
TxD2
107, 138,
TxD1
139
TxD0/IrTxD
Output
Data output pins.
RxD2
RxD1
RxD0/
IrRxD
108, 135,
137
Input
Data input pins.
SCK2
SCK1
SCK0
109, 133,
134
Input/
output
Clock input/output pins.
AN15 to
AN12,
AN7 to
AN0
130 to 127,
126 to 123,
120 to 117
Input
Analog input pins for the A/D converter.
ADTRG
110
Input
Pin for input of an external trigger to start
A/D conversion.
DA3 to
DA0
130, 129,
126, 125
Output
Analog input pins for the D/A converter.
122
Input
The analog power-supply pin for the A/D
converter and D/A converter.
Symbol
Serial communication
interface
(SCI)/smart
card interface
(SCI_0 with
IrDA function)
A/D converter
D/A converter
Pin No.
FP-144H
I/O
Type
A/D converter, AVCC
D/A converter
When the A/D converter and D/A converter
are not used, this pin should be connected to
the system power supply (+3 V).
AVSS
131
Input
The ground pin for the A/D converter and
D/A converter.
This pin should be connected to the system
power supply (0 V).
Vref
121
Input
The reference voltage input pin for the A/D
converter and D/A converter.
When the A/D converter and D/A converter
are not used, this pin should be connected to
the system power supply (+3 V).
Rev. 3.00 Feb 22, 2006 page 13 of 624
REJ09B0281-0300
Section 1 Overview
Type
Symbol
Pin No.
FP-144H
I/O
Function
I/O ports
P17 to
P10
51 to 48,
46 to 43
Input/
output
Eight input/output pins.
P27 to
P20
59 to 52
Input/
output
Eight input/output pins.
P35 to
P30
133 to 135,
137 to 139
Input/
output
Six input/output pins.
P47 to
P40
126 to 123,
120 to 117
Input
Eight input pins.
P57 to
P54
130 to 127
Input
Four input pins.
P53 to
P50
110 to 107
Input/
output
Four input/output pins.
P65 to
P60
84 to 81,
61, 60
Input/
output
Six input/output pins.
P75 to
P70
42 to 40,
36 to 34
Input/
output
Six input/output pins.
P85 to
P80
4 to 2,
142 to 140
Input/
output
Six input/output pins.
PA7 to
PA0
32 to 27,
25, 24
Input/
output
Eight input/output pins.
PB7 to
PB0
23 to 20,
18 to 15
Input/
output
Eight input/output pins.
PC7 to
PC0
14, 13,
11 to 6
Input/
output
Eight input/output pins.
PD7 to
PD0
72 to 75,
77 to 80
Input/
output
Eight input/output pins.
PE7 to
PE0
63 to 66,
68 to 71
Input/
output
Eight input/output pins.
PF7 to
PF0
95, 91 to 85
Input/
output
Eight input/output pins.
PG6 to
PG0
115 to 113,
104 to 101
Input/
output
Seven input/output pins.
PH3 to
PH0
112, 111,
106, 105
Input/
output
Four input/output pins.
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Section 2 CPU
Section 2 CPU
The H8S/2600 CPU is a high-speed central processing unit with an internal 32-bit architecture that
is upward-compatible with the H8/300 and H8/300H CPUs. The H8S/2600 CPU has sixteen 16-bit
general registers, can address a 16-Mbyte linear address space, and is ideal for realtime control.
This section describes the H8S/2600 CPU. The usable modes and address spaces differ depending
on the product. For details on each product, refer to section 3, MCU Operating Modes.
2.1
Features
• Upward-compatible with H8/300 and H8/300H CPUs
Can execute H8/300 and H8/300H object programs
• General-register architecture
Sixteen 16-bit general registers also usable as sixteen 8-bit registers or eight 32-bit registers
• Sixty-nine basic instructions
8/16/32-bit arithmetic and logic instructions
Multiply and divide instructions
Powerful bit-manipulation instructions
Multiply-and-accumulate instruction
• Eight addressing modes
Register direct [Rn]
Register indirect [@ERn]
Register indirect with displacement [@(d:16,ERn) or @(d:32,ERn)]
Register indirect with post-increment or pre-decrement [@ERn+ or @–ERn]
Absolute address [@aa:8, @aa:16, @aa:24, or @aa:32]
Immediate [#xx:8, #xx:16, or #xx:32]
Program-counter relative [@(d:8,PC) or @(d:16,PC)]
Memory indirect [@@aa:8]
• 16-Mbyte address space
Program: 16 Mbytes
Data: 16 Mbytes
• High-speed operation
All frequently-used instructions execute in one or two states
8/16/32-bit register-register add/subtract: 1 state
8 × 8-bit register-register multiply: 3 states
16 ÷ 8-bit register-register divide: 12 states
CPUS260A_020020020400
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Section 2 CPU
16 × 16-bit register-register multiply: 4 states
32 ÷ 16-bit register-register divide: 20 states
• Two CPU operating modes
Normal mode*
Advanced mode
• Power-down state
Transition to power-down state by SLEEP instruction
CPU clock speed selection
Note: * Normal mode is not available in this LSI.
2.1.1
Differences between H8S/2600 CPU and H8S/2000 CPU
The differences between the H8S/2600 CPU and the H8S/2000 CPU are as shown below.
• Register configuration
The MAC register is supported only by the H8S/2600 CPU.
• Basic instructions
The four instructions MAC, CLRMAC, LDMAC, and STMAC are supported only by the
H8S/2600 CPU.
• The number of execution states of the MULXU and MULXS instructions
Execution States
Instruction
MULXU
MULXS
Mnemonic
H8S/2600
H8S/2000
MULXU.B Rs, Rd
3
12
MULXU.W Rs, ERd
4
20
MULXS.B Rs, Rd
4
13
MULXS.W Rs, ERd
5
21
In addition, there are differences in address space, CCR and EXR register functions, power-down
modes, etc., depending on the model.
2.1.2
Differences from H8/300 CPU
In comparison to the H8/300 CPU, the H8S/2600 CPU has the following enhancements.
• More general registers and control registers
Eight 16-bit expanded registers, and one 8-bit and two 32-bit control registers, have been
added.
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Section 2 CPU
• Expanded address space
Normal mode supports the same 64-kbyte address space as the H8/300 CPU.
Advanced mode supports a maximum 16-Mbyte address space.
• Enhanced addressing
The addressing modes have been enhanced to make effective use of the 16-Mbyte address
space.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
Signed multiply and divide instructions have been added.
A multiply-and-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
Note: Normal mode is not available in this LSI.
2.1.3
Differences from H8/300H CPU
In comparison to the H8/300H CPU, the H8S/2600 CPU has the following enhancements.
• Additional control register
One 8-bit and two 32-bit control registers have been added.
• Enhanced instructions
Addressing modes of bit-manipulation instructions have been enhanced.
A multiply-and-accumulate instruction has been added.
Two-bit shift and rotate instructions have been added.
Instructions for saving and restoring multiple registers have been added.
A test and set instruction has been added.
• Higher speed
Basic instructions execute twice as fast.
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Section 2 CPU
2.2
CPU Operating Modes
The H8S/2600 CPU has two operating modes: normal and advanced. Normal mode supports a
maximum 64-kbyte address space. Advanced mode supports a maximum 16-Mbyte total address
space. The mode is selected by the mode pins.
2.2.1
Normal Mode
The exception vector table and stack have the same structure as in the H8/300 CPU.
• Address Space
The H8S/2600 CPU provides linear access to a maximum 64-kbyte address space.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers.
When En is used as a 16-bit register it can contain any value, even when the corresponding
general register (Rn) is used as an address register. If the general register is referenced in the
register indirect addressing mode with pre-decrement (@–Rn) or post-increment (@Rn+) and a
carry or borrow occurs, however, the value in the corresponding extended register (En) will be
affected.
• Instruction Set
All instructions and addressing modes can be used. Only the lower 16 bits of effective
addresses (EA) are valid.
• Exception Vector Table and Memory Indirect Branch Addresses
In normal mode the top area starting at H'0000 is allocated to the exception vector table. One
branch address is stored per 16 bits. The exception vector table in normal mode is shown in
figure 2.1. For details of the exception vector table, see section 4, Exception Handling.
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address. In normal mode the operand is a 16-bit word operand,
providing a 16-bit branch address. Branch addresses can be stored in the top area from H'0000
to H'00FF. Note that this area is also used for the exception vector table.
• Stack Structure
When the program counter (PC) is pushed onto the stack in a subroutine call, and the PC,
condition-code register (CCR), and extended control register (EXR) are pushed onto the stack
in exception handling, they are stored as shown in figure 2.2. EXR is not pushed onto the
stack in interrupt control mode 0. For details, see section 4, Exception Handling.
Note: Normal mode is not available in this LSI.
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Section 2 CPU
H'0000
H'0001
H'0002
H'0003
H'0004
H'0005
H'0006
H'0007
H'0008
H'0009
H'000A
H'000B
Reset exception vector
(Reserved for system use)
(Reserved for system use)
Exception
vector table
Exception vector 1
Exception vector 2
Figure 2.1 Exception Vector Table (Normal Mode)
SP
PC
(16 bits)
EXR*1
SP
Reserved*1*3
*2
(SP
)
CCR
CCR*3
PC
(16 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. lgnored when returning.
Figure 2.2 Stack Structure in Normal Mode
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Section 2 CPU
2.2.2
Advanced Mode
• Address Space
Linear access is provided to a 16-Mbyte maximum address space.
• Extended Registers (En)
The extended registers (E0 to E7) can be used as 16-bit registers, or as the upper 16-bit
segments of 32-bit registers or address registers.
• Instruction Set
All instructions and addressing modes can be used.
• Exception Vector Table and Memory Indirect Branch Addresses
In advanced mode the top area starting at H'00000000 is allocated to the exception vector table
in units of 32 bits. In each 32 bits, the upper 8 bits are ignored and a branch address is stored in
the lower 24 bits (figure 2.3). For details of the exception vector table, see section 4, Exception
Handling.
H'00000000
Reserved
Reset exception vector
H'00000003
H'00000004
Reserved
(Reserved for system use)
H'00000007
H'00000008
Exception vector table
H'0000000B
(Reserved for system use)
H'0000000C
H'00000010
Reserved
Exception vector 1
Figure 2.3 Exception Vector Table (Advanced Mode)
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Section 2 CPU
The memory indirect addressing mode (@@aa:8) employed in the JMP and JSR instructions
uses an 8-bit absolute address included in the instruction code to specify a memory operand
that contains a branch address.
In advanced mode the operand is a 32-bit longword operand, providing a 32-bit branch
address. The upper 8 bits of these 32 bits are a reserved area that is regarded as H'00. Branch
addresses can be stored in the area from H'00000000 to H'000000FF. Note that the first part of
this range is also used for the exception vector table.
• Stack Structure
In advanced mode, when the program counter (PC) is pushed onto the stack in a subroutine
call, and the PC, condition-code register (CCR), and extended control register (EXR) are
pushed onto the stack in exception handling, they are stored as shown in figure 2.4. EXR is not
pushed onto the stack in interrupt control mode 0. For details, see section 4, Exception
Handling.
EXR*1
SP
SP
Reserved*1 *3
Reserved
PC
(24 bits)
(SP*2
)
CCR
PC
(24 bits)
(a) Subroutine Branch
(b) Exception Handling
Notes: 1. When EXR is not used, it is not stored on the stack.
2. SP when EXR is not used.
3. Ignored when returning.
Figure 2.4 Stack Structure in Advanced Mode
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Section 2 CPU
2.3
Address Space
Figure 2.5 shows a memory map of the H8S/2600 CPU. The H8S/2600 CPU provides linear
access to a maximum 64-kbyte address space in normal mode, and a maximum 16-Mbyte
(architecturally 4-Gbyte) address space in advanced mode*. The usable modes and address spaces
differ depending on the product. For details on each product, refer to section 3, MCU Operating
Modes.
Note: * Normal mode is not available in this LSI.
H'0000
H'00000000
64-kbyte
16-Mbyte
H'FFFF
Program area
H'00FFFFFF
Data area
Cannnot be
used in this LSI
H'FFFFFFFF
(a) Normal Mode*
(b) Advanced Mode
Note: * Normal mode cannot be used in this LSI.
Figure 2.5 Memory Map
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Section 2 CPU
2.4
Registers
The H8S/2600 CPU has the internal registers shown in figure 2.6. There are two types of registers:
general registers and control registers. Control registers are a 24-bit program counter (PC), an 8-bit
extended register (EXR), an 8-bit condition code register (CCR), and a 64-bit multiply-accumulate
register (MAC).
General Registers (Rn) and Extended Registers (En)
15
0 7
0 7
0
ER0
E0
R0H
R0L
ER1
E1
R1H
R1L
ER2
E2
R2H
R2L
ER3
E3
R3H
R3L
ER4
E4
R4H
R4L
ER5
E5
R5H
R5L
ER6
E6
R6H
R6L
ER7 (SP)
E7
R7H
R7L
Control Registers (CR)
23
0
PC
7 6 5 4 3 2 1 0
- - - - I2 I1 I0
EXR T
7 6 5 4 3 2 1 0
CCR I UI H U N Z V C
63
41
MAC
32
MACH
Sign extension
MACL
31
0
Legend:
SP:
PC:
EXR:
T:
I2 to I0:
CCR:
I:
UI:
Stack pointer
Program counter
Extended register
Trace bit
Interrupt mask bits
Condition-code register
Interrupt mask bit
User bit or interrupt mask bit*
H:
U:
N:
Z:
V:
C:
MAC:
Half-carry flag
User bit
Negative flag
Zero flag
Overflow flag
Carry flag
Multiply-accumulate register
Note: * UI cannot be used as an interrupt mask bit in this LSI.
Figure 2.6 CPU Registers
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Section 2 CPU
2.4.1
General Registers
The H8S/2600 CPU has eight 32-bit general registers. These general registers are all functionally
alike and can be used as both address registers and data registers. When a general register is used
as a data register, it can be accessed as a 32-bit, 16-bit, or 8-bit register. Figure 2.7 illustrates the
usage of the general registers. When the general registers are used as 32-bit registers or address
registers, they are designated by the letters ER (ER0 to ER7).
The ER registers divide into 16-bit general registers designated by the letters E (E0 to E7) and R
(R0 to R7). These registers are functionally equivalent, providing a maximum sixteen 16-bit
registers. The E registers (E0 to E7) are also referred to as extended registers.
The R registers divide into 8-bit general registers designated by the letters RH (R0H to R7H) and
RL (R0L to R7L). These registers are functionally equivalent, providing a maximum sixteen 8-bit
registers.
The usage of each register can be selected independently.
General register ER7 has the function of stack pointer (SP) in addition to its general-register
function, and is used implicitly in exception handling and subroutine calls. Figure 2.8 shows the
stack.
• Address registers
• 32-bit registers
• 16-bit registers
• 8-bit registers
E registers (extended registers)
(E0 to E7)
ER registers
(ER0 to ER7)
RH registers
(R0H to R7H)
R registers
(R0 to R7)
RL registers
(R0L to R7L)
Figure 2.7 Usage of General Registers
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Section 2 CPU
Free area
SP (ER7)
Stack area
Figure 2.8 Stack
2.4.2
Program Counter (PC)
This 24-bit counter indicates the address of the next instruction the CPU will execute. The length
of all CPU instructions is 2 bytes (one word), so the least significant PC bit is ignored. (When an
instruction is fetched, the least significant PC bit is regarded as 0.)
2.4.3
Extended Register (EXR)
EXR is an 8-bit register that can be manipulated by the LDC, STC, ANDC, ORC, and XORC
instructions. When these instructions except for the STC instruction is executed, all interrupts
including NMI will be masked for three states after execution is completed.
Bit
Bit Name
Initial Value
R/W
Description
7
T
0
R/W
Trace Bit
When this bit is set to 1, a trace exception is started
each time an instruction is executed. When this bit is
cleared to 0, instructions are executed in sequence.
6
—
All 1
—
5
Reserved
They are always read as 1.
4
3
2
I2
1
R/W
1
I1
1
R/W
0
I0
1
R/W
These bits designate the interrupt mask level (0 to
7). For details, refer to section 5, Interrupt Controller.
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Section 2 CPU
2.4.4
Condition-Code Register (CCR)
This 8-bit register contains internal CPU status information, including an interrupt mask bit (I) and
half-carry (H), negative (N), zero (Z), overflow (V), and carry (C) flags.
Operations can be performed on the CCR bits by the LDC, STC, ANDC, ORC, and XORC
instructions. The N, Z, V, and C flags are used as branching conditions for conditional branch
(Bcc) instructions.
Bit
Bit Name
Initial Value
R/W
Description
7
I
1
R/W
Interrupt Mask Bit
Masks interrupts other than NMI when set to 1.
NMI is accepted regardless of the I bit setting.
The I bit is set to 1 by hardware at the start of an
exception-handling sequence. For details, refer to
section 5, Interrupt Controller.
6
UI
Undefined
R/W
User Bit or Interrupt Mask Bit
Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
This bit cannot be used as an interrupt mask bit
in this LSI.
5
H
Undefined
R/W
Half-Carry Flag
When the ADD.B, ADDX.B, SUB.B, SUBX.B,
CMP.B, or NEG.B instruction is executed, this
flag is set to 1 if there is a carry or borrow at bit 3,
and cleared to 0 otherwise. When the ADD.W,
SUB.W, CMP.W, or NEG.W instruction is
executed, the H flag is set to 1 if there is a carry
or borrow at bit 11, and cleared to 0 otherwise.
When the ADD.L, SUB.L, CMP.L, or NEG.L
instruction is executed, the H flag is set to 1 if
there is a carry or borrow at bit 27, and cleared to
0 otherwise.
4
U
Undefined
R/W
User Bit
Can be written and read by software using the
LDC, STC, ANDC, ORC, and XORC instructions.
3
N
Undefined
R/W
Negative Flag
Stores the value of the most significant bit of data
as a sign bit.
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Section 2 CPU
Bit
Bit Name
Initial Value
R/W
Description
2
Z
Undefined
R/W
Zero Flag
Set to 1 to indicate zero data, and cleared to 0 to
indicate non-zero data.
1
V
Undefined
R/W
Overflow Flag
Set to 1 when an arithmetic overflow occurs, and
cleared to 0 otherwise.
0
C
Undefined
R/W
Carry Flag
Set to 1 when a carry occurs, and cleared to 0
otherwise. Used by:
•
Add instructions, to indicate a carry
•
Subtract instructions, to indicate a borrow
•
Shift and rotate instructions, to indicate a
carry
The carry flag is also used as a bit accumulator
by bit manipulation instructions.
2.4.5
Multiply-Accumulate Register (MAC)
This 64-bit register stores the results of multiply-and-accumulate operations. It consists of two 32bit registers denoted MACH and MACL. The lower 10 bits of MACH are valid; the upper bits are
a sign extension.
2.4.6
Initial Values of CPU Internal Registers
When the reset exception handling loads the start address from the vector address, PC is
initialized, the T bit in EXR is cleared to 0, and the I bits in EXR and CCR are set to 1. However,
the general registers and the other CCR bits are not initialized. The initial value of SP (ER7) is
undefined. SP should therefore be initialized by using the MOV.L instruction immediately after a
reset.
2.5
Data Formats
The H8S/2600 CPU can process 1-bit, 4-bit (BCD), 8-bit (byte), 16-bit (word), and 32-bit
(longword) data. Bit-manipulation instructions operate on 1-bit data by accessing bit n (n = 0, 1, 2,
…, 7) of byte operand data. The DAA and DAS decimal-adjust instructions treat byte data as two
digits of 4-bit BCD data.
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Section 2 CPU
2.5.1
General Register Data Formats
Figure 2.9 shows the data formats in general registers.
Data Type
Register Number
Data Format
7
RnH
0
Don't care
7 6 5 4 3 2 1 0
1-bit data
7
1-bit data
RnL
4-bit BCD data
RnH
4-bit BCD data
RnL
Byte data
RnH
Don't care
7
4 3
Upper
0
7 6 5 4 3 2 1 0
0
Lower
Don't care
7
Don't care
7
4 3
Upper
0
Lower
0
Don't care
MSB
LSB
7
Byte data
RnL
0
Don't care
MSB
Figure 2.9 General Register Data Formats (1)
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LSB
Section 2 CPU
Data Type
Register Number
Word data
Rn
Data Format
15
0
MSB
Word data
15
0
MSB
Longword data
LSB
En
LSB
ERn
31
16 15
MSB
En
0
Rn
LSB
Legend:
ERn:
En:
Rn:
RnH:
RnL:
MSB:
LSB:
General register ER
General register E
General register R
General register RH
General register RL
Most significant bit
Least significant bit
Figure 2.9 General Register Data Formats (2)
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Section 2 CPU
2.5.2
Memory Data Formats
Figure 2.10 shows the data formats in memory. The H8S/2600 CPU can access word data and
longword data in memory, but word or longword data must begin at an even address. If an attempt
is made to access word or longword data at an odd address, no address error occurs but the least
significant bit of the address is regarded as 0, so the access starts at the preceding address. This
also applies to instruction fetches.
When ER7 is used as an address register to access the stack, the operand size should be word size
or longword size.
Data Type
Address
Data Format
1-bit data
Address L
7
Byte data
Address L
MSB
Word data
Address 2M
MSB
7
0
6
5
4
3
2
Address 2N
0
LSB
LSB
Address 2M+1
Longword data
1
MSB
Address 2N+1
Address 2N+2
Address 2N+3
Figure 2.10 Memory Data Formats
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LSB
Section 2 CPU
2.6
Instruction Set
The H8S/2600 CPU has 69 types of instructions. The instructions are classified by function in
table 2.1.
Table 2.1
Instruction Classification
Function
Instructions
Size
Types
Data transfer
MOV
1
1
POP* , PUSH*
B/W/L
5
LDM, STM
3
3
MOVFPE* , MOVTPE*
L
B
ADD, SUB, CMP, NEG
B/W/L
ADDX, SUBX, DAA, DAS
B
INC, DEC
B/W/L
ADDS, SUBS
L
MULXU, DIVXU, MULXS, DIVXS
B/W
EXTU, EXTS
4
TAS*
W/L
B
MAC, LDMAC, STMAC, CLRMAC
—
Logic operations
AND, OR, XOR, NOT
B/W/L
4
Shift
SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL, ROTXR B/W/L
8
Bit manipulation
B
14
Branch
BSET, BCLR, BNOT, BTST, BLD, BILD, BST, BIST, BAND,
BIAND, BOR, BIOR, BXOR, BIXOR
2
Bcc* , JMP, BSR, JSR, RTS
—
5
System control
TRAPA, RTE, SLEEP, LDC, STC, ANDC, ORC, XORC, NOP —
9
Arithmetic
operations
Block data transfer EEPMOV
W/L
—
23
1
Total: 69
Legend: B: Byte
W: Word
L: Longword
Notes: 1. POP.W Rn and PUSH.W Rn are identical to MOV.W @SP+, Rn and MOV.W Rn,
@-SP. POP.L ERn and PUSH.L ERn are identical to MOV.L @SP+, ERn and
MOV.L ERn, @-SP.
2. Bcc is the general name for conditional branch instructions.
3. Cannot be used in this LSI.
4. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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2.6.1
Table of Instructions Classified by Function
Tables 2.3 to 2.10 summarize the instructions in each functional category. The notation used in
tables 2.3 to 2.10 is defined below.
Table 2.2
Operation Notation
Symbol
Description
Rd
Rs
General register (destination)*
General register (source)*
Rn
General register*
ERn
General register (32-bit register)
MAC
Multiply-accumulate register (32-bit register)
(EAd)
Destination operand
(EAs)
Source operand
EXR
Extended register
CCR
Condition-code register
N
N (negative) flag in CCR
Z
Z (zero) flag in CCR
V
V (overflow) flag in CCR
C
C (carry) flag in CCR
PC
Program counter
SP
Stack pointer
#IMM
Immediate data
disp
Displacement
+
Addition
–
Subtraction
×
Multiplication
÷
Division
∧
Logical AND
∨
Logical OR
⊕
Logical exclusive OR
→
Move
¬
NOT (logical complement)
:8/:16/:24/:32
Note:
*
8-, 16-, 24-, or 32-bit length
General registers include 8-bit registers (R0H to R7H, R0L to R7L), 16-bit registers (R0
to R7, E0 to E7), and 32-bit registers (ER0 to ER7).
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Section 2 CPU
Table 2.3
Data Transfer Instructions
Instruction
Size*
Function
MOV
B/W/L
(EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
MOVFPE
B
Cannot be used in this LSI.
MOVTPE
B
Cannot be used in this LSI.
POP
W/L
@SP+ → Rn
Pops a general register from the stack. POP.W Rn is identical to MOV.W
@SP+, Rn. POP.L ERn is identical to MOV.L @SP+, ERn.
PUSH
W/L
Rn → @–SP
Pushes a general register onto the stack. PUSH.W Rn is identical to
MOV.W Rn, @–SP. PUSH.L ERn is identical to MOV.L ERn, @–SP.
LDM
L
@SP+ → Rn (register list)
Pops two or more general registers from the stack.
STM
L
Rn (register list) → @–SP
Pushes two or more general registers onto the stack.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Table 2.4
Arithmetic Operations Instructions (1)
Instruction
Size*
Function
ADD
SUB
B/W/L
Rd ± Rs → Rd, Rd ± #IMM → Rd
Performs addition or subtraction on data in two general registers, or on
immediate data and data in a general register. (Immediate byte data
cannot be subtracted from byte data in a general register. Use the SUBX
or ADD instruction.)
ADDX
SUBX
B
Rd ± Rs ± C → Rd, Rd ± #IMM ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in two
general registers, or on immediate data and data in a general register.
INC
DEC
B/W/L
Rd ± 1 → Rd, Rd ± 2 → Rd
Increments or decrements a general register by 1 or 2. (Byte operands
can be incremented or decremented by 1 only.)
ADDS
SUBS
L
Rd ± 1 → Rd, Rd ± 2 → Rd, Rd ± 4 → Rd
Adds or subtracts the value 1, 2, or 4 to or from data in a 32-bit register.
DAA
DAS
B
Rd (decimal adjust) → Rd
Decimal-adjusts an addition or subtraction result in a general register by
referring to the CCR to produce 4-bit BCD data.
MULXU
B/W
Rd × Rs → Rd
Performs unsigned multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
MULXS
B/W
Rd × Rs → Rd
Performs signed multiplication on data in two general registers:
either 8 bits × 8 bits → 16 bits or 16 bits × 16 bits → 32 bits.
DIVXU
B/W
Rd ÷ Rs → Rd
Performs unsigned division on data in two general registers:
either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or
32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Table 2.4
Arithmetic Operations Instructions (2)
Instruction
Size*
Function
DIVXS
B/W
Rd ÷ Rs → Rd
Performs signed division on data in two general registers:
either 16 bits ÷ 8 bits → 8-bit quotient and 8-bit remainder or
32 bits ÷ 16 bits → 16-bit quotient and 16-bit remainder.
CMP
B/W/L
Rd – Rs, Rd – #IMM
Compares data in a general register with data in another general register
or with immediate data, and sets CCR bits according to the result.
NEG
B/W/L
0 – Rd → Rd
Takes the two's complement (arithmetic complement) of data in a
general register.
EXTU
W/L
Rd (zero extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by padding with zeros on the
left.
EXTS
W/L
Rd (sign extension) → Rd
Extends the lower 8 bits of a 16-bit register to word size, or the lower 16
bits of a 32-bit register to longword size, by extending the sign bit.
2
TAS*
B
@ERd – 0, 1 → (<bit 7> of @ERd)
Tests memory contents, and sets the most significant bit (bit 7) to 1.
MAC
—
(EAs) × (EAd) + MAC → MAC
Performs signed multiplication on memory contents and adds the result
to the multiply-accumulate register. The following operations can be
performed:
16 bits × 16 bits + 32 bits → 32 bits, saturating
16 bits × 16 bits + 42 bits → 42 bits, non-saturating
CLRMAC
—
0 → MAC
Clears the multiply-accumulate register to zero.
LDMAC
STMAC
L
Rs → MAC, MAC → Rd
Transfers data between a general register and a multiply-accumulate
register.
1
Notes: 1. Size refers to the operand size.
B: Byte
W: Word
L: Longword
2. Only register ER0, ER1, ER4, or ER5 should be used when using the TAS instruction.
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Table 2.5
Logic Operations Instructions
Instruction
Size*
Function
AND
B/W/L
Rd ∧ Rs → Rd, Rd ∧ #IMM → Rd
Performs a logical AND operation on a general register and another
general register or immediate data.
OR
B/W/L
Rd ∨ Rs → Rd, Rd ∨ #IMM → Rd
Performs a logical OR operation on a general register and another
general register or immediate data.
XOR
B/W/L
Rd ⊕ Rs → Rd, Rd ⊕ #IMM → Rd
Performs a logical exclusive OR operation on a general register and
another general register or immediate data.
NOT
B/W/L
¬ (Rd) → (Rd)
Takes the one's complement (logical complement) of general register
contents.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
Table 2.6
Shift Instructions
Instruction
Size*
Function
SHAL
SHAR
B/W/L
Rd (shift) → Rd
Performs an arithmetic shift on general register contents.
1-bit or 2-bit shift is possible.
SHLL
SHLR
B/W/L
Rd (shift) → Rd
Performs a logical shift on general register contents.
1-bit or 2-bit shift is possible.
ROTL
ROTR
B/W/L
Rd (rotate) → Rd
Rotates general register contents.
1-bit or 2-bit rotation is possible.
ROTXL
ROTXR
B/W/L
Rd (rotate) → Rd
Rotates general register contents through the carry flag.
1-bit or 2-bit rotation is possible.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
L: Longword
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions (1)
Instruction
Size*
Function
BSET
B
1 → (<bit-No.> of <EAd>)
Sets a specified bit in a general register or memory operand to 1. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BCLR
B
0 → (<bit-No.> of <EAd>)
Clears a specified bit in a general register or memory operand to 0. The
bit number is specified by 3-bit immediate data or the lower three bits of a
general register.
BNOT
B
¬ (<bit-No.> of <EAd>) → (<bit-No.> of <EAd>)
Inverts a specified bit in a general register or memory operand. The bit
number is specified by 3-bit immediate data or the lower three bits of a
general register.
BTST
B
¬ (<bit-No.> of <EAd>) → Z
Tests a specified bit in a general register or memory operand and sets or
clears the Z flag accordingly. The bit number is specified by 3-bit
immediate data or the lower three bits of a general register.
BAND
B
C ∧ (<bit-No.> of <EAd>) → C
ANDs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIAND
B
C ∧ ¬ (<bit-No.> of <EAd>) → C
ANDs the carry flag with the inverse of a specified bit in a general
register or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
BOR
B
C ∨ (<bit-No.> of <EAd>) → C
ORs the carry flag with a specified bit in a general register or memory
operand and stores the result in the carry flag.
BIOR
B
C ∨ ¬ (<bit-No.> of <EAd>) → C
ORs the carry flag with the inverse of a specified bit in a general register
or memory operand and stores the result in the carry flag.
The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size.
B: Byte
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Section 2 CPU
Table 2.7
Bit Manipulation Instructions (2)
Instruction
Size*
Function
BXOR
B
C ⊕ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with a specified bit in a general register or
memory operand and stores the result in the carry flag.
BIXOR
B
C ⊕ ¬ (<bit-No.> of <EAd>) → C
Exclusive-ORs the carry flag with the inverse of a specified bit in a
general register or memory operand and stores the result in the carry
flag.
The bit number is specified by 3-bit immediate data.
BLD
B
(<bit-No.> of <EAd>) → C
Transfers a specified bit in a general register or memory operand to the
carry flag.
BILD
B
¬ (<bit-No.> of <EAd>) → C
Transfers the inverse of a specified bit in a general register or memory
operand to the carry flag.
The bit number is specified by 3-bit immediate data.
BST
B
C → (<bit-No.> of <EAd>)
Transfers the carry flag value to a specified bit in a general register or
memory operand.
BIST
B
¬ C → (<bit-No.> of <EAd>)
Transfers the inverse of the carry flag value to a specified bit in a general
register or memory operand.
The bit number is specified by 3-bit immediate data.
Note:
*
Size refers to the operand size.
B: Byte
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Section 2 CPU
Table 2.8
Branch Instructions
Instruction
Size
Function
Bcc
—
Branches to a specified address if a specified condition is true. The
branching conditions are listed below.
Mnemonic
Description
Condition
BRA (BT)
Always (true)
Always
BRN (BF)
Never (false)
Never
BHI
High
C∨Z=0
BLS
Low or same
C∨Z=1
BCC (BHS)
Carry clear
(high or same)
C=0
BCS (BLO)
Carry set (low)
C=1
BNE
Not equal
Z=0
BEQ
Equal
Z=1
BVC
Overflow clear
V=0
BVS
Overflow set
V=1
BPL
Plus
N=0
BMI
Minus
N=1
BGE
Greater or equal
N⊕V=0
BLT
Less than
N⊕V=1
BGT
Greater than
Z ∨ (N ⊕ V) = 0
BLE
Less or equal
Z ∨ (N ⊕ V) = 1
JMP
—
Branches unconditionally to a specified address.
BSR
—
Branches to a subroutine at a specified address.
JSR
—
Branches to a subroutine at a specified address.
RTS
—
Returns from a subroutine
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Section 2 CPU
Table 2.9
System Control Instructions
Instruction
Size*
Function
TRAPA
—
Starts trap-instruction exception handling.
RTE
—
Returns from an exception-handling routine.
SLEEP
—
Causes a transition to a power-down state.
LDC
B/W
(EAs) → CCR, (EAs) → EXR
Moves the contents of a general register or memory, or immediate data
to CCR or EXR. Although CCR and EXR are 8-bit registers, word-size
transfers are performed between them and memory. The upper 8 bits are
valid.
STC
B/W
CCR → (EAd), EXR → (EAd)
Transfers CCR or EXR contents to a general register or memory.
Although CCR and EXR are 8-bit registers, word-size transfers are
performed between them and memory. The upper 8 bits are valid.
ANDC
B
CCR ∧ #IMM → CCR, EXR ∧ #IMM → EXR
Logically ANDs the CCR or EXR contents with immediate data.
ORC
B
CCR ∨ #IMM → CCR, EXR ∨ #IMM → EXR
Logically ORs the CCR or EXR contents with immediate data.
XORC
B
CCR ⊕ #IMM → CCR, EXR ⊕ #IMM → EXR
Logically exclusive-ORs the CCR or EXR contents with immediate data.
NOP
—
PC + 2 → PC
Only increments the program counter.
Note:
*
Size refers to the operand size.
B: Byte
W: Word
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Section 2 CPU
Table 2.10 Block Data Transfer Instructions
Instruction
Size
Function
EEPMOV.B
—
if R4L ≠ 0 then
Repeat @ER5+ → @ER6+
R4L–1 → R4L
Until R4L = 0
else next;
EEPMOV.W
—
if R4 ≠ 0 then
Repeat @ER5+ → @ER6+
R4–1 → R4
Until R4 = 0
else next;
Transfers a data block. Starting from the address set in ER5, transfers
data for the number of bytes set in R4L or R4 to the address location set
in ER6.
Execution of the next instruction begins as soon as the transfer is
completed.
2.6.2
Basic Instruction Formats
The H8S/2600 Series instructions consist of 2-byte (1-word) units. An instruction consists of an
operation field (op), a register field (r), an effective address extension (EA), and a condition field
(cc).
Figure 2.11 shows examples of instruction formats.
• Operation Field
Indicates the function of the instruction, the addressing mode, and the operation to be carried
out on the operand. The operation field always includes the first four bits of the instruction.
Some instructions have two operation fields.
• Register Field
Specifies a general register. Address registers are specified by 3 bits, data registers by 3 bits or
4 bits. Some instructions have two register fields. Some have no register field.
• Effective Address Extension
8, 16, or 32 bits specifying immediate data, an absolute address, or a displacement.
• Condition Field
Specifies the branching condition of Bcc instructions.
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Section 2 CPU
(1) Operation field only
op
NOP, RTS, etc.
(2) Operation field and register fields
op
rm
rn
ADD.B Rn, Rm, etc.
(3) Operation field, register fields, and effective address extension
op
rn
rm
MOV.B @(d:16, Rn), Rm, etc.
EA (disp)
(4) Operation field, effective address extension, and condition field
op
cc
EA (disp)
BRA d:16, etc.
Figure 2.11 Instruction Formats (Examples)
2.7
Addressing Modes and Effective Address Calculation
The H8S/2600 CPU supports the eight addressing modes listed in table 2.11. The usable address
modes are different in each instruction.
Arithmetic and logic instructions can use the register direct and immediate modes. Data transfer
instructions can use all addressing modes except program-counter relative and memory indirect.
Bit manipulation instructions use register direct, register indirect, or absolute addressing mode to
specify an operand, and register direct (BSET, BCLR, BNOT, and BTST instructions) or
immediate (3-bit) addressing mode to specify a bit number in the operand.
Table 2.11 Addressing Modes
No.
Addressing Mode
Symbol
1
Register direct
Rn
2
Register indirect
@ERn
3
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
4
Register indirect with post-increment
Register indirect with pre-decrement
@ERn+
@–ERn
5
Absolute address
@aa:8/@aa:16/@aa:24/@aa:32
6
Immediate
#xx:8/#xx:16/#xx:32
7
Program-counter relative
@(d:8,PC)/@(d:16,PC)
8
Memory indirect
@@aa:8
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Section 2 CPU
2.7.1
Register Direct—Rn
The register field of the instruction code specifies an 8-, 16-, or 32-bit general register containing
the operand. R0H to R7H and R0L to R7L can be specified as 8-bit registers. R0 to R7 and E0 to
E7 can be specified as 16-bit registers. ER0 to ER7 can be specified as 32-bit registers.
2.7.2
Register Indirect—@ERn
The register field of the instruction code specifies an address register (ERn) which contains the
address of the operand on memory. If the address is a program instruction address, the lower 24
bits are valid and the upper 8 bits are all assumed to be 0 (H'00).
2.7.3
Register Indirect with Displacement—@(d:16, ERn) or @(d:32, ERn)
A 16-bit or 32-bit displacement contained in the instruction is added to an address register (ERn)
specified by the register field of the instruction code, and the sum gives the address of a memory
operand. A 16-bit displacement is sign-extended when added.
2.7.4
Register Indirect with Post-Increment or Pre-Decrement—@ERn+ or @-ERn
Register indirect with post-increment—@ERn+: The register field of the instruction code
specifies an address register (ERn) which contains the address of a memory operand. After the
operand is accessed, 1, 2, or 4 is added to the address register contents and the sum is stored in the
address register. The value added is 1 for byte access, 2 for word transfer instruction, or 4 for
longword transfer instruction. For word or longword transfer instruction, the register value should
be even.
Register indirect with pre-decrement—@-ERn: The value 1, 2, or 4 is subtracted from an
address register (ERn) specified by the register field in the instruction code, and the result
becomes the address of a memory operand. The result is also stored in the address register. The
value subtracted is 1 for byte access, 2 for word transfer instruction, or 4 for longword transfer
instruction. For word or longword transfer instruction, the register value should be even.
2.7.5
Absolute Address—@aa:8, @aa:16, @aa:24, or @aa:32
The instruction code contains the absolute address of a memory operand. The absolute address
may be 8 bits long (@aa:8), 16 bits long (@aa:16), 24 bits long (@aa:24), or 32 bits long
(@aa:32). Table 2.12 indicates the accessible absolute address ranges.
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Section 2 CPU
To access data, the absolute address should be 8 bits (@aa:8), 16 bits (@aa:16), or 32 bits
(@aa:32) long. For an 8-bit absolute address, the upper 24 bits are all assumed to be 1 (H'FFFF).
For a 16-bit absolute address, the upper 16 bits are a sign extension. A 32-bit absolute address can
access the entire address space.
A 24-bit absolute address (@aa:24) indicates the address of a program instruction. The upper 8
bits are all assumed to be 0 (H'00).
Table 2.12 Absolute Address Access Ranges
Normal Mode*
Advanced Mode
8 bits (@aa:8)
H'FF00 to H'FFFF
H'FFFF00 to H'FFFFFF
16 bits (@aa:16)
H'0000 to H'FFFF
H'000000 to H'007FFF,
H'FF8000 to H'FFFFFF
Absolute Address
Data address
32 bits (@aa:32)
Program instruction
address
Note:
2.7.6
*
H'000000 to H'FFFFFF
24 bits (@aa:24)
Not available in this LSI.
Immediate—#xx:8, #xx:16, or #xx:32
The instruction code contains 8-bit (#xx:8), 16-bit (#xx:16), or 32-bit (#xx:32) immediate data as
an operand.
The ADDS, SUBS, INC, and DEC instructions contain immediate data implicitly. Some bit
manipulation instructions contain 3-bit immediate data in the instruction code, specifying a bit
number. The TRAPA instruction contains 2-bit immediate data in its instruction code, specifying a
vector address.
2.7.7
Program-Counter Relative—@(d:8, PC) or @(d:16, PC)
This mode is used in the Bcc and BSR instructions. An 8-bit or 16-bit displacement contained in
the instruction code is sign-extended and added to the 24-bit PC contents to generate a branch
address. Only the lower 24 bits of this branch address are valid; the upper 8 bits are all assumed to
be 0 (H'00). The PC value to which the displacement is added is the address of the first byte of the
next instruction, so the possible branching range is –126 to +128 bytes (–63 to +64 words) or –
32766 to +32768 bytes (–16383 to +16384 words) from the branch instruction. The resulting value
should be an even number.
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Section 2 CPU
2.7.8
Memory Indirect—@@aa:8
This mode can be used by the JMP and JSR instructions. The instruction code contains an 8-bit
absolute address specifying a memory operand. This memory operand contains a branch address.
The upper bits of the absolute address are all assumed to be 0, so the address range is 0 to 255
(H'0000 to H'00FF in normal mode, H'000000 to H'0000FF in advanced mode).
In normal mode the memory operand is a word operand and the branch address is 16 bits long. In
advanced mode the memory operand is a longword operand, the first byte of which is assumed to
be all 0 (H'00). Note that the first part of the address range is also the exception vector area. For
further details, refer to section 4, Exception Handling.
If an odd address is specified in word or longword memory access, or as a branch address, the
least significant bit is regarded as 0, causing data to be accessed or instruction code to be fetched
at the address preceding the specified address. (For further information, see section 2.5.2, Memory
Data Formats.)
Note: Normal mode is not available in this LSI.
Specified
by @aa:8
Branch address
Specified
by @aa:8
Reserved
Branch address
(a) Normal Mode*
(a) Advanced Mode
Note: * Normal mode is not available in this LSI.
Figure 2.12 Branch Address Specification in Memory Indirect Mode
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Section 2 CPU
2.7.9
Effective Address Calculation
Table 2.13 indicates how effective addresses are calculated in each addressing mode. In normal
mode the upper 8 bits of the effective address are ignored in order to generate a 16-bit address.
Note: Normal mode is not available in this LSI.
Table 2.13 Effective Address Calculation (1)
No
1
Addressing Mode and Instruction Format
op
2
Effective Address Calculation
Effective Address (EA)
Register direct (Rn)
rm
Operand is general register contents.
rn
Register indirect (@ERn)
0
31
op
3
31
24 23
0
Don't care
General register contents
r
Register indirect with displacement
@(d:16,ERn)/@(d:32,ERn)
0
31
General register contents
op
r
31
disp
Sign extension
Register indirect with post-increment or
pre-decrement
• Register indirect with post-increment @ERn+
op
disp
0
31
31
24 23
1, 2, or 4
0
31
General register contents
31
24 23
Don't care
op
0
Don't care
General register contents
r
• Register indirect with pre-decrement @-ERn
0
0
31
4
24 23
Don't care
r
1, 2, or 4
Operand Size
Byte
Word
Longword
Rev. 3.00 Feb 22, 2006 page 46 of 624
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Offset
1
2
4
0
Section 2 CPU
Table 2.13 Effective Address Calculation (2)
No
5
Addressing Mode and Instruction Format
Effective Address Calculation
Effective Address (EA)
Absolute address
@aa:8
31
op
@aa:16
31
op
0
H'FFFF
24 23
16 15
0
Don't care Sign extension
abs
@aa:24
31
op
8 7
24 23
Don't care
abs
24 23
0
Don't care
abs
@aa:32
op
31
6
Immediate
#xx:8/#xx:16/#xx:32
op
7
0
24 23
Don't care
abs
Operand is immediate data.
IMM
0
23
Program-counter relative
PC contents
@(d:8,PC)/@(d:16,PC)
op
disp
23
0
Sign
extension
disp
31
24 23
0
Don't care
8
Memory indirect @@aa:8
• Normal mode*
8 7
31
op
abs
0
abs
H'000000
15
0
31
24 23
Don't care
Memory contents
16 15
0
H'00
• Advanced mode
31
op
abs
8 7
H'000000
31
0
abs
0
31
24 23
Don't care
0
Memory contents
Note: * Normal mode is not available in this LSI.
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Section 2 CPU
2.8
Processing States
The H8S/2600 CPU has five main processing states: the reset state, exception handling state,
program execution state, bus-released state, and program stop state. Figure 2.13 indicates the state
transitions.
• Reset State
The CPU and on-chip peripheral modules are all initialized and stop. When the RES input goes
low, all current processing stops and the CPU enters the reset state. All interrupts are masked
in the reset state. Reset exception handling starts when the RES signal changes from low to
high. For details, refer to section 4, Exception Handling.
The reset state can also be entered by a watchdog timer overflow.
• Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU alters the normal
processing flow due to an exception source, such as, a reset, trace, interrupt, or trap instruction.
The CPU fetches a start address (vector) from the exception vector table and branches to that
address. For further details, refer to section 4, Exception Handling.
• Program Execution State
In this state the CPU executes program instructions in sequence.
• Bus-Released State
In a product which has a bus master other than the CPU, such as a direct memory access
controller (DMAC) and a data transfer controller (DTC), the bus-released state occurs when
the bus has been released in response to a bus request from a bus master other than the CPU.
While the bus is released, the CPU halts operations.
• Program stop state
This is a power-down state in which the CPU stops operating. The program stop state occurs
when a SLEEP instruction is executed or the CPU enters hardware standby mode. For further
details, refer to section 19, Power-Down Modes.
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Section 2 CPU
End of bus request
Bus request
g
nd
lin
lin
g
ha
nd
n
ha
ep
re
ex
fo
of
st
d
que
t re
ue
Re
q
En
xc
ce
pt
tio
ion
En
d
=0
BY
SS EEP tion
SL truc
ins
Exception
handling state
n
Bus-released state
io
= 1 ruct
BY nst
SS EP i
E
SL
of
bu
s
re
Bu
qu
sr
es
eq
t
ue
st
Program execution state
up
terr
Sleep mode
st
In
External interrupt request
Software standby
mode
RES = High
Reset state
*1
STBY = High,
RES = Low
Hardware standby
mode*2
Reset state
Power down state*3
Notes: 1. From any state except hardware standby mode, a transition to the reset state occurs whenever RES goes low.
A transition can also be made to the reset state when the watchdog timer overflows.
2. In every state, when the STBY pin becomes low, the hardware standby mode is entered.
3. For details, refer to section 19, Power-Down Modes.
Figure 2.13 State Transitions
2.9
Usage Note
2.9.1
Usage Notes on Bit-wise Operation Instructions
The BSET, BCLR, BNOT, BST, and BIST instructions are used to read data in byte-wise, operate
the data in bit-wise, and write the result of the bit-wise operation in bit-wise again. Therefore,
special care is necessary to use these instructions for the registers and the ports that include writeonly bit.
The BCLR instruction can be used to clear the flags in the internal I/O registers to 0. In this time,
if it is obvious that the flag has been set to 1 in the interrupt handler, there is no need to read the
flag beforehand.
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Section 2 CPU
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Section 3 MCU Operating Modes
Section 3 MCU Operating Modes
3.1
Operating Mode Selection
The H8S/2668 Group has twelve operating modes (modes 1 to 7).
These modes are determined by the mode pin (MD2 to MD0) setting.
Modes 1, 2, and 4 to 6 are externally expanded modes in which the CPU can access an external
memory and peripheral devices. In the externally expanded mode, each area can be switched to 8bit or 16-bit address space by the bus controller. If one of areas is set to 16-bit address space, the
bus mode is 16 bits. If all areas are set to 8-bit address space, the bus mode is 8 bits.
Mode 7 is a single-chip activation externally expanded mode in which the CPU can switch to
access an external memory and peripheral devices at the beginning of a program execution.
Mode 3 is a boot mode in which the flash memory can be accessed.
For details, refer to section 17, Flash Memory (F-ZTAT version).
Do not change MD2 to MD0 pin settings during operation.
Table 3.1
MCU Operating Mode Selection
MCU
Operating
Mode
MD2
MD1
MD0
CPU
Operating
Mode
1
0
0
1
Advanced
2
0
1
0
3
0
1
4
1
0
5
1
6
7
External Data Bus
On-Chip
ROM
Initial
Width
Max.
Value
Expanded mode with
on-chip ROM disabled
Disabled
16 bits
16 bits
Advanced
Expanded mode with
on-chip ROM disabled
Disabled
8 bits
16 bits
1
Advanced
Boot mode
Enabled
—
16 bits
0
Advanced
Expanded mode with
on-chip ROM enabled
Enabled
8 bits
16 bits
0
1
Advanced
Expanded mode with
on-chip ROM enabled
Enabled
16 bits
16 bits
1
1
0
Advanced
Expanded mode with
on-chip ROM enabled
Enabled
8 bits
16 bits
1
1
1
Advanced
Single-chip mode
Enabled
—
16 bits
Description
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Section 3 MCU Operating Modes
3.2
Register Descriptions
The following registers are related to the operating mode.
• Mode control register (MDCR)
• System control register (SYSCR)
3.2.1
Mode Control Register (MDCR)
MDCR monitors the current operating mode of the H8S/2668 Group chip.
Bit
Bit Name
Initial Value
R/W
Descriptions
7 to
3
—
All 0
—
Reserved
2
MDS2
—*
R
Mode Select 2 to 0
1
MDS1
—*
R
0
MDS0
—*
R
These bits indicate the input levels at pins MD2 to
MD0 (the current operating mode). Bits MDS2 to
MDS0 correspond to MD2 to MD0. MDS2 to MDS0
are read-only bits and they cannot be written to. The
mode pin (MD2 to MD0) input levels are latched into
these bits when MDCR is read. These latches are
canceled by a reset.
Note:
These bits are always read as 0 and cannot be
modified.
*
3.2.2
Determined by pins MD2 to MD0.
System Control Register (SYSCR)
SYSCR selects saturating or non-saturating calculation for the MAC instruction, controls CPU
access to the flash memory control registers (FLMCR1, FLMCR2, EBR1, and EBR2), sets
external bus mode, and enables or disables on-chip RAM.
Bit
Bit Name
Initial Value
R/W
Descriptions
7, 6
—
All 1
R/W
Reserved
The initial value should not be modified.
5
MACS
0
R/W
MAC Saturation
Selects either saturating or non-saturating calculation
for the MAC instruction.
0: Non-saturating calculation for MAC instruction
1: Saturating calculation for MAC instruction
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Section 3 MCU Operating Modes
Bit
Bit Name
Initial Value
R/W
Descriptions
4
—
0
R/W
Reserved
The initial value should not be modified.
3
FLSHE
0
R/W
Flash Memory Control Register Enable
Controls CPU access to the flash memory control
registers (FLMCR1, FLMCR2, EBR1, and EBR2). If
this bit is set to 1, the flash memory control registers
can be read/written to. If this bit is cleared to 0, the
flash memory control registers are not selected. At
this time, the contents of the flash memory control
registers are maintained.
0: Flash memory control registers are not selected
for area H'FFFFC8 to H'FFFFCB
1: Flash memory control registers are selected for
area H'FFFFC8 to H'FFFFCB
2
—
0
—
1
EXPE
—
R/W
Reserved
This bit is always read as 0 and cannot be modified.
External Bus Mode Enable
Sets external bus mode.
In modes 1, 2, and 4 to 6, this bit is fixed at 1 and
cannot be modified. In mode 3 and 7, this bit has an
initial value of 0, and can be read and written.
Writing of 0 to EXPE when its value is 1 should only
be carried out when an external bus cycle is not
being executed.
0: External bus disabled
1: External bus enabled
0
RAME
1
R/W
RAM Enable
Enables or disables the on-chip RAM. The RAME bit
is initialized when the reset status is released.
0: On-chip RAM is disabled
1: On-chip RAM is enabled
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Section 3 MCU Operating Modes
3.3
Operating Mode Descriptions
3.3.1
Mode 1
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F
to H carry bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for all areas by the bus controller, the bus mode switches to 8 bits.
3.3.2
Mode 2
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is disabled.
Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F
to H carry bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for all areas by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus.
3.3.3
Mode 3
This mode is a boot mode of the flash memory. This mode is the same as mode 7, except for
accessing to the flash memory.
3.3.4
Mode 4
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in the on-chip ROM connected to the first half of area 0 is executed.
Ports A to C function as input ports immediately after a reset, but can be set to function as an
address bus. For details, see section 8, I/O Ports. Ports D and E function as a data bus, and parts of
ports F to H carry bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any area by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus. User program mode is entered by setting 1 to the SWE bit of FLMCR1.
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Section 3 MCU Operating Modes
3.3.5
Mode 5
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in an external ROM connected to the first half of area 0 is executed.
Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F
to H carry bus control signals.
The initial bus mode after a reset is 16 bits, with 16-bit access to all areas. However, if 8-bit access
is designated for any area by the bus controller, the bus mode switches to 8 bits.
User program mode is entered by setting 1 to the SWE bit of FLMCR1.
3.3.6
Mode 6
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled.
The program in an external ROM connected to the first half of area 0 is executed.
Ports A to C function as an address bus, ports D and E function as a data bus, and parts of ports F
to H carry bus control signals.
The initial bus mode after a reset is 8 bits, with 8-bit access to all areas. However, if 16-bit access
is designated for any area by the bus controller, the bus mode switches to 16 bits and port E
functions as a data bus.
User program mode is entered by setting 1 to the SWE bit of FLMCR1.
3.3.7
Mode 7
The CPU can access a 16-Mbyte address space in advanced mode. The on-chip ROM is enabled,
and the chip starts up in single-chip mode. External addresses cannot be used in single-chip mode.
The initial mode after a reset is single-chip mode, with all I/O ports available for use as
input/output ports. However, the mode can be switched to externally expanded mode by setting 1
to the EXPE bit of SYSCR and then the external address space is enabled. When externally
expanded mode is selected, all areas are initially designated as 16-bit access space. The function of
pins in ports A to H is the same as in externally expanded mode with on-chip ROM enabled.
In the flash memory version, user program mode is entered by setting 1 to the SWE bit of
FLMCR1.
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Section 3 MCU Operating Modes
3.3.8
Pin Functions
The pin functions of ports A to H are switched according to operating mode. Table 3.2 shows the
pin functions in each operating mode.
Table 3.2
Pin Functions in Each Operating Mode
Port
Mode 1
Mode 2
Mode 3
Mode 4
Mode 5
Mode 6
Mode 7
Port A
PA7 to PA5
P*/A
P*/A
P*/A
P*/A
P*/A
P*/A
P*/A
PA4 to PA0
A
A
A
A
Port B
A
A
Port C
A
Port D
D
Port E
PF7, PF6
P/D*
P/C*
PF5, PF4
C
PF3
P/C*
PF2 to PF0
PG6 to PG1
Port F
Port G
PG0
Port H
P*/A
P*/A
A
A
A
P*/A
P*/A
A
A
P*/A
P*/A
D
P*/D
P*/D
P*/D
P*/D
P*/D
D
D
P*/D
P*/D
P*/D
P*/C
P*/C
P/C*
P/D*
P/C*
P/C*
P*/C
C
C
C
C
P/C*
P/C*
P/C*
P/C*
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P/C*
P*/C
P/C*
P*/C
P*/C
P*/C
P*/C
P/C*
P*/C
P/C*
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
P*/C
Legend: P: I/O port
A: Address bus output
D: Data bus input/output
C: Control signals, clock input/output
Note: * After reset
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Section 3 MCU Operating Modes
3.4
Memory Map in Each Operating Mode
Figure 3.1 shows memory maps.
RAM: 16 kbytes
Modes 1 and 2
(expanded modes
with on-chip ROM disabled)
H'000000
ROM: 384 kbytes
RAM: 16 kbytes
Mode 4
(expanded mode
with on-chip ROM enabled)
ROM: 384 kbytes
RAM: 16 kbytes
Mode 3
(boot mode)
H'000000
H'000000
On-chip ROM
On-chip ROM
H'060000
H'060000
External
address space
External address
space/reserved area*2
H'FF8000
H'FF8000
H'FF8000
On-chip RAM/external
address space*1
H'FFC000
H'FFFC00
H'FFFC00
Internal I/O registers
H'FFFF00 External address space
H'FFFF20
Internal I/O registers
H'FFFFFF
On-chip RAM/external
address space*1
On-chip RAM*3
H'FFC000 External address space
H'FFFF00
H'FFFF20
H'FFFFFF
External
address space
External address
space/reserved area*2
Internal I/O registers
External address
space/reserved area*2
Internal I/O registers
H'FFC000 External address space
H'FFFC00
Internal I/O registers
H'FFFF00
External address space
H'FFFF20
Internal I/O registers
H'FFFFFF
Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.
2. External address space when EXPE = 0.
Reserved when EXPE = 0.
3. On-chip RAM is used during modifying flash memory.
Figure 3.1 Memory Map (1)
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Section 3 MCU Operating Modes
ROM: 384 kbytes
RAM: 16 kbytes
Modes 5 and 6
(external ROM activation
expanded modes
with on-chip ROM enabled)
H'000000
ROM: 384 kbytes
RAM: 16 kbytes
Mode 7
(single-chip activation
expanded mode
with on-chip ROM enabled)
H'000000
On-chip ROM
External
address space
H'060000
H'100000
External address
space/reserved area*2
On-chip ROM
H'140000
External
address space
H'FFA000
H'FFA000
On-chip RAM/external
address space*1
On-chip RAM/external
address space*3
H'FFC000 External address space
H'FFC000
H'FFFC00
H'FFFC00
Internal I/O registers
H'FFFF00 External address space
H'FFFF20
Internal I/O registers
H'FFFFFF
H'FFFF00
H'FFFF20
H'FFFFFF
External address
space/reserved area*2
Internal I/O registers
External address
space/reserved area*2
Internal I/O registers
Notes: 1. This area is specified as an external address area by clearing the RAME bit of SYSCR to 0.
2. When EXPE = 1, external address space; when EXPE = 0, reserved area.
3. When EXPE = 1, external address space when RAME = 0, on-chip RAM when RAME = 1.
When EXPE = 0, on-chip RAM area.
Figure 3.1 Memory Map (2)
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Section 4 Exception Handling
Section 4 Exception Handling
4.1
Exception Handling Types and Priority
As table 4.1 indicates, exception handling may be caused by a reset, trace, interrupt, or trap
instruction. Exception handling is prioritized as shown in table 4.1. If two or more exceptions
occur simultaneously, they are accepted and processed in order of priority. Exception sources, the
stack structure, and operation of the CPU vary depending on the interrupt control mode. For
details on the interrupt control mode, refer to section 5, Interrupt Controller.
Table 4.1
Exception Types and Priority
Priority
Exception Type
Start of Exception Handling
High
Reset
Starts immediately after a low-to-high transition at the RES
pin, or when the watchdog timer overflows. The CPU enters
the reset state when the RES pin is low.
1
Trace*
Direct transition*
Low
Starts when execution of the current instruction or exception
handling ends, if the trace (T) bit in the EXR is set to 1.
2
Starts when the direct transition occurs by execution of the
SLEEP instruction.
Interrupt
Starts when execution of the current instruction or exception
3
handling ends, if an interrupt request has been issued.*
4
Trap instruction*
Started by execution of a trap instruction (TRAPA)
Notes: 1. Traces are enabled only in interrupt control mode 2. Trace exception handling is not
executed after execution of an RTE instruction.
2. Not available in this LSI.
3. Interrupt detection is not performed on completion of ANDC, ORC, XORC, or LDC
instruction execution, or on completion of reset exception handling.
4. Trap instruction exception handling requests are accepted at all times in program
execution state.
4.2
Exception Sources and Exception Vector Table
Different vector addresses are assigned to different exception sources. Table 4.2 lists the exception
sources and their vector addresses. Since the usable modes differ depending on the product, for
details on each product, refer to section 3, MCU Operating Modes.
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Section 4 Exception Handling
Table 4.2
Exception Handling Vector Table
Vector Address*
1
Exception Source
Vector Number
Normal Mode*
Advanced Mode
Power-on reset
2
Manual reset*
0
H'0000 to H'0001
H'0000 to H'0003
1
H'0002 to H'0003
H'0004 to H'0007
Reserved for system use
2
H'0004 to H'0005
H'0008 to H'000B
3
H'0006 to H'0007
H'000C to H'000F
4
H'0008 to H'0019
H'0010 to H'0013
Trace
5
H'000A to H'000B
H'0014 to H'0017
2
Interrupt (direct transition)*
6
H'000C to H'000D
H'0018 to H'001B
Interrupt (NMI)
7
H'000E to H'000F
H'001C to H'001F
Trap instruction (#0)
8
H'0010 to H'0011
H'0020 to H'0023
(#1)
9
H'0012 to H'0013
H'0024 to H'0027
(#2)
10
H'0014 to H'0015
H'0028 to H'002B
(#3)
11
H'0016 to H'0017
H'002C to H'002F
12
H'0018 to H'0019
H'0030 to H'0033
13
H'001A to H'001B
H'0034 to H'0037
14
H'001C to H'001D
H'0038 to H'003B
15
H'001E to H'001F
H'003C to H'003F
IRQ0
16
H'0020 to H'0021
H'0040 to H'0043
IRQ1
17
H'0022 to H'0023
H'0044 to H'0047
IRQ2
18
H'0024 to H'0025
H'0048 to H'004B
IRQ3
19
H'0026 to H'0027
H'004C to H'004F
IRQ4
20
H'0028 to H'0029
H'0050 to H'0053
IRQ5
21
H'002A to H'002B
H'0054 to H'0057
Reserved for system use
External interrupt
2
IRQ6
22
H'002C to H'002D
H'0058 to H'005B
IRQ7
23
H'002E to H'002F
H'005C to H'005F
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Section 4 Exception Handling
Vector Address*
1
Exception Source
Vector Number
Normal Mode*
Advanced Mode
Reserved by system
24
H'0030 to H'0031
H'0060 to H'0063
25
H'0032 to H'0033
H'0064 to H'0067
26
H'0034 to H'0035
H'0068 to H'006B
27
H'0036 to H'0037
H'006C to H'006F
28
H'0038 to H'0039
H'0070 to H'0073
29
H'003A to H'003B
H'0074 to H'0077
30
H'003C to H'003D
H'0078 to H'007B
31
H'003E to H'003F
H'007C to H'007F
32

99
H'0040 to H'0041

H'00C6 to H'00C7
H'0080 to H'0083

H'018C to H'018F
Internal interrupt*
3
2
Notes: 1. Lower 16 bits of the address.
2. Not available in this LSI.
3. For details of internal interrupt vectors, see section 5.5, Interrupt Exception Handling
Vector Table.
4.3
Reset
A reset has the highest exception priority. When the RES pin goes low, all processing halts and
this LSI enters the reset. To ensure that this LSI is reset, hold the RES pin low for at least 20 ms at
power-up. To reset the chip during operation, hold the RES pin low for at least 20 states. A reset
initializes the internal state of the CPU and the registers of on-chip peripheral modules.
The chip can also be reset by overflow of the watchdog timer. For details see section 12,
Watchdog Timer.
The interrupt control mode is 0 immediately after reset.
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Section 4 Exception Handling
4.3.1
Reset exception handling
When the RES pin goes high after being held low for the necessary time, this LSI starts reset
exception handling as follows:
1. The internal state of the CPU and the registers of the on-chip peripheral modules are
initialized, the T bit is cleared to 0 in EXR, and the I bit is set to 1 in EXR and CCR.
2. The reset exception handling vector address is read and transferred to the PC, and program
execution starts from the address indicated by the PC.
Figures 4.1 and 4.2 show examples of the reset sequence.
Vector fetch
Prefetch of first
Internal
processing program instruction
(1)
(3)
φ
RES
Internal
address bus
(5)
Internal read
signal
Internal write
signal
Internal data
bus
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Figure 4.1 Reset Sequence (Advanced Mode with On-chip ROM Enabled)
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Section 4 Exception Handling
Internal
processing
Vector fetch
*
*
Prefetch of first
program instruction
*
φ
RES
Address bus
(1)
(3)
(5)
RD
HWR, LWR
D15 to D0
High
(2)
(4)
(6)
(1)(3) Reset exception handling vector address (when reset, (1)=H'000000, (3)=H'000002)
(2)(4) Start address (contents of reset exception handling vector address)
(5) Start address ((5)=(2)(4))
(6) First program instruction
Note: * Seven program wait states are inserted.
Figure 4.2 Reset Sequence (Advanced Mode with On-chip ROM Disabled)
4.3.2
Interrupts after Reset
If an interrupt is accepted after a reset but before the stack pointer (SP) is initialized, the PC and
CCR will not be saved correctly, leading to a program crash. To prevent this, all interrupt requests,
including NMI, are disabled immediately after a reset. Since the first instruction of a program is
always executed immediately after the reset state ends, make sure that this instruction initializes
the stack pointer (example: MOV.L #xx: 32, SP).
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Section 4 Exception Handling
4.3.3
On-Chip Peripheral Functions after Reset Release
After reset release, MSTPCR is initialized to H'0FFF and all modules except the DTC enter
module stop mode.
Consequently, on-chip peripheral module registers cannot be read or written to. Register reading
and writing is enabled when module stop mode is exited.
4.4
Traces
Traces are enabled in interrupt control mode 2. Trace mode is not activated in interrupt control
mode 0, irrespective of the state of the T bit. For details on interrupt control modes, see section 5,
Interrupt Controller.
If the T bit in EXR is set to 1, trace mode is activated. In trace mode, a trace exception occurs on
completion of each instruction. Trace mode is not affected by interrupt masking. Table 4.3 shows
the state of CCR and EXR after execution of trace exception handling. Trace mode is canceled by
clearing the T bit in EXR to 0. The T bit saved on the stack retains its value of 1, and when control
is returned from the trace exception handling routine by the RTE instruction, trace mode resumes.
Trace exception handling is not carried out after execution of the RTE instruction.
Interrupts are accepted even within the trace exception handling routine.
Table 4.3
Status of CCR and EXR after Trace Exception Handling
Interrupt Control Mode
CCR
I
0
2
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
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EXR
UI
I2 to I0
T
Trace exception handling cannot be used.
1
—
—
0
Section 4 Exception Handling
4.5
Interrupts
Interrupts are controlled by the interrupt controller. The interrupt controller has two interrupt
control modes and can assign interrupts other than NMI to eight priority/mask levels to enable
multiplexed interrupt control. The source to start interrupt exception handling and the vector
address differ depending on the product. For details, refer to section 5, Interrupt Controller.
The interrupt exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
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Section 4 Exception Handling
4.6
Trap Instruction
Trap instruction exception handling starts when a TRAPA instruction is executed. Trap instruction
exception handling can be executed at all times in the program execution state.
The trap instruction exception handling is as follows:
1. The values in the program counter (PC), condition code register (CCR), and extended register
(EXR) are saved in the stack.
2. The interrupt mask bit is updated and the T bit is cleared to 0.
3. A vector address corresponding to the interrupt source is generated, the start address is loaded
from the vector table to the PC, and program execution starts from that address.
The TRAPA instruction fetches a start address from a vector table entry corresponding to a vector
number from 0 to 3, as specified in the instruction code.
Table 4.4 shows the status of CCR and EXR after execution of trap instruction exception handling.
Table 4.4
Status of CCR and EXR after Trap Instruction Exception Handling
Interrupt Control Mode
CCR
EXR
I
UI
I2 to I0
T
0
1
—
—
—
2
1
—
—
0
Legend:
1: Set to 1
0: Cleared to 0
—: Retains value prior to execution.
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Section 4 Exception Handling
4.7
Stack Status after Exception Handling
Figure 4.3 shows the stack after completion of trap instruction exception handling and interrupt
exception handling.
(a) Normal Modes*2
SP
EXR
Reserved*1
SP
CCR
CCR
CCR*1
CCR*1
PC (16 bits)
PC (16 bits)
Interrupt control mode 0
Interrupt control mode 2
(b) Advanced Modes
SP
EXR
Reserved*1
SP
CCR
PC (24 bits)
Interrupt control mode 0
CCR
PC (24 bits)
Interrupt control mode 2
Notes: 1. Ignored on return.
2. Normal modes are not available in this LSI.
Figure 4.3 Stack Status after Exception Handling
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Section 4 Exception Handling
4.8
Usage Note
When accessing word data or longword data, this LSI assumes that the lowest address bit is 0. The
stack should always be accessed by word transfer instruction or longword transfer instruction, and
the value of the stack pointer (SP, ER7) should always be kept even. Use the following
instructions to save registers:
PUSH.W
Rn
(or MOV.W Rn, @-SP)
PUSH.L
ERn
(or MOV.L ERn, @-SP)
Use the following instructions to restore registers:
POP.W
Rn
(or MOV.W @SP+, Rn)
POP.L
ERn
(or MOV.L @SP+, ERn)
Setting SP to an odd value may lead to a malfunction. Figure 4.4 shows an example of operation
when the SP value is odd.
Address
CCR
R1L
SP
SP
H'FFFEFA
H'FFFEFB
PC
PC
H'FFFEFC
H'FFFEFD
H'FFFEFE
SP
H'FFFEFF
TRAP instruction executed
SP set to H'FFFEFF
MOV.B R1L, @-ER7
Data saved above SP
Contents of CCR lost
Legend:
CCR: Condition code register
PC: Program counter
R1L: General register R1L
SP: Stack pointer
Note: This diagram illustrates an example in which the interrupt control mode is 0, in advanced mode.
Figure 4.4 Operation when SP Value Is Odd
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Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.1
Features
• Two interrupt control modes
Any of two interrupt control modes can be set by means of the INTM1 and INTM0 bits in the
interrupt control register (INTCR).
• Priorities settable with IPR
An interrupt priority register (IPR) is provided for setting interrupt priorities. Eight priority
levels can be set for each module for all interrupts except NMI. NMI is assigned the highest
priority level of 8, and can be accepted at all times.
• Independent vector addresses
All interrupt sources are assigned independent vector addresses, making it unnecessary for the
source to be identified in the interrupt handling routine.
• Nine external interrupts
NMI is the highest-priority interrupt, and is accepted at all times. Rising edge or falling edge
can be selected for NMI. Falling edge, rising edge, or both edge detection, or level sensing, can
be selected for IRQ7 to IRQ0.
• DTC control
DTC activations are performed by means of interrupts.
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Section 5 Interrupt Controller
A block diagram of the interrupt controller is shown in figure 5.1.
CPU
INTM1 INTM0
INTCR
NMIEG
NMI input
NMI input unit
IRQ input
IRQ input unit
ISR
SSIER ITSR ISCR IER
Interrupt
request
Vector
number
Priority
determination
Internal
interrupt
sources
SWDTEND
to TEI
I
I2 to I0
IPR
Interrupt controller
Legend:
ISCR: IRQ sense control register
IER:
IRQ enable register
ISR:
IRQ status register
IPR:
Interrupt priority register
INTCR: Interrupt control register
ITSR: IRQ pin select register
SSIER: Software standby release IRQ enable register
Figure 5.1 Block Diagram of Interrupt Controller
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CCR
EXR
Section 5 Interrupt Controller
5.2
Input/Output Pins
Table 5.1 shows the pin configuration of the interrupt controller.
Table 5.1
Pin Configuration
Name
I/O
Function
NMI
Input
Nonmaskable external interrupt
IRQ7 to IRQ0
Input
Rising or falling edge can be selected.
Maskable external interrupts
Rising, falling, or both edges, or level sensing, can be
selected.
5.3
Register Descriptions
The interrupt controller has the following registers.
• Interrupt control register (INTCR)
• IRQ sense control register H (ISCRH)
• IRQ sense control register L (ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• IRQ pin select register (ITSR)
• Software standby release IRQ enable register (SSIER)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register I (IPRI)
• Interrupt priority register J (IPRJ)
• Interrupt priority register K (IPRK)
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Section 5 Interrupt Controller
5.3.1
Interrupt Control Register (INTCR)
INTCR selects the interrupt control mode, and the detected edge for NMI.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
—
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
5
INTM1
0
R/W
Interrupt Control Select Mode 1 and 0
4
INTM0
0
R/W
These bits select either of two interrupt control
modes for the interrupt controller.
00: Interrupt control mode 0
Interrupts are controlled by I bit.
01: Setting prohibited.
10: Interrupt control mode 2
Interrupts are controlled by bits I2 to I0, and
IPR.
11: Setting prohibited.
3
NMIEG
0
R/W
NMI Edge Select
Selects the input edge for the NMI pin.
0: Interrupt request generated at falling edge of
NMI input
1: Interrupt request generated at rising edge of
NMI input
2 to 0
—
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
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Section 5 Interrupt Controller
5.3.2
Interrupt Priority Registers A to K (IPRA to IPRK)
IPR are eleven 16-bit readable/writable registers that set priorities (levels 7 to 0) for interrupts
other than NMI.
The correspondence between interrupt sources and IPR settings is shown in table 5.2 (Interrupt
Sources, Vector Addresses, and Interrupt Priorities). Setting a value in the range from H'0 to H'7
in the 3-bit groups of bits 14 to 12, 10 to 8, 6 to 4, and 2 to 0 sets the priority of the corresponding
interrupt. IPR should be read in word size.
Bit
Bit Name
Initial Value
R/W
Description
15
—
0
—
Reserved
This bit is always read as 0 and cannot be
modified.
14
IPR14
1
R/W
13
IPR13
1
R/W
Sets the priority of the corresponding interrupt
source.
12
IPR12
1
R/W
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
11
—
0
—
Reserved
This bit is always read as 0 and cannot be
modified.
10
IPR10
1
R/W
9
IPR9
1
R/W
Sets the priority of the corresponding interrupt
source.
8
IPR8
1
R/W
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0 and cannot be
modified.
6
IPR6
1
R/W
5
IPR5
1
R/W
Sets the priority of the corresponding interrupt
source.
4
IPR4
1
R/W
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
3
—
0
—
Reserved
This bit is always read as 0 and cannot be
modified.
2
IPR2
1
R/W
1
IPR1
1
R/W
Sets the priority of the corresponding interrupt
source.
0
IPR0
1
R/W
000: Priority level 0 (Lowest)
001: Priority level 1
010: Priority level 2
011: Priority level 3
100: Priority level 4
101: Priority level 5
110: Priority level 6
111: Priority level 7 (Highest)
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Section 5 Interrupt Controller
5.3.3
IRQ Enable Register (IER)
IER controls enabling and disabling of interrupt requests IRQ7 to IRQ0.
Bit
Bit Name
15 to 8 IRQ15E
Initial Value
R/W
Description
0
R/W
Reserved
These bits can be read and modified. The write
value should always be 0.
7
IRQ7E
0
R/W
IRQ7 Enable
The IRQ7 interrupt request is enabled when this
bit is 1.
6
IRQ6E
0
R/W
IRQ6 Enable
The IRQ6 interrupt request is enabled when this
bit is 1.
5
IRQ5E
0
R/W
IRQ5 Enable
The IRQ5 interrupt request is enabled when this
bit is 1.
4
IRQ4E
0
R/W
IRQ4 Enable
The IRQ4 interrupt request is enabled when this
bit is 1.
3
IRQ3E
0
R/W
IRQ3 Enable
The IRQ3 interrupt request is enabled when this
bit is 1.
2
IRQ2E
0
R/W
IRQ2 Enable
The IRQ2 interrupt request is enabled when this
bit is 1.
1
IRQ1E
0
R/W
IRQ1 Enable
The IRQ1 interrupt request is enabled when this
bit is 1.
0
IRQ0E
0
R/W
IRQ0 Enable
The IRQ0 interrupt request is enabled when this
bit is 1.
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Section 5 Interrupt Controller
5.3.4
IRQ Sense Control Registers (ISCR)
ISCR select the source that generates an interrupt request at pins IRQ7 to IRQ0.
Bit
Bit Name
Initial Value
R/W
Description
15
IRQ7SCB
0
R/W
14
IRQ7SCA
0
R/W
IRQ7 Sense Control B
IRQ7 Sense Control A
00: Interrupt request generated at IRQ7 input
low level
01: Interrupt request generated at falling edge
of IRQ7 input
10: Interrupt request generated at rising edge of
IRQ7 input
11: Interrupt request generated at both falling
and rising edges of IRQ7 input
13
IRQ6SCB
0
R/W
12
IRQ6SCA
0
R/W
IRQ6 Sense Control B
IRQ6 Sense Control A
00: Interrupt request generated at IRQ6 input
low level
01: Interrupt request generated at falling edge
of IRQ6 input
10: Interrupt request generated at rising edge of
IRQ6 input
11: Interrupt request generated at both falling
and rising edges of IRQ6 input
11
IRQ5SCB
0
R/W
10
IRQ5SCA
0
R/W
IRQ5 Sense Control B
IRQ5 Sense Control A
00: Interrupt request generated at IRQ5 input
low level
01: Interrupt request generated at falling edge
of IRQ5 input
10: Interrupt request generated at rising edge of
IRQ5 input
11: Interrupt request generated at both falling
and rising edges of IRQ5 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
9
IRQ4SCB
0
R/W
8
IRQ4SCA
0
R/W
IRQ4 Sense Control B
IRQ4 Sense Control A
00: Interrupt request generated at IRQ4 input
low level
01: Interrupt request generated at falling edge
of IRQ4 input
10: Interrupt request generated at rising edge of
IRQ4 input
11: Interrupt request generated at both falling
and rising edges of IRQ4 input
7
IRQ3SCB
0
R/W
6
IRQ3SCA
0
R/W
IRQ3 Sense Control B
IRQ3 Sense Control A
00: Interrupt request generated at IRQ3 input
low level
01: Interrupt request generated at falling edge
of IRQ3 input
10: Interrupt request generated at rising edge of
IRQ3 input
11: Interrupt request generated at both falling
and rising edges of IRQ3 input
5
IRQ2SCB
0
R/W
4
IRQ2SCA
0
R/W
IRQ2 Sense Control B
IRQ2 Sense Control A
00: Interrupt request generated at IRQ2 input
low level
01: Interrupt request generated at falling edge
of IRQ2 input
10: Interrupt request generated at rising edge of
IRQ2 input
11: Interrupt request generated at both falling
and rising edges of IRQ2 input
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Section 5 Interrupt Controller
Bit
Bit Name
Initial Value
R/W
Description
3
IRQ1SCB
0
R/W
2
IRQ1SCA
0
R/W
IRQ1 Sense Control B
IRQ1 Sense Control A
00: Interrupt request generated at IRQ1 input
low level
01: Interrupt request generated at falling edge
of IRQ1 input
10: Interrupt request generated at rising edge of
IRQ1 input
11: Interrupt request generated at both falling
and rising edges of IRQ1 input
1
IRQ0SCB
0
R/W
0
IRQ0SCA
0
R/W
IRQ0 Sense Control B
IRQ0 Sense Control A
00: Interrupt request generated at IRQ0 input
low level
01: Interrupt request generated at falling edge
of IRQ0 input
10: Interrupt request generated at rising edge of
IRQ0 input
11: Interrupt request generated at both falling
and rising edges of IRQ0 input
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Section 5 Interrupt Controller
5.3.5
IRQ Status Register (ISR)
ISR is an IRQ7 to IRQ0 interrupt request flag register.
Bit
Bit Name
15 to 8 —
Initial Value
R/W
Description
All 0
—
Reserved
These bits are always read as 0 and cannot be
modified.
7
IRQ7F
0
6
IRQ6F
0
R/(W)*
R/(W)*
5
IRQ5F
0
R/(W)*
4
IRQ4F
0
3
IRQ3F
0
R/(W)*
R/(W)*
2
IRQ2F
0
1
IRQ1F
0
R/(W)*
R/(W)*
0
IRQ0F
0
R/(W)*
[Setting conditions]
When the interrupt source selected by ISCR
occurs
[Clearing conditions]
•
Cleared by reading IRQnF flag when IRQnF
= 1, then writing 0 to IRQnF flag
•
When interrupt exception handling is
executed when low-level detection is set
and IRQn input is high
•
When IRQn interrupt exception handling is
executed when falling, rising, or both-edge
detection is set
•
When the DTC is activated by an IRQn
interrupt, and the DISEL bit in MRB of the
DTC is cleared to 0
(n=15 to 0)
Note:
*
Only 0 can be written, to clear the flag.
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Section 5 Interrupt Controller
5.3.6
IRQ Pin Select Register (ITSR)
ITSR selects input pins IRQ7 to IRQ0.
Bit
Bit Name
15 to 8 —
Initial Value
R/W
Description
All 0
R/W
Reserved
These bits can be read and modified. The write
value should always be 0.
7
ITS7
0
R/W
Selects IRQ7 input pin.
0: P57
1: PH3
6
ITS6
0
R/W
Selects IRQ6 input pin.
0: P56
1: PH2
5
ITS5
0
R/W
Selects IRQ5 input pin.
0: P55
1: P85
4
ITS4
0
R/W
Selects IRQ4 input pin.
0: P54
1: P84
3
ITS3
0
R/W
Selects IRQ3 input pin.
0: P53
1: P83
2
ITS2
0
R/W
Selects IRQ2 input pin.
0: P52
1: P82
1
ITS1
0
R/W
Selects IRQ1 input pin.
0: P51
1: P81
0
ITS0
0
R/W
Selects IRQ0 input pin.
0: P50
1: P80
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Section 5 Interrupt Controller
5.3.7
Software Standby Release IRQ Enable Register (SSIER)
SSIER selects the IRQ pins used to recover from the software standby state.
Bit
Bit Name
15 to 8 —
Initial Value
R/W
Description
All 0
R/W
Reserved
These bits can be read and modified. The write
value should always be 0.
7
SSI7
0
R/W
Software Standby Release IRQ Setting
6
SSI6
0
R/W
5
SSI5
0
R/W
These bits select the IRQn pins used to recover
from the software standby state.
4
SSI4
0
R/W
3
SSI3
0
R/W
2
SSI2
0
R/W
1
SSI1
0
R/W
0
SSI0
0
R/W
0: IRQn requests are not sampled in the
software standby state (Initial value when n =
7 to 3)
1: When an IRQn request occurs in the
software standby state, the chip recovers
from the software standby state after the
elapse of the oscillation settling time (Initial
value when n = 2 to 0)
(n = 15 to 0)
5.4
Interrupt Sources
5.4.1
External Interrupts
There are nine external interrupts: NMI and IRQ7 to IRQ0. These interrupts can be used to restore
the chip from software standby mode.
NMI Interrupt: Nonmaskable interrupt request (NMI) is the highest-priority interrupt, and is
always accepted by the CPU regardless of the interrupt control mode or the status of the CPU
interrupt mask bits. The NMIEG bit in INTCR can be used to select whether an interrupt is
requested at a rising edge or a falling edge on the NMI pin.
IRQ7 to IRQ0 Interrupts: Interrupts IRQ7 to IRQ0 are requested by an input signal at pins IRQ7
to IRQ0. Interrupts IRQ7 to IRQ0 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ7 to IRQ0.
• Enabling or disabling of interrupt requests IRQ7 to IRQ0 can be selected with IER.
• The interrupt priority level can be set with IPR.
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Section 5 Interrupt Controller
• The status of interrupt requests IRQ7 to IRQ0 is indicated in ISR. ISR flags can be cleared to 0
by software.
When IRQ7 to IRQ0 interrupt requests occur at low level of IRQn, the corresponding IRQ should
be held low until an interrupt handling starts. Then the corresponding IRQ should be set to high in
the interrupt handling routine and clear the IRQnF bit (n = 0 to 7) in ISR to 0. Interrupts may not
be executed when the corresponding IRQ is set to high before the interrupt handling starts.
Detection of IRQ7 to IRQ0 interrupts does not depend on whether the relevant pin has been set for
input or output. However, when a pin is used as an external interrupt input pin, do not clear the
corresponding DDR to 0 and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ15 to IRQ0 is shown in figure 5.2.
IRQnE
IRQnSCA, IRQnSCB
IRQnF
Edge/
level detection
circuit
IRQn
input
S
Q
IRQn interrupt
request
R
Clear signal
Note: n = 7 to 0
Figure 5.2 Block Diagram of Interrupts IRQ7 to IRQ0
5.4.2
Internal Interrupts
The sources for internal interrupts from on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that select enabling or disabling of these interrupts. They can be controlled
independently. When the enable bit is set to 1, an interrupt request is issued to the interrupt
controller.
• The interrupt priority level can be set by means of IPR.
• The DTC can be activated by a TPU, SCI, or other interrupt request.
• When the DTC is activated by an interrupt request, it is not affected by the interrupt control
mode or CPU interrupt mask bit.
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Section 5 Interrupt Controller
5.5
Interrupt Exception Handling Vector Table
Table 5.2 shows interrupt exception handling sources, vector addresses, and interrupt priorities.
For default priorities, the lower the vector number, the higher the priority. When interrupt control
mode 2 is set, priorities among modules can be set by means of the IPR. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
Table 5.2
Interrupt
Source
Interrupt Sources, Vector Addresses, and Interrupt Priorities
Origin of
Interrupt
Source
Vector Address*
Vector
Number
Advanced Mode
IPR
Priority
DTC
Activation
7
H'001C
—
High
—
IRQ0
16
H'0040
IPRA14 to IPRA12
IRQ1
17
H'0044
IPRA10 to IPRA8
IRQ2
18
H'0048
IPRA6 to IPRA4
IRQ3
19
H'004C
IPRA2 to IPRA0
IRQ4
20
H'0050
IPRB14 to IPRB12
External pin NMI
IRQ5
21
H'0054
IPRB10 to IPRB8
IRQ6
22
H'0058
IPRB6 to IPRB4
IRQ7
23
H'005C
IPRB2 to IPRB0
Reserved by system
24
H'0060
IPRC14 to IPRC12
—
25
H'0064
IPRC10 to IPRC8
—
26
H'0068
IPRC6 to IPRC4
—
27
H'006C
IPRC2 to IPRC0
—
28
H'0070
IPRD14 to IPRD12
—
29
H'0074
IPRD10 to IPRD8
—
30
H'0078
IPRD6 to IPRD4
—
31
H'007C
IPRD2 to IPRD0
—
DTC
SWDTEND
32
H'0080
IPRE14 to IPRE12
WDT
WOVI
33
H'0084
IPRE10 to IPRE8
—
—
Reserved for
system use
34
H'0088
IPRE6 to IPRE4
—
35
H'008C
IPRE2 to IPRE0
—
Reserved for
system use
36
H'0090
IPRF14 to IPRF12
—
37
H'0094
Low
—
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Section 5 Interrupt Controller
Vector Address*
Interrupt
Source
Origin of
Interrupt
Source
A/D
ADI
—
Reserved for
system use
TPU_0
TGI0A
40
H'00A0
TGI0B
41
H'00A4
TGI0C
42
H'00A8
TGI0D
43
H'00AC
TCI0V
44
H'00B0
Reserved for
system use
45
H'00B4
46
H'00B8
47
H'00BC
TGI1A
48
H'00C0
TGI1B
49
H'00C4
TCI1V
50
H'00C8
—
TCI1U
51
H'00CC
—
—
TPU_1
TPU_2
TPU_3
—
TPU_4
Vector
Number
Advanced Mode
IPR
Priority
38
H'0098
IPRF10 to IPRF8
High
39
H'009C
TGI2A
52
H'00D0
TGI2B
53
H'00D4
TCI2V
54
H'00D8
DTC
Activation
—
IPRF6 to IPRF4
—
IPRF6 to IPRF4
—
—
—
IPRF2 to IPRF0
IPRG14 to IPRG12
—
TCI2U
55
H'00DC
TGI3A
56
H'00E0
TGI3B
57
H'00E4
TGI3C
58
H'00E8
TGI3D
59
H'00EC
TCI3V
60
H'00F0
—
Reserved for
system use
61
H'00F4
—
62
H'00F8
—
63
H'00FC
TGI4A
64
H'0100
TGI4B
65
H'0104
TCI4V
66
H'0108
TCI4U
67
H'010C
Rev. 3.00 Feb 22, 2006 page 84 of 624
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—
IPRG10 to IPRG8
—
IPRG6 to IPRG4
—
Low
—
Section 5 Interrupt Controller
Vector Address*
Interrupt
Source
Origin of
Interrupt
Source
TPU_5
TGI5A
TGI5B
TCI5V
70
H'0118
—
TCI5U
71
H'011C
—
CMIA0
72
H'0120
TMR_0
Vector
Number
Advanced Mode
IPR
Priority
68
H'0110
IPRG2 to IPRG0
High
69
H'0114
DTC
Activation
IPRH14 to IPRH12
CMIB0
73
H'0124
OVI0
74
H'0128
—
—
Reserved for
system use
75
H'012C
—
TMR_1
CMIA1
76
H'0130
—
SCI_0
SCI_1
SCI_2
IPRH10 to IPRH8
CMIB1
77
H'0134
OVI1
78
H'0138
—
Reserved for
system use
79
H'013C
—
80
H'0140
81
H'0144
82
H'0148
83
H'014C
84
H'0150
IPRH6 to IPRH4
IPRH0 to IPRH0
—
85
H'0154
IPRI14 to IPRI12
—
86
H'0158
IPRI10 to IPRI8
—
87
H'015C
IPRI6 to IPRI4
—
IPRI2 to IPRI0
—
ERI0
88
H'0160
RXI0
89
H'0164
TXI0
90
H'0168
TEI0
91
H'016C
ERI1
92
H'0170
RXI1
93
H'0174
TXI1
94
H'0178
TEI1
95
H'017C
ERI2
96
H'0180
RXI2
97
H'0184
TXI2
98
H'0188
TEI2
99
H'018C
—
IPRJ14 to IPRJ12
—
—
IPRJ10 to IPRJ8
—
Low
—
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Section 5 Interrupt Controller
Interrupt
Source
—
Note:
Origin of
Interrupt
Source
Reserved for
system use
*
Vector Address*
Vector
Number
Advanced Mode
IPR
Priority
IPRJ6 to IPRJ4
High
DTC
Activation
100
H'0190
101
H'0194
—
102
H'0198
—
103
H'019C
—
104
H'01A0
105
H'01A4
—
106
H'01A8
—
107
H'01AC
—
108
H'01B0
109
H'01B4
—
110
H'01B8
—
111
H'01BC
—
112
H'01C0
113
H'01C4
—
114
H'01C8
—
115
H'01CC
—
116
H'01D0
117
H'01D4
—
118
H'01D8
—
119
H'01DC
—
120
H'01E0
121
H'01E4
—
122
H'01E8
—
123
H'01EC
—
124
H'01F0
—
125
H'01F4
—
126
H'01F8
127
H'01EC
Lower 16 bits of the start address.
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IPRJ2 to IPRJ0
—
—
IPRK14 to IPRK12
—
IPRK10 to IPRK8
—
IPRK6 to IPRK4
—
IPRK2 to IPRK0
—
—
Low
—
Section 5 Interrupt Controller
5.6
Interrupt Control Modes and Interrupt Operation
The interrupt controller has two modes: interrupt control mode 0 and interrupt control mode 2.
Interrupt operations differ depending on the interrupt control mode. The interrupt control mode is
selected by INTCR. Table 5.3 shows the differences between interrupt control mode 0 and
interrupt control mode 2.
Table 5.3
Interrupt Control Modes
Interrupt
Control Mode
Priority Setting
Registers
Interrupt
Mask Bits Description
0
Default
I
The priorities of interrupt sources are fixed at
the default settings.
Interrupt sources except for NMI is masked by
the I bit.
2
IPR
I2 to I0
8 priority levels except for NMI can be set with
IPR.
8-level interrupt mask control is performed by
bits I2 to I0.
5.6.1
Interrupt Control Mode 0
In interrupt control mode 0, interrupt requests except for NMI is masked by the I bit of CCR in the
CPU. Figure 5.3 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. If the I bit is set to 1, only an NMI interrupt is accepted, and other interrupt requests are held
pending. If the I bit is cleared, an interrupt request is accepted.
3. Interrupt requests are sent to the interrupt controller, the highest-ranked interrupt according to
the priority system is accepted, and other interrupt requests are held pending.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC and CCR are saved to the stack area by interrupt exception handling. The PC saved on
the stack shows the address of the first instruction to be executed after returning from the
interrupt handling routine.
6. Next, the I bit in CCR is set to 1. This masks all interrupts except NMI.
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Section 5 Interrupt Controller
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
Program execution status
No
Interrupt generated?
Yes
Yes
NMI
No
I=0
No
Hold
pending
Yes
No
IRQ0
No
Yes
IRQ1
Yes
TEI_2
Yes
Save PC and CCR
I←1
Read vector address
Branch to interrupt handling routine
Figure 5.3 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 0
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Section 5 Interrupt Controller
5.6.2
Interrupt Control Mode 2
In interrupt control mode 2, mask control is done in eight levels for interrupt requests except for
NMI by comparing the EXR interrupt mask level (I2 to I0 bits) in the CPU and the IPR setting.
Figure 5.4 shows a flowchart of the interrupt acceptance operation in this case.
1. If an interrupt source occurs when the corresponding interrupt enable bit is set to 1, an
interrupt request is sent to the interrupt controller.
2. When interrupt requests are sent to the interrupt controller, the interrupt with the highest
priority according to the interrupt priority levels set in IPR is selected, and lower-priority
interrupt requests are held pending. If a number of interrupt requests with the same priority are
generated at the same time, the interrupt request with the highest priority according to the
priority system shown in table 5.2 is selected.
3. Next, the priority of the selected interrupt request is compared with the interrupt mask level set
in EXR. An interrupt request with a priority no higher than the mask level set at that time is
held pending, and only an interrupt request with a priority higher than the interrupt mask level
is accepted.
4. When the CPU accepts an interrupt request, it starts interrupt exception handling after
execution of the current instruction has been completed.
5. The PC, CCR, and EXR are saved to the stack area by interrupt exception handling. The PC
saved on the stack shows the address of the first instruction to be executed after returning from
the interrupt handling routine.
6. The T bit in EXR is cleared to 0. The interrupt mask level is rewritten with the priority level of
the accepted interrupt.
If the accepted interrupt is NMI, the interrupt mask level is set to H'7.
7. The CPU generates a vector address for the accepted interrupt and starts execution of the
interrupt handling routine at the address indicated by the contents of the vector address in the
vector table.
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Section 5 Interrupt Controller
Program execution status
Interrupt generated?
No
Yes
Yes
NMI
No
Level 7 interrupt?
No
Yes
Mask level 6
or below?
Level 6 interrupt?
No
No
Yes
Level 1 interrupt?
Yes
Mask level 5
or below?
No
No
Yes
Yes
Mask level 0?
No
Yes
Save PC, CCR, and EXR
Hold
pending
Clear T bit to 0
Update mask level
Read vector address
Branch to interrupt handling routine
Figure 5.4 Flowchart of Procedure Up to Interrupt Acceptance
in Interrupt Control Mode 2
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Section 5 Interrupt Controller
5.6.3
Interrupt Exception Handling Sequence
Figure 5.5 shows the interrupt exception handling sequence. The example shown is for the case
where interrupt control mode 0 is set in advanced mode, and the program area and stack area are
in on-chip memory.
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Figure 5.5 Interrupt Exception Handling
(1)
(2)
(4)
(3)
Internal
operation
Instruction prefetch address (Not executed.
This is the contents of the saved PC, the return address.)
(2) (4) Instruction code (Not executed.)
(3)
Instruction prefetch address (Not executed.)
(5)
SP-2
(7)
SP-4
(1)
Internal
data bus
Internal
write signal
Internal
read signal
Internal
address bus
Interrupt
request signal
φ
Interrupt level determination Instruction
Wait for end of instruction
prefetch
Interrupt
acceptance
(7)
(8)
(10)
(9)
(12)
(11)
Internal
operation
(14)
(13)
Interrupt handling
routine instruction
prefetch
Saved PC and saved CCR
Vector address
Interrupt handling routine start address (Vector address contents)
Interrupt handling routine start address ((13) = (10)(12))
First instruction of interrupt handling routine
(6)
(6) (8)
(9) (11)
(10) (12)
(13)
(14)
(5)
stack
Vector fetch
Section 5 Interrupt Controller
Section 5 Interrupt Controller
5.6.4
Interrupt Response Times
Table 5.4 shows interrupt response times - the interval between generation of an interrupt request
and execution of the first instruction in the interrupt handling routine. The execution status
symbols used in table 5.4 are explained in table 5.5.
This LSI is capable of fast word transfer to on-chip memory, and have the program area in on-chip
ROM and the stack area in on-chip RAM, enabling high-speed processing.
Table 5.4
Interrupt Response Times
Normal Mode*
5
Advanced Mode
Interrupt
control
mode 0
Interrupt
control
mode 2
Interrupt
control
mode 0
Interrupt
control
mode 2
3
3
3
3
No.
Execution Status
1
Interrupt priority determination*
2
Number of wait states until executing 1 to 19 +2·SI 1 to 19+2·SI
2
instruction ends*
1 to 19+2·SI 1 to 19+2·SI
3
PC, CCR, EXR stack save
2·SK
3·SK
2·SK
3·SK
4
Vector fetch
SI
SI
2·SI
2·SI
5
3
Instruction fetch*
2·SI
2·SI
2·SI
2·SI
6
Internal processing*
2
2
2
2
11 to 31
12 to 32
12 to 32
13 to 33
4
Total (using on-chip memory)
Notes: 1.
2.
3.
4.
5.
1
Two states in case of internal interrupt.
Refers to MULXS and DIVXS instructions.
Prefetch after interrupt acceptance and interrupt handling routine prefetch.
Internal processing after interrupt acceptance and internal processing after vector fetch.
Not available in this LSI.
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Section 5 Interrupt Controller
Table 5.5
Number of States in Interrupt Handling Routine Execution Statuses
Object of Access
External Device
8 Bit Bus
16 Bit Bus
Symbol
Internal
Memory
2-State
Access
3-State
Access
2-State
Access
3-State
Access
Instruction fetch SI
1
4
6+2m
2
3+m
Branch address read SJ
Stack manipulation SK
Legend:
m: Number of wait states in an external device access.
5.6.5
DTC Activation by Interrupt
The DTC can be activated by an interrupt. In this case, the following options are available:
• Interrupt request to CPU
• Activation request to DTC
• Selection of a number of the above
For details of interrupt requests that can be used to activate the DTC, see table 5.2 and section 7,
Data Transfer Controller.
Figure 5.6 shows a block diagram of the DTC and interrupt controller.
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Section 5 Interrupt Controller
Interrupt
request
IRQ
interrupt
On-chip
supporting
module
Interrupt source
clear signal
DTC activation
request vector
number
Selection
circuit
Select
signal
Clear signal
DTCER
Control logic
DTC
Clear signal
DTVECR
SWDTE
clear signal
Determination of
priority
CPU interrupt
request vector
number
CPU
I, I2 to I0
Interrupt controller
Figure 5.6 DTC and Interrupt Controller
(1) Selection of Interrupt Source: Interrupt factors are selected as DTC activation source or
CPU interrupt source by the DTCE bit of DTCERA to DTCERF of DTC.
By specifying the DISEL bit of the DTC’s MRB, it is possible to clear the DTCE bit to 0 after
DTC data transfer, and request a CPU interrupt.
If DTC carries out the designate number of data transfers and the transfer counter reads 0, after
DTC data transfer, the DTCE bit is also cleared to 0, and an interrupt is requested to the CPU.
(2) Determination of Priority: The DTC activation source is selected in accordance with the
default priority order, and is not affected by mask or priority levels.
(3) Operation Order: If the same interrupt is selected as a DTC activation source and a CPU
interrupt source, the DTC data transfer is performed first, followed by CPU interrupt exception
handling.
Table 5.6 shows the interrupt factor clear control and selection of interrupt factors by specification
of the DTCE bit of DTC's DTCERA to DTCERH, and the DISEL bit of DTC's MRB.
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Section 5 Interrupt Controller
Table 5.6
Interrupt Source Selection and Clearing Control
Settings
DTC
Interrupt Sources Selection/Clearing Control
DTCE
DISEL
DTC
0
*
X
1
0
CPU
X
1
*
*
X
X
Legend:
: The relevant interrupt is used. Interrupt source clearing is performed.
(The CPU should clear the source flag in the interrupt handling routine.)
: The relevant interrupt is used. The interrupt source is not cleared.
X : The relevant interrupt cannot be used.
* : Don’t care
Note: The SCI or A/D converter interrupt source is cleared when the DTC reads or writes to the
prescribed register, and is not dependent upon the DISEL bit.
5.7
Usage Notes
5.7.1
Contention between Interrupt Generation and Disabling
When an interrupt enable bit is cleared to 0 to mask interrupts, the masking becomes effective
after execution of the instruction.
When an interrupt enable bit is cleared to 0 by an instruction such as BCLR or MOV, if an
interrupt is generated during execution of the instruction, the interrupt concerned will still be
enabled on completion of the instruction, and so interrupt exception handling for that interrupt will
be executed on completion of the instruction. However, if there is an interrupt request of higher
priority than that interrupt, interrupt exception handling will be executed for the higher-priority
interrupt, and the lower-priority interrupt will be ignored. The same also applies when an interrupt
source flag is cleared to 0. Figure 5.7 shows an example in which the TCIEV bit in the TPU’s
TIER_0 register is cleared to 0. The above contention will not occur if an enable bit or interrupt
source flag is cleared to 0 while the interrupt is masked.
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Section 5 Interrupt Controller
TIER_0 write cycle by CPU
TCIV exception handling
φ
Internal
address bus
TIER_0 address
Internal
write signal
TCIEV
TCFV
TCIV
interrupt signal
Figure 5.7 Contention between Interrupt Generation and Disabling
5.7.2
Instructions that Disable Interrupts
Instructions that disable interrupts are LDC, ANDC, ORC, and XORC. After any of these
instructions is executed, all interrupts including NMI are disabled and the next instruction is
always executed. When the I bit is set by one of these instructions, the new value becomes valid
two states after execution of the instruction ends.
5.7.3
Times when Interrupts are Disabled
There are times when interrupt acceptance is disabled by the interrupt controller.
The interrupt controller disables interrupt acceptance for a 3-state period after the CPU has
updated the mask level with an LDC, ANDC, ORC, or XORC instruction.
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Section 5 Interrupt Controller
5.7.4
Interrupts during Execution of EEPMOV Instruction
Interrupt operation differs between the EEPMOV.B instruction and the EEPMOV.W instruction.
With the EEPMOV.B instruction, an interrupt request (including NMI) issued during the transfer
is not accepted until the transfer is completed.
With the EEPMOV.W instruction, if an interrupt request is issued during the transfer, interrupt
exception handling starts at a break in the transfer cycle. The PC value saved on the stack in this
case is the address of the next instruction. Therefore, if an interrupt is generated during execution
of an EEPMOV.W instruction, the following coding should be used.
L1:
5.7.5
EEPMOV.W
MOV.W
R4,R4
BNE
L1
Change of IRQ Pin Select Register (ITSR) Setting
When the ITSR setting is changed, an edge occurs internally and the IRQnF bit (n = 0 to 7) of ISR
may be set to 1 at the unintended timing if the selected pin level before the change is different
from the selected pin level after the change. If the IRQn interrupt request (n = 0 to 7) is enabled,
the interrupt exception handling is executed. To prevent the unintended interrupt, ITSR setting
should be changed while the IRQn interrupt request is disabled, then the IRQnF bit should be
cleared to 0.
5.7.6
Note on IRQ Status Register (ISR)
Since IRQnF flags may be set to 1 depending on the pin states after a reset, be sure to read from
ISR after a reset and then write 0 to clear the IRQnF flags.
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Section 6 Bus Controller (BSC)
Section 6 Bus Controller (BSC)
This LSI has an on-chip bus controller (BSC) that manages the external address space divided into
eight areas.
The bus controller also has a bus arbitration function, and controls the operation of the bus
masterships—the CPU and data transfer controller (DTC).
6.1
Features
• Manages external address space in area units
Manages the external address space divided into eight areas of 2 Mbytes
Bus specifications can be set independently for each area
• Basic bus interface
Chip select signals (CS0 to CS7) can be output for areas 0 to 7
8-bit access or 16-bit access can be selected for each area
2-state access or 3-state access can be selected for each area
Program wait states can be inserted for each area
• Bus arbitration function
Includes a bus arbiter that arbitrates bus mastershipship between the CPU and DTC
BSCS203A_010020020400
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Section 6 Bus Controller (BSC)
A block diagram of the bus controller is shown in figure 6.1.
Area decoder
External bus controller
Internal bus master bus request signal
Internal bus master bus acknowledge signal
External bus
arbiter
Internal bus controller
Internal bus
arbiter
Control registers
Internal data bus
ABWCR
ASTCR
WTCRAH WTCRAL
WTCRBH WTCRBL
RDNCR
CSACRH
CSACRL
BCR
Legend:
ABWCR:
ASTCR:
WTCRAH, WTCRAL,
WTCRBH, and WTCRBL:
RDNCR:
CSACRH and CSACRL:
Bus width control register
Access state control register
Wait control registers AH, AL, BH, and BL
Read strobe timing control register
CS assertion period control registers H and L
Figure 6.1 Block Diagram of Bus Controller
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WAIT
BREQ
BACK
BREQO
External bus
control signals
Internal bus control signals
CPU bus request signal
DTC bus request signal
CPU bus acknowledge signal
DTC bus acknowledge signal
CS7 to CS0
Section 6 Bus Controller (BSC)
6.2
Input/Output Pins
Table 6.1 summarizes the pin configuration of the bus controller.
Table 6.1
Pin Configuration
Name
Symbol
I/O
Function
Address strobe
AS
Output
Strobe signal indicating that an external address
space is accessed and address output on
address bus is enabled.
Read
RD
Output
Strobe signal indicating that an external address
space is being read.
High write/write enable
HWR
Output
Strobe signal indicating that an external address
space is written to, and upper half (D15 to D8) of
data bus is enabled.
Low write
LWR
Output
Strobe signal indicating that an external address
space is written to, and lower half (D7 to D0) of
data bus is enabled.
Chip select 0
CS0
Output
Strobe signal indicating that area 0 is selected.
Chip select 1
CS1
Output
Strobe signal indicating that area 1 is selected
Chip select 2
CS2
Output
Strobe signal indicating that area 2 is selected.
Chip select 3
CS3
Output
Strobe signal indicating that area 3 is selected.
Chip select 4
CS4
Output
Strobe signal indicating that area 4 is selected.
Chip select 5
CS5
Output
Strobe signal indicating that area 5 is selected.
Chip select 6
CS6
Output
Strobe signal indicating that area 6 is selected.
Chip select 7
CS7
Output
Strobe signal indicating that area 7 is selected.
Wait
WAIT
Input
Wait request signal when accessing external
address space.
Bus request
BREQ
Input
Request signal for release of bus to external bus
master.
Bus request
acknowledge
BACK
Output
Acknowledge signal indicating that bus has been
released to external bus master.
Bus request output
BREQO
Output
External bus request signal used when internal
bus master accesses external address space
when external bus is released.
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Section 6 Bus Controller (BSC)
6.3
Register Descriptions
The bus controller has the following registers.
• Bus width control register (ABWCR)
• Access state control register (ASTCR)
• Wait control register AH (WTCRAH)
• Wait control register AL (WTCRAL)
• Wait control register BH (WTCRBH)
• Wait control register BL (WTCRBL)
• Read strobe timing control register (RDNCR)
• CS assertion period control register H (CSACRH)
• CS assertion period control register L (CSACRL)
• Bus control register (BCR)
6.3.1
Bus Width Control Register (ABWCR)
ABWCR designates each area in the external address space as either 8-bit access space or 16-bit
access space.
Bit
Bit Name
Initial Value*
R/W
Description
7
ABW7
1/0
R/W
Area 7 to 0 Bus Width Control
6
ABW6
1/0
R/W
5
ABW5
1/0
R/W
4
ABW4
1/0
R/W
These bits select whether the corresponding
area is to be designated as 8-bit access space
or 16-bit access space.
3
ABW3
1/0
R/W
2
ABW2
1/0
R/W
1
ABW1
1/0
R/W
0
ABW0
1/0
R/W
Note:
*
0: Area n is designated as 16-bit access space
1: Area n is designated as 8-bit access space
(n = 7 to 0)
In modes 2, 4, and 6, ABWCR is initialized to 1. In modes 1, 5, and 7, ABWCR is
initialized to 0.
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Section 6 Bus Controller (BSC)
6.3.2
Access State Control Register (ASTCR)
ASTCR designates each area in the external address space as either 2-state access space or 3-state
access space.
Bit
Bit Name
Initial Value
R/W
Description
7
AST7
1
R/W
Area 7 to 0 Access State Control
6
AST6
1
R/W
5
AST5
1
R/W
4
AST4
1
R/W
3
AST3
1
R/W
These bits select whether the corresponding
area is to be designated as 2-state access
space or 3-state access space. Wait state
insertion is enabled or disabled at the same
time.
2
AST2
1
R/W
0: Area n is designated as 2-state access space
1
AST1
1
R/W
Wait state insertion in area n access is disabled
0
AST0
1
R/W
1: Area n is designated as 3-state access space
Wait state insertion in area n access is enabled
(n = 7 to 0)
6.3.3
Wait Control Registers AH, AL, BH, and BL (WTCRAH, WTCRAL, WTCRBH,
and WTCRBL)
WTCRA and WTCRB select the number of program wait states for each area in the external
address space.
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Section 6 Bus Controller (BSC)
• WTCRAH
Bit
Bit Name
Initial Value
R/W
Description
15
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
14
13
12
W72
W71
W70
1
1
1
R/W
R/W
R/W
Area 7 Wait Control 2 to 0
These bits select the number of program wait
states when accessing area 7 while AST7 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
10
W62
1
R/W
Area 6 Wait Control 2 to 0
9
W61
1
R/W
8
W60
1
R/W
These bits select the number of program wait
states when accessing area 6 while AST6 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
• WT ARAL
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
6
W52
5
W51
4
W50
1
1
1
R/W
Area 5 Wait Control 2 to 0
R/W
These bits select the number of program wait
states when accessing area 5 while AST5 bit in
ASTCR = 1.
R/W
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
3
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
2
W42
1
R/W
Area 4 Wait Control 2 to 0
1
W41
1
R/W
0
W40
1
R/W
These bits select the number of program wait
states when accessing area 4 while AST4 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
• WTCRBH
Bit
Bit Name
Initial Value
R/W
Description
15
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
14
W32
1
R/W
Area 3 Wait Control 2 to 0
13
W31
1
R/W
12
W30
1
R/W
These bits select the number of program wait
states when accessing area 3 while AST3 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
11
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
10
W22
1
R/W
Area 2 Wait Control 2 to 0
9
W21
1
R/W
8
W20
1
R/W
These bits select the number of program wait
states when accessing area 2 while AST2 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
• WTCRBL
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
6
W12
1
R/W
Area 1 Wait Control 2 to 0
5
W11
1
R/W
4
W10
1
R/W
These bits select the number of program wait
states when accessing area 1 while AST1 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
3
—
0
R
Reserved
This bit is always read as 0 and cannot be
modified.
2
W02
1
R/W
Area 0 Wait Control 2 to 0
1
W01
1
R/W
0
W00
1
R/W
These bits select the number of program wait
states when accessing area 0 while AST0 bit in
ASTCR = 1.
000: Program wait not inserted
001: 1 program wait state inserted
010: 2 program wait states inserted
011: 3 program wait states inserted
100: 4 program wait states inserted
101: 5 program wait states inserted
110: 6 program wait states inserted
111: 7 program wait states inserted
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Section 6 Bus Controller (BSC)
6.3.4
Read Strobe Timing Control Register (RDNCR)
RDNCR selects the read strobe signal (RD) negation timing in an external address space read
access.
Bit
Bit Name
Initial Value
R/W
Description
7
RDN7
0
R/W
Read Strobe Timing Control 7 to 0
6
RDN6
0
R/W
5
RDN5
0
R/W
These bits set the negation timing of the read
strobe in a corresponding area read access.
4
RDN4
0
R/W
3
RDN3
0
R/W
2
RDN2
0
R/W
1
RDN1
0
R/W
0
RDN0
0
R/W
As shown in figure 6.2, the read strobe for an
area for which the RDNn bit is set to 1 is
negated one half-state earlier than that for an
area for which the RDNn bit is cleared to 0. The
read data setup and hold time specifications are
also one half-state earlier.
0: In an area n read access, the RD is negated
at the end of the read cycle
1: In an area n read access, the RD is negated
one half-state before the end of the read
cycle
(n = 7 to 0)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
RD
RDNn = 0
Data
RD
RDNn = 1
Data
Figure 6.2 Read Strobe Negation Timing (Example of 3-State Access Space)
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Section 6 Bus Controller (BSC)
6.3.5
CS Assertion Period Control Registers H, L (CSACRH, CSACRL)
CSACRH and CSACRL select whether or not the assertion period of the basic bus interface chip
select signals (CSn) and address signals is to be extended. Extending the assertion period of the
CSn and address signals allows flexible interfacing to external I/O devices.
• CSACRH
Bit
Bit Name
Initial Value
R/W
Description
7
CSXH7
0
R/W
6
CSXH6
0
R/W
CS and Address Signal Assertion Period
Control 1
5
CSXH5
0
R/W
4
CSXH4
0
R/W
3
CSXH3
0
R/W
2
CSXH2
0
R/W
1
CSXH1
0
R/W
0
CSXH0
0
R/W
These bits specify whether or not the Th cycle is
to be inserted (see figure 6.3). When an area
for which the CSXHn bit is set to 1 is accessed,
a one-state Th cycle, in which only the CSn and
address signals are asserted, is inserted before
the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (Th) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (Th) is extended
(n = 7 to 0)
• CSACRL
Bit
Bit Name
Initial Value
R/W
Description
7
CSXT7
0
R/W
6
CSXT6
0
R/W
CS and Address Signal Assertion Period
Control 2
5
CSXT5
0
R/W
4
CSXT4
0
R/W
3
CSXT3
0
R/W
2
CSXT2
0
R/W
1
CSXT1
0
R/W
0
CSXT0
0
R/W
These bits specify whether or not the Tt cycle
shown in figure 6.3 is to be inserted. When an
area for which the CSXTn bit is set to 1 is
accessed, a one-state Tt cycle, in which only
the CSn and address signals are asserted, is
inserted before the normal access cycle.
0: In area n basic bus interface access, the CSn
and address assertion period (Tt) is not
extended
1: In area n basic bus interface access, the CSn
and address assertion period (Tt) is extended
(n = 7 to 0)
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Section 6 Bus Controller (BSC)
Bus cycle
Th
T1
T2
T3
Tt
Address
CS
RD
Read
Data
HWR, LWR
Write
Data
Figure 6.3 CS and Address Assertion Period Extension
(Example of 3-State Access Space and RDNn = 0)
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Section 6 Bus Controller (BSC)
6.3.6
Bus Control Register (BCR)
BCR is used for idle cycle settings, selection of the external bus released state protocol, enabling
or disabling of the write data buffer function, and enabling or disabling of WAIT pin input.
Bit
Bit Name
Initial Value
R/W
Description
15
BRLE
0
R/W
External Bus Release Enable
Enables or disables external bus release.
0: External bus release disabled
BREQ, BACK, and BREQO pins can be used
as I/O ports
1: External bus release enabled
14
BREQOE
0
R/W
BREQO Pin Enable
Controls outputting the bus request signal
(BREQO) to the external bus master in the
external bus released state, when an internal
bus master performs an external address space
access.
0: BREQO output disabled
BREQO pin can be used as I/O port
1: BREQO output enabled
13
—
0
R/W
Reserved
This bit can be read from or written to.
However, the write value should always be 0.
12
IDLC
1
R/W
Idle Cycle State Number Select
Specifies the number of states in the idle cycle
set by ICIS2, ICIS1, and ICIS0.
0: Idle cycle comprises 1 state
1: Idle cycle comprises 2 states
11
ICIS1
1
R/W
Idle Cycle Insert 1
When consecutive external read cycles are
performed in different areas, an idle cycle can
be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
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Section 6 Bus Controller (BSC)
Bit
Bit Name
Initial Value
R/W
Description
10
ICIS0
1
R/W
Idle Cycle Insert 0
When an external read cycle and external write
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
9
WDBE
0
R/W
Write Data Buffer Enable
The write data buffer function can be used for
an external write cycle.
0: Write data buffer function not used
1: Write data buffer function used
8
WAITE
0
R/W
WAIT Pin Enable
Selects enabling or disabling of wait input by
the WAIT pin.
0: Wait input by WAIT pin disabled
WAIT pin can be used as I/O port
1: Wait input by WAIT pin enabled
7
to
3
—
2
ICIS2
All 0
R/W
Reserved
These are readable/writable bits, but the write
value should always be 0.
0
R/W
Idle Cycle Insert 2
When an external write cycle and external read
cycle are performed consecutively, an idle cycle
can be inserted between the bus cycles.
0: Idle cycle not inserted
1: Idle cycle inserted
1,0
—
All 0
R/W
Reserved
These bits can be read from or written to.
However, the write value should always be 0.
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Section 6 Bus Controller (BSC)
6.3.7
Refresh Timer Counter (RTCNT)
RTCNT is an 8-bit readable/writable up-counter. RTCNT counts up using the internal clock
selected by bits RTCK2 to RTCK0 in REFCR.
When RTCNT matches RTCOR (compare match), the CMF flag in REFCR is set to 1 and
RTCNT is cleared to H'00. If the RFSHE bit in REFCR is set to 1 at this time, a refresh cycle is
started. If the RFSHE bit is cleared to 0 and the CMIE bit in REFCR is set to 1, a compare match
interrupt (CMI) is generated.
RTCNT is initialized to H'00 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
6.3.8
Refresh Time Constant Register (RTCOR)
RTCOR is an 8-bit readable/writable register that sets the period for compare match operations
with RTCNT.
The values of RTCOR and RTCNT are constantly compared, and if they match, the CMF flag in
REFCR is set to 1 and RTCNT is cleared to H'00.
RTCOR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
6.4
Bus Control
6.4.1
Area Division
The bus controller divides the 16-Mbyte address space into eight areas, 0 to 7, in 2-Mbyte units,
and performs bus control for external address space in area units. Chip select signals (CS0 to CS7)
can be output for each area. In normal mode, a part of area 0, 64-kbyte address space, is
controlled. Figure 6.4 shows an outline of the memory map.
Note: Normal mode is not available in this LSI.
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Section 6 Bus Controller (BSC)
H'000000
H'0000
Area 0
(2 Mbytes)
H'1FFFFF
H'200000
Area 1
(2 Mbytes)
H'3FFFFF
H'400000
Area 2
(2 Mbytes)
H'FFFF
H'5FFFFF
H'600000
Area 3
(2 Mbytes)
H'7FFFFF
H'800000
Area 4
(2 Mbytes)
H'9FFFFF
H'A00000
Area 5
(2 Mbytes)
H'BFFFFF
H'C00000
Area 6
(2 Mbytes)
H'DFFFFF
H'E00000
Area 7
(2 Mbytes)
H'FFFFFF
(1) Advanced mode
(2) Normal mode*
Note: * Not available in this LSI
Figure 6.4 Area Divisions
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Section 6 Bus Controller (BSC)
6.4.2
Bus Specifications
The external address space bus specifications consist of five elements: bus width, number of
access states, number of program wait states, read strobe timing, and chip select (CS) assertion
period extension states. The bus width and number of access states for on-chip memory and
internal I/O registers are fixed, and are not affected by the bus controller.
Bus Width: A bus width of 8 or 16 bits can be selected with ABWCR. An area for which an 8-bit
bus is selected functions as an 8-bit access space, and an area for which a 16-bit bus is selected
functions as a 16-bit access space. If all areas are designated as 8-bit access space, 8-bit bus mode
is set; if any area is designated as 16-bit access space, 16-bit bus mode is set.
Number of Access States: Two or three access states can be selected with ASTCR. An area for
which 2-state access is selected functions as a 2-state access space, and an area for which 3-state
access is selected functions as a 3-state access space.
When 2-state access space is designated, wait insertion is disabled. When 3-state access space is
designated, it is possible to insert program waits by means of the WTCRA and WTCRB, and
external waits by means of the WAIT pin.
Number of Program Wait States: When 3-state access space is designated by ASTCR, the
number of program wait states to be inserted automatically is selected with WTCRA and WTCRB.
From 0 to 7 program wait states can be selected. Table 6.2 shows the bus specifications (bus
width, and number of access states and program wait states) for each basic bus interface area.
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Section 6 Bus Controller (BSC)
Table 6.2
Bus Specifications for Each Area (Basic Bus Interface)
ABWCR
ASTCR
ABWn
ASTn
Wn2
Wn1
Wn0
Bus Width
Access
States
Program Wait
States
0
0
—
—
—
16
2
0
1
0
0
0
3
0
WTCRA, WTCRB
1
1
0
1
1
1
1
0
2
1
3
0
4
1
5
0
6
1
7
0
—
—
—
1
0
0
0
1
1
1
0
1
Bus Specifications (Basic Bus Interface)
8
2
0
3
0
1
0
2
1
3
0
4
1
5
0
6
1
7
(n = 0 to 7)
Read Strobe Timing: RDNCR can be used to select either of two negation timings (at the end of
the read cycle or one half-state before the end of the read cycle) for the read strobe (RD) used in
the basic bus interface space.
Chip Select (CS
CS)
CS Assertion Period Extension States: Some external I/O devices require a setup
time and hold time between address and CS signals and strobe signals such as RD, HWR, and
LWR. CSACR can be used to insert states in which only the CS, AS, and address signals are
asserted before and after a basic bus space access cycle.
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Section 6 Bus Controller (BSC)
6.4.3
Memory Interfaces
The memory interfaces in this LSI allows direct connection of ROM, SRAM, and so on.
The initial state of each area is basic bus interface, 3-state access space. The initial bus width is
selected according to the operating mode.
Area 0: Area 0 includes on-chip ROM in expanded mode with on-chip ROM enabled and the
space excluding on-chip ROM is external address space, and in expanded mode with on-chip
ROM disabled, all of area 0 is external address space.
When area 0 external space is accessed, the CS0 signal can be output.
Area 1: In externally expanded mode, all of area 1 is external address space.
When area 1 external address space is accessed, the CS1 signal can be output.
Areas 2 to 5: In externally expanded mode, areas 2 to 5 are all external address space.
When area 2 to 5 external space is accessed, signals CS2 to CS5 can be output.
Area 6: In externally expanded mode, all of area 6 is external space.
When area 6 external space is accessed, the CS6 signal can be output.
Area 7: Area 7 includes the on-chip RAM and internal/O registers. In externally expanded mode,
the space excluding the on-chip RAM and internal I/O registers is external address space. The onchip RAM is enabled when the RAME bit is set to 1 in the system control register (SYSCR); when
the RAME bit is cleared to 0, the on-chip RAM is disabled and the corresponding addresses are in
external address space.
When area 7 external address space is accessed, the CS7 signal can be output.
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Section 6 Bus Controller (BSC)
6.4.4
Chip Select Signals
This LSI can output chip select signals (CS0 to CS7) for areas 0 to 7. The signal outputs low when
the corresponding external space area is accessed. Figure 6.5 shows an example of CS0 to CS7
signals output timing.
Enabling or disabling of CS0 to CS7 signals output is set by the data direction register (DDR) bit
for the port corresponding to the CS0 to CS7 pins.
In expanded mode with on-chip ROM disabled, the CS0 pin is placed in the output state after a
reset. Pins CS1 to CS7 are placed in the input state after a reset and so the corresponding DDR bits
should be set to 1 when outputting signals CS1 to CS7.
In expanded mode with on-chip ROM enabled, pins CS0 to CS7 are all placed in the input state
after a reset and so the corresponding DDR bits should be set to 1 when outputting signals CS0 to
CS7.
Bus cycle
T1
T2
T3
φ
Address bus
Area n external address
CSn
Figure 6.5 CSn Signal Output Timing (n = 0 to 7)
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Section 6 Bus Controller (BSC)
6.5
Basic Bus Interface
The basic bus interface enables direct connection of ROM, SRAM, and so on.
6.5.1
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The bus
controller has a data alignment function, and when accessing external address space, controls
whether the upper data bus (D15 to D8) or lower data bus (D7 to D0) is used according to the bus
specifications for the area being accessed (8-bit access space or 16-bit access space) and the data
size.
8-Bit Access Space: Figure 6.6 illustrates data alignment control for the 8-bit access space. With
the 8-bit access space, the upper data bus (D15 to D8) is always used for accesses. The amount of
data that can be accessed at one time is one byte: a word access is performed as two byte accesses,
and a longword access, as four byte accesses.
Upper data bus
D15
Lower data bus
D8 D7
D0
Byte size
Word size
1st bus cycle
2nd bus cycle
1st bus cycle
Longword
size
2nd bus cycle
3rd bus cycle
4th bus cycle
Figure 6.6 Access Sizes and Data Alignment Control (8-Bit Access Space)
16-Bit Access Space: Figure 6.7 illustrates data alignment control for the 16-bit access space.
With the 16-bit access space, the upper data bus (D15 to D8) and lower data bus (D7 to D0) are
used for accesses. The amount of data that can be accessed at one time is one byte or one word,
and a longword access is executed as two word accesses.
In byte access, whether the upper or lower data bus is used is determined by whether the address is
even or odd. The upper data bus is used for an even address, and the lower data bus for an odd
address.
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Section 6 Bus Controller (BSC)
Upper data bus
D15
Byte size
• Even address
Byte size
• Odd address
Lower data bus
D8 D7
D0
Word size
Longword
size
1st bus cycle
2nd bus cycle
Figure 6.7 Access Sizes and Data Alignment Control (16-bit Access Space)
6.5.2
Valid Strobes
Table 6.3 shows the data buses used and valid strobes for the access spaces.
In a read, the RD signal is valid for both the upper and the lower half of the data bus. In a write,
the HWR signal is valid for the upper half of the data bus, and the LWR signal for the lower half.
Table 6.3
Data Buses Used and Valid Strobes
Access
Size
Read/
Write
Address
Valid
Strobe
Upper Data Bus Lower Data Bus
(D15 to D8)
(D7 to D0)
8-bit access
space
Byte
Read
—
RD
Valid
Write
—
HWR
16-bit access
space
Byte
Read
Even
RD
Area
Hi-Z
Odd
Write
Word
Invalid
Valid
Invalid
Invalid
Valid
Even
HWR
Valid
Hi-Z
Odd
LWR
Hi-Z
Valid
Read
—
RD
Valid
Valid
Write
—
HWR, LWR
Valid
Valid
Note: Hi-Z: High-impedance state
Invalid: Input state; input value is ignored.
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Section 6 Bus Controller (BSC)
6.5.3
Basic Timing
8-Bit, 2-State Access Space: Figure 6.8 shows the bus timing for an 8-bit, 2-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.8 Bus Timing for 8-Bit, 2-State Access Space
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Section 6 Bus Controller (BSC)
8-Bit, 3-State Access Space: Figure 6.9 shows the bus timing for an 8-bit, 3-state access space.
When an 8-bit access space is accessed, the upper half (D15 to D8) of the data bus is used. The
LWR pin is always fixed high. Wait states can be inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
High
LWR
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.9 Bus Timing for 8-Bit, 3-State Access Space
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Section 6 Bus Controller (BSC)
16-Bit, 2-State Access Space: Figures 6.10 to 6.12 show bus timings for a 16-bit, 2-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for odd addresses, and the lower half (D7 to D0) for even addresses. Wait states cannot be
inserted.
Bus cycle
T1
T2
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.10 Bus Timing for 16-Bit, 2-State Access Space
(Even Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
High impedance
D15 to D8
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.11 Bus Timing for 16-Bit, 2-State Access Space
(Odd Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T2
T1
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.12 Bus Timing for 16-Bit, 2-State Access Space
(Word Access)
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Section 6 Bus Controller (BSC)
16-Bit, 3-State Access Space: Figures 6.13 to 6.15 show bus timings for a 16-bit, 3-state access
space. When a 16-bit access space is accessed, the upper half (D15 to D8) of the data bus is used
for the even address, and the lower half (D7 to D0) for the odd address. Wait states can be
inserted.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Invalid
HWR
LWR
High
Write
D15 to D8
D7 to D0
Valid
High impedance
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.13 Bus Timing for 16-Bit, 3-State Access Space
(Even Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Invalid
D7 to D0
Valid
HWR
High
LWR
Write
D15 to D8
D7 to D0
High impedance
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.14 Bus Timing for 16-Bit, 3-State Access Space
(Odd Address Byte Access)
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Section 6 Bus Controller (BSC)
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
Read
D15 to D8
Valid
D7 to D0
Valid
HWR
LWR
Write
D15 to D8
Valid
D7 to D0
Valid
Notes: 1. n = 0 to 7
2. When RDNn = 0
Figure 6.15 Bus Timing for 16-Bit, 3-State Access Space
(Word Access)
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Section 6 Bus Controller (BSC)
6.5.4
Wait Control
When accessing external space, this LSI can extend the bus cycle by inserting one or more wait
states (Tw). There are two ways of inserting wait states: program wait insertion and pin wait
insertion using the WAIT pin.
Program Wait Insertion: From 0 to 7 wait states can be inserted automatically between the T2
state and T3 state on an individual area basis in 3-state access space, according to the settings in
WTCRA and WTCRB.
Pin Wait Insertion: Setting the WAITE bit to 1 in BCR enables wait input by means of the
WAIT pin. When an external address space is accessed in this state, a program wait is first
inserted in accordance with the settings in WTCRA and WTCRB. If the WAIT pin is low at the
falling edge of φ in the last T2 or Tw state, another Tw state is inserted. If the WAIT pin is held low,
Tw states are inserted until it goes high. This is useful when inserting seven or more Tw states, or
when changing the number of Tw states to be inserted for different external devices. The WAITE
bit setting applies to all areas. Figure 6.16 shows an example of wait state insertion timing.
The settings after a reset are: 3-state access, insertion of 7 program wait states, and WAIT input
disabled.
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Section 6 Bus Controller (BSC)
By program wait
T1
T2
Tw
By WAIT pin
Tw
Tw
T3
φ
WAIT
Address bus
AS
RD
Read
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Notes: 1. Downward arrows indicate the timing of WAIT pin sampling.
2. When RDN = 0
Figure 6.16 Example of Wait State Insertion Timing
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Section 6 Bus Controller (BSC)
6.5.5
Read Strobe (RD
RD)
RD Timing
The read strobe (RD) timing can be changed for individual areas by setting bits RDN7 to RDN0 to
1 in RDNCR. Figure 6.17 shows an example of the timing when the read strobe timing is changed
in basic bus 3-state access space.
Bus cycle
T1
T2
T3
φ
Address bus
CSn
AS
RD
RDNn = 0
Data bus
RD
RDNn = 1
Data bus
Figure 6.17 Example of Read Strobe Timing
6.5.6
Extension of Chip Select (CS
CS)
CS Assertion Period
Some external I/O devices require a setup time and hold time between address and CS signals and
strobe signals such as RD, HWR, and LWR. Settings can be made in the CSACR register to insert
states in which only the CS, AS, and address signals are asserted before and after a basic bus space
access cycle. Extension of the CS assertion period can be set for individual areas. With the CS
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Section 6 Bus Controller (BSC)
assertion extension period in write access, the data setup and hold times are less stringent since the
write data is output to the data bus.
Figure 6.18 shows an example of the timing when the CS assertion period is extended in basic bus
3-state access space.
Bus cycle
Th
T1
T2
T3
Tt
φ
Address bus
CSn
AS
Read
(when
RDNn = 0)
RD
Data bus
Read data
HWR, LWR
Write
Data bus
Write data
Figure 6.18 Example of Timing when Chip Select Assertion Period Is Extended
Both extension state Th inserted before the basic bus cycle and extension state Tt inserted after the
basic bus cycle, or only one of these, can be specified for individual areas. Insertion or noninsertion can be specified for the Th state with the upper 8 bits (CSXH7 to CSXH0) in the CSACR
register, and for the Tt state with the lower 8 bits (CSXT7 to CSXT0).
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Section 6 Bus Controller (BSC)
6.6
Idle Cycle
6.6.1
Operation
When this LSI accesses external address space, it can insert an idle cycle (Ti) between bus cycles
in the following three cases: (1) when read accesses in different areas occur consecutively, (2)
when a write cycle occurs immediately after a read cycle, and (3) when a read cycle occurs
immediately after a write cycle. Insertion of a 1-state or 2-state idle cycle can be selected with the
IDLC bit in BCR. By inserting an idle cycle it is possible, for example, to avoid data collisions
between ROM, etc., with a long output floating time, and high-speed memory, I/O interfaces, and
so on.
Consecutive Reads in Different Areas: If consecutive reads in different areas occur while the
ICIS1 bit is set to 1 in BCR, an idle cycle is inserted at the start of the second read cycle.
Figure 6.19 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a read cycle for SRAM, each
being located in a different area. In (a), an idle cycle is not inserted, and a collision occurs in bus
cycle B between the read data from ROM and that from SRAM. In (b), an idle cycle is inserted,
and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS1 = 0)
T2
T3
Data collision
Ti
T1
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
Figure 6.19 Example of Idle Cycle Operation
(Consecutive Reads in Different Areas)
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Bus cycle B
T2
Section 6 Bus Controller (BSC)
Write after Read: If an external write occurs after an external read while the ICIS0 bit is set to 1
in BCR, an idle cycle is inserted at the start of the write cycle.
Figure 6.20 shows an example of the operation in this case. In this example, bus cycle A is a read
cycle for ROM with a long output floating time, and bus cycle B is a CPU write cycle. In (a), an
idle cycle is not inserted, and a collision occurs in bus cycle B between the read data from ROM
and the CPU write data. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR
HWR
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS0 = 0)
Data collision
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS0 = 1, initial value)
Figure 6.20 Example of Idle Cycle Operation (Write after Read)
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Section 6 Bus Controller (BSC)
Read after Write: If an external read occurs after an external write while the ICIS2 bit is set to 1
in BCR, an idle cycle is inserted at the start of the read cycle.
Figure 6.21 shows an example of the operation in this case. In this example, bus cycle A is a CPU
write cycle and bus cycle B is a read cycle from an external device. In (a), an idle cycle is not
inserted, and a collision occurs in bus cycle B between the CPU write data and read data from an
external device. In (b), an idle cycle is inserted, and a data collision is prevented.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
HWR, LWR
HWR
Data bus
Data bus
Long output floating time
(a) No idle cycle insertion
(ICIS2 = 0)
Data collision
T2
T3
Bus cycle B
Ti
T1
Idle cycle
(b) Idle cycle insertion
(ICIS2 = 1, initial value)
Figure 6.21 Example of Idle Cycle Operation (Read after Write)
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T2
Section 6 Bus Controller (BSC)
Relationship between Chip Select (CS
CS)
RD)
CS Signal and Read (RD
RD Signal: Depending on the
system’s load conditions, the RD signal may lag behind the CS signal. An example is shown in
figure 6.22. In this case, with the setting for no idle cycle insertion (a), there may be a period of
overlap between the bus cycle A RD signal and the bus cycle B CS signal. Setting idle cycle
insertion, as in (b), however, will prevent any overlap between the RD and CS signals. In the
initial state after reset release, idle cycle insertion (b) is set.
Bus cycle A
T1
T2
T3
Bus cycle B
T1
Bus cycle A
T2
T1
φ
φ
Address bus
Address bus
CS (area A)
CS (area A)
CS (area B)
CS (area B)
RD
RD
Overlap period between CS (area B)
and RD may occur
T2
T3
Bus cycle B
Ti
T1
T2
Idle cycle
(b) Idle cycle insertion
(ICIS1 = 1, initial value)
(a) No idle cycle insertion
(ICIS1 = 0)
Figure 6.22 Relationship between Chip Select (CS
CS)
RD)
CS and Read (RD
RD
6.6.2
Pin States in Idle Cycle
Table 6.4 shows the pin states in an idle cycle.
Table 6.4
Pin States in Idle Cycle
Pins
Pin State
A23 to A0
Contents of following bus cycle
D15 to D0
High impedance
CSn (n = 7 to 0)
High
AS
High
RD
High
HWR, LWR
High
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Section 6 Bus Controller (BSC)
6.7
Write Data Buffer Function
This LSI has a write data buffer function for the external data bus. Using the write data buffer
function enables external writes to be executed in parallel with internal accesses. The write data
buffer function is made available by setting the WDBE bit to 1 in BCR.
Figure 6.23 shows an example of the timing when the write data buffer function is used. When this
function is used, if an external address space write continues for two states or longer, and there is
an internal access next, an external write only is executed in the first state, but from the next state
onward an internal access (on-chip memory or internal I/O register read/write) is executed in
parallel with the external address space write rather than waiting until it ends.
On-chip memory read Internal I/O register read
External write cycle
T1
T2
TW
TW
T3
Internal address bus
Internal memory
Internal I/O register address
Internal read signal
A23 to A0
External address
CSn
External space
write
HWR, LWR
D15 to D0
Figure 6.23 Example of Timing when Write Data Buffer Function Is Used
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Section 6 Bus Controller (BSC)
6.8
Bus Release
This LSI can release the external bus in response to a bus request from an external device. In the
external bus released state, internal bus masters continue to operate as long as there is no external
access. If any of the following requests are issued in the external bus released state, the BREQO
signal can be driven low to output a bus request externally.
• When an internal bus master wants to perform an external access
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode
6.8.1
Operation
In externally expanded mode, the bus can be released to an external device by setting the BRLE
bit to 1 in BCR. Driving the BREQ pin low issues an external bus request to this LSI. When the
BREQ pin is sampled, at the prescribed timing the BACK pin is driven low, and the address bus,
data bus, and bus control signals are placed in the high-impedance state, establishing the external
bus released state.
In the external bus released state, internal bus masters can perform accesses using the internal bus.
When an internal bus master wants to make an external access, it temporarily defers initiation of
the bus cycle, and waits for the bus request from the external bus master to be canceled. If a
SLEEP instruction is executed to place the chip in software standby mode or all-module-clocksstopped mode, software standby and all-module-clocks-stopped control are deferred until the bus
request from the external bus master is canceled.
If the BREQOE bit is set to 1 in BCR, the BREQO pin can be driven low when any of the
following requests are issued, to request cancellation of the bus request externally.
• When an internal bus master wants to perform an external access
• When a SLEEP instruction is executed to place the chip in software standby mode or allmodule-clocks-stopped mode
When the BREQ pin is driven high, the BACK pin is driven high at the prescribed timing and the
external bus released state is terminated.
If an external bus release request and external access occur simultaneously, the order of priority is
as follows:
(High) External bus release > External access by internal bus master (Low)
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Section 6 Bus Controller (BSC)
6.8.2
Pin States in External Bus Released State
Table 6.5 shows pin states in the external bus released state.
Table 6.5
Pin States in Bus Released State
Pins
Pin State
A23 to A0
High impedance
D15 to D0
High impedance
CSn (n = 7 to 0)
High impedance
AS
High impedance
RD
High impedance
HWR, LWR
High impedance
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Section 6 Bus Controller (BSC)
6.8.3
Transition Timing
Figure 6.24 shows the timing for transition to the bus released state.
External space
access cycle
CPU
cycle
External bus released state
T1
T2
φ
High-Z
Address bus
High-Z
Data bus
High-Z
AS
High-Z
RD
High-Z
HWR, LWR
BREQ
BACK
BREQO
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[8]
[1] Low level of BREQ signal is sampled at rise of ø.
[2] Bus control signal returns to be high at end of external space access cycle.
At least one state from sampling of BREQ signal.
[3] BACK signal is driven low, releasing bus to external bus master.
[4] BREQ signal state is also sampled in external bus released state.
[5] High level of BREQ signal is sampled.
[6] BACK signal is driven high, ending external bus release cycle.
[7] When there is external access of internal bus master during external
bus release while BREQOE bit is set to 1, BREQO signal goes low.
[8] Normally BREQO signal goes high 1.5 states after rising edge of BACK signal.
Figure 6.24 Bus Released State Transition Timing
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Section 6 Bus Controller (BSC)
6.9
Bus Arbitration
This LSI has a bus arbiter that arbitrates bus mastership operations (bus arbitration).
There are two bus masters—the CPU and DTC—that perform read/write operations when they
have possession of the bus. Each bus master requests the bus by means of a bus request signal. The
bus arbiter determines priorities at the prescribed timing, and permits use of the bus by means of a
bus request acknowledge signal. The selected bus master then takes possession of the bus and
begins its operation.
6.9.1
Operation
The bus arbiter detects the bus masters’ bus request signals, and if the bus is requested, sends a bus
request acknowledge signal to the bus master. If there are bus requests from more than one bus
master, the bus request acknowledge signal is sent to the one with the highest priority. When a bus
master receives the bus request acknowledge signal, it takes possession of the bus until that signal
is canceled.
The order of priority of the bus masterships is as follows:
(High) DTC > CPU (Low)
6.9.2
Bus Transfer Timing
Even if a bus request is received from a bus master with a higher priority than that of the bus
master that has acquired the bus and is currently operating, the bus is not necessarily transferred
immediately. There are specific timings at which each bus master can relinquish the bus.
CPU: The CPU is the lowest-priority bus master, and if a bus request is received from the DTC,
the bus arbiter transfers the bus to the bus master that issued the request. The timing for transfer of
the bus is as follows:
• The bus is transferred at a break between bus cycles. However, if a bus cycle is executed in
discrete operations, as in the case of a longword-size access, the bus is not transferred between
the component operations.
• With bit manipulation instructions such as BSET and BCLR, the sequence of operations is:
data read (read), relevant bit manipulation operation (modify), write-back (write). The bus is
not transferred during this read-modify-write cycle, which is executed as a series of bus cycles.
• If the CPU is in sleep mode, the bus is transferred immediately.
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Section 6 Bus Controller (BSC)
DTC: The DTC sends the bus arbiter a request for the bus when an activation request is generated.
The DTC can release the bus after a vector read, a register information read (3 states), a single data
transfer, or a register information write (3 states). It does not release the bus during a register
information read (3 states), a single data transfer, or a register information write (3 states).
External Bus Release: When the BREQ pin goes low and an external bus release request is issued
while the BRLE bit is set to 1 in BCR, a bus request is sent to the bus arbiter.
External bus release can be performed on completion of an external bus cycle.
6.10
Bus Controller Operation in Reset
In a reset, this LSI, including the bus controller, enters the reset state immediately, and any
executing bus cycle is aborted.
6.11
Usage Notes
6.11.1
External Bus Release Function and All-Module-Clocks-Stopped Mode
In this LSI, if the ACSE bit is set to 1 in MSTPCR, and then a SLEEP instruction is executed with
the setting for all peripheral module clocks to be stopped (MSTPCR = H'FFFF) or for operation of
the 8-bit timer module alone (MSTPCR = H'FFFE), and a transition is made to the sleep state, the
all-module-clocks-stopped mode is entered in which the clock is also stopped for the bus
controller and I/O ports. In this state, the external bus release function is halted. To use the
external bus release function in sleep mode, the ACSE bit in MSTPCR must be cleared to 0.
Conversely, if a SLEEP instruction to place the chip in all-module-clocks-stopped mode is
executed in the external bus released state, the transition to all-module-clocks-stopped mode is
deferred and performed until after the bus is recovered.
6.11.2
External Bus Release Function and Software Standby
In this LSI, internal bus mastership operation does not stop even while the bus is released, as long
as the program is running in on-chip ROM, etc., and no external access occurs. If a SLEEP
instruction to place the chip in software standby mode is executed while the external bus is
released, the transition to software standby mode is deferred and performed after the bus is
recovered.
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Section 6 Bus Controller (BSC)
Also, since clock oscillation halts in software standby mode, if BREQ goes low in this mode,
indicating an external bus release request, the request cannot be answered until the chip has
recovered from the software standby state.
6.11.3
BREQO Output Timing
When the BREQOE bit is set to 1 and the BREQO signal is output, BREQO may go low before
the BACK signal.
This will occur if the next external access request occurs while internal bus arbitration is in
progress after the chip samples a low level of BREQ.
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Section 7 Data Transfer Controller (DTC)
Section 7 Data Transfer Controller (DTC)
This LSI includes a data transfer controller (DTC). The DTC can be activated by an interrupt or
software, to transfer data.
Figure 7.1 shows a block diagram of the DTC. The DTC’s register information is stored in the onchip RAM. When the DTC is used, the RAME bit in SYSCR must be set to 1. A 32-bit bus
connects the DTC to the on-chip RAM (1 kbyte), enabling 32-bit/1-state reading and writing of
the DTC register information.
7.1
Features
• Transfer possible over any number of channels
• Three transfer modes
Normal, repeat, and block transfer modes available
• One activation source can trigger a number of data transfers (chain transfer)
• Direct specification of 16-Mbyte address space possible
• Activation by software is possible
• Transfer can be set in byte or word units
• A CPU interrupt can be requested for the interrupt that activated the DTC
• Module stop mode can be set
DTCH809A_010020020400
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Section 7 Data Transfer Controller (DTC)
Internal address bus
On-chip
RAM
Internal data bus
CPU interrupt
request
Legend:
MRA, MRB:
CRA, CRB:
SAR:
DAR:
DTCERA to DTCERG:
DTVECR:
DTC mode registers A and B
DTC transfer count registers A and B
DTC source address register
DTC destination address register
DTC enable registers A to G
DTC vector register
Figure 7.1 Block Diagram of DTC
7.2
Register information
MRA MRB
CRA
CRB
DAR
SAR
Control logic
DTC
DTC activation
request
DTVECR
Interrupt
request
DTCERA
to
DTCERG
Interrupt controller
Register Descriptions
DTC has the following registers.
• DTC mode register A (MRA)
• DTC mode register B (MRB)
• DTC source address register (SAR)
• DTC destination address register (DAR)
• DTC transfer count register A (CRA)
• DTC transfer count register B (CRB)
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Section 7 Data Transfer Controller (DTC)
These six registers cannot be directly accessed from the CPU. When activated, the DTC reads a set
of register information that is stored in an on-chip RAM to the corresponding DTC registers and
transfers data. After the data transfer, it writes a set of updated register information back to the
RAM.
• DTC enable registers A to H (DTCERA to DTCERH)
• DTC vector register (DTVECR)
7.2.1
DTC Mode Register A (MRA)
MRA selects the DTC operating mode.
Bit
Bit Name
Initial Value
R/W
Description
7
SM1
Undefined
—
Source Address Mode 1 and 0
6
SM0
Undefined
—
These bits specify an SAR operation after a data
transfer.
0x: SAR is fixed
10: SAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: SAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
5
DM1
Undefined
—
Destination Address Mode 1 and 0
4
DM0
Undefined
—
These bits specify a DAR operation after a data
transfer.
0x: DAR is fixed
10: DAR is incremented after a transfer
(by +1 when Sz = 0; by +2 when Sz = 1)
11: DAR is decremented after a transfer
(by –1 when Sz = 0; by –2 when Sz = 1)
3
MD1
Undefined
—
DTC Mode
2
MD0
Undefined
—
These bits specify the DTC transfer mode.
00: Normal mode
01: Repeat mode
10: Block transfer mode
11: Setting prohibited
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Section 7 Data Transfer Controller (DTC)
Bit
Bit Name
Initial Value
R/W
Description
1
DTS
Undefined
—
DTC Transfer Mode Select
Specifies whether the source side or the destination
side is set to be a repeat area or block area, in
repeat mode or block transfer mode.
0: Destination side is repeat area or block area
1: Source side is repeat area or block area
0
Sz
Undefined
—
DTC Data Transfer Size
Specifies the size of data to be transferred.
0: Byte-size transfer
1: Word-size transfer
Legend:
X: Don’t care
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Section 7 Data Transfer Controller (DTC)
7.2.2
DTC Mode Register B (MRB)
MRB selects the DTC operating mode.
Bit
Bit Name
Initial Value
R/W
Description
7
CHNE
Undefined
—
DTC Chain Transfer Enable
When this bit is set to 1, a chain transfer will be
performed. For details, refer to section 7.5.4, Chain
Transfer.
In data transfer with CHNE set to 1, determination of
the end of the specified number of transfers, clearing
of the activation source flag, and clearing of DTCER
is not performed.
6
DISEL
Undefined
—
DTC Interrupt Select
When this bit is set to 1, a CPU interrupt request is
generated every time after a data transfer ends.
When this bit is set to 0, a CPU interrupt request is
generated at the time when the specified number of
data transfer ends.
5
CHNS
Undefined
—
DTC Chain Transfer Select
Specifies the chain transfer condition.
0: Chain transfer every time
1: Chain transfer only when transfer counter = 0
4
to
0
7.2.3
—
Undefined
—
Reserved
These bits have no effect on DTC operation, and
should always be written with 0.
DTC Source Address Register (SAR)
SAR is a 24-bit register that designates the source address of data to be transferred by the DTC.
For word-size transfer, specify an even source address.
7.2.4
DTC Destination Address Register (DAR)
DAR is a 24-bit register that designates the destination address of data to be transferred by the
DTC. For word-size transfer, specify an even destination address.
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Section 7 Data Transfer Controller (DTC)
7.2.5
DTC Transfer Count Register A (CRA)
CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.
In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65,536). It is
decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.
In repeat mode or block transfer mode, the CRA is divided into two parts: the upper 8 bits
(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL
functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is
transferred, and the contents of CRAH are sent when the count reaches H'00.
7.2.6
DTC Transfer Count Register B (CRB)
CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in
block transfer mode. It functions as a 16-bit transfer counter (1 to 65,536) that is decremented by 1
every time data is transferred, and transfer ends when the count reaches H'0000.
7.2.7
DTC Enable Registers A to H (DTCERA to DTCERH)
DTCER which is comprised of seven registers, DTCERA to DTCERH, is a register that specifies
DTC activation interrupt sources. The correspondence between interrupt sources and DTCE bits is
shown in table 7.1. For DTCE bit setting, use bit manipulation instructions such as BSET and
BCLR for reading and writing. If all interrupts are masked, multiple activation sources can be set
at one time (only at the initial setting) by writing data after executing a dummy read on the
relevant register.
Bit
Bit Name
Initial Value
R/W
Description
7
DTCE7
0
R/W
DTC Activation Enable
6
DTCE6
0
R/W
5
DTCE5
0
R/W
Setting this bit to 1 specifies a relevant interrupt
source to a DTC activation source.
4
DTCE4
0
R/W
[Clearing conditions]
3
DTCE3
0
R/W
•
2
DTCE2
0
R/W
When the DISEL bit is 1 and the data transfer has
ended
1
DTCE1
0
R/W
•
0
DTCE0
0
R/W
When the specified number of transfers have
ended
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These bits are not cleared when the DISEL bit is 0
and the specified number of transfers have not
ended
Section 7 Data Transfer Controller (DTC)
7.2.8
DTC Vector Register (DTVECR)
DTVECR enables or disables DTC activation by software, and sets a vector number for the
software activation interrupt.
Bit
Bit Name
Initial Value
R/W
Description
7
SWDTE
0
R/W
DTC Software Activation Enable
Setting this bit to 1 activates DTC. Only 1 can be
written to this bit.
[Clearing conditions]
•
When the DISEL bit is 0 and the specified
number of transfers have not ended
•
When 0 is written to the DISEL bit after a
software-activated data transfer end interrupt
(SWDTEND) request has been sent to the CPU.
When the DISEL bit is 1 and data transfer has ended
or when the specified number of transfers have
ended, this bit will not be cleared.
6
DTVEC6
0
R/W
DTC Software Activation Vectors 6 to 0
5
DTVEC5
0
R/W
4
DTVEC4
0
R/W
These bits specify a vector number for DTC software
activation.
3
DTVEC3
0
R/W
2
DTVEC2
0
R/W
1
DTVEC1
0
R/W
0
DTVEC0
0
R/W
The vector address is expressed as H'0400 + (vector
number × 2). For example, when DTVEC6 to
DTVEC0 = H'10, the vector address is H'0420. When
the bit SWDTE is 0, these bits can be written.
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Section 7 Data Transfer Controller (DTC)
7.3
Activation Sources
The DTC operates when activated by an interrupt or by a write to DTVECR by software. An
interrupt request can be directed to the CPU or DTC, as designated by the corresponding DTCER
bit. At the end of a data transfer (or the last consecutive transfer in the case of chain transfer), the
activation source or corresponding DTCER bit is cleared. The activation source flag, in the case
of RXI0, for example, is the RDRF flag of SCI_0.
When an interrupt has been designated a DTC activation source, existing CPU mask level and
interrupt controller priorities have no effect. If there is more than one activation source at the same
time, the DTC operates in accordance with the default priorities.
Figure 7.2 shows a block diagram of activation source control. For details see section 5, Interrupt
Controller.
Source flag cleared
Clear
controller
Clear
DTCER
On-chip
supporting
module
IRQ interrupt
Interrupt
request
Selection circuit
Select
DTVECR
Clear request
DTC
CPU
Interrupt controller
Interrupt mask
Figure 7.2 Block Diagram of DTC Activation Source Control
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Section 7 Data Transfer Controller (DTC)
7.4
Location of Register Information and DTC Vector Table
Locate the register information in the on-chip RAM (addresses: H'FFBC00 to H'FFBFFF).
Register information should be located at the address that is multiple of four within the range.
Locating the register information in address space is shown in figure 7.3. Locate the MRA, SAR,
MRB, DAR, CRA, and CRB registers, in that order, from the start address of the register
information. In the case of chain transfer, register information should be located in consecutive
areas as shown in figure 7.3 and the register information start address should be located at the
corresponding vector address to the activation source. The DTC reads the start address of the
register information from the vector address set for each activation source, and then reads the
register information from that start address.
When the DTC is activated by software, the vector address is obtained from: H'0400 +
(DTVECR[6:0] × 2). For example, if DTVECR is H'10, the vector address is H'0420.
The configuration of the vector address is the same in both normal* and advanced modes, a 2-byte
unit being used in both cases. These two bytes specify the lower bits of the register information
start address.
Note: * Not available in this LSI.
Lower addresses
0
Start address of
register information
1
2
3
MRA
SAR
MRB
DAR
Register information
CRB
CRA
Chain transfer
MRA
SAR
MRB
DAR
CRB
CRA
Register information
for second transfer
in case of chain
transfer
Four bytes
Figure 7.3 Correspondence between DTC Vector Address and Register Information
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Section 7 Data Transfer Controller (DTC)
Table 7.1
Interrupt Sources, DTC Vector Addresses, and Corresponding DTCEs
Origin of
Activation
Source
Activation
Source
Vector
Number
DTC
Vector Address
Software
Write to DTVECR
DTVECR
External pin
IRQ0
DTCE*
Priority
H'0400 + (DTVECR
[6:0] × 2)
—
High
16
H'0420
DTCEA7
IRQ1
17
H'0422
DTCEA6
IRQ2
18
H'0424
DTCEA5
IRQ3
19
H'0426
DTCEA4
IRQ4
20
H'0428
DTCEA3
IRQ5
21
H'042A
DTCEA2
IRQ6
22
H'042C
DTCEA1
IRQ7
Reserved
23
H'042E
DTCEA0
24
H'0430
DTCEB7
25
H'0432
DTCEB6
26
H'0434
DTCEB5
17
H'0436
DTCEB4
18
H'0438
DTCEB3
19
H'043A
DTCEB2
30
H'043C
DTCEB1
31
H'043E
DTCEB0
A/D
ADI
38
H'044C
DTCEC6
TPU_0
TGI0A
40
H'0450
DTCEC5
TGI0B
41
H'0452
DTCEC4
TGI0C
42
H'0454
DTCEC3
TGI0D
43
H'0456
DTCEC2
TGI1A
48
H'0460
DTCEC1
TGI1B
49
H'0462
DTCEC0
TPU_1
TPU_2
TGI2A
52
H'0468
DTCED7
TGI2B
53
H'046A
DTCED6
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Low
Section 7 Data Transfer Controller (DTC)
Origin of
Activation
Source
TPU_3
TPU_4
TPU_5
TMR_0
TMR_1
Activation
Source
SCI_1
SCI_2
Note:
*
DTC
Vector Address
DTCE*
Priority
High
TGI3A
56
H'0470
DTCED5
TGI3B
57
H'0472
DTCED4
TGI3C
58
H'0474
DTCED3
TGI3D
59
H'0476
DTCED2
TGI4A
64
H'0480
DTCED1
TGI4B
65
H'0482
DTCED0
TGI5A
68
H'0488
DTCEE7
TGI5B
69
H'048A
DTCEE6
CMIA0
72
H'0490
DTCEE3
CMIB0
73
H'0492
DTCEE2
CMIA1
76
H'0498
DTCEE1
CMIB1
77
H'049A
DTCEE0
80
H'04A0
DTCEF7
81
H'04A2
DTCEF6
82
H'04A4
DTCEF5
83
H'04A6
DTCEF4
RXI0
89
H'04B2
DTCEF3
TXI0
90
H'04B4
DTCEF2
RXI1
93
H'04BA
DTCEF1
TXI1
94
H'04BC
DTCEF0
RXI2
97
H'04C2
DTCEG7
TXI2
98
H'04C4
DTCEG6
Reserved
SCI_0
Vector
Number
Low
DTCE bits with no corresponding interrupt are reserved, and should be written with 0.
When clearing the software standby state or all-module-clocks-stop mode with an
interrupt, write 0 to the corresponding DTCE bit.
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Section 7 Data Transfer Controller (DTC)
7.5
Operation
The DTC stores register information in the on-chip RAM. When activated, the DTC reads register
information that is already stored in the on-chip RAM and transfers data on the basis of that
register information. After the data transfer, it writes updated register information back to the onchip RAM. Pre-storage of register information in the on-chip RAM makes it possible to transfer
data over any required number of channels. There are three transfer modes: normal mode, repeat
mode, and block transfer mode. Setting the CHNE bit to 1 makes it possible to perform a number
of transfers with a single activation (chain transfer). A setting can also be made to have chain
transfer performed only when the transfer counter value is 0. This enables DTC re-setting to be
performed by the DTC itself.
The 24-bit SAR designates the DTC transfer source address and the 24-bit DAR designates the
transfer destination address. After each transfer, SAR and DAR are independently incremented,
decremented, or left fixed.
Figure 7.4 shows a flowchart of DTC operation, and table 7.2 summarizes the chain transfer
conditions (combinations for performing the second and third transfers are omitted).
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Section 7 Data Transfer Controller (DTC)
Start
Read DTC vector
Next transfer
Read register information
Data transfer
Write register information
CHNE = 1?
Yes
No
CHNS = 0?
Yes
Transfer counter = 0
or DISEL = 1?
No
No
Yes
Transfer
counter = 0?
Yes
No
DISEL = 1?
Yes
No
Clear activation flag
Clear DTCER
End
Interrupt exception
handling
Figure 7.4 Flowchart of DTC Operation
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Section 7 Data Transfer Controller (DTC)
Table 7.2
Chain Transfer Conditions
1st Transfer
2nd Transfer
CHNE
CHNS
DISEL
CR
CHNE
CHNS
DISEL
CR
DTC Transfer
0
—
0
Not 0
—
—
—
—
Ends at 1st transfer
0
—
0
0
—
—
—
—
Ends at 1st transfer
0
—
1
—
—
—
—
—
Interrupt request to CPU
1
0
—
—
0
—
0
Not 0
Ends at 2nd transfer
0
—
0
0
Ends at 2nd transfer
0
—
1
—
Interrupt request to CPU
1
1
0
Not 0
—
—
—
—
Ends at 1st transfer
1
1
—
0
0
—
0
Not 0
Ends at 2nd transfer
0
—
0
0
Ends at 2nd transfer
0
—
1
—
Interrupt request to CPU
—
—
—
—
Ends at 1st transfer
1
1
1
Not 0
Interrupt request to CPU
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Section 7 Data Transfer Controller (DTC)
7.5.1
Normal Mode
In normal mode, one operation transfers one byte or one word of data. Table 7.3 lists the register
function in normal mode. From 1 to 65,536 transfers can be specified. Once the specified number
of transfers has ended, a CPU interrupt can be requested.
Table 7.3
Register Function in Normal Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register A
CRA
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
DAR
Transfer
Figure 7.5 Memory Mapping in Normal Mode
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Section 7 Data Transfer Controller (DTC)
7.5.2
Repeat Mode
In repeat mode, one operation transfers one byte or one word of data. Table 7.4 lists the register
function in repeat mode. From 1 to 256 transfers can be specified. Once the specified number of
transfers has ended, the initial state of the transfer counter and the address register specified as the
repeat area is restored, and transfer is repeated. In repeat mode the transfer counter value does not
reach H'00, and therefore CPU interrupts cannot be requested when DISEL = 0.
Table 7.4
Register Function in Repeat Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds number of transfers
DTC transfer count register AL
CRAL
Designates transfer count
DTC transfer count register B
CRB
Not used
SAR
or
DAR
Repeat area
Transfer
Figure 7.6 Memory Mapping in Repeat Mode
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DAR
or
SAR
Section 7 Data Transfer Controller (DTC)
7.5.3
Block Transfer Mode
In block transfer mode, one operation transfers one block of data. Either the transfer source or the
transfer destination is designated as a block area. Table 7.5 lists the register function in block
transfer mode.
The block size is 1 to 256. When the transfer of one block ends, the initial state of the block size
counter and the address register specified as the block area is restored. The other address register
is then incremented, decremented, or left fixed. From 1 to 65,536 transfers can be specified. Once
the specified number of transfers has ended, a CPU interrupt is requested.
Table 7.5
Register Function in Block Transfer Mode
Name
Abbreviation
Function
DTC source address register
SAR
Designates source address
DTC destination address register
DAR
Designates destination address
DTC transfer count register AH
CRAH
Holds block size
DTC transfer count register AL
CRAL
Designates block size count
DTC transfer count register B
CRB
Designates transfer count
First block
SAR
or
DAR
Block area
Transfer
DAR
or
SAR
Nth block
Figure 7.7 Memory Mapping in Block Transfer Mode
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Section 7 Data Transfer Controller (DTC)
7.5.4
Chain Transfer
Setting the CHNE bit to 1 enables a number of data transfers to be performed consecutively in
response to a single transfer request. SAR, DAR, CRA, CRB, MRA, and MRB, which define data
transfers, can be set independently.
Figure 7.8 shows the operation of chain transfer. When activated, the DTC reads the register
information start address stored at the vector address, and then reads the first register information
at that start address. The CHNE bit in MRB is checked after the end of data transfer, if the value is
1, the next register information, which is located consecutively, is read and transfer is performed.
This operation is repeated until the end of data transfer of register information with CHNE = 0. It
is also possible, by setting both the CHNE bit and CHNS bit to 1, to specify execution of chain
transfer only when the transfer counter value is 0.
In the case of transfer with CHNE set to 1, an interrupt request to the CPU is not generated at the
end of the specified number of transfers or by setting of the DISEL bit to 1, and the interrupt
source flag for the activation source is not affected.
Source
Destination
Register information
CHNE=1
DTC vector
address
Register information
start address
Register information
CHNE=0
Source
Destination
Figure 7.8 Operation of Chain Transfer
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Section 7 Data Transfer Controller (DTC)
7.5.5
Interrupt Sources
An interrupt request is issued to the CPU when the DTC finishes the specified number of data
transfers, or a data transfer for which the DISEL bit was set to 1. In the case of interrupt activation,
the interrupt set as the activation source is generated. These interrupts to the CPU are subject to
CPU mask level and interrupt controller priority level control.
In the case of activation by software, a software activated data transfer end interrupt (SWDTEND)
is generated.
When the DISEL bit is 1 and one data transfer has ended, or the specified number of transfers has
ended, after data transfer ends, the SWDTE bit is held at 1 and an SWDTEND interrupt is
generated. The interrupt handling routine should clear the SWDTE bit to 0.
When the DTC is activated by software, an SWDTEND interrupt is not generated during a data
transfer wait or during data transfer even if the SWDTE bit is set to 1.
7.5.6
Operation Timing
φ
DTC activation
request
DTC
request
Vector read
Data transfer
Address
Read Write
Transfer
information read
Transfer
information write
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)
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Section 7 Data Transfer Controller (DTC)
φ
DTC activation
request
DTC
request
Data transfer
Vector read
Read Write Read Write
Address
Transfer
information read
Transfer
information write
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2)
φ
DTC activation
request
DTC
request
Data transfer
Data transfer
Read Write
Read Write
Vector read
Address
Transfer
information read
Transfer
information
write
Transfer
information
read
Transfer
information write
Figure 7.11 DTC Operation Timing (Example of Chain Transfer)
7.5.7
Number of DTC Execution States
Table 7.6 lists execution status for a single DTC data transfer, and table 7.7 shows the number of
states required for each execution status.
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Section 7 Data Transfer Controller (DTC)
Table 7.6
DTC Execution Status
Mode
Vector Read
I
Register Information
Read/Write
Data Read
J
K
Data Write
L
Internal
Operations
M
Normal
1
6
1
1
3
Repeat
1
6
1
1
3
Block transfer
1
6
N
N
3
Legend:
N: Block size (initial setting of CRAH and CRAL)
Table 7.7
Number of States Required for Each Execution Status
OnChip
RAM
OnChip
ROM
Bus width
32
16
8
16
Access states
1
1
2
2
2
3
2
3
SI
—
1
—
—
4
6+2m
2
3+m
Register information
read/write
SJ
1
—
—
—
—
—
—
—
Byte data read
SK
1
1
2
2
2
3+m
2
3+m
Word data read
SK
1
1
4
2
4
6+2m
2
3+m
Byte data write
SL
1
1
2
2
2
3+m
2
3+m
Word data write
SL
1
1
4
2
4
6+2m
2
3+m
Object to be Accessed
Execution
status
Vector read
Internal operation SM
On-Chip I/O
Registers
External Devices
8
16
1
The number of execution states is calculated from the formula below. Note that Σ means the sum
of all transfers activated by one activation event (the number in which the CHNE bit is set to 1,
plus 1).
Number of execution states = I · SI + Σ (J · SJ + K · SK + L · SL) + M · SM
For example, when the DTC vector address table is located in on-chip ROM, normal mode is set,
and data is transferred from the on-chip ROM to an internal I/O register, the time required for the
DTC operation is 13 states. The time from activation to the end of the data write is 10 states.
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Section 7 Data Transfer Controller (DTC)
7.6
Procedures for Using DTC
7.6.1
Activation by Interrupt
The procedure for using the DTC with interrupt activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the enable bits for the interrupt sources to be used as the activation sources to 1. The DTC
is activated when an interrupt used as an activation source is generated.
5. After the end of one data transfer, or after the specified number of data transfers have ended,
the DTCE bit is cleared to 0 and a CPU interrupt is requested. If the DTC is to continue
transferring data, set the DTCE bit to 1.
7.6.2
Activation by Software
The procedure for using the DTC with software activation is as follows:
1. Set the MRA, MRB, SAR, DAR, CRA, and CRB register information in the on-chip RAM.
2. Set the start address of the register information in the DTC vector address.
3. Check that the SWDTE bit is 0.
4. Write 1 to SWDTE bit and the vector number to DTVECR.
5. Check the vector number written to DTVECR.
6. After the end of one data transfer, if the DISEL bit is 0 and a CPU interrupt is not requested,
the SWDTE bit is cleared to 0. If the DTC is to continue transferring data, set the SWDTE bit
to 1. When the DISEL bit is 1, or after the specified number of data transfers have ended, the
SWDTE bit is held at 1 and a CPU interrupt is requested.
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Section 7 Data Transfer Controller (DTC)
7.7
Examples of Use of the DTC
7.7.1
Normal Mode
An example is shown in which the DTC is used to receive 128 bytes of data via the SCI.
1. Set MRA to fixed source address (SM1 = SM0 = 0), incrementing destination address (DM1 =
1, DM0 = 0), normal mode (MD1 = MD0 = 0), and byte size (Sz = 0). The DTS bit can have
any value. Set MRB for one data transfer by one interrupt (CHNE = 0, DISEL = 0). Set the
SCI RDR address in SAR, the start address of the RAM area where the data will be received in
DAR, and 128 (H'0080) in CRA. CRB can be set to any value.
2. Set the start address of the register information at the DTC vector address.
3. Set the corresponding bit in DTCER to 1.
4. Set the SCI to the appropriate receive mode. Set the RIE bit in SCR to 1 to enable the reception
complete (RXI) interrupt. Since the generation of a receive error during the SCI reception
operation will disable subsequent reception, the CPU should be enabled to accept receive error
interrupts.
5. Each time reception of one byte of data ends on the SCI, the RDRF flag in SSR is set to 1, an
RXI interrupt is generated, and the DTC is activated. The receive data is transferred from RDR
to RAM by the DTC. DAR is incremented and CRA is decremented. The RDRF flag is
automatically cleared to 0.
6. When CRA becomes 0 after the 128 data transfers have ended, the RDRF flag is held at 1, the
DTCE bit is cleared to 0, and an RXI interrupt request is sent to the CPU. The interrupt
handling routine should perform wrap-up processing.
7.7.2
Chain Transfer
An example of DTC chain transfer is shown in which pulse output is performed using the PPG.
Chain transfer can be used to perform pulse output data transfer and PPG output trigger cycle
updating. Repeat mode transfer to the PPG’s NDR is performed in the first half of the chain
transfer, and normal mode transfer to the TPU’s TGR in the second half. This is because clearing
of the activation source and interrupt generation at the end of the specified number of transfers are
restricted to the second half of the chain transfer (transfer when CHNE = 0).
1. Perform settings for transfer to the PPG’s NDR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), repeat mode (MD1 = 0,
MD0 = 1), and word size (Sz = 1). Set the source side as a repeat area (DTS = 1). Set MRB to
chain mode (CHNE = 1, DISEL = 0). Set the data table start address in SAR, the NDRH
address in DAR, and the data table size in CRAH and CRAL. CRB can be set to any value.
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Section 7 Data Transfer Controller (DTC)
2. Perform settings for transfer to the TPU’s TGR. Set MRA to source address incrementing
(SM1 = 1, SM0 = 0), fixed destination address (DM1 = DM0 = 0), normal mode (MD1 = MD0
= 0), and word size (Sz = 1). Set the data table start address in SAR, the TGRA address in
DAR, and the data table size in CRA. CRB can be set to any value.
3. Locate the TPU transfer register information consecutively after the NDR transfer register
information.
4. Set the start address of the NDR transfer register information to the DTC vector address.
5. Set the bit corresponding to TGIA in DTCER to 1.
6. Set TGRA as an output compare register (output disabled) with TIOR, and enable the TGIA
interrupt with TIER.
7. Set the initial output value in PODR, and the next output value in NDR. Set bits in DDR and
NDER for which output is to be performed to 1. Using PCR, select the TPU compare match to
be used as the output trigger.
8. Set the CST bit in TSTR to 1, and start the TCNT count operation.
9. Each time a TGRA compare match occurs, the next output value is transferred to NDR and the
set value of the next output trigger period is transferred to TGRA. The activation source TGFA
flag is cleared.
10. When the specified number of transfers are completed (the TPU transfer CRA value is 0), the
TGFA flag is held at 1, the DTCE bit is cleared to 0, and a TGIA interrupt request is sent to the
CPU. Termination processing should be performed in the interrupt handling routine.
7.7.3
Chain Transfer when Counter = 0
By executing a second data transfer, and performing re-setting of the first data transfer, only when
the counter value is 0, it is possible to perform 256 or more repeat transfers.
An example is shown in which a 128-kbyte input buffer is configured. The input buffer is assumed
to have been set to start at lower address H'0000. Figure 7.12 shows the chain transfer when the
counter value is 0.
1. For the first transfer, set the normal mode for input data. Set fixed transfer source address
(G/A, etc.), CRA = H'0000 (65,536 times), and CHNE = 1, CHNS = 1, and DISEL = 0.
2. Prepare the upper 8-bit addresses of the start addresses for each of the 65,536 transfer start
addresses for the first data transfer in a separate area (in ROM, etc.). For example, if the input
buffer comprises H'200000 to H'21FFFF, prepare H'21 and H'20.
3. For the second transfer, set repeat mode (with the source side as the repeat area) for re-setting
the transfer destination address for the first data transfer. Use the upper 8 bits of DAR in the
first register information area as the transfer destination. Set CHNE = DISEL = 0. If the above
input buffer is specified as H'200000 to H'21FFFF, set the transfer counter to 2.
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Section 7 Data Transfer Controller (DTC)
4. Execute the first data transfer 65,536 times by means of interrupts. When the transfer counter
for the first data transfer reaches 0, the second data transfer is started. Set the upper 8 bits of
the transfer source address for the first data transfer to H'21. The lower 16 bits of the transfer
destination address of the first data transfer and the transfer counter are H'0000.
5. Next, execute the first data transfer the 65,536 times specified for the first data transfer by
means of interrupts. When the transfer counter for the first data transfer reaches 0, the second
data transfer is started. Set the upper 8 bits of the transfer source address for the first data
transfer to H'20. The lower 16 bits of the transfer destination address of the first data transfer
and the transfer counter are H'0000.
6. Steps 4 and 5 are repeated endlessly. As repeat mode is specified for the second data transfer,
an interrupt request is not sent to the CPU.
Input circuit
Input buffer
First data
transfer register
information
Chain transfer
(counter = 0)
Second data
transfer register
information
Upper 8 bits
of DAR
Figure 7.12 Chain Transfer when Counter = 0
Rev. 3.00 Feb 22, 2006 page 169 of 624
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Section 7 Data Transfer Controller (DTC)
7.7.4
Software Activation
An example is shown in which the DTC is used to transfer a block of 128 bytes of data by means
of software activation. The transfer source address is H'1000 and the destination address is
H'2000. The vector number is H'60, so the vector address is H'04C0.
1. Set MRA to incrementing source address (SM1 = 1, SM0 = 0), incrementing destination
address (DM1 = 1, DM0 = 0), block transfer mode (MD1 = 1, MD0 = 0), and byte size (Sz =
0). The DTS bit can have any value. Set MRB for one block transfer by one interrupt (CHNE =
0). Set the transfer source address (H'1000) in SAR, the destination address (H'2000) in DAR,
and 128 (H'8080) in CRA. Set 1 (H'0001) in CRB.
2. Set the start address of the register information at the DTC vector address (H'04C0).
3. Check that the SWDTE bit in DTVECR is 0. Check that there is currently no transfer activated
by software.
4. Write 1 to the SWDTE bit and the vector number (H'60) to DTVECR. The write data is H'E0.
5. Read DTVECR again and check that it is set to the vector number (H'60). If it is not, this
indicates that the write failed. This is presumably because an interrupt occurred between steps
3 and 4 and led to a different software activation. To activate this transfer, go back to step 3.
6. If the write was successful, the DTC is activated and a block of 128 bytes of data is transferred.
7. After the transfer, an SWDTEND interrupt occurs. The interrupt handling routine should clear
the SWDTE bit to 0 and perform other wrap-up processing.
Rev. 3.00 Feb 22, 2006 page 170 of 624
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Section 7 Data Transfer Controller (DTC)
7.8
Usage Notes
7.8.1
Module Stop Mode Setting
DTC operation can be disabled or enabled using the module stop control register. The initial
setting is for DTC operation to be enabled. Register access is disabled by setting module stop
mode. Module stop mode cannot be set while the DTC is activated. For details, refer to section 19,
Power-Down Modes.
7.8.2
On-Chip RAM
The MRA, MRB, SAR, DAR, CRA, and CRB registers are all located in on-chip RAM. When the
DTC is used, the RAME bit in SYSCR must not be cleared to 0.
7.8.3
DTCE Bit Setting
For DTCE bit setting, use bit manipulation instructions such as BSET and BCLR. If all interrupts
are disabled, multiple activation sources can be set at one time (only at the initial setting) by
writing data after executing a dummy read on the relevant register.
• Chain Transfer
When chain transfer is used, clearing of the activation source or DTCER is performed when
the last of the chain of data transfers is executed. SCI and high-speed A/D converter
interrupt/activation sources, on the other hand, are cleared when the DTC reads or writes to the
prescribed register.
Therefore, when the DTC is activated by an interrupt or activation source, if a read/write of the
relevant register is not included in the last chained data transfer, the interrupt or activation
source will be retained.
Rev. 3.00 Feb 22, 2006 page 171 of 624
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Section 7 Data Transfer Controller (DTC)
Rev. 3.00 Feb 22, 2006 page 172 of 624
REJ09B0281-0300
Section 8 I/O Ports
Section 8 I/O Ports
Table 8.1 summarizes the port functions. The pins of each port also have other functions such as
input/output or external interrupt input pins of on-chip peripheral modules. Each I/O port includes
a data direction register (DDR) that controls input/output, a data register (DR) that stores output
data, and a port register (PORT) used to read the pin states. The input-only ports do not have a DR
or DDR register.
Ports A to E have a built-in pull-up MOS function and an input pull-up MOS control register
(PCR) to control the on/off state of input pull-up MOS.
Ports 3 and A include an open-drain control register (ODR) that controls the on/off state of the
output buffer PMOS.
Ports 1 to 3, 5 (P50 to P53), and 6 to 8 can drive a single TTL load and 30 pF capacitive load.
Ports A to H can drive a single TTL load and 50 pF capacitive load.
All of the I/O ports can drive a Darlington transistor when outputting data.
Ports 1 and 2 are Schmitt-triggered inputs. Ports 5,6, F (PF1, PF2), and H (PH2, PH3) are Schmitttriggered inputs when used as the IRQ input.
Rev. 3.00 Feb 22, 2006 page 173 of 624
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Section 8 I/O Ports
Table 8.1
Port
Port Functions
Description
Port General I/O port
1 also functioning
as PPG outputs,
and TPU I/Os
Modes
1 and 5
Modes
2 and 6
Mode 7
Mode 4
P17/PO15/TIOCB2/TCLKD
P16/PO14/TIOCA2
EXPE = 1
EXPE = 0
Input/
Output
Type
Schmitttriggered
input
P15/PO13/TIOCB1/TCLKC
P14/PO12/TIOCA1
P13/PO11/TIOCD0/TCLKB
P12/PO10/TIOCC0/TCLKA
P11/PO9/TIOCB0
P10/PO8/TIOCA0
Port General I/O port
2 also functioning
as PPG outputs,
TPU I/Os, and
interrupt inputs
P27/PO7/TIOCB5
P26/PO6/TIOCA5
Schmitttriggered
input
P25/PO5/TIOCB4
P24/PO4/TIOCA4
P23/PO3/TIOCD3
P22/PO2/TIOCC3
P21/PO1/TIOCB3
P20/PO0/TIOCA3
Port General I/O port
3 also functioning
as SCI I/Os
P35/SCK1
P34/SCK0
P33/RxD1
P32/RxD0/IrRxD
P31/TxD1
P30/TxD0/IrTxD
Port General I/O port
4 also functioning
as A/D converter
analog inputs and
D/A converter
analog outputs
P47/AN7/DA1
P46/AN6/DA0
P45/AN5
P44/AN4
P43/AN3
P42/AN2
P41/AN1
P40/AN0
Rev. 3.00 Feb 22, 2006 page 174 of 624
REJ09B0281-0300
Opendrain
output
enable
Section 8 I/O Ports
Port
Description
Port General I/O port
5 also functioning
as interrupt inputs,
A/D converter
analog inputs, and
D/A converter
analog outputs
General I/O port
also functioning
as interrupt inputs,
A/D converter
analog inputs, and
SCI I/Os
Modes
1 and 5
Modes
2 and 6
Mode 7
Mode 4
EXPE = 1
EXPE = 0
P57/AN15/DA3/IRQ7
Input/
Output
Type
Schmitttriggered
input
when
used as
IRQ input
P56/AN14/DA2/IRQ6
P55/AN13/IRQ5
P54/AN12/IRQ4
P53/ADTRG/IRQ3
Schmitttriggered
input
when
used as
IRQ input
P52/SCK2/IRQ2
P51/RxD2/IRQ1
P50/TxD2/IRQ0
Port General I/O port
P65/TMO1
6 also functioning
P64/TMO0
as interrupt inputs,
P63/TMCI1
and TMR I/Os
P62/TMCI0
P61/TMRI1
P60/TMRI0
Port General I/O port
7
P75
P75
P75
P74
P74
P74
P73
P73
P73
P72
P72
P72
P71
P71
P71
P70
P70
P70
Port General I/O port
P85/IRQ5
8 as interrupt inputs P84/IRQ4
P85/IRQ5
P85/IRQ5
P84/IRQ4
P84/IRQ4
P83/IRQ3
P83/IRQ3
P83/IRQ3
P82/IRQ2
P82/IRQ2
P82/IRQ2
P81/IRQ1
P81/IRQ1
P81/IRQ1
P80/IRQ0
P80/IRQ0
P80/IRQ0
Schmitttriggered
input
when
used as
IRQ input
Rev. 3.00 Feb 22, 2006 page 175 of 624
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Section 8 I/O Ports
Port
Description
Port General I/O port
A also functioning
as address
outputs
Port General I/O port
B also functioning
as address
outputs
Port General I/O port
C also functioning
as address
outputs
Port General I/O port
D also functioning
as data I/Os
Modes
1 and 5
Modes
2 and 6
Mode 7
Mode 4
EXPE = 1
EXPE = 0
PA7/A23
PA7/A23 PA7/A23
PA7
PA6/A22
PA6/A22 PA6/A22
PA6
PA5/A21
PA5/A21 PA5/A21
PA5
A20
PA4/A20 PA4/A20
PA4
A19
PA3/A19 PA3/A19
PA3
A18
PA2/A18 PA2/A18
PA2
A17
PA1/A17 PA1/A17
PA1
A16
PA0/A16 PA0/A16
PA0
A15
PB7/A15 PB7/A15
PB7
A14
PB6/A14 PB6/A14
PB6
A13
PB5/A13 PB5/A13
PB5
A12
PB4/A12 PB4/A12
PB4
A11
PB3/A11 PB3/A11
PB3
A10
PB2/A10 PB2/A10
PB2
A9
PB1/A9
PB1/A9
PB1
A8
PB0/A8
PB0/A8
PB0
A7
PC7/A7
PC7/A7
PC7
A6
PC6/A6
PC6/A6
PC6
A5
PC5/A5
PC5/A5
PC5
A4
PC4/A4
PC4/A4
PC4
A3
PC3/A3
PC3/A3
PC3
A2
PC2/A2
PC2/A2
PC2
A1
PC1/A1
PC1/A1
PC1
A0
PC0/A0
PC0/A0
PC0
D15
D15
PD7
D14
D14
PD6
D13
D13
PD5
D12
D12
PD4
D11
D11
PD3
D10
D10
PD2
D9
D9
PD1
D8
D8
PD0
Rev. 3.00 Feb 22, 2006 page 176 of 624
REJ09B0281-0300
Input/
Output
Type
Built-in
input pullup MOS
Opendrain
output
enable
Built-in
input pullup MOS
Built-in
input pullup MOS
Built-in
input pullup MOS
Section 8 I/O Ports
Port
Description
Port General I/O port
E also functioning
as data I/Os
Port General I/O port
F also functioning
as interrupt inputs
and bus control
I/Os
Port General I/O port
G also functioning
as bus control
I/Os
Port General I/O port
H also functioning
as interrupt inputs
and bus control
I/Os
Modes
1 and 5
Modes
2 and 6
Mode 7
Mode 4
EXPE = 1
EXPE = 0
D7
PE7/D7
PE7/D7
PE7/D7
PE7
D6
PE6/D6
PE6/D6
PE6/D6
PE6
D5
PE5/D5
PE5/D5
PE5/D5
PE5
D4
PE4/D4
PE4/D4
PE4/D4
PE4
D3
PE3/D3
PE3/D3
PE3/D3
PE3
D2
PE2/D2
PE2/D2
PE2/D2
PE2
D1
PE1/D1
PE1/D1
PE1/D1
PE1
D0
PE0/D0
PE0/D0
PE0/D0
PE0
PF7/φ
PF7/φ
PF7/φ
PF6/AS
PF6/AS
PF6
RD
RD
PF5
HWR
HWR
PF4
PF3/LWR
PF3/LWR
PF3
PF2
PF2
PF2
PF1
PF1
PF1
PF0/WAIT
PF0/WAIT
PF0
PG6
PG6
PG6
PG5
PG5
PG5
PG4
PG4
PG4
PG3/CS3
PG3/CS3
PG3
PG2/CS2
PG2/CS2
PG2
PG1/CS1
PG1/CS1
PG1
PG0/CS0
PG0/CS0
PG0
PH3/CS7/(IRQ7)
PH3/CS7/(IRQ7)
PH3/(IRQ7)
PH2/CS6/(IRQ6)
PH2/CS6/(IRQ6)
PH2/(IRQ6)
PH1/CS5
PH1/CS5
PH1
PH0/CS4
PH0/CS4
PH0
Input/
Output
Type
Built-in
input pullup MOS
Schmitttriggered
input
when
used as
IRQ input
Rev. 3.00 Feb 22, 2006 page 177 of 624
REJ09B0281-0300
Section 8 I/O Ports
8.1
Port 1
Port 1 is an 8-bit I/O port that also has other functions. The port 1 has the following registers.
• Port 1 data direction register (P1DDR)
• Port 1 data register (P1DR)
• Port 1 register (PORT1)
8.1.1
Port 1 Data Direction Register (P1DDR)
The individual bits of P1DDR specify input or output for the pins of port 1.
P1DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DDR
0
W
6
P16DDR
0
W
5
P15DDR
0
W
When a pin function is specified to a general purpose
I/O, setting this bit to 1 makes the corresponding port
1 pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
4
P14DDR
0
W
3
P13DDR
0
W
2
P12DDR
0
W
1
P11DDR
0
W
0
P10DDR
0
W
Rev. 3.00 Feb 22, 2006 page 178 of 624
REJ09B0281-0300
Section 8 I/O Ports
8.1.2
Port 1 Data Register (P1DR)
P1DR stores output data for the port 1 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P17DR
0
R/W
6
P16DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
P15DR
0
R/W
4
P14DR
0
R/W
3
P13DR
0
R/W
2
P12DR
0
R/W
1
P11DR
0
R/W
0
P10DR
0
R/W
8.1.3
Port 1 Register (PORT1)
PORT1 shows the pin states.
PORT1 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P17
Undefined*
R
6
P16
R
5
P15
Undefined*
Undefined*
If a port 1 read is performed while P1DDR bits are set
to 1, the P1DR values are read. If a port 1 read is
performed while P1DDR bits are cleared to 0, the pin
states are read.
Undefined*
Undefined*
R
R
R
4
P14
3
P13
2
P12
1
P11
Undefined*
Undefined*
0
P10
Undefined*
Note:
*
R
R
R
Determined by the states of pins P17 to P10.
Rev. 3.00 Feb 22, 2006 page 179 of 624
REJ09B0281-0300
Section 8 I/O Ports
8.1.4
Pin Functions
Port 1 pins also function as PPG outputs and TPU I/Os. The correspondence between the register
specification and the pin functions is shown below.
P17/PO15/TIOCB2/TCLKD: The pin function is switched as shown below according to the
combination of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0
in TIOR2, and bits CCLR1 and CCLR0 in TCR2), bits TPSC2 to TPSC0 in TCR0 and TCR5, bit
NDER15 in NDERH, and bit P17DDR.
TPU channel 2
settings
(1) in table below
(2) in table below
P17DDR
—
0
1
1
NDER15
—
—
0
1
TIOCB2 output
P17 input
P17 output
Pin function
PO15 output
TIOCB2 input*
TCLKD input*
1
2
Notes: 1. TIOCB2 input when MD3 to MD0 = B'0000, B000, and B'01xx and IOB3 = 1.
2. TCLKD input when the setting for either TCR0 or TCR5 is TPSC2 to TPSC0 = B'111.
TCLKD input when channels 2 and 4 are set to phase counting mode.
TPU channel 2
settings
MD3 to MD0
IOB3 to IOB0
(2)
(1)
B'0000, B'01xx
B'0000
B'0100
B'0001 to
B'0011
(2)
B'0010
B'xx00
—
B'0101 to
B'0111
CCLR1, CCLR0
—
—
—
Output function
—
Output
compare
output
—
Rev. 3.00 Feb 22, 2006 page 180 of 624
REJ09B0281-0300
(1)
(2)
B'0011
B'xx00
B'1xxx
x: Don’t care
(2)
Other than B'xx00
Other than
B'10
PWM mode PWM mode
1 output
2 output
B'10
—
Section 8 I/O Ports
P16/PO14/TIOCA2: The pin function is switched as shown below according to the combination
of the TPU channel 2 settings (by bits MD3 to MD0 in TMDR2, bits IOB3 to IOB0 in TIOR2, and
bits CCLR1 and CCLR0 in TCR2), bit NDER14 in NDERH, and bit P16DDR.
TPU channel 2
settings
(1) in table below
(2) in table below
P16DDR
—
0
1
1
NDER14
—
—
0
1
TIOCA2 output
P16 input
P16 output
PO14 output
Pin function
1
TIOCA2 input*
Note:
1. TIOCA2 input when MD3 to MD0 = B'0000, B'000, and B'01xx and IOB3 = 1.
TPU channel 2
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01xx
B'0000
B'0100
B'0001 to
B'0011
(2)
(1)
B'001x
B'0010
B'xx00
(1)
(2)
B'0011
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
x: Don’t care
Note: 2. TIOCB2 output disabled.
Rev. 3.00 Feb 22, 2006 page 181 of 624
REJ09B0281-0300
Section 8 I/O Ports
P15/PO13/TIOCB1/TCLKC: The pin function is switched as shown below according to the
combination of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR1, bits IOB3 to IOB0
in TIOR1, and bits CCLR1 and CCLR0 in TCR1), bits TPSC2 to TPSC0 in TCR0, TCR2, TCR4,
and TCR5, bit NDER13 in NDERH, and bit P15DDR.
TPU channel 1
settings
(1) in table below
(2) in table below
P15DDR
—
0
1
1
NDER13
—
—
0
1
TIOCB1 output
P15 input
P15 output
Pin function
PO13 output
TIOCB1 input*
TCLKC input*
1
2
Notes: 1. TIOCB1 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
2. TCLKC input when the setting for either TCR0 or TCR2 is TPSC2 to TPSC0 = B'110, or
when the setting for either TCR4 or TCR5 is TPSC2 to TPSC0 = B'101.
TCLKC input when phase counting mode is set for channels 2 and 4.
TPU channel 1
settings
MD3 to MD0
IOB3 to IOB0
(2)
(1)
B'0000, B'01xx
B'0000
B'0100
B'0001 to
B'0011
(2)
(2)
B'0010
(1)
(2)
B'0011
B'xx00
B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
x: Don’t care
Rev. 3.00 Feb 22, 2006 page 182 of 624
REJ09B0281-0300
Section 8 I/O Ports
P14/PO12/TIOCA1: The pin function is switched as shown below according to the combination
of the TPU channel 1 settings (by bits MD3 to MD0 in TMDR1, bits IOA3 to IOA0 in TIOR1,
and bits CCLR1 and CCLR0 in TCR1), bit NDER12 in NDERH, and bit P14DDR.
TPU channel 1
settings
(1) in table below
(2) in table below
P14DDR
—
0
1
1
NDER12
—
—
0
1
TIOCA1 output
P14 input
P14 output
PO12 output
Pin function
1
TIOCA1 input*
Note: 1. TIOCA1 input when MD3 to MD0 = B'0000, B'000, and B'01xx and IOA3 to IOA0 =
B'10xx.
TPU channel 1
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01xx
B'0000
B'0100
B'0001 to
B'0011
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other
than B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR1, CCLR0
—
—
—
—
Other than
B'01
B'01
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
x: Don’t care
Note: 2. TIOCB1 output disabled.
Rev. 3.00 Feb 22, 2006 page 183 of 624
REJ09B0281-0300
Section 8 I/O Ports
P13/PO11/TIOCD0/TCLKB: The pin function is switched as shown below according to the
combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOD3 to IOD0
in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR2, bit
NDER11 in NDERH, and bit P13DDR.
TPU channel 0
settings
(1) in table below
(2) in table below
P13DDR
—
0
1
1
NDER11
—
—
0
1
TIOCD0 output
P13 input
Pin function
P13 output
PO11 output
TIOCD0 input*
TCLKB input*
1
2
Notes: 1. TIOCD0 input when MD3 to MD0 = B'0000 and IOD3 = B'10xx.
2. TCLKB input when the setting for any of TCR0 to TCR2 is TPSC2 to TPSC0 = B'101.
TCLKB input when phase counting mode is set for channels 1 and 5.
TPU channel 0
settings
(2)
MD3 to MD0
IOD3 to IOD0
(1)
B'0000
B'0000
B'0100
(2)
(2)
B'0010
B'0001 to
B'0011
(1)
(2)
B'0011
—
B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR2, CCLR0
—
—
—
—
Other than
B'110
B'110
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
x: Don’t care
Rev. 3.00 Feb 22, 2006 page 184 of 624
REJ09B0281-0300
Section 8 I/O Ports
P12/PO10/TIOCC0/TCLKA: The pin function is switched as shown below according to the
combination of the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOC3 to IOC0
in TIOR0L, and bits CCLR2 to CCLR0 in TCR0), bits TPSC2 to TPSC0 in TCR0 to TCR5, bit
NDER10 in NDERH, and bit P12DDR.
TPU channel 0
settings
(1) in table below
(2) in table below
P12DDR
—
0
1
1
NDER10
—
—
0
1
TIOCC0 output
P12 input
P12 output
Pin function
TIOCC0 input*
TCLKA input*
PO10 output
1
2
Notes: 1. TIOCC0 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
2. TCLKA input when the setting for any of TCR0 to TCR5 is TPSC2 to TPSC0 = B'100.
TCLKA input when phase counting mode is set for channels 1 and 5.
TPU channel 0
settings
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other
than B'xx00
Other than B'xx00
B'0000
B'0100
B'1xxx
B'0001 to
B'0011
CCLR2, CCLR0
—
—
—
—
Other than
B'101
B'101
Output function
—
Output
compare
output
—
3
PWM*
mode 1
output
PWM mode
2 output
—
B'0101 to
B'0111
x: Don’t care
Note: 3. TIOCD0 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR0.
Rev. 3.00 Feb 22, 2006 page 185 of 624
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Section 8 I/O Ports
P11/PO9/TIOCB0: The pin function is switched as shown below according to the combination of
the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0 and bits IOB3 to IOB0 in TIOR0H),
bit NDER9 in NDERH, and bit P11DDR.
TPU channel 0
settings
(1) in table below
(2) in table below
P11DDR
—
0
1
1
NDER9
—
—
0
1
TIOCB0 output
P11 input
P11 output
PO9 output
Pin function
TIOCB0 input*
Note:
*
TIOCB0 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
TPU channel 0
settings
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000
(2)
(2)
B'0010
B'0000
B'0100
B'1xxx
B'0001 to
B'0011
CCLR2, CCLR0
—
Output function
—
(1)
(2)
B'0011
—
B'xx00
Other than B'xx00
—
—
—
Other than
B'010
B'010
Output
compare
output
—
—
PWM mode
2 output
—
B'0101 to
B'0111
x: Don’t care
Rev. 3.00 Feb 22, 2006 page 186 of 624
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Section 8 I/O Ports
P10/PO8/TIOCA0: The pin function is switched as shown below according to the combination of
the TPU channel 0 settings (by bits MD3 to MD0 in TMDR0, bits IOA3 to IOA0 in TIOR0H, and
bits CCLR2 to CCLR0 in TCR0), bit NDER8 in NDERH, and bit P10DDR.
TPU channel 0
settings
(1) in table
below
(2) in table below
P10DDR
—
0
1
1
NDER8
—
—
0
1
TIOCA0 output
P10 input
P10 output
PO8 output
Pin function
1
TIOCA0 input*
Note:
1. TIOCA0 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
TPU channel 0
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
B'0000
B'0100
B'0001 to
B'0011
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other
than B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR2, CCLR0
—
—
—
—
Other than
B'001
B'001
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
x: Don’t care
Note: 2. TIOCB0 output disabled.
Rev. 3.00 Feb 22, 2006 page 187 of 624
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Section 8 I/O Ports
8.2
Port 2
Port 2 is an 8-bit I/O port that also has other functions. The port 2 has the following registers.
• Port 2 data direction register (P2DDR)
• Port 2 data register (P2DR)
• Port 2 register (PORT2)
8.2.1
Port 2 Data Direction Register (P2DDR)
The individual bits of P2DDR specify input or output for the pins of port 2.
P2DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DDR
0
W
6
P26DDR
0
W
5
P25DDR
0
W
When a pin function is specified to a general purpose
I/O, setting this bit to 1 makes the corresponding port
1 pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
4
P24DDR
0
W
3
P23DDR
0
W
2
P22DDR
0
W
1
P21DDR
0
W
0
P20DDR
0
W
Rev. 3.00 Feb 22, 2006 page 188 of 624
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Section 8 I/O Ports
8.2.2
Port 2 Data Register (P2DR)
P2DR stores output data for the port 2 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
P27DR
0
R/W
6
P26DR
0
R/W
Output data for a pin is stored when the pin function is
specified to a general purpose I/O.
5
P25DR
0
R/W
4
P24DR
0
R/W
3
P23DR
0
R/W
2
P22DR
0
R/W
1
P21DR
0
R/W
0
P20DR
0
R/W
8.2.3
Port 2 Register (PORT2)
PORT2 shows the pin states.
PORT2 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P27
Undefined*
R
6
P26
R
5
P25
Undefined*
Undefined*
If a port 2 read is performed while P2DDR bits are set
to 1, the P2DR values are read. If a port 2 read is
performed while P2DDR bits are cleared to 0, the pin
states are read.
Undefined*
Undefined*
R
R
R
4
P24
3
P23
2
P22
1
P21
Undefined*
Undefined*
0
P20
Undefined*
Note:
*
R
R
R
Determined by the states of pins P27 to P20.
Rev. 3.00 Feb 22, 2006 page 189 of 624
REJ09B0281-0300
Section 8 I/O Ports
8.2.4
Pin Functions
Port 2 pins also function as PPG outputs and TPU I/Os. The correspondence between the register
specification and the pin functions is shown below.
P27/PO7/TIOCB5: The pin function is switched as shown below according to the combination of
the TPU channel 5 settings (by bits MD3 to MD0 in TMDR5, bits IOB3 to IOB0 in TIOR5, and
bits CCLR1 and CCLR0 in TCR5), bit NDER7 in NDERL, and bit P27DDR.
TPU channel 5
settings
(1) in table below
(2) in table below
P27DDR
—
0
1
1
NDER7
—
—
0
1
TIOCB5 output
P27 input
P27 output
PO7 output
Pin function
TIOCB5 input*
Note:
*
TIOCB5 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 = 1.
TPU channel 5
settings
MD3 to MD0
IOB3 to IOB0
(2)
(1)
B'0000, B'01xx
B'0000
B'0100
B'0001 to
B'0011
(2)
(2)
(1)
B'0010
B'0011
B'xx00
Other than B'xx00
(2)
B'1xxx
B'0101 to
B'0111
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
x: Don’t care
Rev. 3.00 Feb 22, 2006 page 190 of 624
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Section 8 I/O Ports
P26/PO6/TIOCA5: The pin function is switched as shown below according to the combination of
the TPU channel 5 settings (by bits MD3 to MD0 in TMDR5, bits IOA3 to IOA0 in TIOR5, and
bits CCLR1 and CCLR0 in TCR5), bit NDER6 in NDERL, and bit P26DDR.
TPU channel 5
settings
(1) in table below
(2) in table below
P26DDR
—
0
1
1
NDER6
—
—
0
1
TIOCA5 output
P26 input
P26 output
PO6 output
Pin function
1
TIOCA5 input*
Note:
1. TIOCA5 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 = 1.
TPU channel 5
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01xx
B'0000
B'0100
B'0001 to
B'0011
(2)
(2)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other than
B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR1, CCLR0
—
—
—
—
Other than
B'01
B'01
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
x: Don’t care
Note: 2. TIOCB5 output disabled.
Rev. 3.00 Feb 22, 2006 page 191 of 624
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Section 8 I/O Ports
P25/PO5/TIOCB4: The pin function is switched as shown below according to the combination of
the TPU channel 4 settings (by bits MD3 to MD0 in TMDR4, bits IOB3 to IOB0 in TIOR4, and
bits CCLR1 and CCLR0 in TCR4), bit NDER5 in NDERL, and bit P25DDR.
TPU channel 4
settings
(1) in table below
(2) in table below
P25DDR
—
0
1
1
NDER5
—
—
0
1
TIOCB4 output
P25 input
P25 output
PO5 output
Pin function
TIOCB4 input*
Note:
*
TIOCB4 input when MD3 to MD0 = B'0000 or B'01xx and IOB3 to IOB0 = B'10xx.
TPU channel 5
settings
MD3 to MD0
IOB3 to IOB0
(2)
(1)
B'0000, B'01xx
B'0000
B'0100
B'0001 to
B'0011
(2)
(2)
B'0010
(1)
(2)
B'0011
—
B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR1, CCLR0
—
—
—
—
Other than
B'10
B'10
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
x: Don’t care
Rev. 3.00 Feb 22, 2006 page 192 of 624
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Section 8 I/O Ports
P24/PO4/TIOCA4: The pin function is switched as shown below according to the combination of
the TPU channel 4 settings (by bits MD3 to MD0 in TMDR4 and bits IOA3 to IOA0 in TIOR4),
bit NDER4 in NDERL, and bit P24DDR.
TPU channel 4
settings
(1) in table
below
(2) in table below
P24DDR
—
0
1
1
NDER4
—
—
0
1
TIOCA4 output
P24 input
P24 output
PO4 output
Pin function
1
TIOCA4 input*
Note:
1. TIOCA4 input when MD3 to MD0 = B'0000 or B'01xx and IOA3 to IOA0 = B'10xx.
TPU channel 4
settings
MD3 to MD0
IOA3 to IOA0
(2)
(1)
B'0000, B'01xx
B'0000
B'0100
B'0001 to
B'0011
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other
than B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR1, CCLR0
—
—
—
—
Other than
B'01
B'01
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
x: Don’t care
Note: 2. TIOCB4 output disabled.
Rev. 3.00 Feb 22, 2006 page 193 of 624
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Section 8 I/O Ports
P23/PO3/TIOCD3: The pin function is switched as shown below according to the combination of
the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOD3 to IOD0 in TIOR3L, and
bits CCLR2 to CCLR0 in TCR3), bit NDER3 in NDERL, and bit P23DDR.
TPU channel 3
settings
(1) in table below
(2) in table below
P23DDR
—
0
1
1
NDER3
—
—
0
1
TIOCD3 output
P23 input
P23 output
PO3 output
Pin function
TIOCD3 input*
Note:
*
TIOCD3 input when MD3 to MD0 = B'0000 and IOD3 to IOD0 = B'10xx.
TPU channel 3
settings
(2)
MD3 to MD0
IOD3 to IOD0
(1)
B'0000
B'0000
B'0100
(2)
(2)
B'0010
B'0001 to
B'0011
(1)
(2)
B'0011
—
B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR2 to
CCLR0
—
—
—
—
Other than
B'110
B'110
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
x: Don’t care
Rev. 3.00 Feb 22, 2006 page 194 of 624
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Section 8 I/O Ports
P22/PO2/TIOCC3: The pin function is switched as shown below according to the combination of
the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOC3 to IOC0 in TIOR3L, and
bits CCLR2 to CCLR0 in TCR3), bit NDER2 in NDERL, and bit P22DDR.
TPU channel 3
settings
(1) in table
below
(2) in table below
P22DDR
—
0
1
1
NDER2
—
—
0
1
TIOCC3 output
P22 input
P22 output
PO2 output
Pin function
1
TIOCC3 input*
Note:
1. TIOCC3 input when MD3 to MD0 = B'0000 and IOC3 to IOC0 = B'10xx.
TPU channel 3
settings
(2)
MD3 to MD0
IOC3 to IOC0
(1)
B'0000
B'0000
B'0100
B'0001 to
B'0011
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other
than B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR2 to
CCLR0
—
—
—
—
Other than
B'101
B'101
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
x: Don’t care
Note: 2. TIOCD3 output disabled.
Output disabled and settings (2) effective when BFA = 1 or BFB = 1 in TMDR3.
Rev. 3.00 Feb 22, 2006 page 195 of 624
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Section 8 I/O Ports
P21/PO1/TIOCB3: The pin function is switched as shown below according to the combination of
the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOB3 to IOB0 in TIOR3H, and
bits CCLR2 to CCLR0 in TCR3), bit NDER1 in NDERL, and bit P21DDR.
TPU channel 3
settings
(1) in table below
(2) in table below
P21DDR
—
0
1
1
NDER1
—
—
0
1
TIOCB3 output
P21 input
P21 output
PO1 output
Pin function
TIOCB3 input*
Note:
*
TIOCB3 input when MD3 to MD0 = B'0000 and IOB3 to IOB0 = B'10xx.
TPU channel 3
settings
(2)
MD3 to MD0
IOB3 to IOB0
(1)
B'0000
B'0000
B'0100
(2)
(2)
B'0010
B'0001 to
B'0011
(1)
(2)
B'0011
—
B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR2 to
CCLR0
—
—
—
—
Other than
B'010
B'010
Output function
—
Output
compare
output
—
—
PWM mode
2 output
—
x: Don’t care
Rev. 3.00 Feb 22, 2006 page 196 of 624
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Section 8 I/O Ports
P20/PO0/TIOCA3: The pin function is switched as shown below according to the combination of
the TPU channel 3 settings (by bits MD3 to MD0 in TMDR3, bits IOA3 to IOA0 in TIOR3H, and
bits CCLR2 to CCLR0 in TCR3), bit NDER0 in NDERL, and bit P20DDR.
TPU channel 3
settings
(1) in table
below
(2) in table below
P20DDR
—
0
1
1
NDER0
—
—
0
1
TIOCA3 output
P20 input
P20 output
PO0 output
Pin function
1
TIOCA3 input*
Note:
1. TIOCA3 input when MD3 to MD0 = B'0000 and IOA3 to IOA0 = B'10xx.
TPU channel 3
settings
(2)
MD3 to MD0
IOA3 to IOA0
(1)
B'0000
B'0000
B'0100
B'0001 to
B'0011
(2)
(1)
(1)
(2)
B'001x
B'0010
B'0011
B'xx00
Other
than B'xx00
Other than B'xx00
B'1xxx
B'0101 to
B'0111
CCLR2 to
CCLR0
—
—
—
—
Other than
B'001
B'001
Output function
—
Output
compare
output
—
2
PWM*
mode 1
output
PWM mode
2 output
—
x: Don’t care
Note: 2. TIOCB3 output disabled.
Rev. 3.00 Feb 22, 2006 page 197 of 624
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Section 8 I/O Ports
8.3
Port 3
Port 3 is a 6-bit I/O port that also has other functions. The port 3 has the following registers.
• Port 3 data direction register (P3DDR)
• Port 3 data register (P3DR)
• Port 3 register (PORT3)
• Port 3 open drain control register (P3ODR)
• Port function control register 2 (PFCR2)
8.3.1
Port 3 Data Direction Register (P3DDR)
The individual bits of P3DDR specify input or output for the pins of port 3.
P3DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0.
5
P35DDR
0
W
4
P34DDR
0
W
3
P33DDR
0
W
When a pin function is specified to a general purpose
I/O, setting this bit to 1 makes the corresponding port
1 pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
2
P32DDR
0
W
1
P31DDR
0
W
0
P30DDR
0
W
Rev. 3.00 Feb 22, 2006 page 198 of 624
REJ09B0281-0300
Section 8 I/O Ports
8.3.2
Port 3 Data Register (P3DR)
P3DR stores output data for the port 3 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P35DR
0
R/W
4
P34DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
3
P33DR
0
R/W
2
P32DR
0
R/W
1
P31DR
0
R/W
0
P30DR
0
R/W
8.3.3
Port 3 Register (PORT3)
PORT3 shows the pin states.
PORT3 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
When these bits are read, undefined value is
returned.
5
P35
R
4
P34
Undefined*
Undefined*
R
If a port 3 read is performed while P3DDR bits are set
to 1, the P3DR values are read. If a port 1 read is
performed while P3DDR bits are cleared to 0, the pin
states are read.
R
3
P33
2
P32
Undefined*
Undefined*
P31
Undefined*
R
P30
Undefined*
R
1
0
Note:
*
R
Determined by the states of pins P35 to P30.
Rev. 3.00 Feb 22, 2006 page 199 of 624
REJ09B0281-0300
Section 8 I/O Ports
8.3.4
Port 3 Open Drain Control Register (P3ODR)
P3ODR controls the output status for each port 3 pin.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P35ODR
0
R/W
4
P34ODR
0
R/W
3
P33ODR
0
R/W
Setting a P3ODR bit to 1 makes the corresponding
port 3 pin an NMOS open-drain output pin, while
clearing the bit to 0 makes the pin a CMOS output
pin.
2
P32ODR
0
R/W
1
P31ODR
0
R/W
0
P30ODR
0
R/W
8.3.5
Port Function Control Register 2 (PFCR2)
PFCR2 controls the I/O port.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 0
—
Reserved
3
ASOE
These bits are always read as 0. The write value
should always be 0.
1
R/W
AS Output Enable
Selects to enable or disable the AS output pin.
0: PF6 is designated as I/O port
1: PF6 is designated as AS output pin
2
LWROE
1
R/W
LWR Output Enable
Selects to enable or disable the LWR output pin.
0: PF3 is designated as I/O port
1: PF3 is designated as LWR output pin
1, 0
—
All 0
—
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 3.00 Feb 22, 2006 page 200 of 624
REJ09B0281-0300
Section 8 I/O Ports
8.3.6
Pin Functions
Port 3 pins also function as SCI I/Os and a bus control signal output. The correspondence between
the register specification and the pin functions is shown below.
P35/SCK1: The pin function is switched as shown below according to the combination of the C/A
bit in SMR of SCI_1, bits CKE0 and CKE1, and bit P35DDR.
CKE1
0
C/A
0
CKE0
0
P35DDR
Pin function
Note:
1
*
1
—
1
—
—
0
1
—
—
—
P35 input
P35 output*
SCK1 output*
SCK1 output*
SCK1 input
NMOS open-drain output when P35ODR = 1.
P34/SCK0: The pin function is switched as shown below according to the combination of bit C/A
in SMR of SCI_0, bits CKE0 and CKE1 in SCR, and bit P34DDR.
CKE1
0
C/A
0
CKE0
0
P34DDR
Pin function
Note:
1
*
1
—
1
—
—
0
1
—
—
—
P34 input
P34 output*
SCK0 output*
SCK0 output*
SCK0 input
NMOS open-drain output when P34ODR = 1.
P33/RxD1: The pin function is switched as shown below according to the combination of bit RE
in SCR of SCI_1 and bit P33DDR.
RE
0
P33DDR
Pin function
Note:
*
1
0
1
—
P33 input
P33 output*
RxD1 input
NMOS open-drain output when P33ODR = 1.
Rev. 3.00 Feb 22, 2006 page 201 of 624
REJ09B0281-0300
Section 8 I/O Ports
P32/RxD0/IrRxD: The pin function is switched as shown below according to the combination of
bit RE in SCR of SCI_0 and bit P32DDR.
RE
0
P32DDR
Pin function
Note:
*
1
0
1
—
P32 input
P32 output*
RxD0/IrRxD input
NMOS open-drain output when P32ODR = 1.
P31/TxD1: The pin function is switched as shown below according to the combination of bit TE
in SCR of SCI_1 and bit P31DDR.
TE
0
P31DDR
Pin function
Note:
*
1
0
1
—
P31 input
P31 output*
TxD1 output*
NMOS open-drain output when P31ODR = 1.
P30/TxD0/IrTxD: The pin function is switched as shown below according to the combination of
bit TE in SCR of SCI_0 and bit P30DDR.
TE
0
P30DDR
Pin function
Note:
*
1
0
1
—
P30 input
P30 output*
RxD0/IrRxD output*
NMOS open-drain output when P30ODR = 1.
Rev. 3.00 Feb 22, 2006 page 202 of 624
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Section 8 I/O Ports
8.4
Port 4
Port 4 is an 8-bit input-only port. Port 4 has the following register.
• Port 4 register (PORT4)
8.4.1
Port 4 Register (PORT4)
PORT4 is an 8-bit read-only register that shows port 4 pin states.
PORT4 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
P47
R
6
P46
Undefined*
Undefined*
The pin states are always read when a port 4 read is
performed.
Undefined*
Undefined*
R
Undefined*
Undefined*
R
Undefined*
Undefined*
R
5
P45
4
P44
3
P43
2
P42
1
P41
0
P40
Note:
*
R
R
R
R
Determined by the states of pins P47 to P40.
Rev. 3.00 Feb 22, 2006 page 203 of 624
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Section 8 I/O Ports
8.5
Port 5
Port 5 comprises a 4-bit I/O port (P53 to P50) and a 4-bit input-only port (P57 to P54). The 4-bit
input-only port does not have the data direction register and data register. The port 5 has the
following registers.
• Port 5 data direction register (P5DDR)
• Port 5 data register (P5DR)
• Port 5 register (PORT5)
8.5.1
Port 5 Data Direction Register (P5DDR)
The individual bits of P5DDR specify input or output for the pins of port 5.
P5DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 0
—
Reserved
3
P53DDR
0
W
2
P52DDR
0
W
1
P51DDR
0
W
0
P50DDR
0
W
When these bits are read, undefined value is
returned.
8.5.2
When a pin function is specified to a general
purpose I/O, setting this bit to 1 makes the
corresponding port 1 pin an output pin, while
clearing this bit to 0 makes the pin an input pin.
Port 5 Data Register (P5DR)
P5DR stores output data for the port 5 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 0
—
Reserved
3
P53DR
0
R/W
2
P52DR
0
R/W
1
P51DR
0
R/W
0
P50DR
0
R/W
These bits are always read as 0 and cannot be
modified.
Rev. 3.00 Feb 22, 2006 page 204 of 624
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Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
Section 8 I/O Ports
8.5.3
Port 5 Register (PORT5)
PORT5 shows the pin states.
PORT5 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
P57
Undefined*
R
6
P56
R
When bits P57 to P54 are read, the pin states are
always read from bits 7 to 4.
5
P55
Undefined*
Undefined*
4
P54
R
3
P53
Undefined*
Undefined*
2
P52
Undefined*
R
1
P51
R
0
P50
Undefined*
Undefined*
7
Note:
*
8.5.4
R
R
If bits P53 to P50 are read while P5DDR bits are set
to 1, the P5DR values are read. If a port 5 read is
performed while P5DDR bits are cleared to 0, the
pin states are read.
R
Determined by the states of pins P57 to P50.
Pin Functions
Port 5 pins also function as SCI I/Os, A/D converter inputs, A/D converter analog inputs, D/A
converter analog outputs, and interrupt inputs. The correspondence between the register
specification and the pin functions is shown below.
P57/AN15/DA3/IRQ7
IRQ7:
IRQ7 The pin function is switched as shown below according to bit ITS7 in
ITSR.
Pin function
IRQ7 interrupt input pin*
AN15 input
DA3 output
Note:
*
IRQ7 input when ITS7 = 0.
Rev. 3.00 Feb 22, 2006 page 205 of 624
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Section 8 I/O Ports
P56/AN14/DA2/IRQ6
IRQ6:
IRQ6 The pin function is switched as shown below according to bit ITS6 in
ITSR.
IRQ6 interrupt input pin*
Pin function
AN14 input
DA2 output
Note:
*
IRQ6 input when ITS6 = 0.
P55/AN13/IRQ5
IRQ5:
IRQ5 The pin function is switched as shown below according to bit ITS5 in ITSR.
IRQ5 interrupt input*
Pin function
AN13 input
Note:
*
IRQ5 input when ITS5 = 0.
P54/AN12/IRQ4
IRQ4:
IRQ4 The pin function is switched as shown below according to bit ITS4 in ITSR.
IRQ4 interrupt input*
Pin function
AN12 input
Note:
*
IRQ4 input when ITS4 = 0.
P53/ADTRG
ADTRG/IRQ3
ADTRG IRQ3:
IRQ3 The pin function is switched as shown below according to the combination of
bits TRGS1 and TRGS0 in the A/D control register (ADCR), bit ITS3 in ITSR, and bit P53DDR.
P53DDR
Pin function
0
1
P53 input
P53 output
1
ADTRG input*
IRQ3 interrupt input*
Notes: 1. ADTRG input when TRGS1 = TRGS0 = 0.
2. IRQ3 input when ITS3 = 0.
Rev. 3.00 Feb 22, 2006 page 206 of 624
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2
Section 8 I/O Ports
P52/SCK2/IRQ2
IRQ2:
IRQ2 The pin function is switched as shown below according to the combination of
bit C/A in SMR of SCI_2, bits CKE0 and CKE1 in SCR, bit ITS2 in ITSR, and bit P52DDR.
CKE1
0
C/A
1
0
CKE0
0
P52DDR
Pin function
1
—
1
—
—
0
1
—
—
—
P52 input
P52 output
SCK2 output
SCK2 output
SCK2 input
IRQ2 interrupt input*
Note:
*
IRQ2 input when ITS2 = 0.
P51/RxD2/IRQ1
IRQ1:
IRQ1 The pin function is switched as shown below according to the combination of
bit RE in SCR of SCI_2, bit ITS1 in ITSR, and bit P51DDR.
RE
0
P51DDR
Pin function
1
0
1
—
P51 input
P51 output
RxD2 input
IRQ1 interrupt input*
Note:
*
IRQ1 input when ITS1 = 0.
P50/TxD2/IRQ0
IRQ0:
IRQ0 The pin function is switched as shown below according to the combination of
bit TE in SCR of SCI_2, bit ITS0 in ITSR, and bit P50DDR.
TE
0
P50DDR
Pin function
1
0
1
—
P50 input
P50 output
TxD2 input
IRQ0 interrupt input*
Note:
*
IRQ0 input when ITS0 = 0.
Rev. 3.00 Feb 22, 2006 page 207 of 624
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Section 8 I/O Ports
8.6
Port 6
Port 6 is a 6-bit I/O port that also has other functions. The port 6 has the following registers.
• Port 6 data direction register (P6DDR)
• Port 6 data register (P6DR)
• Port 6 register (PORT6)
8.6.1
Port 6 Data Direction Register (P6DDR)
The individual bits of P6DDR specify input or output for the pins of port 6.
P6DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0.
5
P65DDR
0
W
4
P64DDR
0
W
3
P63DDR
0
W
When a pin function is specified to a general purpose
I/O, setting this bit to 1 makes the corresponding port
1 pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
2
P62DDR
0
W
1
P61DDR
0
W
0
P60DDR
0
W
Rev. 3.00 Feb 22, 2006 page 208 of 624
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Section 8 I/O Ports
8.6.2
Port 6 Data Register (P6DR)
P6DR stores output data for the port 6 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P65DR
0
R/W
4
P64DR
0
R/W
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
3
P63DR
0
R/W
2
P62DR
0
R/W
1
P61DR
0
R/W
0
P60DR
0
R/W
8.6.3
Port 6 Register (PORT6)
PORT6 shows the pin states.
PORT6 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
Undefined
—
Reserved
6
—
Undefined
—
These bits are reserved, if read they will return an
undefined value.
5
P65
R
4
P64
Undefined*
Undefined*
R
If a port 6 read is performed while P6DDR bits are set
to 1, the P6DR values are read. If a port 6 read is
performed while P6DDR bits are cleared to 0, the pin
states are read.
R
3
P63
2
P62
Undefined*
Undefined*
P61
Undefined*
R
P60
Undefined*
R
1
0
Note:
*
R
Determined by the states of pins P65 to P60.
Rev. 3.00 Feb 22, 2006 page 209 of 624
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Section 8 I/O Ports
8.6.4
Pin Functions
Port 6 pins function as 8-bit timer I/Os. The correspondence between the register specification and
the pin functions is shown below.
P65/TMO1: The pin function is switched as shown below according to the combination of bits
OS3 to OS0 in TCSR1 of the 8-bit timer, and bit P65DDR.
OS3 to OS0
P65DDR
Pin function
All 0
Not all 0
0
1
—
P65 input
P65 output
TMO1 output
P64/TMO0: The pin function is switched as shown below according to the combination of bits
OS3 to OS0 in TCSR1 of the 8-bit timer, and bit P64DDR.
OS3 to OS0
P64DDR
Pin function
All 0
Not all 0
0
1
—
P64 input
P64 output
TMO0 output
P63/TMCI1: The pin function is switched as shown below according to the bit P63DDR.
P63DDR
0
Pin function
1
P63 input
P63 output
TMCI1 input*
Note:
*
When used as the external clock input pin of TMR, the external clock is selected by the
CKS2 to CKS0 bits of TCR_1.
P62/TMCI0: The pin function is switched as shown below according to the bit P62DDR.
P62DDR
Pin function
0
1
P62 input
P62 output
TMCI0 input*
Note:
*
When used as the external clock input pin of TMR, the external clock is selected by the
CKS2 to CKS0 bits of TCR_0.
Rev. 3.00 Feb 22, 2006 page 210 of 624
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Section 8 I/O Ports
P61/TMRI1: The pin function is switched as shown below according to the combination of bit
P61DDR.
P61DDR
Pin function
0
1
P61 input
P61 output
TMRI1 input*
Note:
*
When used as the counter reset of TMR, the CCLR1 and CCLR0 bits of TCR_1 are
both set to 1.
P60/TMRI0: The pin function is switched as shown below according to the bit P60DDR.
P60DDR
0
Pin function
1
P60 input
P60 output
TMRI0 input*
Note:
*
When used as the counter reset of TMR, the CCLR1 and CCLR0 bits of TCR_0 are
respectively set to 1.
Rev. 3.00 Feb 22, 2006 page 211 of 624
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Section 8 I/O Ports
8.7
Port 7
Port 7 is a 6-bit I/O port that also has other functions. The port 7 has the following registers.
• Port 7 data direction register (P7DDR)
• Port 7 data register (P7DR)
• Port 7 register (PORT7)
8.7.1
Port 7 Data Direction Register (P7DDR)
The individual bits of P7DDR specify input or output for the pins of port 7.
P7DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0.
5
P75DDR
0
W
4
P74DDR
0
W
3
P73DDR
0
W
When a pin function is specified to a general purpose
I/O, setting this bit to 1 makes the corresponding port
1 pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
2
P72DDR
0
W
1
P71DDR
0
W
0
P70DDR
0
W
Rev. 3.00 Feb 22, 2006 page 212 of 624
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Section 8 I/O Ports
8.7.2
Port 7 Data Register (P7DR)
P7DR stores output data for the port 7 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P75DR
0
R/W
4
P74DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
3
P73DR
0
R/W
2
P72DR
0
R/W
1
P71DR
0
R/W
0
P70DR
0
R/W
8.7.3
Port 7 Register (PORT7)
PORT7 shows the pin states.
PORT7 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
Undefined
—
Reserved
6
—
Undefined
—
These bits are reserved, if read they will return an
undefined value.
5
P75
R
4
P74
Undefined*
Undefined*
R
If a port 7 read is performed while P7DDR bits are set
to 1, the P7DR values are read. If a port 7 read is
performed while P7DDR bits are cleared to 0, the pin
states are read.
R
3
P73
2
P72
Undefined*
Undefined*
P71
Undefined*
R
P70
Undefined*
R
1
0
Note:
*
R
Determined by the states of pins P75 to P70.
Rev. 3.00 Feb 22, 2006 page 213 of 624
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Section 8 I/O Ports
8.8
Port 8
Port 8 is a 6-bit I/O port that also has other functions. The port 8 has the following registers.
• Port 8 data direction register (P8DDR)
• Port 8 data register (P8DR)
• Port 8 register (PORT8)
8.8.1
Port 8 Data Direction Register (P8DDR)
The individual bits of P8DDR specify input or output for the pins of port 8.
P8DDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0.
5
P85DDR
0
W
4
P84DDR
0
W
3
P83DDR
0
W
When a pin function is specified to a general purpose
I/O, setting this bit to 1 makes the corresponding port
1 pin an output pin, while clearing this bit to 0 makes
the pin an input pin.
2
P82DDR
0
W
1
P81DDR
0
W
0
P80DDR
0
W
Rev. 3.00 Feb 22, 2006 page 214 of 624
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Section 8 I/O Ports
8.8.2
Port 8 Data Register (P8DR)
P8DR stores output data for the port 8 pins.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
6
—
0
—
These bits are always read as 0 and cannot be
modified.
5
P85DR
0
R/W
4
P84DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
3
P83DR
0
R/W
2
P82DR
0
R/W
1
P81DR
0
R/W
0
P80DR
0
R/W
8.8.3
Port 8 Register (PORT8)
PORT8 shows the pin states.
PORT8 cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
Undefined
—
Reserved
6
—
Undefined
—
These bits are reserved, if read they will return an
undefined value.
5
P85
R
4
P84
Undefined*
Undefined*
R
If a port 8 read is performed while P8DDR bits are set
to 1, the P8DR values are read. If a port 8 read is
performed while P8DDR bits are cleared to 0, the pin
states are read.
R
3
P83
2
P82
Undefined*
Undefined*
P81
Undefined*
R
P80
Undefined*
R
1
0
Note:
*
R
Determined by the states of pins P85 to P80.
Rev. 3.00 Feb 22, 2006 page 215 of 624
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Section 8 I/O Ports
8.8.4
Pin Functions
Port 8 pins also function as interrupt inputs. The correspondence between the register specification
and the pin functions is shown below.
P85/IRQ5
IRQ5:
IRQ5 The pin function is switched as shown below according to the combination of bit
P85DDR, and bit ITS5 in ITSR.
P85DDR
Pin function
0
1
P85 input
P85 output
IRQ5 interrupt input*
Note:
*
IRQ5 input when ITS5 = 1.
P84/IRQ4
IRQ4:
IRQ4 The pin function is switched as shown below according to the combination of bit
P84DDR, and bit ITS4 in ITSR.
P84DDR
Pin function
0
1
P84 input
P84 output
IRQ4 interrupt input*
Note:
*
IRQ4 input when ITS4 = 1.
P83/IRQ3
IRQ3:
IRQ3 The pin function is switched as shown below according to the combination of bit
P83DDR, and bit ITS3 in ITSR.
P83DDR
Pin function
0
1
P83 input
P83 output
IRQ3 interrupt input*
Note:
*
IRQ3 input when ITS3 = 1.
P82/IRQ2
IRQ2:
IRQ2 The pin function is switched as shown below according to the combination of bit
P82DDR, and bit ITS2 in ITSR.
P82DDR
0
Pin function
1
P82 input
P82 output
IRQ2 interrupt input*
Note:
*
IRQ2 input when ITS2 = 1.
Rev. 3.00 Feb 22, 2006 page 216 of 624
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Section 8 I/O Ports
P81/IRQ1
IRQ1:
IRQ1 The pin function is switched as shown below according to the combination of bit
P81DDR and bit ITS1 in ITSR.
P81DDR
Pin function
0
1
P81 input
P81 output
IRQ1 interrupt input*
Note:
*
IRQ1 input when ITS1 = 1.
P80/IRQ0
IRQ0:
IRQ0 The pin function is switched as shown below according to the combination of bit
P80DDR and bit ITS0 in ITSR.
P80DDR
Pin function
0
1
P80 input
P80 output
IRQ0 interrupt input*
Note:
8.9
*
IRQ0 input when ITS0 = 1.
Port A
Port A is an 8-bit I/O port that also has other functions. The port A has the following registers.
• Port A data direction register (PADDR)
• Port A data register (PADR)
• Port A register (PORTA)
• Port A pull-up MOS control register (PAPCR)
• Port A open-drain control register (PAODR)
• Port function control register 1 (PFCR1)
Rev. 3.00 Feb 22, 2006 page 217 of 624
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Section 8 I/O Ports
8.9.1
Port A Data Direction Register (PADDR)
The individual bits of PADDR specify input or output for the pins of port A. PADDR cannot be
read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DDR
0
W
•
6
PA6DDR
0
W
5
PA5DDR
0
W
4
PA4DDR
0
W
3
PA3DDR
0
W
2
PA2DDR
0
W
1
PA1DDR
0
W
0
PA0DDR
0
W
Modes 1, 2, 5, and 6
Pins PA4 to PA0 are address outputs regardless
of the PADDR settings.
For pins PA7 to PA5, when the corresponding bit
of A23E to A21E is set to 1, setting a PADDR bit
to 1 makes the corresponding port A pin an
address output, while clearing the bit to 0 makes
the pin an input port. Clearing one of bits A23E to
A21E to 0 makes the corresponding port A pin an
I/O port, and its function can be switched with
PADDR.
•
Mode 4
When the corresponding bit of A23E to A16E is
set to 1, setting a PADDR bit to 1 makes the
corresponding port A pin an address output, while
clearing the bit to 0 makes the pin an input port.
Clearing one of bits A23E to A16E to 0 makes the
corresponding port A pin an I/O port, and its
function can be switched with PADDR.
•
Mode 7 (when EXPE = 1)
When the corresponding bit of A23E to A16E is
set to 1, setting a PADDR bit to 1 makes the
corresponding port A pin an address output, while
clearing the bit to 0 makes the pin an input port.
Clearing one of bits A23E to A16E to 0 makes the
corresponding port A pin an I/O port; setting the
corresponding PADDR bit to 1 makes the pin an
output port, while clearing the bit to 0 makes the
pin an input port.
•
Mode 7 (when EXPE = 0)
Port A is an I/O port, and its pin functions can be
switched with PADDR.
Rev. 3.00 Feb 22, 2006 page 218 of 624
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Section 8 I/O Ports
8.9.2
Port A Data Register (PADR)
PADR stores output data for the port A pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7DR
0
R/W
6
PA6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PA5DR
0
R/W
4
PA4DR
0
R/W
3
PA3DR
0
R/W
2
PA2DR
0
R/W
1
PA1DR
0
R/W
0
PA0DR
0
R/W
8.9.3
Port A Register (PORTA)
PORTA shows port A pin states.
PORTA cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7
Undefined*
R
6
PA6
R
5
PA5
Undefined*
Undefined*
If a port A read is performed while PADDR bits are
set to 1, the PADR values are read. If a port A read
is performed while PADDR bits are cleared to 0, the
pin states are read.
Undefined*
Undefined*
R
R
R
4
PA4
3
PA3
2
PA2
1
PA1
Undefined*
Undefined*
0
PA0
Undefined*
Note:
*
R
R
R
Determined by the states of pins PA7 to PA0.
Rev. 3.00 Feb 22, 2006 page 219 of 624
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Section 8 I/O Ports
8.9.4
Port A Pull-Up MOS Control Register (PAPCR)
PAPCR controls the input pull-up MOS function. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and
all the bits are valid in modes 4 and 7.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7PCR
0
R/W
6
PA6PCR
0
R/W
When a pin function is specified to an input port,
setting the corresponding bit to 1 turns on the input
pull-up MOS for that pin.
5
PA5PCR
0
R/W
4
PA4PCR
0
R/W
3
PA3PCR
0
R/W
2
PA2PCR
0
R/W
1
PA1PCR
0
R/W
0
PA0PCR
0
R/W
8.9.5
Port A Open Drain Control Register (PAODR)
PAODR specifies an output type of port A.
Bit
Bit Name
Initial Value
R/W
Description
7
PA7ODR
0
R/W
6
PA6ODR
0
R/W
Setting the corresponding bit to 1 specifies a pin
output type to NMOS open-drain output, while
clearing this bit to 0 specifies that to CMOS output.
5
PA5ODR
0
R/W
4
PA4ODR
0
R/W
3
PA3ODR
0
R/W
2
PA2ODR
0
R/W
1
PA1ODR
0
R/W
0
PA0ODR
0
R/W
8.9.6
Port Function Control Register 1 (PFCR1)
PFCR1 performs I/O port control. Bits 7 to 5 are valid in modes 1, 2, 5, and 6, and all the bits are
valid in modes 4 and 7.
Rev. 3.00 Feb 22, 2006 page 220 of 624
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Section 8 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
7
A23E
1
R/W
Address 23 Enable
Enables or disables output for address output 23 (A23).
0: DR output when PA7DDR = 1
1: A23 output when PA7DDR = 1
6
A22E
1
R/W
Address 22 Enable
Enables or disables output for address output 22 (A22).
0: DR output when PA6DDR = 1
1: A22 output when PA6DDR = 1
5
A21E
1
R/W
Address 21 Enable
Enables or disables output for address output 21 (A21).
0: DR output when PA5DDR = 1
1: A21 output when PA5DDR = 1
4
A20E
1
R/W
Address 20 Enable
Enables or disables output for address output 20 (A20).
0: DR output when PA4DDR = 1
1: A20 output when PA4DDR = 1
3
A19E
1
R/W
Address 19 Enable
Enables or disables output for address output 19 (A19).
0: DR output when PA3DDR = 1
1: A19 output when PA3DDR = 1
2
A18E
1
R/W
Address 18 Enable
Enables or disables output for address output 18 (A18).
0: DR output when PA2DDR = 1
1: A18 output when PA2DDR = 1
1
A17E
1
R/W
Address 17 Enable
Enables or disables output for address output 17 (A17).
0: DR output when PA1DDR = 1
1: A17 output when PA1DDR = 1
0
A16E
1
R/W
Address 16 Enable
Enables or disables output for address output 16 (A16).
0: DR output when PA0DDR = 1
1: A16 output when PA0DDR = 1
Rev. 3.00 Feb 22, 2006 page 221 of 624
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Section 8 I/O Ports
8.9.7
Pin Functions
Port A pins also function as address outputs. The correspondence between the register
specification and the pin functions is shown below.
PA7/A23, PA6/A22, PA5/A21: The pin function is switched as shown below according to the
operating mode, bit EXPE, bits A23E to A21E, and bit PADDR.
Operating
mode
1, 2, 4, 5, 6
EXPE
—
AxxE
PADDR
Pin function
7
0
0
1
1
—
0
1
0
1
0
1
0
1
0
1
0
1
PA
input
PA
output
PA
input
Address
output
PA
input
PA
output
PA
input
PA
output
PA
input
Address
output
PA4/A20, PA3/A19, PA2/A18, PA1/A17, PA20/A16: The pin function is switched as shown
below according to the operating mode, bit EXPE, bits A20E to A16E, and bit PADDR.
Operating
mode
1, 2, 5,
6
4
EXPE
—
—
AxxE
—
PADDR
—
0
1
0
1
0
1
0
1
0
1
Address
output
PA
input
PA
output
PA
input
Address
output
PA
input
PA
output
PA
input
PA
output
PA
input
Address
output
Pin function
8.9.8
7
0
0
1
1
—
0
1
Port A Input Pull-Up MOS States
Port A has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used by pins PA7 to PA5 in modes 1, 2, 5, and 6, and by all pins in
modes 4 and 7. Input pull-up MOS can be specified as on or off on a bit-by-bit basis.
Table 8.2 summarizes the input pull-up MOS states.
Rev. 3.00 Feb 22, 2006 page 222 of 624
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Section 8 I/O Ports
Table 8.2
Input Pull-Up MOS States (Port A)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Off
Off
On/Off
On/Off
4, 7
PA7 to PA0
1, 2, 5, 6
PA7 to PA5
On/Off
On/Off
PA4 to PA0
Off
Off
Legend:
Off:
Input pull-up MOS is always off.
On/Off: On when PADDR = 0 and PAPCR = 1; otherwise off.
8.10
Port B
Port B is an 8-bit I/O port that also has other functions. The port B has the following registers.
• Port B data direction register (PBDDR)
• Port B data register (PBDR)
• Port B register (PORTB)
• Port B pull-up MOS control register (PBPCR)
8.10.1
Port B Data Direction Register (PBDDR)
The individual bits of PBDDR specify input or output for the pins of port B.
PBDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DDR
0
W
•
6
PB6DDR
0
W
5
PB5DDR
0
W
4
PB4DDR
0
W
3
PB3DDR
0
W
2
PB2DDR
0
W
1
PB1DDR
0
W
0
PB0DDR
0
W
Modes 1, 2, 5, and 6
Port B pins are address outputs regardless of the
PBDDR settings.
•
Modes 4 and 7 (when EXPE = 1)
Setting a PBDDR bit to 1 makes the
corresponding port B pin an address output, while
clearing the bit to 0 makes the pin an input port.
•
Mode 7 (when EXPE = 0)
Port B is an I/O port, and its pin functions can be
switched with PBDDR.
Rev. 3.00 Feb 22, 2006 page 223 of 624
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Section 8 I/O Ports
8.10.2
Port B Data Register (PBDR)
PBDR is stores output data for the port B pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7DR
0
R/W
6
PB6DR
0
R/W
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
5
PB5DR
0
R/W
4
PB4DR
0
R/W
3
PB3DR
0
R/W
2
PB2DR
0
R/W
1
PB1DR
0
R/W
0
PB0DR
0
R/W
8.10.3
Port B Register (PORTB)
PORTB shows port B pin states.
PORTB cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7
Undefined*
R
6
PB6
R
5
PB5
Undefined*
Undefined*
If a port B read is performed while PBDDR bits are
set to 1, the PBDR values are read. If a port B read
is performed while PBDDR bits are cleared to 0, the
pin states are read.
Undefined*
Undefined*
R
R
R
4
PB4
3
PB3
2
PB2
1
PB1
Undefined*
Undefined*
0
PB0
Undefined*
Note:
*
R
R
R
Determined by the states of pins PB7 to PB0.
Rev. 3.00 Feb 22, 2006 page 224 of 624
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Section 8 I/O Ports
8.10.4
Port B Pull-Up MOS Control Register (PBPCR)
PBPCR controls the on/off state of input pull-up MOS of port B. PBPCR is valid in modes 4 and
7.
Bit
Bit Name
Initial Value
R/W
Description
7
PB7PCR
0
R/W
6
PB6PCR
0
R/W
When a pin function is specified to an input port,
setting the corresponding bit to 1 turns on the input
pull-up MOS for that pin.
5
PB5PCR
0
R/W
4
PB4PCR
0
R/W
3
PB3PCR
0
R/W
2
PB2PCR
0
R/W
1
PB1PCR
0
R/W
0
PB0PCR
0
R/W
8.10.5
Pin Functions
Port B pins also function as address outputs. The correspondence between the register
specification and the pin functions is shown below.
PB7/A15, PB6/A14, PB5/A13, PB4/A12, PB3/A11, PB2/A10, PB1/A9, PB0/A8: The pin
function is switched as shown below according to the operating mode, bit EXPE, and bit PBDDR.
Operating mode
1, 2, 5, 6
4
EXPE
—
—
PBDDR
—
0
1
0
1
0
1
Address
output
PB
input
Address
output
PB
input
PB
output
PB
input
Address
output
Pin function
7
0
1
Rev. 3.00 Feb 22, 2006 page 225 of 624
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Section 8 I/O Ports
8.10.6
Port B Input Pull-Up MOS States
Port B has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in modes 4 and 7. Input pull-up MOS can be specified as on or
off on a bit-by-bit basis.
In modes 3, 4 and 7, when a PBDDR bit is cleared to 0, setting the corresponding PBPCR bit to 1
turns on the input pull-up MOS for that pin.
Table 8.3 summarizes the input pull-up MOS states.
Table 8.3
Input Pull-Up MOS States (Port B)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 5, 6
Off
Off
Off
Off
On/Off
On/Off
4, 7
Legend:
Off:
Input pull-up MOS is always off.
On/Off: On when PBDDR = 0 and PBPCR = 1; otherwise off.
8.11
Port C
Port C is an 8-bit I/O port that also has other functions. The port C has the following registers.
• Port C data direction register (PCDDR)
• Port C data register (PCDR)
• Port C register (PORTC)
• Port C pull-up MOS control register (PCPCR)
Rev. 3.00 Feb 22, 2006 page 226 of 624
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Section 8 I/O Ports
8.11.1
Port C Data Direction Register (PCDDR)
The individual bits of PCDDR specify input or output for the pins of port C.
PCDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DDR
0
W
•
6
PC6DDR
0
W
5
PC5DDR
0
W
4
PC4DDR
0
W
3
PC3DDR
0
W
2
PC2DDR
0
W
1
PC1DDR
0
W
0
PC0DDR
0
W
8.11.2
Modes 1, 2, 5, and 6
Port C pins are address outputs regardless of the
PCDDR settings.
•
Modes 4 and 7 (when EXPE = 1)
Setting a PCDDR bit to 1 makes the
corresponding port C pin an address output, while
clearing the bit to 0 makes the pin an input port.
•
Mode 7 (when EXPE = 0)
Port C is an I/O port, and its pin functions can be
switched with PCDDR.
Port C Data Register (PCDR)
PCDR stores output data for the port C pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7DR
0
R/W
6
PC6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PC5DR
0
R/W
4
PC4DR
0
R/W
3
PC3DR
0
R/W
2
PC2DR
0
R/W
1
PC1DR
0
R/W
0
PC0DR
0
R/W
Rev. 3.00 Feb 22, 2006 page 227 of 624
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Section 8 I/O Ports
8.11.3
Port C Register (PORTC)
PORTC is shows port C pin states.
PORTC cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
PC7
Undefined*
R
6
PC6
R
5
PC5
Undefined*
Undefined*
If a port C read is performed while PCDDR bits are
set to 1, the PCDR values are read. If a port C read
is performed while PCDDR bits are cleared to 0, the
pin states are read.
4
PC4
R
3
PC3
Undefined*
Undefined*
2
PC2
Undefined*
R
1
PC1
R
0
PC0
Undefined*
Undefined*
7
Note:
8.11.4
*
R
R
R
Determined by the states of pins PC7 to PC0.
Port C Pull-Up MOS Control Register (PCPCR)
PCPCR controls the on/off state of input pull-up MOS of port C. PCPCR is valid in modes 4 and
7.
Bit
Bit Name
Initial Value
R/W
Description
7
PC7PCR
0
R/W
6
PC6PCR
0
R/W
When a pin function is specified to an input port,
setting the corresponding bit to 1 turns on the input
pull-up MOS for that pin.
5
PC5PCR
0
R/W
4
PC4PCR
0
R/W
3
PC3PCR
0
R/W
2
PC2PCR
0
R/W
1
PC1PCR
0
R/W
0
PC0PCR
0
R/W
Rev. 3.00 Feb 22, 2006 page 228 of 624
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Section 8 I/O Ports
8.11.5
Pin Functions
Port C pins also function as address outputs. The correspondence between the register
specification and the pin functions is shown below.
PC7/A7, PC6/A6, PC5/A5, PC4/A4, PC3/A3, PC2/A2, PC1/A1, PC0/A0: The pin function is
switched as shown below according to the operating mode, bit EXPE, and bit PCDDR.
Operating mode
1, 2, 5, 6
4
EXPE
—
—
PCDDR
—
0
1
0
1
0
1
Address
output
PC
input
Address
output
PC
input
PC
output
PC
input
Address
output
Pin function
8.11.6
7
0
1
Port C Input Pull-Up MOS States
Port C has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in modes 4 and 7. Input pull-up MOS can be specified as on or
off on a bit-by-bit basis.
In modes 4 and 7, when a PCDDR bit is cleared to 0, setting the corresponding PCPCR bit to 1
turns on the input pull-up MOS for that pin.
Table 8.4 summarizes the input pull-up MOS states.
Table 8.4
Input Pull-Up MOS States (Port C)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 5, 6
Off
Off
Off
Off
On/Off
On/Off
4, 7
Legend:
Off:
Input pull-up MOS is always off.
On/Off: On when PCDDR = 0 and PCPCR = 1; otherwise off.
Rev. 3.00 Feb 22, 2006 page 229 of 624
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Section 8 I/O Ports
8.12
Port D
Port D is an 8-bit I/O port that also has other functions. The port D has the following registers.
• Port D data direction register (PDDDR)
• Port D data register (PDDR)
• Port D register (PORTD)
• Port D pull-up MOS control register (PDPCR)
8.12.1
Port D Data Direction Register (PDDDR)
The individual bits of PDDDR specify input or output for the pins of port D.
PDDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DDR
0
W
•
6
PD6DDR
0
W
5
PD5DDR
0
W
4
PD4DDR
0
W
3
PD3DDR
0
W
2
PD2DDR
0
W
1
PD1DDR
0
W
0
PD0DDR
0
W
Rev. 3.00 Feb 22, 2006 page 230 of 624
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Modes 1, 2, 4, 5, 6, and 7 (when EXPE = 1)
Port D is automatically designated for data
input/output.
•
Mode 7 (when EXPE = 0)
Port D is an I/O port, and its pin functions can be
switched with PDDDR.
Section 8 I/O Ports
8.12.2
Port D Data Register (PDDR)
PDDR stores output data for the port D pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7DR
0
R/W
6
PD6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PD5DR
0
R/W
4
PD4DR
0
R/W
3
PD3DR
0
R/W
2
PD2DR
0
R/W
1
PD1DR
0
R/W
0
PD0DR
0
R/W
8.12.3
Port D Register (PORTD)
PORTD shows port D pin states.
PORTD cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PD7
Undefined*
R
6
PD6
R
5
PD5
Undefined*
Undefined*
If a port D read is performed while PDDDR bits are
set to 1, the PDDR values are read. If a port D read
is performed while PDDDR bits are cleared to 0, the
pin states are read.
Undefined*
Undefined*
R
R
R
4
PD4
3
PD3
2
PD2
1
PD1
Undefined*
Undefined*
0
PD0
Undefined*
Note:
*
R
R
R
Determined by the states of pins PD7 to PD0.
Rev. 3.00 Feb 22, 2006 page 231 of 624
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Section 8 I/O Ports
8.12.4
Port D Pull-up Control Register (PDPCR)
PDPCR controls on/off states of the input pull-up MOS of port D. PDPCR is valid in mode 7.
Bit
Bit Name
7
PD7PCR
0
R/W
6
PD6PCR
0
R/W
5
PD5PCR
0
R/W
4
PD4PCR
0
R/W
3
PD3PCR
0
R/W
2
PD2PCR
0
R/W
1
PD1PCR
0
R/W
0
PD0PCR
0
R/W
8.12.5
Initial Value
R/W
Description
When the pin is in its input state, the input pull-up
MOS of the input pin is on when the corresponding bit
is set to 1.
Pin Functions
Port D pins also function as data I/Os. The correspondence between the register specification and
the pin functions is shown below.
PD7/D15, PD6/D14, PD5/D13, PD4/D12, PD3/D11, PD2/D10, PD1/D9, PD0/D8: The pin
function is switched as shown below according to the operating mode, bit EXPE, and bit PDDDR.
Operating mode
1, 2, 4, 5, 6
7
EXPE
—
PDDDR
—
0
1
—
Data I/O
PD input
PD output
Data I/O
Pin function
Rev. 3.00 Feb 22, 2006 page 232 of 624
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0
1
Section 8 I/O Ports
8.12.6
Port D Input Pull-Up MOS States
Port D has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in mode 7. Input pull-up MOS can be specified as on or off on
a bit-by-bit basis.
In mode 7, when a PDDDR bit is cleared to 0, setting the corresponding PDPCR bit to 1 turns on
the input pull-up MOS for that pin.
Table 8.5 summarizes the input pull-up MOS states.
Table 8.5
Input Pull-Up MOS States (Port D)
Mode
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
1, 2, 4, 5, 6
Off
Off
Off
Off
On/Off
On/Off
7
Legend:
OFF: Input pull-up MOS is always off.
On/Off: On when PDDDR = 0 and PDPCR = 1; otherwise off.
Rev. 3.00 Feb 22, 2006 page 233 of 624
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Section 8 I/O Ports
8.13
Port E
Port E is an 8-bit I/O port that also has other functions. The port E has the following registers.
• Port E data direction register (PEDDR)
• Port E data register (PEDR)
• Port E register (PORTE)
• Port E pull-up MOS control register (PEPCR)
8.13.1
Port E Data Direction Register (PEDDR)
The individual bits of PEDDR specify input or output for the pins of port E.
PEDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DDR
0
W
•
6
PE6DDR
0
W
5
PE5DDR
0
W
4
PE4DDR
0
W
3
PE3DDR
0
W
2
PE2DDR
0
W
1
PE1DDR
0
W
0
PE0DDR
0
W
Modes 1, 2, 4, 5, and 6
When 8-bit bus mode is selected, port E functions
as an I/O port. The pin states can be changed
with PEDDR.
When 16-bit bus mode is selected, port E is
designated for data input/output.
For details on 8-bit and 16-bit bus modes, see
section 6, Bus Controller.
•
Mode 7 (when EXPE = 1)
When 8-bit bus mode is selected, port E functions
as an I/O port. Setting a PEDDR bit to 1 makes
the corresponding port E pin an output port, while
clearing the bit to 0 makes the pin an input port.
When 16-bit bus mode is selected, port E is
designated for data input/output.
•
Mode 7 (when EXPE = 0)
Port E is an I/O port, and its pin functions can be
switched with PEDDR.
Rev. 3.00 Feb 22, 2006 page 234 of 624
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Section 8 I/O Ports
8.13.2
Port E Data Register (PEDR)
PEDR stores output data for the port E pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7DR
0
R/W
6
PE6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PE5DR
0
R/W
4
PE4DR
0
R/W
3
PE3DR
0
R/W
2
PE2DR
0
R/W
1
PE1DR
0
R/W
0
PE0DR
0
R/W
8.13.3
Port E Register (PORTE)
PORTE shows port E pin states.
PORTE cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PE7
Undefined*
R
6
PE6
R
5
PE5
Undefined*
Undefined*
If a port E read is performed while PEDDR bits are
set to 1, the PEDR values are read. If a port E read
is performed while PEDDR bits are cleared to 0, the
pin states are read.
Undefined*
Undefined*
R
R
R
4
PE4
3
PE3
2
PE2
1
PE1
Undefined*
Undefined*
0
PE0
Undefined*
Note:
*
R
R
R
Determined by the states of pins PE7 to PE0.
Rev. 3.00 Feb 22, 2006 page 235 of 624
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Section 8 I/O Ports
8.13.4
Port E Pull-up Control Register (PEPCR)
PEPCR controls on/off states of the input pull-up MOS of port E. PEPCR is valid in 8-bit bus
mode.
Bit
Bit Name
7
PE7PCR
0
R/W
6
PE6PCR
0
R/W
5
PE5PCR
0
R/W
4
PE4PCR
0
R/W
3
PE3PCR
0
R/W
2
PE2PCR
0
R/W
1
PE1PCR
0
R/W
0
PE0PCR
0
R/W
8.13.5
Initial Value
R/W
Description
When the pin is in its input state, the input pull-up
MOS of the input pin is on when the corresponding bit
is set to 1.
Pin Functions
Port E pins also function as data I/Os. The correspondence between the register specification and
the pin functions is shown below.
PE7/D7, PE6/D6, PE5/D5, PE4/D4, PE3/D3, PE2/D2, PE1/D1, PE0/D0: The pin function is
switched as shown below according to the operating mode, bus mode, bit EXPE, and bit PEDDR.
Operating mode
Bus mode
1, 2, 4, 5, 6
All areas
8-bit space
At least
one area
16-bit
space
—
All areas
8-bit space
At least
one area
16-bit
space
—
—
0
1
1
EXPE
PEDDR
Pin function
7
0
1
—
0
1
0
1
—
PE
input
PE
output
Data I/O
PE
input
PE
output
PE
input
PE
output
Data I/O
Rev. 3.00 Feb 22, 2006 page 236 of 624
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Section 8 I/O Ports
8.13.6
Port E Input Pull-Up MOS States
Port E has a built-in input pull-up MOS function that can be controlled by software. This input
pull-up MOS function can be used in 8-bit bus mode. Input pull-up MOS can be specified as on or
off on a bit-by-bit basis. In 8-bit bus mode, when a PEDDR bit is cleared to 0, setting the
corresponding PEPCR bit to 1 turns on the input pull-up MOS for that pin.
Table 8.6 summarizes the input pull-up MOS states.
Table 8.6
Input Pull-Up MOS States (Port E)
Mode
1, 2, 4 to 7
8-bit bus
Reset
Hardware
Standby Mode
Software
Standby Mode
In Other
Operations
Off
Off
On/Off
On/Off
Off
Off
16-bit bus
Legend:
Off:
Input pull-up MOS is always off.
On/Off: On when PEDDR = 0 and PEPCR = 1; otherwise off.
8.14
Port F
Port F is an 8-bit I/O port that also has other functions. The port F has the following registers. For
details on the port function control register 2, refer to section 8.3.5, Port Function Control Register
2 (PFCR2).
• Port F data direction register (PFDDR)
• Port F data register (PFDR)
• Port F register (PORTF)
• Port Function Control Register 2 (PFCR2)
Rev. 3.00 Feb 22, 2006 page 237 of 624
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Section 8 I/O Ports
8.14.1
Port F Data Direction Register (PFDDR)
The individual bits of PFDDR specify input or output for the pins of port F.
PFDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7DDR
1/0*
W
•
6
PF6DDR
0
W
5
PF5DDR
0
W
4
PF4DDR
0
W
3
PF3DDR
0
W
2
PF2DDR
0
W
1
PF1DDR
0
W
0
PF0DDR
0
W
Modes 1, 2, 4, 5, and 6
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pin PF6 functions as the AS output pin when
ASOE is set to 1. When ASOE is cleared to 0, pin
PF6 is an I/O port and its function can be
switched with PF6DDR.
Pins PF5 and PF4 are automatically designated
as bus control outputs (RD and HWR).
Pin PF3 functions as the LWR output pin when
LWROE is set to 1. When LWROE is cleared to 0,
pin PF3 is an I/O port and its function can be
switched with PF3DDR.
Pins PF2 and PF1 are input/output port and their
functions are switched with PFDDR.
Pin PF0 functions as bus control input/output pin
(WAIT) when the appropriate bus controller
settings are made. Otherwise, this pin is output
port when the corresponding PFDDR bit is set to
1, and input port when the bit is cleared to 0.
•
Mode 7 (when EXPE = 1)
Pin PF7 to PF1 function in the same way as in
modes 1, 2, 4, 5, and 6.
Pin PF0 functions as bus control input/output pin
(WAIT) when the appropriate PFCR2 settings are
made. Otherwise, this pin is I/O port, and this
function can be switched with PFDDR.
•
Mode 7 (when EXPE = 0)
Pin PF7 functions as the φ output pin when the
corresponding PFDDR bit is set to 1, and as an
input port when the bit is cleared to 0.
Pins PF6 to PF0 are I/O ports, and their functions
can be switched with PFDDR.
Note:
*
PF7DDR is initialized to 1 in modes 1, 2, 4, 5, and 6, and to 0 in mode 7.
Rev. 3.00 Feb 22, 2006 page 238 of 624
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Section 8 I/O Ports
8.14.2
Port F Data Register (PFDR)
PFDR stores output data for the port F pins.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7DR
0
R/W
6
PF6DR
0
R/W
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
5
PF5DR
0
R/W
4
PF4DR
0
R/W
3
PF3DR
0
R/W
2
PF2DR
0
R/W
1
PF1DR
0
R/W
0
PF0DR
0
R/W
8.14.3
Port F Register (PORTF)
PORTF shows port F pin states.
PORTF cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
PF7
Undefined*
R
6
PF6
R
5
PF5
Undefined*
Undefined*
If a port F read is performed while PFDDR bits are
set to 1, the PFDR values are read. If a port F read is
performed while PFDDR bits are cleared to 0, the pin
states are read.
Undefined*
Undefined*
R
R
R
4
PF4
3
PF3
2
PF2
1
PF1
Undefined*
Undefined*
0
PF0
Undefined*
Note:
*
R
R
R
Determined by the states of pins PF7 to PF0.
Rev. 3.00 Feb 22, 2006 page 239 of 624
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Section 8 I/O Ports
8.14.4
Pin Functions
Port F pins also function as external interrupt inputs, bus control signal I/Os, and system clock
outputs (φ). The correspondence between the register specification and the pin functions is shown
below.
PF7/φ
φ: The pin function is switched as shown below according to bit PF7DDR.
Operating mode
1, 2, 4 to 7
PFDDR
Pin function
0
1
PF7 input
φ output
PF6/AS
AS:
AS The pin function is switched as shown below according to the operating mode, bit
ASOE, bit EXPE, and bit PF6DDR.
Operating mode
1, 2, 4, 5, 6
EXPE
7
—
0
ASOE
1
PF6DDR
—
0
1
0
1
—
0
1
AS
output
PF6
input
PF6
output
PF6
input
PF6
output
AS
output
PF6
input
PF6
output
Pin function
0
1
—
1
0
PF5/RD
RD:
RD The pin function is switched as shown below according to the operating mode, bit
EXPE, and bit PF5DDR.
Operating mode
1, 2, 4, 5, 6
7
EXPE
—
PF5DDR
—
0
1
—
RD output
PF5 input
PF5 output
RD output
Pin function
0
1
PF4/HWR
HWR:
HWR The pin function is switched as shown below according to the operating mode, bit
EXPE, and bit PF4DDR.
Operating mode
1, 2, 4, 5, 6
7
EXPE
—
PF4DDR
—
0
1
—
HWR output
PF4 input
PF4 output
HWR output
Pin function
Rev. 3.00 Feb 22, 2006 page 240 of 624
REJ09B0281-0300
0
1
Section 8 I/O Ports
PF3/LWR
LWR:
LWR The pin function is switched as shown below according to the operating mode, bit
EXPE, bit PF3DDR, and bit LWROE.
Operating mode
1, 2, 4, 5, 6
EXPE
7
—
0
LWROD
1
PF3DDR
—
0
1
0
1
—
0
1
LWR
output
PF3
input
PF3
output
PF3
input
PF3
output
LWR
output
PF3
input
PF3
output
Pin function
0
1
—
1
0
PF2: The pin function is switched as shown below according to the bit PF2DDR.
PF2DDR
Pin function
0
1
PF2 input
PF2 output
PF1: The pin function is switched as shown below according to the bit PF1DDR.
PF1DDR
Pin function
0
1
PF1 input
PF1 output
PF0/WAIT
WAIT:
WAIT The pin function is switched as shown below according to the operating mode, bit
EXPE, bit WAITE of BCR, and bit PF0DDR.
Operating mode
1, 2, 4, 5, 6
EXPE
—
WAITE
PF0DDR
Pin function
7
0
0
1
1
—
0
1
0
1
—
0
1
0
1
—
PF0
input
PF0
output
WAIT
input
PF0
input
PF0
output
PF0
input
PF0
output
WAIT
input
Rev. 3.00 Feb 22, 2006 page 241 of 624
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Section 8 I/O Ports
8.15
Port G
Port G is a 7-bit I/O port that also has other functions. The port G has the following registers.
• Port G data direction register (PGDDR)
• Port G data register (PGDR)
• Port G register (PORTG)
• Port Function Control Register 0 (PFCR0)
8.15.1
Port G Data Direction Register (PGDDR)
The individual bits of PGDDR specify input or output for the pins of port G.
PGDDR cannot be read; if it is, an undefined value will be read.
Rev. 3.00 Feb 22, 2006 page 242 of 624
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Section 8 I/O Ports
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
If read, it returns an undefined value.
6
PG6DDR
0
W
5
PG5DDR
0
W
4
PG4DDR
0
W
3
PG3DDR
0
W
2
PG2DDR
0
W
1
PG1DDR
0
W
0
PG0DDR
1/0*
W
•
Modes 1, 2, 4, 5, and 6
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ)
when the appropriate bus controller settings are
made. Otherwise, these pins are I/O ports, and
their functions can be switched with PGDDR.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS
output pins when the corresponding PGDDR bit is
set to 1, and as input ports when the bit is cleared
to 0. When CS3E to CS0E are cleared to 0, pins
PG3 to PG0 are I/O ports, and their functions can
be switched with PGDDR.
•
Mode 7 (when EXPE = 1)
Pins PG6 to PG4 function as bus control
input/output pins (BREQO, BACK, and BREQ)
when the appropriate bus controller settings are
made. Otherwise, these pins are output ports
when the corresponding PGDDR bit is set to 1,
and as input ports when the bit is cleared to 0.
When the CS output enable bits (CS3E to CS0E)
are set to 1, pins PG3 to PG0 function as CS
output pins when the corresponding PGDDR bit is
set to 1, and as input ports when the bit is cleared
to 0. When CS3E to CS0E are cleared to 0, pins
PG3 to PG0 are I/O ports, and their functions can
be switched with PGDDR.
•
Mode 7 (when EXPE = 0)
Pins PG6 to PG0 are I/O ports, and their functions
can be switched with PGDDR.
Note:
*
PG0DDR is initialized to 1 in modes 1, 2, 5, and 6, and to 0 in modes 4 and 7.
Rev. 3.00 Feb 22, 2006 page 243 of 624
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Section 8 I/O Ports
8.15.2
Port G Data Register (PGDR)
PGDR stores output data for the port G pins.
Bit
Bit Name
Initial Value
R/W
Description
7
—
0
—
Reserved
This bit is always read as 0, and cannot be modified.
6
PG6DR
0
R/W
5
PG5DR
0
R/W
4
PG4DR
0
R/W
3
PG3DR
0
R/W
2
PG2DR
0
R/W
1
PG1DR
0
R/W
0
PG0DR
0
R/W
8.15.3
An output data for a pin is stored when the pin
function is specified to a general purpose I/O.
Port G Register (PORTG)
PORTG shows port G pin states.
PORTG cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
—
Undefined
—
Reserved
6
PG6
R
5
PG5
Undefined*
Undefined*
4
PG4
R
3
PG3
Undefined*
Undefined*
R
R
If this bit is read, it will return an undefined value.
2
PG2
1
PG1
Undefined*
Undefined*
PG0
Undefined*
0
Note:
*
R
If a port G read is performed while PGDDR bits are
set to 1, the PGDR values are read. If a port G read
is performed while PGDDR bits are cleared to 0, the
pin states are read.
R
R
Determined by the states of pins PG6 to PG0.
Rev. 3.00 Feb 22, 2006 page 244 of 624
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Section 8 I/O Ports
8.15.4
Port Function Control Register 0 (PFCR0)
PFCR0 performs I/O port control.
Bit
Bit Name
Initial Value
R/W
Description
7
CS7E
1
R/W
CS7 to CS0 Enable
6
CS6E
1
R/W
5
CS5E
1
R/W
These bits enable or disable the corresponding CSn
output.
4
CS4E
1
R/W
3
CS3E
1
R/W
2
CS2E
1
R/W
1
CS1E
1
R/W
0
CS0E
1
R/W
8.15.5
0: Pin is designated as I/O port
1: Pin is designated as CSn output pin
(n = 7 to 0)
Pin Functions
Port G pins also function as bus control signal I/Os. The correspondence between the register
specification and the pin functions is shown below.
PG6/BREQ
BREQ:
BREQ The pin function is switched as shown below according to the operating mode, bit
EXPE, bit BRLE, and bit PG6DDR.
Operating mode
1, 2, 4, 5, 6
EXPE
—
BRLE
PG6DDR
Pin function
7
0
0
1
1
—
0
1
0
1
—
0
1
0
1
—
PG6
input
PG6
output
BREQ
input
PG6
input
PG6
output
PG6
input
PG6
output
BREQ
input
Rev. 3.00 Feb 22, 2006 page 245 of 624
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Section 8 I/O Ports
PG5/BACK
BACK:
BACK The pin function is switched as shown below according to the operating mode, bit
EXPE, bit BRLE, and bit PG5DDR.
Operating mode
1, 2, 4, 5, 6
EXPE
7
—
BRLE
0
0
PG5DDR
Pin function
1
1
—
0
1
0
1
—
0
1
0
1
—
PG5
input
PG5
output
BACK
output
PG5
input
PG5
output
PG5
input
PG5
output
BACK
output
PG4/BREQO
BREQO:
BREQO The pin function is switched as shown below according to the operating mode, bit
EXPE, bit BRLE, bit BREQO, and bit PG4DDR.
Operating
mode
1, 2, 4, 5, 6
EXPE
—
BRLE
0
BREQO
—
PG4DDR
Pin
function
7
0
1
0
1
1
—
0
1
—
—
0
1
0
1
0
1
—
0
1
0
1
0
1
—
PG4
input
PG4
output
PG4
input
PG4
output
BREQO
output
PG4
input
PG4
output
PG4
input
PG4
output
PG4
input
PG4
output
BREQO
output
PG3/CS3
CS3/,
CS2,
CS1,
CS0:
CS3 PG2/CS2
CS2 PG1/CS1
CS1 PG0/CS0
CS0 The pin function is switched as shown below
according to the operating mode, bit EXPE, bit CsnE, and bit PGnDDR.
Operating mode
1, 2, 4, 5, 6
EXPE
—
CSnE
PGnDDR
Pin function
7
0
0
1
1
—
0
1
0
1
0
1
0
1
0
1
0
1
PGn
input
PGn
output
PGn
input
CSn
output
PGn
input
PGn
output
PGn
input
PGn
output
PGn
input
CSn
output
(n = 0 to 3)
Rev. 3.00 Feb 22, 2006 page 246 of 624
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Section 8 I/O Ports
8.16
Port H
Port H is a 4-bit I/O port that also has other functions. The port H has the following registers. For
details on the port function control register 0, refer to section 8.15.4, Port Function Control
Register 0 (PFCR0).
• Port H data direction register (PHDDR)
• Port H data register (PHDR)
• Port H register (PORTH)
• Port Function Control Register 0 (PFCR0)
8.16.1
Port H Data Direction Register (PHDDR)
The individual bits of PHDDR specify input or output for the pins of port H.
PHDDR cannot be read; if it is, an undefined value will be read.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 0
—
Reserved
3
PH3DDR
0
W
2
PH2DDR
0
W
1
PH1DDR
0
W
0
PH0DDR
0
W
If these bits are read, they will return an undefined
value.
•
Modes 1, 2, 4, 5, 6, and 7 (when EXPE = 1)
When the OE output enable bit (OEE) and OE
output select bit (OES) are set to 1, pin PH3
functions as the OE output pin. Otherwise, when
bit CS7E is set to 1, pin PH3 functions as a CS
output pin when the corresponding PHDDR bit is
set to 1, and as an input port when the bit is
cleared to 0. When bit CS7E is cleared to 0, pin
PH3 is an I/O port, and its function can be
switched with PHDDR.
When the CS output enable bits (CS7E to
CS4E) are set to 1, pins PH2 to PH0 function as
CS output pins when the corresponding PHDDR
bit is set to 1, and as I/O ports when the bit is
cleared to 0. When CS6E to CS4E are cleared
to 0, pins PH2 to PH0 are I/O ports, and their
functions can be switched with PHDDR.
•
Mode 7 (when EXPE = 0)
Pins PH3 to PH0 are I/O ports, and their
functions can be switched with PHDDR.
Rev. 3.00 Feb 22, 2006 page 247 of 624
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Section 8 I/O Ports
8.16.2
Port H Data Register (PHDR)
PHDR stores output data for the port H pins.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 0
—
Reserved
3
PH3DR
0
R/W
2
PH2DR
0
R/W
1
PH1DR
0
R/W
0
PH0DR
0
R/W
These bits are reserved; they are always read as 0
and cannot be modified.
8.16.3
Output data for a pin is stored when the pin function
is specified to a general purpose I/O.
Port H Register (PORTH)
PORTH shows port H pin states.
PORTH cannot be modified.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
Undefined
—
Reserved
3
PH3
Undefined*
R
2
PH2
R
1
PH1
Undefined*
Undefined*
0
PH0
Undefined*
R
Note:
If these bits are read, they will return an undefined
value.
*
R
If a port H read is performed while PHDDR bits are
set to 1, the PHDR values are read. If a port H read is
performed while PHDDR bits are cleared to 0, the pin
states are read.
Determined by the states of pins PH3 to PH0.
Rev. 3.00 Feb 22, 2006 page 248 of 624
REJ09B0281-0300
Section 8 I/O Ports
8.16.4
Pin Functions
Port H pins also function as bus control signal I/Os and external interrupt inputs. The
correspondence between the register specification and the pin functions is shown below.
PH3/CS7
CS7/OE
CS7 OE/(IRQ7
OE IRQ7):
IRQ7 The pin function is switched as shown below according to the operating
mode, bit EXPE, bit CS7E, and bit PH3DDR.
Operating mode
1, 2, 4, 5, 6
EXPE
—
CS7E
0
0
PH3DDR
Pin function
Note:
7
*
1
1
—
0
1
0
1
0
PH3
input
PH3
output
PH3
input
CS7
output
PH3
input
0
1
PH3
output
IRQ7 input*
1
0
1
0
1
PH3
input
PH3
output
PH3
input
CS7
output
IRQ7 interrupt input pin when bit ITS7 is set to 1 in ITSR
PH2/CS6
CS6/(IRQ6
CS6 IRQ6):
IRQ6 The pin function is switched as shown below according to the operating mode,
bit EXPE, bit CS6E, and bit PH2DDR.
Operating mode
1, 2, 4, 5, 6
EXPE
—
CS6E
0
0
PH2DDR
Pin function
Note:
7
*
1
1
—
0
0
1
0
1
0
1
PH2
input
PH2
output
PH2
input
CS6
output
PH2
input
PH2
output
0
PH2
input
IRQ6 interrupt input*
1
1
0
1
PH2
output
PH2
input
CS6
output
IRQ6 interrupt input pin when bit ITS6 is set to 1 in ITSR.
Rev. 3.00 Feb 22, 2006 page 249 of 624
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Section 8 I/O Ports
PH1/CS5
CS5:
CS5 The pin function is switched as shown below according to the operating mode, bit
EXPE, bit CS5E, and bit PH1DDR.
Operating mode
1, 2, 4, 5, 6
EXPE
—
CS5E
PH1DDR
Pin function
7
0
0
1
1
—
0
1
0
1
0
1
0
1
0
1
0
1
PH1
input
PH1
output
PH1
input
CS5
output
PH1
input
PH1
output
PH1
input
PH1
output
PH1
input
CS5
output
PH0/CS4
CS4:
CS4 The pin function is switched as shown below according to the operating mode, bit
EXPE, bit CS4E, and bit PH0DDR.
Operating mode
1, 2, 4, 5, 6
EXPE
—
CS4E
PH0DDR
Pin function
3, 7
0
0
1
1
—
0
1
0
1
0
1
0
1
0
1
0
1
PH0
input
PH0
output
PH0
input
CS4
output
PH0
input
PH0
output
PH0
input
PH0
output
PH0
input
CS4
output
Rev. 3.00 Feb 22, 2006 page 250 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Section 9 16-Bit Timer Pulse Unit (TPU)
This LSI has an on-chip 16-bit timer pulse unit (TPU) that comprises six 16-bit timer channels.
The function list of the 16-bit timer unit and its block diagram are shown in table 9.1 and figure
9.1, respectively.
9.1
Features
• Maximum 16-pulse input/output
• Selection of 8 counter input clocks for each channel
• The following operations can be set for each channel:
Waveform output at compare match
Input capture function
Counter clear operation
Synchronous operations:
Multiple timer counters (TCNT) can be written to simultaneously
Simultaneous clearing by compare match and input capture possible
Register simultaneous input/output possible by counter synchronous operation
Maximum of 15-phase PWM output possible by combination with synchronous operation
• Buffer operation settable for channels 0 and 3
• Phase counting mode settable independently for each of channels 1, 2, 4, and 5
• Cascaded operation
• Fast access via internal 16-bit bus
• 26 interrupt sources
• Automatic transfer of register data
• Programmable pulse generator (PPG) output trigger can be generated
• A/D converter conversion start trigger can be generated
• Module stop mode can be set
TIMTPU1A_000020020400
Rev. 3.00 Feb 22, 2006 page 251 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.1
TPU Functions
Item
Channel 0 Channel 1 Channel 2 Channel 3 Channel 4 Channel 5
Count clock
φ/1
φ/4
φ/16
φ/64
TCLKA
TCLKB
TCLKC
TCLKD
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKB
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKB
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
TCLKA
φ/1
φ/4
φ/16
φ/64
φ/1024
TCLKA
TCLKC
φ/1
φ/4
φ/16
φ/64
φ/256
TCLKA
TCLKC
TCLKD
General registers
(TGR)
TGRA_0
TGRB_0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
TGRA_3
TGRB_3
TGRA_4
TGRB_4
TGRA_5
TGRB_5
General registers/
buffer registers
TGRC_0
TGRD_0
—
—
TGRC_3
TGRD_3
—
—
I/O pins
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
TIOCB1
TIOCA2
TIOCB2
TIOCA3
TIOCB3
TIOCC3
TIOCD3
TIOCA4
TIOCB4
TIOCA5
TIOCB5
Counter clear
function
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
TGR
compare
match or
input
capture
—
—
Compare 0 output
match
1 output
output
Toggle
output
Input capture
function
Synchronous
operation
PWM mode
Phase counting
mode
Buffer operation
—
—
—
Rev. 3.00 Feb 22, 2006 page 252 of 624
REJ09B0281-0300
—
Section 9 16-Bit Timer Pulse Unit (TPU)
Item
Channel 0
Channel 1
Channel 2
Channel 3
Channel 4
Channel 5
DTC
TGR
activation compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
TGR
compare
match or
input capture
A/D
TGRA
converter compare
trigger
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
TGRA
compare
match or
input capture
PPG
trigger
TGRA/
TGRB
compare
match or
input capture
TGRA/
TGRB
compare
match or
input capture
TGRA/
TGRB
compare
match or
input capture
TGRA/
—
TGRB
compare
match or
input capture
—
Interrupt
sources
5 sources
4 sources
4 sources
5 sources
4 sources
4 sources
• Compare
• Compare
• Compare
• Compare
• Compare
• Compare
match or
match or
match or
match or
match or
match or
input
input
input
input
input
input
capture 0A
capture 1A
capture 2A
capture 3A
capture 4A
capture 5A
• Compare
• Compare
• Compare
• Compare
• Compare
• Compare
match or
match or
match or
match or
match or
match or
input
input
input
input
input
input
capture 0B
capture 1B
capture 2B
capture 3B
capture 4B
capture 5B
• Compare
• Overflow
match or
• Underflow
input
capture 0C
• Overflow
• Underflow
• Compare
• Overflow
match or
• Underflow
input
capture 3C
• Compare
match or
input
capture 0D
• Compare
match or
input
capture 3D
• Overflow
• Overflow
• Overflow
• Underflow
Legend:
: Possible
— : Not possible
Rev. 3.00 Feb 22, 2006 page 253 of 624
REJ09B0281-0300
TGRD
TGRB
TGRC
TGRB
A/D conversion start request signal
TGRD
TGRB
TGRB
TGRB
PPG output trigger signal
Interrupt request signals
Channel 0: TGI0A
TGI0B
TGI0C
TGI0D
TCI0V
Channel 1: TGI1A
TGI1B
TCI1V
TCI1U
Channel 2: TGI2A
TGI2B
TCI2V
TCI2U
Timer interrupt enable register
Timer status register
Timer general registers (A, B, C, D)
Timer counter
Figure 9.1 Block Diagram of TPU
Rev. 3.00 Feb 22, 2006 page 254 of 624
REJ09B0281-0300
Interrupt request signals
Channel 3: TGI3A
TGI3B
TGI3C
TGI3D
TCI3V
Channel 4: TGI4A
TGI4B
TCI4V
TCI4U
Channel 5: TGI5A
TGI5B
TCI5V
TCI5U
Internal data bus
TGRC
TCNT
TCNT
TGRA
TCNT
TGRA
TGRA
Bus interface
TGRB
TCNT
TCNT
TGRA
TCNT
Module data bus
TGRA
TSR
TSR
TSR
TIER
TIER
TSR
TIOR
TIORH TIORL
TIER:
TSR:
TGR (A, B, C, D):
TCNT:
TGRA
TSR
TIER
TIER
TIER
TSTR TSYR
TSR
TIOR
TIER
TMDR
TIORH TIORL
TIOR
TIOR
TCR
TMDR
Channel 4
TCR
TMDR
Channel 5
TCR
Control logic
Common
TMDR
TCR
TMDR
Channel 1
TCR
Channel 0
Timer start register
Timer synchronous register
Timer control register
Timer mode register
Timer I/O control registers (H, L)
TMDR
Channel 2
Legend:
TSTR:
TSYR:
TCR:
TMDR:
TIOR (H, L):
Control logic for channels 0 to 2
Input/output pins
Channel 0:
TIOCA0
TIOCB0
TIOCC0
TIOCD0
Channel 1:
TIOCA1
TIOCB1
Channel 2:
TIOCA2
TIOCB2
TCR
Clock input
Internal clock: φ/1
φ/4
φ/16
φ/64
φ/256
φ/1024
φ/4096
External clock: TCLKA
TCLKB
TCLKC
TCLKD
Control logic for channels 3 to 5
Input/output pins
TIOCA3
Channel 3:
TIOCB3
TIOCC3
TIOCD3
TIOCA4
Channel 4:
TIOCB4
TIOCA5
Channel 5:
TIOCB5
Channel 3
Section 9 16-Bit Timer Pulse Unit (TPU)
Section 9 16-Bit Timer Pulse Unit (TPU)
9.2
Table 9.2
Input/Output Pins
Pin Configuration
Channel
Symbol
I/O
Function
All
TCLKA
Input
External clock A input pin
(Channel 1 and 5 phase counting mode A phase input)
TCLKB
Input
External clock B input pin
(Channel 1 and 5 phase counting mode B phase input)
TCLKC
Input
External clock C input pin
(Channel 2 and 4 phase counting mode A phase input)
TCLKD
Input
External clock D input pin
(Channel 2 and 4 phase counting mode B phase input)
TIOCA0
I/O
TGRA_0 input capture input/output compare output/PWM output pin
TIOCB0
I/O
TGRB_0 input capture input/output compare output/PWM output pin
TIOCC0
I/O
TGRC_0 input capture input/output compare output/PWM output pin
TIOCD0
I/O
TGRD_0 input capture input/output compare output/PWM output pin
TIOCA1
I/O
TGRA_1 input capture input/output compare output/PWM output pin
TIOCB1
I/O
TGRB_1 input capture input/output compare output/PWM output pin
TIOCA2
I/O
TGRA_2 input capture input/output compare output/PWM output pin
TIOCB2
I/O
TGRB_2 input capture input/output compare output/PWM output pin
TIOCA3
I/O
TGRA_3 input capture input/output compare output/PWM output pin
TIOCB3
I/O
TGRB_3 input capture input/output compare output/PWM output pin
TIOCC3
I/O
TGRC_3 input capture input/output compare output/PWM output pin
TIOCD3
I/O
TGRD_3 input capture input/output compare output/PWM output pin
TIOCA4
I/O
TGRA_4 input capture input/output compare output/PWM output pin
TIOCB4
I/O
TGRB_4 input capture input/output compare output/PWM output pin
TIOCA5
I/O
TGRA_5 input capture input/output compare output/PWM output pin
TIOCB5
I/O
TGRB_5 input capture input/output compare output/PWM output pin
0
1
2
3
4
5
Rev. 3.00 Feb 22, 2006 page 255 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
9.3
Register Descriptions
The TPU has the following registers in each channel.
• Timer control register_0 (TCR_0)
• Timer mode register_0 (TMDR_0)
• Timer I/O control register H_0 (TIORH_0)
• Timer I/O control register L_0 (TIORL_0)
• Timer interrupt enable register_0 (TIER_0)
• Timer status register_0 (TSR_0)
• Timer counter_0 (TCNT_0)
• Timer general register A_0 (TGRA_0)
• Timer general register B_0 (TGRB_0)
• Timer general register C_0 (TGRC_0)
• Timer general register D_0 (TGRD_0)
• Timer control register_1 (TCR_1)
• Timer mode register_1 (TMDR_1)
• Timer I/O control register _1 (TIOR_1)
• Timer interrupt enable register_1 (TIER_1)
• Timer status register_1 (TSR_1)
• Timer counter_1 (TCNT_1)
• Timer general register A_1 (TGRA_1)
• Timer general register B_1 (TGRB_1)
• Timer control register_2 (TCR_2)
• Timer mode register_2 (TMDR_2)
• Timer I/O control register_2 (TIOR_2)
• Timer interrupt enable register_2 (TIER_2)
• Timer status register_2 (TSR_2)
• Timer counter_2 (TCNT_2)
• Timer general register A_2 (TGRA_2)
• Timer general register B_2 (TGRB_2)
• Timer control register_3 (TCR_3)
• Timer mode register_3 (TMDR_3)
• Timer I/O control register H_3 (TIORH_3)
• Timer I/O control register L_3 (TIORL_3)
• Timer interrupt enable register_3 (TIER_3)
Rev. 3.00 Feb 22, 2006 page 256 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
• Timer status register_3 (TSR_3)
• Timer counter_3 (TCNT_3)
• Timer general register A_3 (TGRA_3)
• Timer general register B_3 (TGRB_3)
• Timer general register C_3 (TGRC_3)
• Timer general register D_3 (TGRD_3)
• Timer control register_4 (TCR_4)
• Timer mode register_4 (TMDR_4)
• Timer I/O control register _4 (TIOR_4)
• Timer interrupt enable register_4 (TIER_4)
• Timer status register_4 (TSR_4)
• Timer counter_4 (TCNT_4)
• Timer general register A_4 (TGRA_4)
• Timer general register B_4 (TGRB_4)
• Timer control register_5 (TCR_5)
• Timer mode register_5 (TMDR_5)
• Timer I/O control register_5 (TIOR_5)
• Timer interrupt enable register_5 (TIER_5)
• Timer status register_5 (TSR_5)
• Timer counter_5 (TCNT_5)
• Timer general register A_5 (TGRA_5)
• Timer general register B_5 (TGRB_5)
Common Registers
• Timer start register (TSTR)
• Timer synchronous register (TSYR)
Rev. 3.00 Feb 22, 2006 page 257 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.1
Timer Control Register (TCR)
The TCR registers control the TCNT operation for each channel. The TPU has a total of six TCR
registers, one for each channel. TCR register settings should be made only when TCNT operation
is stopped.
Bit
Bit Name
Initial Value
R/W
Description
7
CCLR2
0
R/W
Counter Clear 2 to 0
6
CCLR1
0
R/W
5
CCLR0
0
R/W
These bits select the TCNT counter clearing source.
See tables 9.3 and 9.4 for details.
4
CKEG1
0
R/W
Clock Edge 1 and 0
3
CKEG0
0
R/W
These bits select the input clock edge. When the
input clock is counted using both edges, the input
clock period is halved (e.g. φ/4 both edges = φ/2
rising edge). If phase counting mode is used on
channels 1, 2, 4, and 5, this setting is ignored and
the phase counting mode setting has priority. Internal
clock edge selection is valid when the input clock is
φ/4 or slower. This setting is ignored if the input clock
is φ/1, or when overflow/underflow of another
channel is selected.
00: Count at rising edge
01: Count at falling edge
1x: Count at both edges
Legend: x: Don’t care
2
TPSC2
0
R/W
Time Prescaler 2 to 0
1
TPSC1
0
R/W
0
TPSC0
0
R/W
These bits select the TCNT counter clock. The clock
source can be selected independently for each
channel. See tables 9.5 to 9.10 for details.
Rev. 3.00 Feb 22, 2006 page 258 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.3
CCLR2 to CCLR0 (Channels 0 and 3)
Channel
Bit 7
CCLR2
Bit 6
CCLR1
Bit 5
CCLR0
Description
0, 3
0
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
1
1
0
1
0
TCNT clearing disabled
1
TCNT cleared by TGRC compare match/input
2
capture*
0
TCNT cleared by TGRD compare match/input
2
capture*
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. When TGRC or TGRD is used as a buffer register, TCNT is not cleared because the
buffer register setting has priority, and compare match/input capture does not occur.
Table 9.4
CCLR2 to CCLR0 (Channels 1, 2, 4, and 5)
Channel
Bit 7
Bit 6
2
Reserved* CCLR1
Bit 5
CCLR0
Description
1, 2, 4, 5
0
0
TCNT clearing disabled
1
TCNT cleared by TGRA compare match/input
capture
0
TCNT cleared by TGRB compare match/input
capture
1
TCNT cleared by counter clearing for another
channel performing synchronous clearing/
1
synchronous operation*
0
1
Notes: 1. Synchronous operation setting is performed by setting the SYNC bit in TSYR to 1.
2. Bit 7 is reserved in channels 1, 2, 4, and 5. It is always read as 0 and cannot be
modified.
Rev. 3.00 Feb 22, 2006 page 259 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.5
TPSC2 to TPSC0 (Channel 0)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
0
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
1
1
0
1
Table 9.6
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
External clock: counts on TCLKD pin input
TPSC2 to TPSC0 (Channel 1)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
1
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
Internal clock: counts on φ/256
1
Counts on TCNT2 overflow/underflow
1
1
0
1
Note: This setting is ignored when channel 1 is in phase counting mode.
Rev. 3.00 Feb 22, 2006 page 260 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.7
TPSC2 to TPSC0 (Channel 2)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
2
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
1
1
0
1
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKB pin input
0
External clock: counts on TCLKC pin input
1
Internal clock: counts on φ/1024
Note: This setting is ignored when channel 2 is in phase counting mode.
Table 9.8
TPSC2 to TPSC0 (Channel 3)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
3
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
Internal clock: counts on φ/1024
0
Internal clock: counts on φ/256
1
Internal clock: counts on φ/4096
1
1
0
1
Rev. 3.00 Feb 22, 2006 page 261 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.9
TPSC2 to TPSC0 (Channel 4)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
4
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
1
1
0
1
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/1024
1
Counts on TCNT5 overflow/underflow
Note: This setting is ignored when channel 4 is in phase counting mode.
Table 9.10 TPSC2 to TPSC0 (Channel 5)
Channel
Bit 2
TPSC2
Bit 1
TPSC1
Bit 0
TPSC0
Description
5
0
0
0
Internal clock: counts on φ/1
1
Internal clock: counts on φ/4
0
Internal clock: counts on φ/16
1
Internal clock: counts on φ/64
0
External clock: counts on TCLKA pin input
1
External clock: counts on TCLKC pin input
0
Internal clock: counts on φ/256
1
External clock: counts on TCLKD pin input
1
1
0
1
Note: This setting is ignored when channel 5 is in phase counting mode.
Rev. 3.00 Feb 22, 2006 page 262 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.2
Timer Mode Register (TMDR)
TMDR registers are used to set the operating mode for each channel. The TPU has six TMDR
registers, one for each channel. TMDR register settings should be made only when TCNT
operation is stopped.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
—
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
5
BFB
0
R/W
Buffer Operation B
Specifies whether TGRB is to operate in the normal
way, or TGRB and TGRD are to be used together for
buffer operation. When TGRD is used as a buffer
register, TGRD input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRD, bit
5 is reserved. It is always read as 0 and cannot be
modified.
0: TGRB operates normally
1: TGRB and TGRD used together for buffer
operation
4
BFA
0
R/W
Buffer Operation A
Specifies whether TGRA is to operate in the normal
way, or TGRA and TGRC are to be used together for
buffer operation. When TGRC is used as a buffer
register, TGRC input capture/output compare is not
generated.
In channels 1, 2, 4, and 5, which have no TGRC, bit
4 is reserved. It is always read as 0 and cannot be
modified.
0: TGRA operates normally
1: TGRA and TGRC used together for buffer
operation
3
MD3
0
R/W
Modes 3 to 0
2
MD2
0
R/W
These bits are used to set the timer operating mode.
1
MD1
0
R/W
0
MD0
0
R/W
MD3 is a reserved bit. In a write, it should always be
written with 0. See table 9.11 for details.
Rev. 3.00 Feb 22, 2006 page 263 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.11 MD3 to MD0
Bit 3
1
MD3*
Bit 2
2
MD2*
Bit 1
MD1
Bit 0
MD0
Description
0
0
0
0
Normal operation
1
Reserved
0
PWM mode 1
1
PWM mode 2
0
Phase counting mode 1
1
Phase counting mode 2
0
Phase counting mode 3
1
Phase counting mode 4
x
—
1
1
0
1
1
x
x
Legend: x: Don’t care
Notes: 1. MD3 is a reserved bit. In a write, it should always be written with 0.
2. Phase counting mode cannot be set for channels 0 and 3. In this case, 0 should always
be written to MD2.
Rev. 3.00 Feb 22, 2006 page 264 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.3
Timer I/O Control Register (TIOR)
TIOR registers control the TGR registers. The TPU has eight TIOR registers, two each for
channels 0 and 3, and one each for channels 1, 2, 4, and 5. Care is required since TIOR is affected
by the TMDR setting.
The initial output specified by TIOR is valid when the counter is stopped (the CST bit in TSTR is
cleared to 0). Note also that, in PWM mode 2, the output at the point at which the counter is
cleared to 0 is specified.
When TGRC or TGRD is designated for buffer operation, this setting is invalid and the register
operates as a buffer register.
TIORH_0, TIOR_1, TIOR_2, TIORH_3, TIOR_4, TIOR_5
Bit
Bit Name
Initial
Value
R/W
Description
7
IOB3
0
R/W
I/O Control B3 to B0
6
IOB2
0
R/W
5
IOB1
0
R/W
4
IOB0
0
R/W
Specify the function of TGRB.
For details, see tables 9.12, 9.14, 9.15, 9.16, 9.18,
and 9.19.
3
IOA3
0
R/W
I/O Control A3 to A0
2
IOA2
0
R/W
1
IOA1
0
R/W
0
IOA0
0
R/W
Specify the function of TGRA.
For details, see tables 9.20, 9.22, 9.23, 9.24, 9.26,
and 9.27.
TIORL_0, TIORL_3
Bit
Bit Name
Initial
Value
R/W
Description
7
IOD3
0
R/W
I/O Control D3 to D0
6
IOD2
0
R/W
5
IOD1
0
R/W
Specify the function of TGRD.
For details, see tables 9.13, and 9.17.
4
IOD0
0
R/W
3
IOC3
0
R/W
I/O Control C3 to C0
2
IOC2
0
R/W
1
IOC1
0
R/W
Specify the function of TGRC.
For details, see tables 9.21, and 9.25
0
IOC0
0
R/W
Rev. 3.00 Feb 22, 2006 page 265 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.12 TIORH_0
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_0
Function
0
0
0
0
Output
compare
register
1
TIOCB0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCB0 pin
Input capture at rising edge
Capture input source is TIOCB0 pin
Input capture at falling edge
1
x
Capture input source is TIOCB0 pin
x
x
Capture input source is channel 1/count clock
Input capture at TCNT_1 count- up/count-down*
Input capture at both edges
1
Legend: x: Don’t care
Note: * When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
Rev. 3.00 Feb 22, 2006 page 266 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.13 TIORL_0
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_0
Function
0
0
0
0
Output
compare
2
register*
1
TIOCD0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
2
register*
Capture input source is TIOCD0 pin
Input capture at rising edge
Capture input source is TIOCD0 pin
Input capture at falling edge
1
x
x
x
Capture input source is TIOCD0 pin
Input capture at both edges
1
Capture input source is channel 1/count clock
Input capture at TCNT_1 count-up/count-down*
1
Legend: x: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_1 are set to B'000 and φ/1 is used as the TCNT_1
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_0 is set to 1 and TGRD_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 3.00 Feb 22, 2006 page 267 of 624
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Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.14 TIOR_1
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_1
Function
0
0
0
0
Output
compare
register
1
TIOCB1 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCB1 pin
Input capture at rising edge
Capture input source is TIOCB1 pin
Input capture at falling edge
1
x
Capture input source is TIOCB1 pin
x
x
TGRC_0 compare match/input capture
Input capture at both edges
1
Input capture at generation of TGRC_0 compare
match/input capture
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 268 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.15 TIOR_2
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_2
Function
0
0
0
0
Output
compare
register
1
TIOCB2 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
x
0
0
1
Input
capture
register
Capture input source is TIOCB2 pin
Input capture at rising edge
Capture input source is TIOCB2 pin
Input capture at falling edge
1
x
Capture input source is TIOCB2 pin
Input capture at both edges
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 269 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.16 TIORH_3
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_3
Function
0
0
0
0
Output
compare
register
1
TIOCB3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCB3 pin
Input capture at rising edge
Capture input source is TIOCB3 pin
Input capture at falling edge
1
x
Capture input source is TIOCB3 pin
x
x
Capture input source is channel 4/count clock
Input capture at both edges
1
Input capture at TCNT_4 count-up/count-down*
Legend: x: Don’t care
Note: * When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
Rev. 3.00 Feb 22, 2006 page 270 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.17 TIORL_3
Description
Bit 7
IOD3
Bit 6
IOD2
Bit 5
IOD1
Bit 4
IOD0
TGRD_3
Function
0
0
0
0
Output
compare
2
register*
1
TIOCD3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
2
register*
Capture input source is TIOCD3 pin
Input capture at rising edge
Capture input source is TIOCD3 pin
Input capture at falling edge
1
x
x
x
Capture input source is TIOCD3 pin
Input capture at both edges
1
Capture input source is channel 4/count clock
Input capture at TCNT_4 count-up/count-down*
1
Legend: x: Don’t care
Notes: 1. When bits TPSC2 to TPSC0 in TCR_4 are set to B'000 and φ/1 is used as the TCNT_4
count clock, this setting is invalid and input capture is not generated.
2. When the BFB bit in TMDR_3 is set to 1 and TGRD_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 3.00 Feb 22, 2006 page 271 of 624
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Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.18 TIOR_4
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_4
Function
0
0
0
0
Output
compare
register
1
TIOCB4 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCB4 pin
Input capture at rising edge
Capture input source is TIOCB4 pin
Input capture at falling edge
1
x
Capture input source is TIOCB4 pin
x
x
Capture input source is TGRC_3 compare
match/input capture
Input capture at both edges
1
Input capture at generation of TGRC_3 compare
match/input capture
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 272 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.19 TIOR_5
Description
Bit 7
IOB3
Bit 6
IOB2
Bit 5
IOB1
Bit 4
IOB0
TGRB_5
Function
0
0
0
0
Output
compare
register
1
TIOCB5 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
x
0
0
1
Input
capture
register
Capture input source is TIOCB5 pin
Input capture at rising edge
Capture input source is TIOCB5 pin
Input capture at falling edge
1
x
Capture input source is TIOCB5 pin
Input capture at both edges
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 273 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.20 TIORH_0
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_0
Function
0
0
0
0
Output
compare
register
1
TIOCA0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCA0 pin
Input capture at rising edge
Capture input source is TIOCA0 pin
Input capture at falling edge
1
x
Capture input source is TIOCA0 pin
x
x
Capture input source is channel 1/count clock
Input capture at both edges
1
Input capture at TCNT_1 count-up/count-down
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 274 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.21 TIORL_0
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_0
Function
0
0
0
0
Output
compare
register*
1
TIOCC0 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*
Capture input source is TIOCC0 pin
Input capture at rising edge
Capture input source is TIOCC0 pin
Input capture at falling edge
1
x
Capture input source is TIOCC0 pin
x
x
Capture input source is channel 1/count clock
Input capture at both edges
1
Input capture at TCNT_1 count-up/count-down
Legend: x: Don’t care
Note: * When the BFA bit in TMDR_0 is set to 1 and TGRC_0 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 3.00 Feb 22, 2006 page 275 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.22 TIOR_1
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_1
Function
0
0
0
0
Output
compare
register
1
TIOCA1 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCA1 pin
Input capture at rising edge
Capture input source is TIOCA1 pin
Input capture at falling edge
1
x
Capture input source is TIOCA1 pin
x
x
Capture input source is TGRA_0 compare
match/input capture
Input capture at both edges
1
Input capture at generation of channel
0/TGRA_0 compare match/input capture
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 276 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.23 TIOR_2
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_2
Function
0
0
0
0
Output
compare
register
1
TIOCA2 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
x
0
0
1
Input
capture
register
Capture input source is TIOCA2 pin
Input capture at rising edge
Capture input source is TIOCA2 pin
Input capture at falling edge
1
x
Capture input source is TIOCA2 pin
Input capture at both edges
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 277 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.24 TIORH_3
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_3
Function
0
0
0
0
Output
compare
register
1
TIOCA3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCA3 pin
Input capture at rising edge
Capture input source is TIOCA3 pin
Input capture at falling edge
1
x
Capture input source is TIOCA3 pin
x
x
Capture input source is channel 4/count clock
Input capture at both edges
1
Input capture at TCNT_4 count-up/count-down
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 278 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.25 TIORL_3
Description
Bit 3
IOC3
Bit 2
IOC2
Bit 1
IOC1
Bit 0
IOC0
TGRC_3
Function
0
0
0
0
Output
compare
register*
1
TIOCC3 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
1
Input
capture
register*
Capture input source is TIOCC3 pin
Input capture at rising edge
Capture input source is TIOCC3 pin
Input capture at falling edge
1
x
Capture input source is TIOCC3 pin
x
x
Capture input source is channel 4/count clock
Input capture at both edges
1
Input capture at TCNT_4 count-up/count-down
Legend: x: Don’t care
Note: * When the BFA bit in TMDR_3 is set to 1 and TGRC_3 is used as a buffer register, this
setting is invalid and input capture/output compare is not generated.
Rev. 3.00 Feb 22, 2006 page 279 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.26 TIOR_4
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_4
Function
0
0
0
0
Output
compare
register
1
TIOCA4 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
0
0
0
Input
capture
register
1
Capture input source is TIOCA4 pin
Input capture at rising edge
Capture input source is TIOCA4 pin
Input capture at falling edge
1
x
Capture input source is TIOCA4 pin
x
x
Capture input source is TGRA_3 compare
match/input capture
Input capture at both edges
1
Input capture at generation of TGRA_3 compare
match/input capture
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 280 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.27 TIOR_5
Description
Bit 3
IOA3
Bit 2
IOA2
Bit 1
IOA1
Bit 0
IOA0
TGRA_5
Function
0
0
0
0
Output
compare
register
1
TIOCA5 Pin Function
Output disabled
Initial output is 0 output
0 output at compare match
1
0
Initial output is 0 output
1 output at compare match
1
Initial output is 0 output
Toggle output at compare match
1
0
0
Output disabled
1
Initial output is 1 output
0 output at compare match
1
0
Initial output is 1 output
1 output at compare match
1
Initial output is 1 output
Toggle output at compare match
1
x
0
0
1
Input
capture
register
Input capture source is TIOCA5 pin
Input capture at rising edge
Input capture source is TIOCA5 pin
Input capture at falling edge
1
x
Input capture source is TIOCA5 pin
Input capture at both edges
Legend: x: Don’t care
Rev. 3.00 Feb 22, 2006 page 281 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.4
Timer Interrupt Enable Register (TIER)
TIER registers control enabling or disabling of interrupt requests for each channel. The TPU has
six TIER registers, one for each channel.
Bit
Bit Name
Initial value
R/W
Description
7
TTGE
0
R/W
A/D Conversion Start Request Enable
Enables or disables generation of A/D conversion
start requests by TGRA input capture/compare
match.
0: A/D conversion start request generation disabled
1: A/D conversion start request generation enabled
6
—
1
—
Reserved
This bit is always read as 1 and cannot be modified.
5
TCIEU
0
R/W
Underflow Interrupt Enable
Enables or disables interrupt requests (TCIU) by the
TCFU flag when the TCFU flag in TSR is set to 1 in
channels 1, 2, 4, and 5.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
0: Interrupt requests (TCIU) by TCFU disabled
1: Interrupt requests (TCIU) by TCFU enabled
4
TCIEV
0
R/W
Overflow Interrupt Enable
Enables or disables interrupt requests (TCIV) by the
TCFV flag when the TCFV flag in TSR is set to 1.
0: Interrupt requests (TCIV) by TCFV disabled
1: Interrupt requests (TCIV) by TCFV enabled
3
TGIED
0
R/W
TGR Interrupt Enable D
Enables or disables interrupt requests (TGID) by the
TGFD bit when the TGFD bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGID) by TGFD bit disabled
1: Interrupt requests (TGID) by TGFD bit enabled
Rev. 3.00 Feb 22, 2006 page 282 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial value
R/W
Description
2
TGIEC
0
R/W
TGR Interrupt Enable C
Enables or disables interrupt requests (TGIC) by the
TGFC bit when the TGFC bit in TSR is set to 1 in
channels 0 and 3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
0: Interrupt requests (TGIC) by TGFC bit disabled
1: Interrupt requests (TGIC) by TGFC bit enabled
1
TGIEB
0
R/W
TGR Interrupt Enable B
Enables or disables interrupt requests (TGIB) by the
TGFB bit when the TGFB bit in TSR is set to 1.
0: Interrupt requests (TGIB) by TGFB bit disabled
1: Interrupt requests (TGIB) by TGFB bit enabled
0
TGIEA
0
R/W
TGR Interrupt Enable A
Enables or disables interrupt requests (TGIA) by the
TGFA bit when the TGFA bit in TSR is set to 1.
0: Interrupt requests (TGIA) by TGFA bit disabled
1: Interrupt requests (TGIA) by TGFA bit enabled
Rev. 3.00 Feb 22, 2006 page 283 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.5
Timer Status Register (TSR)
TSR registers indicate the status of each channel. The TPU has six TSR registers, one for each
channel.
Bit
Bit Name
Initial value
R/W
Description
7
TCFD
1
R
Count Direction Flag
Status flag that shows the direction in which TCNT
counts in channels 1, 2, 4, and 5.
In channels 0 and 3, bit 7 is reserved. It is always
read as 1 and cannot be modified.
0: TCNT counts down
1: TCNT counts up
6
—
1
—
Reserved
This bit is always read as 1 and cannot be modified.
5
TCFU
0
R/(W)*
Underflow Flag
Status flag that indicates that TCNT underflow has
occurred when channels 1, 2, 4, and 5 are set to
phase counting mode.
In channels 0 and 3, bit 5 is reserved. It is always
read as 0 and cannot be modified.
[Setting condition]
When the TCNT value underflows (changes from
H'0000 to H'FFFF)
[Clearing condition]
When 0 is written to TCFU after reading TCFU = 1
4
TCFV
0
R/(W)*
Overflow Flag
Status flag that indicates that TCNT overflow has
occurred.
[Setting condition]
When the TCNT value overflows (changes from
H'FFFF to H'0000)
[Clearing condition]
When 0 is written to TCFV after reading TCFV = 1
Rev. 3.00 Feb 22, 2006 page 284 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial value
R/W
Description
3
TGFD
0
R/(W)*
Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD
input capture or compare match in channels 0 and
3.
In channels 1, 2, 4, and 5, bit 3 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRD while TGRD is functioning
as output compare register
•
When TCNT value is transferred to TGRD by
input capture signal while TGRD is functioning
as input capture register
[Clearing conditions]
2
TGFC
0
R/(W)*
•
When DTC is activated by TGID interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFD after reading TGFD =
1
Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC
input capture or compare match in channels 0 and
3.
In channels 1, 2, 4, and 5, bit 2 is reserved. It is
always read as 0 and cannot be modified.
[Setting conditions]
•
When TCNT = TGRC while TGRC is functioning
as output compare register
•
When TCNT value is transferred to TGRC by
input capture signal while TGRC is functioning
as input capture register
[Clearing conditions]
•
When DTC is activated by TGIC interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFC after reading TGFC =
1
Rev. 3.00 Feb 22, 2006 page 285 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
Bit
Bit Name
Initial value
R/W
Description
1
TGFB
0
R/(W)*
Input Capture/Output Compare Flag B
Status flag that indicates the occurrence of TGRB
input capture or compare match.
[Setting conditions]
•
When TCNT = TGRB while TGRB is functioning
as output compare register
•
When TCNT value is transferred to TGRB by
input capture signal while TGRB is functioning
as input capture register
[Clearing conditions]
0
TGFA
0
R/(W)*
•
When DTC is activated by TGIB interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFB after reading TGFB =
1
Input Capture/Output Compare Flag A
Status flag that indicates the occurrence of TGRA
input capture or compare match.
[Setting conditions]
•
When TCNT = TGRA while TGRA is functioning
as output compare register
•
When TCNT value is transferred to TGRA by
input capture signal while TGRA is functioning
as input capture register
[Clearing conditions]
Note:
*
•
When DTC is activated by TGIA interrupt while
DISEL bit of MRB in DTC is 0
•
When 0 is written to TGFA after reading TGFA =
1
Only 0 can be written, for flag clearing.
Rev. 3.00 Feb 22, 2006 page 286 of 624
REJ09B0281-0300
Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.6
Timer Counter (TCNT)
The TCNT registers are 16-bit readable/writable counters. The TPU has six TCNT counters, one
for each channel.
The TCNT counters are initialized to H'0000 by a reset, or in hardware standby mode.
The TCNT counters cannot be accessed in 8-bit units; they must always be accessed as a 16-bit
unit.
9.3.7
Timer General Register (TGR)
The TGR registers are 16-bit readable/writable registers with a dual function as output compare
and input capture registers. The TPU has 16 TGR registers, four each for channels 0 and 3 and two
each for channels 1, 2, 4, and 5. TGRC and TGRD for channels 0 and 3 can also be designated for
operation as buffer registers. The TGR registers cannot be accessed in 8-bit units; they must
always be accessed as a 16-bit unit. TGR buffer register combinations are TGRA–TGRC and
TGRB–TGRD.
9.3.8
Timer Start Register (TSTR)
TSTR selects operation/stoppage for channels 0 to 5. When setting the operating mode in TMDR
or setting the count clock in TCR, first stop the TCNT counter.
Bit
Bit Name
Initial value
R/W
Description
7, 6
—
All 0
—
Reserved
These bits should always be written with 0.
5
CST5
0
R/W
Counter Start 5 to 0
4
CST4
0
R/W
These bits select operation or stoppage for TCNT.
3
CST3
0
R/W
2
CST2
0
R/W
1
CST1
0
R/W
0
CST0
0
R/W
If 0 is written to the CST bit during operation with the
TIOC pin designated for output, the counter stops but
the TIOC pin output compare output level is retained.
If TIOR is written to when the CST bit is cleared to 0,
the pin output level will be changed to the set initial
output value.
0: TCNT_5 to TCNT_0 count operation is stopped
1: TCNT_5 to TCNT_0 performs count operation
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.3.9
Timer Synchronous Register (TSYR)
TSYR selects independent operation or synchronous operation for the TCNT counters of channels
0 to 5. A channel performs synchronous operation when the corresponding bit in TSYR is set to 1.
Bit
Bit Name
Initial value
R/W
Description
7, 6
—
All 0
R/W
Reserved
These bits should always be written with 0.
5
SYNC5
0
R/W
Timer Synchronization 5 to 0
4
SYNC4
0
R/W
3
SYNC3
0
R/W
These bits select whether operation is independent
of or synchronized with other channels.
2
SYNC2
0
R/W
1
SYNC1
0
R/W
0
SYNC0
0
R/W
When synchronous operation is selected,
synchronous presetting of multiple channels, and
synchronous clearing through counter clearing on
another channel are possible.
To set synchronous operation, the SYNC bits for at
least two channels must be set to 1. To set
synchronous clearing, in addition to the SYNC bit,
the TCNT clearing source must also be set by means
of bits CCLR2 to CCLR0 in TCR.
0: TCNT_5 to TCNT_0 operates independently
(TCNT presetting /clearing is unrelated to
other channels)
1: TCNT_5 to TCNT_0 performs synchronous
operation (TCNT synchronous presetting/
synchronous clearing is possible)
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.4
Operation
9.4.1
Basic Functions
Each channel has a TCNT and TGR register. TCNT performs up-counting, and is also capable of
free-running operation, periodic counting, and external event counting.
Each TGR can be used as an input capture register or output compare register.
Counter Operation: When one of bits CST0 to CST5 is set to 1 in TSTR, the TCNT counter for
the corresponding channel starts counting. TCNT can operate as a free-running counter, periodic
counter, and so on.
1. Example of count operation setting procedure
Figure 9.2 shows an example of the count operation setting procedure.
[1] Select the counter
clock with bits
TPSC2 to TPSC0 in
TCR. At the same
time, select the
input clock edge
with bits CKEG1
and CKEG0 in TCR.
Operation selection
Select counter clock
[1]
Periodic counter
Select counter clearing source
[2]
Select output compare register
[3]
Set period
[4]
Start count
[5]
<Periodic counter>
[2] For periodic counter
operation, select the
TGR to be used as
the TCNT clearing
source with bits
CCLR2 to CCLR0 in
TCR.
Free-running counter
[3] Designate the TGR
selected in [2] as an
output compare
register by means of
TIOR.
[4] Set the periodic
counter cycle in the
TGR selected in [2].
Start count
<Free-running counter>
[5]
[5] Set the CST bit in
TSTR to 1 to start
the counter
operation.
Figure 9.2 Example of Counter Operation Setting Procedure
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Section 9 16-Bit Timer Pulse Unit (TPU)
2. Free-running count operation and periodic count operation
Immediately after a reset, the TPU’s TCNT counters are all designated as free-running
counters. When the relevant bit in TSTR is set to 1 the corresponding TCNT counter starts upcount operation as a free-running counter. When TCNT overflows (changes from H'FFFF to
H'0000), the TCFV bit in TSR is set to 1. If the value of the corresponding TCIEV bit in TIER
is 1 at this point, the TPU requests an interrupt. After overflow, TCNT starts counting up again
from H'0000.
Figure 9.3 illustrates free-running counter operation.
TCNT value
H'FFFF
H'0000
Time
CST bit
TCFV
Figure 9.3 Free-Running Counter Operation
When compare match is selected as the TCNT clearing source, the TCNT counter for the
relevant channel performs periodic count operation. The TGR register for setting the period is
designated as an output compare register, and counter clearing by compare match is selected
by means of bits CCLR2 to CCLR0 in TCR. After the settings have been made, TCNT starts
count-up operation as a periodic counter when the corresponding bit in TSTR is set to 1. When
the count value matches the value in TGR, the TGF bit in TSR is set to 1 and TCNT is cleared
to H'0000.
If the value of the corresponding TGIE bit in TIER is 1 at this point, the TPU requests an
interrupt. After a compare match, TCNT starts counting up again from H'0000.
Figure 9.4 illustrates periodic counter operation.
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Section 9 16-Bit Timer Pulse Unit (TPU)
Counter cleared by TGR
compare match
TCNT value
TGR
H'0000
Time
CST bit
Flag cleared by software or
DTC activation
TGF
Figure 9.4 Periodic Counter Operation
Waveform Output by Compare Match: The TPU can perform 0, 1, or toggle output from the
corresponding output pin using a compare match.
1. Example of setting procedure for waveform output by compare match
Figure 9.5 shows an example of the setting procedure for waveform output by a compare
match.
Output selection
Select waveform output mode
[1]
[1] Select initial value 0 output or 1 output, and
compare match output value 0 output, 1 output,
or toggle output, by means of TIOR. The set
initial value is output at the TIOC pin until the
first compare match occurs.
[2] Set the timing for compare match generation in
TGR.
Set output timing
[2]
Start count
[3]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
<Waveform output>
Figure 9.5 Example of Setting Procedure for Waveform Output by Compare Match
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Section 9 16-Bit Timer Pulse Unit (TPU)
2. Examples of waveform output operation
Figure 9.6 shows an example of 0 output/1 output.
In this example, TCNT has been designated as a free-running counter, and settings have been
made so that 1 is output by compare match A, and 0 is output by compare match B. When the
set level and the pin level match, the pin level does not change.
TCNT value
H'FFFF
TGRA
TGRB
Time
H'0000
No change
No change
1 output
TIOCA
No change
TIOCB
No change
0 output
Figure 9.6 Example of 0 Output/1 Output Operation
Figure 9.7 shows an example of toggle output.
In this example TCNT has been designated as a periodic counter (with counter clearing
performed by compare match B), and settings have been made so that output is toggled by both
compare match A and compare match B.
TCNT value
Counter cleared by TGRB compare match
H'FFFF
TGRB
TGRA
Time
H'0000
Toggle output
TIOCB
Toggle output
TIOCA
Figure 9.7 Example of Toggle Output Operation
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Section 9 16-Bit Timer Pulse Unit (TPU)
Input Capture Function: The TCNT value can be transferred to TGR on detection of the TIOC
pin input edge.
Rising edge, falling edge, or both edges can be selected as the detection edge. For channels 0, 1, 3,
and 4, it is also possible to specify another channel’s counter input clock or compare match signal
as the input capture source.
Note: When another channel’s counter input clock is used as the input capture input for channels
0 and 3, φ/1 should not be selected as the counter input clock used for input capture input.
Input capture will not be generated if φ/1 is selected.
1. Example of setting procedure for input capture operation
Figure 9.8 shows an example of the setting procedure for input capture operation.
[1] Designate TGR as an input capture register by
means of TIOR, and select the input capture
source and input signal edge (rising edge, falling
edge, or both edges).
Input selection
Select input capture input
[1]
Start count
[2]
[2] Set the CST bit in TSTR to 1 to start the count
operation.
<Input capture operation>
Figure 9.8 Example of Setting Procedure for Input Capture Operation
2. Example of input capture operation
Figure 9.9 shows an example of input capture operation.
In this example both rising and falling edges have been selected as the TIOCA pin input
capture input edge, falling edge has been selected as the TIOCB pin input capture input edge,
and counter clearing by TGRB input capture has been designated for TCNT.
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Section 9 16-Bit Timer Pulse Unit (TPU)
Counter cleared by TIOCB
input (falling edge)
TCNT value
H'0180
H'0160
H'0010
H'0005
Time
H'0000
TIOCA
TGRA
H'0005
H'0160
H'0010
TIOCB
TGRB
H'0180
Figure 9.9 Example of Input Capture Operation
9.4.2
Synchronous Operation
In synchronous operation, the values in multiple TCNT counters can be rewritten simultaneously
(synchronous presetting). Also, multiple of TCNT counters can be cleared simultaneously
(synchronous clearing) by making the appropriate setting in TCR.
Synchronous operation enables TGR to be incremented with respect to a single time base.
Channels 0 to 5 can all be designated for synchronous operation.
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Section 9 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation Setting Procedure: Figure 9.10 shows an example of the
synchronous operation setting procedure.
Synchronous operation
selection
Set synchronous
operation
[1]
Synchronous presetting
Set TCNT
Synchronous clearing
[2]
Clearing
source generation
channel?
No
Yes
<Synchronous presetting>
Select counter
clearing source
[3]
Set synchronous
counter clearing
[4]
Start count
[5]
Start count
[5]
<Counter clearing>
<Synchronous clearing>
[1] Set to 1 the SYNC bits in TSYR corresponding to the channels to be designated for synchronous operation.
[2] When the TCNT counter of any of the channels designated for synchronous operation is written to, the
same value is simultaneously written to the other TCNT counters.
[3] Use bits CCLR2 to CCLR0 in TCR to specify TCNT clearing by input capture/output compare, etc.
[4] Use bits CCLR2 to CCLR0 in TCR to designate synchronous clearing for the counter clearing source.
[5] Set to 1 the CST bits in TSTR for the relevant channels, to start the count operation.
Figure 9.10 Example of Synchronous Operation Setting Procedure
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Section 9 16-Bit Timer Pulse Unit (TPU)
Example of Synchronous Operation: Figure 9.11 shows an example of synchronous operation.
In this example, synchronous operation and PWM mode 1 have been designated for channels 0 to
2, TGRB_0 compare match has been set as the channel 0 counter clearing source, and
synchronous clearing has been set for the channel 1 and 2 counter clearing source.
Three-phase PWM waveforms are output from pins TIOCA0, TIOCA1, and TIOCA2. At this
time, synchronous presetting, and synchronous clearing by TGRB_0 compare match, is performed
for channel 0 to 2 TCNT counters, and the data set in TGRB_0 is used as the PWM cycle.
For details on PWM modes, see section 9.4.5, PWM Modes.
Synchronous clearing by TGRB_0 compare match
TCNT0 to TCNT2 values
TGRB_0
TGRB_1
TGRA_0
TGRB_2
TGRA_1
TGRA_2
Time
H'0000
TIOCA_0
TIOCA_1
TIOCA_2
Figure 9.11 Example of Synchronous Operation
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.3
Buffer Operation
Buffer operation, provided for channels 0 and 3, enables TGRC and TGRD to be used as buffer
registers.
Buffer operation differs depending on whether TGR has been designated as an input capture
register or a compare match register.
Table 9.28 shows the register combinations used in buffer operation.
Table 9.28 Register Combinations in Buffer Operation
Channel
Timer General Register
Buffer Register
0
TGRA_0
TGRC_0
TGRB_0
TGRD_0
TGRA_3
TGRC_3
TGRB_3
TGRD_3
3
• When TGR is an output compare register
When a compare match occurs, the value in the buffer register for the corresponding channel is
transferred to the timer general register.
This operation is illustrated in figure 9.12.
Compare match signal
Buffer register
Timer general
register
Comparator
TCNT
Figure 9.12 Compare Match Buffer Operation
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Section 9 16-Bit Timer Pulse Unit (TPU)
• When TGR is an input capture register
When input capture occurs, the value in TCNT is transferred to TGR and the value previously
held in the timer general register is transferred to the buffer register.
This operation is illustrated in figure 9.13.
Input capture
signal
Timer general
register
Buffer register
TCNT
Figure 9.13 Input Capture Buffer Operation
Example of Buffer Operation Setting Procedure: Figure 9.14 shows an example of the buffer
operation setting procedure.
[1] Designate TGR as an input capture register or
output compare register by means of TIOR.
Buffer operation
[1]
[2] Designate TGR for buffer operation with bits
BFA and BFB in TMDR.
Set buffer operation
[2]
[3] Set the CST bit in TSTR to 1 to start the count
operation.
Start count
[3]
Select TGR function
<Buffer operation>
Figure 9.14 Example of Buffer Operation Setting Procedure
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Section 9 16-Bit Timer Pulse Unit (TPU)
Examples of Buffer Operation:
1. When TGR is an output compare register
Figure 9.15 shows an operation example in which PWM mode 1 has been designated for
channel 0, and buffer operation has been designated for TGRA and TGRC. The settings used
in this example are TCNT clearing by compare match B, 1 output at compare match A, and 0
output at compare match B.
As buffer operation has been set, when compare match A occurs the output changes and the
value in buffer register TGRC is simultaneously transferred to timer general register TGRA.
This operation is repeated each time compare match A occurs.
For details on PWM modes, see section 9.4.5, PWM Modes.
TCNT value
TGRB_0
H'0520
H'0450
H'0200
TGRA_0
Time
H'0000
TGRC_0 H'0200
H'0450
H'0520
Transfer
TGRA_0
H'0200
H'0450
TIOCA
Figure 9.15 Example of Buffer Operation (1)
2. When TGR is an input capture register
Figure 9.16 shows an operation example in which TGRA has been designated as an input
capture register, and buffer operation has been designated for TGRA and TGRC.
Counter clearing by TGRA input capture has been set for TCNT, and both rising and falling
edges have been selected as the TIOCA pin input capture input edge.
As buffer operation has been set, when the TCNT value is stored in TGRA upon occurrence of
input capture A, the value previously stored in TGRA is simultaneously transferred to TGRC.
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Section 9 16-Bit Timer Pulse Unit (TPU)
TCNT value
H'0F07
H'09FB
H'0532
H'0000
Time
TIOCA
H'0532
TGRA
TGRC
H'0F07
H'09FB
H'0532
H'0F07
Figure 9.16 Example of Buffer Operation (2)
9.4.4
Cascaded Operation
In cascaded operation, two 16-bit counters for different channels are used together as a 32-bit
counter.
This function works by counting the channel 1 (channel 4) counter clock at overflow/underflow of
TCNT_2 (TCNT_5) as set in bits TPSC2 to TPSC0 in TCR.
Underflow occurs only when the lower 16-bit TCNT is in phase-counting mode.
Table 9.29 shows the register combinations used in cascaded operation.
Note: When phase counting mode is set for channel 1 or 4, the counter clock setting is invalid
and the counter operates independently in phase counting mode.
Table 9.29 Cascaded Combinations
Combination
Upper 16 Bits
Lower 16 Bits
Channels 1 and 2
TCNT_1
TCNT_2
Channels 4 and 5
TCNT_4
TCNT_5
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Section 9 16-Bit Timer Pulse Unit (TPU)
Example of Cascaded Operation Setting Procedure: Figure 9.17 shows an example of the
setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
(channel 4) TCR to B'1111 to select TCNT_2
(TCNT_5) overflow/underflow counting.
[2] Set the CST bit in TSTR for the upper and lower
channel to 1 to start the count operation.
<Cascaded operation>
Figure 9.17 Cascaded Operation Setting Procedure
Examples of Cascaded Operation: Figure 9.18 illustrates the operation when counting upon
TCNT_2 overflow/underflow has been set for TCNT_1, TGRA_1 and TGRA_2 have been
designated as input capture registers, and the TIOC pin rising edge has been selected.
When a rising edge is input to the TIOCA1 and TIOCA2 pins simultaneously, the upper 16 bits of
the 32-bit data are transferred to TGRA_1, and the lower 16 bits to TGRA_2.
TCNT_1
clock
TCNT_1
H'03A1
H'03A2
TCNT_2
clock
TCNT_2
H'FFFF
H'0000
H'0001
TIOCA1,
TIOCA2
TGRA_1
H'03A2
TGRA_2
H'0000
Figure 9.18 Example of Cascaded Operation (1)
Figure 9.19 illustrates the operation when counting upon TCNT_2 overflow/underflow has been
set for TCNT_1, and phase counting mode has been designated for channel 2.
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Section 9 16-Bit Timer Pulse Unit (TPU)
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
TCLKC
TCLKD
TCNT_2
FFFD
TCNT_1
FFFE
FFFF
0000
0000
0001
0002
0001
0000
0001
FFFF
0000
Figure 9.19 Example of Cascaded Operation (2)
9.4.5
PWM Modes
In PWM mode, PWM waveforms are output from the output pins. 0, 1, or toggle output can be
selected as the output level in response to compare match of each TGR.
Settings of TGR registers can output a PWM waveform in the range of 0–% to 100–% duty cycle.
Designating TGR compare match as the counter clearing source enables the cycle to be set in that
register. All channels can be designated for PWM mode independently. Synchronous operation is
also possible.
There are two PWM modes, as described below.
• PWM mode 1
PWM output is generated from the TIOCA and TIOCC pins by pairing TGRA with TGRB and
TGRC with TGRD. The outputs specified by bits IOA3 to IOA0 and IOC3 to IOC0 in TIOR
are output from the TIOCA and TIOCC pins at compare matches A and C, respectively. The
outputs specified by bits IOB3 to IOB0 and IOD3 to IOD0 in TIOR are output at compare
matches B and D, respectively. The initial output value is the value set in TGRA or TGRC. If
the set values of paired TGRs are identical, the output value does not change when a compare
match occurs.
In PWM mode 1, a maximum 8-phase PWM output is possible.
• PWM mode 2
PWM output is generated using one TGR as the cycle register and the others as duty cycle
registers. The output specified in TIOR is performed by means of compare matches. Upon
counter clearing by a synchronization register compare match, the output value of each pin is
the initial value set in TIOR. If the set values of the cycle and duty cycle registers are identical,
the output value does not change when a compare match occurs.
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Section 9 16-Bit Timer Pulse Unit (TPU)
In PWM mode 2, a maximum 15-phase PWM output is possible by combined use with
synchronous operation.
The correspondence between PWM output pins and registers is shown in table 9.30.
Table 9.30 PWM Output Registers and Output Pins
Output Pins
Channel
Registers
PWM Mode 1
PWM Mode 2
0
TGRA_0
TIOCA0
TIOCA0
TGRB_0
TGRC_0
TIOCB0
TIOCC0
TGRD_0
1
TGRA_1
TIOCD0
TIOCA1
TGRB_1
2
TGRA_2
TGRA_3
TIOCA2
TIOCA3
TGRA_4
TIOCC3
TGRA_5
TGRB_5
TIOCC3
TIOCD3
TIOCA4
TGRB_4
5
TIOCA3
TIOCB3
TGRD_3
4
TIOCA2
TIOCB2
TGRB_3
TGRC_3
TIOCA1
TIOCB1
TGRB_2
3
TIOCC0
TIOCA4
TIOCB4
TIOCA5
TIOCA5
TIOCB5
Note: In PWM mode 2, PWM output is not possible for the TGR register in which the cycle is set.
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Section 9 16-Bit Timer Pulse Unit (TPU)
Example of PWM Mode Setting Procedure: Figure 9.20 shows an example of the PWM mode
setting procedure.
PWM mode
Select counter clock
[1]
[1] Select the counter clock with bits TPSC2 to
TPSC0 in TCR. At the same time, select the
input clock edge with bits CKEG1 and CKEG0 in
TCR.
[2] Use bits CCLR2 to CCLR0 in TCR to select the
TGR to be used as the TCNT clearing source.
Select counter clearing source
Select waveform output level
Set TGR
[2]
[3]
[4]
[3] Use TIOR to designate the TGR as an output
compare register, and select the initial value and
output value.
[4] Set the cycle in the TGR selected in [2], and
set the duty in the other TGRs.
[5] Select the PWM mode with bits MD3 to MD0 in
TMDR.
Set PWM mode
[5]
Start count
[6]
[6] Set the CST bit in TSTR to 1 to start the count
operation.
<PWM mode>
Figure 9.20 Example of PWM Mode Setting Procedure
Examples of PWM Mode Operation: Figure 9.21 shows an example of PWM mode 1 operation.
In this example, TGRA compare match is set as the TCNT clearing source, 0 is set for the TGRA
initial output value and output value, and 1 is set as the TGRB output value.
In this case, the value set in TGRA is used as the cycle, and the values set in TGRB registers as
the duty cycle.
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Section 9 16-Bit Timer Pulse Unit (TPU)
TCNT value
TGRA
Counter cleared by
TGRA compare match
TGRB
H'0000
Time
TIOCA
Figure 9.21 Example of PWM Mode Operation (1)
Figure 9.22 shows an example of PWM mode 2 operation.
In this example, synchronous operation is designated for channels 0 and 1, TGRB_1 compare
match is set as the TCNT clearing source, and 0 is set for the initial output value and 1 for the
output value of the other TGR registers (TGRA_0 to TGRD_0, TGRA_1), to output a 5-phase
PWM waveform.
In this case, the value set in TGRB_1 is used as the cycle, and the values set in the other TGRs as
the duty cycle.
TCNT value
Counter cleared by
TGRB_1 compare match
TGRB_1
TGRA_1
TGRD_0
TGRC_0
TGRB_0
TGRA_0
H'0000
Time
TIOCA0
TIOCB0
TIOCC0
TIOCD0
TIOCA1
Figure 9.22 Example of PWM Mode Operation (2)
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Section 9 16-Bit Timer Pulse Unit (TPU)
Figure 9.23 shows examples of PWM waveform output with 0% duty cycle and 100% duty cycle
in PWM mode.
TCNT value
TGRB rewritten
TGRA
TGRB
TGRB rewritten
TGRB
rewritten
H'0000
Time
0% duty
TIOCA
Output does not change when cycle register and duty register
compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB rewritten
TGRB
H'0000
Time
100% duty
TIOCA
Output does not change when cycle register and duty
register compare matches occur simultaneously
TCNT value
TGRB rewritten
TGRA
TGRB rewritten
TGRB
TGRB rewritten
Time
H'0000
100% duty
TIOCA
0% duty
Figure 9.23 Example of PWM Mode Operation (3)
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.4.6
Phase Counting Mode
In phase counting mode, the phase difference between two external clock inputs is detected and
TCNT is incremented/decremented accordingly. This mode can be set for channels 1, 2, 4, and 5.
When phase counting mode is set, an external clock is selected as the counter input clock and
TCNT operates as an up/down-counter regardless of the setting of bits TPSC2 to TPSC0 and bits
CKEG1 and CKEG0 in TCR. However, the functions of bits CCLR1 and CCLR0 in TCR, and of
TIOR, TIER, and TGR are valid, and input capture/compare match and interrupt functions can be
used.
This can be used for two-phase encoder pulse input.
When overflow occurs while TCNT is counting up, the TCFV flag in TSR is set; when underflow
occurs while TCNT is counting down, the TCFU flag is set.
The TCFD bit in TSR is the count direction flag. Reading the TCFD flag provides an indication of
whether TCNT is counting up or down.
Table 9.31 shows the correspondence between external clock pins and channels.
Table 9.31 Clock Input Pins in Phase Counting Mode
External Clock Pins
Channels
A-Phase
B-Phase
When channel 1 or 5 is set to phase counting mode
TCLKA
TCLKB
When channel 2 or 4 is set to phase counting mode
TCLKC
TCLKD
Example of Phase Counting Mode Setting Procedure: Figure 9.24 shows an example of the
phase counting mode setting procedure.
[1] Select phase counting mode with bits MD3 to
MD0 in TMDR.
[2] Set the CST bit in TSTR to 1 to start the count
operation.
Phase counting mode
Select phase counting mode
[1]
Start count
[2]
<Phase counting mode>
Figure 9.24 Example of Phase Counting Mode Setting Procedure
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Section 9 16-Bit Timer Pulse Unit (TPU)
Examples of Phase Counting Mode Operation: In phase counting mode, TCNT counts up or
down according to the phase difference between two external clocks. There are four modes,
according to the count conditions.
1. Phase counting mode 1
Figure 9.25 shows an example of phase counting mode 1 operation, and table 9.32 summarizes
the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 9.25 Example of Phase Counting Mode 1 Operation
Table 9.32 Up/Down-Count Conditions in Phase Counting Mode 1
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
High level
High level
Down-count
Low level
High level
Low level
Legend:
: Rising edge
: Falling edge
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Section 9 16-Bit Timer Pulse Unit (TPU)
2. Phase counting mode 2
Figure 9.26 shows an example of phase counting mode 2 operation, and table 9.33 summarizes
the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Up-count
Down-count
Time
Figure 9.26 Example of Phase Counting Mode 2 Operation
Table 9.33 Up/Down-Count Conditions in Phase Counting Mode 2
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Don’t care
Low level
Low level
High level
High level
Up-count
Don’t care
Low level
High level
Low level
Down-count
Legend:
: Rising edge
: Falling edge
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Section 9 16-Bit Timer Pulse Unit (TPU)
3. Phase counting mode 3
Figure 9.27 shows an example of phase counting mode 3 operation, and table 9.34 summarizes
the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 9.27 Example of Phase Counting Mode 3 Operation
Table 9.34
Up/Down-Count Conditions in Phase Counting Mode 3
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Don’t care
Low level
Low level
High level
Up-count
High level
Down-count
Low level
Don’t care
High level
Low level
Legend:
: Rising edge
: Falling edge
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Section 9 16-Bit Timer Pulse Unit (TPU)
4. Phase counting mode 4
Figure 9.28 shows an example of phase counting mode 4 operation, and table 9.35 summarizes
the TCNT up/down-count conditions.
TCLKA (channels 1 and 5)
TCLKC (channels 2 and 4)
TCLKB (channels 1 and 5)
TCLKD (channels 2 and 4)
TCNT value
Down-count
Up-count
Time
Figure 9.28 Example of Phase Counting Mode 4 Operation
Table 9.35 Up/Down-Count Conditions in Phase Counting Mode 4
TCLKA (Channels 1 and 5)
TCLKC (Channels 2 and 4)
TCLKB (Channels 1 and 5)
TCLKD (Channels 2 and 4)
High level
Operation
Up-count
Low level
Low level
Don’t care
High level
High level
Down-count
Low level
High level
Don’t care
Low level
Legend:
: Rising edge
: Falling edge
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Section 9 16-Bit Timer Pulse Unit (TPU)
Phase Counting Mode Application Example: Figure 9.29 shows an example in which phase
counting mode is designated for channel 1, and channel 1 is coupled with channel 0 to input servo
motor 2-phase encoder pulses in order to detect the position or speed.
Channel 1 is set to phase counting mode 1, and the encoder pulse A-phase and B-phase are input
to TCLKA and TCLKB.
Channel 0 operates with TCNT counter clearing by TGRC_0 compare match; TGRA_0 and
TGRC_0 are used for the compare match function, and are set with the speed control cycle and
position control cycle. TGRB_0 is used for input capture, with TGRB_0 and TGRD_0 operating
in buffer mode. The channel 1 counter input clock is designated as the TGRB_0 input capture
source, and detection of the pulse width of 2-phase encoder 4-multiplication pulses is performed.
TGRA_1 and TGRB_1 for channel 1 are designated for input capture, channel 0 TGRA_0 and
TGRC_0 compare matches are selected as the input capture source, and the up/down-counter
values for the control cycles are stored.
This procedure enables accurate position/speed detection to be achieved.
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Section 9 16-Bit Timer Pulse Unit (TPU)
Channel 1
TCLKA
TCLKB
Edge
detection
circuit
TCNT_1
TGRA_1
(speed cycle capture)
TGRB_1
(position cycle capture)
TCNT_0
TGRA_0
(speed control cycle)
+
-
TGRC_0
(position control cycle)
+
-
TGRB_0 (pulse width capture)
TGRD_0 (buffer operation)
Channel 0
Figure 9.29 Phase Counting Mode Application Example
9.5
Interrupt Sources
There are three kinds of TPU interrupt source: TGR input capture/compare match, TCNT
overflow, and TCNT underflow. Each interrupt source has its own status flag and enable/disable
bit, allowing generation of interrupt request signals to be enabled or disabled individually.
When an interrupt request is generated, the corresponding status flag in TSR is set to 1. If the
corresponding enable/disable bit in TIER is set to 1 at this time, an interrupt is requested. The
interrupt request is cleared by clearing the status flag to 0.
Relative channel priorities can be changed by the interrupt controller, but the priority order within
a channel is fixed. For details, see section 5, Interrupt Controller.
Table 9.36 lists the TPU interrupt sources.
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Section 9 16-Bit Timer Pulse Unit (TPU)
Table 9.36 TPU Interrupts
Channel
Name
Interrupt Source
Interrupt
Flag
DTC
Activation
0
TGI0A
TGRA_0 input capture/compare match
TGFA_0
Possible
TGI0B
TGRB_0 input capture/compare match
TGFB_0
Possible
TGI0C
TGRC_0 input capture/compare match
TGFC_0
Possible
TGI0D
TGRD_0 input capture/compare match
TGFD_0
Possible
1
2
3
4
5
TCI0V
TCNT_0 overflow
TCFV_0
Not possible
TGI1A
TGRA_1 input capture/compare match
TGFA_1
Possible
TGI1B
TGRB_1 input capture/compare match
TGFB_1
Possible
TCI1V
TCNT_1 overflow
TCFV_1
Not possible
TCI1U
TCNT_1 underflow
TCFU_1
Not possible
TGI2A
TGRA_2 input capture/compare match
TGFA_2
Possible
TGI2B
TGRB_2 input capture/compare match
TGFB_2
Possible
TCI2V
TCNT_2 overflow
TCFV_2
Not possible
TCI2U
TCNT_2 underflow
TCFU_2
Not possible
TGI3A
TGRA_3 input capture/compare match
TGFA_3
Possible
TGI3B
TGRB_3 input capture/compare match
TGFB_3
Possible
TGI3C
TGRC_3 input capture/compare match
TGFC_3
Possible
TGI3D
TGRD_3 input capture/compare match
TGFD_3
Possible
TCI3V
TCNT_3 overflow
TCFV_3
Not possible
TGI4A
TGRA_4 input capture/compare match
TGFA_4
Possible
TGI4B
TGRB_4 input capture/compare match
TGFB_4
Possible
TCI4V
TCNT_4 overflow
TCFV_4
Not possible
TCI4U
TCNT_4 underflow
TCFU_4
Not possible
TGI5A
TGRA_5 input capture/compare match
TGFA_5
Possible
TGI5B
TGRB_5 input capture/compare match
TGFB_5
Possible
TCI5V
TCNT_5 overflow
TCFV_5
Not possible
TCI5U
TCNT_5 underflow
TCFU_5
Not possible
Note: This table shows the initial state immediately after a reset. The relative channel priorities
can be changed by the interrupt controller.
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Section 9 16-Bit Timer Pulse Unit (TPU)
Input Capture/Compare Match Interrupt: An interrupt is requested if the TGIE bit in TIER is
set to 1 when the TGF flag in TSR is set to 1 by the occurrence of a TGR input capture/compare
match on a particular channel. The interrupt request is cleared by clearing the TGF flag to 0. The
TPU has 16 input capture/compare match interrupts, four each for channels 0 and 3, and two each
for channels 1, 2, 4, and 5.
Overflow Interrupt: An interrupt is requested if the TCIEV bit in TIER is set to 1 when the
TCFV flag in TSR is set to 1 by the occurrence of TCNT overflow on a channel. The interrupt
request is cleared by clearing the TCFV flag to 0. The TPU has six overflow interrupts, one for
each channel.
Underflow Interrupt: An interrupt is requested if the TCIEU bit in TIER is set to 1 when the
TCFU flag in TSR is set to 1 by the occurrence of TCNT underflow on a channel. The interrupt
request is cleared by clearing the TCFU flag to 0. The TPU has four underflow interrupts, one
each for channels 1, 2, 4, and 5.
9.6
DTC Activation
The DTC can be activated by the TGR input capture/compare match interrupt for a channel. For
details, see section 7, Data Transfer Controller (DTC).
A total of 16 TPU input capture/compare match interrupts can be used as DTC activation sources,
four each for channels 0 and 3, and two each for channels 1, 2, 4, and 5.
9.7
A/D Converter Activation
The A/D converter can be activated by the TGRA input capture/compare match for a channel.
If the TTGE bit in TIER is set to 1 when the TGFA flag in TSR is set to 1 by the occurrence of a
TGRA input capture/compare match on a particular channel, a request to start A/D conversion is
sent to the A/D converter. If the TPU conversion start trigger has been selected on the A/D
converter side at this time, A/D conversion is started.
In the TPU, a total of six TGRA input capture/compare match interrupts can be used as A/D
converter conversion start sources, one for each channel.
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.8
Operation Timing
9.8.1
Input/Output Timing
TCNT Count Timing: Figure 9.30 shows TCNT count timing in internal clock operation, and
figure 9.31 shows TCNT count timing in external clock operation.
φ
Falling edge
Internal clock
Rising edge
TCNT
input clock
TCNT
N–1
N
N+1
N+2
Figure 9.30 Count Timing in Internal Clock Operation
φ
External clock
Rising edge
Falling edge
Falling edge
TCNT
input clock
TCNT
N–1
N
N+1
Figure 9.31 Count Timing in External Clock Operation
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N+2
Section 9 16-Bit Timer Pulse Unit (TPU)
Output Compare Output Timing: A compare match signal is generated in the final state in
which TCNT and TGR match (the point at which the count value matched by TCNT is updated).
When a compare match signal is generated, the output value set in TIOR is output at the output
compare output pin. After a match between TCNT and TGR, the compare match signal is not
generated until the (TIOC pin) TCNT input clock is generated.
Figure 9.32 shows output compare output timing.
φ
TCNT
input clock
N
TCNT
N+1
N
TGR
Compare
match signal
TIOC pin
Figure 9.32 Output Compare Output Timing
Input Capture Signal Timing: Figure 9.33 shows input capture signal timing.
φ
Input capture
input
Input capture
signal
TCNT
TGR
N
N+1
N+2
N+2
N
Figure 9.33 Input Capture Input Signal Timing
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Section 9 16-Bit Timer Pulse Unit (TPU)
Timing for Counter Clearing by Compare Match/Input Capture: Figure 9.34 shows the
timing when counter clearing by compare match occurrence is specified, and figure 9.35 shows the
timing when counter clearing by input capture occurrence is specified.
φ
Compare
match signal
Counter
clear signal
TCNT
N
TGR
N
H'0000
Figure 9.34 Counter Clear Timing (Compare Match)
φ
Input capture
signal
Counter clear
signal
TCNT
N
H'0000
N
TGR
Figure 9.35 Counter Clear Timing (Input Capture)
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Section 9 16-Bit Timer Pulse Unit (TPU)
Buffer Operation Timing: Figures 9.36 and 9.37 show the timings in buffer operation.
φ
TCNT
n
n+1
Compare
match signal
TGRA,
TGRB
n
TGRC,
TGRD
N
N
Figure 9.36 Buffer Operation Timing (Compare Match)
φ
Input capture
signal
TCNT
N
TGRA,
TGRB
n
TGRC,
TGRD
N+1
N
N+1
n
N
Figure 9.37 Buffer Operation Timing (Input Capture)
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.8.2
Interrupt Signal Timing
TGF Flag Setting Timing in Case of Compare Match: Figure 9.38 shows the timing for setting
of the TGF flag in TSR by compare match occurrence, and the TGI interrupt request signal timing.
φ
TCNT input
clock
TCNT
N
TGR
N
N+1
Compare
match signal
TGF flag
TGI interrupt
Figure 9.38 TGI Interrupt Timing (Compare Match)
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Section 9 16-Bit Timer Pulse Unit (TPU)
TGF Flag Setting Timing in Case of Input Capture: Figure 9.39 shows the timing for setting of
the TGF flag in TSR by input capture occurrence, and the TGI interrupt request signal timing.
φ
Input capture
signal
TCNT
TGR
N
N
TGF flag
TGI interrupt
Figure 9.39 TGI Interrupt Timing (Input Capture)
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Section 9 16-Bit Timer Pulse Unit (TPU)
TCFV Flag/TCFU Flag Setting Timing: Figure 9.40 shows the timing for setting of the TCFV
flag in TSR by overflow occurrence, and the TCIV interrupt request signal timing.
Figure 9.41 shows the timing for setting of the TCFU flag in TSR by underflow occurrence, and
the TCIU interrupt request signal timing.
φ
TCNT input
clock
TCNT
(overflow)
H'FFFF
H'0000
Overflow
signal
TCFV flag
TCIV interrupt
Figure 9.40 TCIV Interrupt Setting Timing
φ
TCNT
input clock
TCNT
(underflow)
H'0000
H'FFFF
Underflow
signal
TCFU flag
TCIU interrupt
Figure 9.41 TCIU Interrupt Setting Timing
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Section 9 16-Bit Timer Pulse Unit (TPU)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC is activated, the flag is cleared automatically. Figure 9.42 shows the timing
for status flag clearing by the CPU, and figure 9.43 shows the timing for status flag clearing by the
DTC.
TSR write cycle
T1
T2
φ
Address
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 9.42 Timing for Status Flag Clearing by CPU
DTC
read cycle
T1
DTC
write cycle
T1
T2
T2
φ
Address
Source address
Destination
address
Status flag
Interrupt
request
signal
Figure 9.43 Timing for Status Flag Clearing by DTC Activation
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9
Usage Notes
9.9.1
Module Stop Mode Setting
TPU operation can be disabled or enabled using the module stop control register. The initial
setting is for TPU operation to be halted. Register access is enabled by clearing module stop
mode. For details, refer to section 19, Power-Down Modes.
9.9.2
Input Clock Restrictions
The input clock pulse width must be at least 1.5 states in the case of single-edge detection, and at
least 2.5 states in the case of both-edge detection. The TPU will not operate properly with a
narrower pulse width.
In phase counting mode, the phase difference and overlap between the two input clocks must be at
least 1.5 states, and the pulse width must be at least 2.5 states. Figure 9.44 shows the input clock
conditions in phase counting mode.
Overlap
Phase
Phase
diffedifference Overlap rence
Pulse width
Pulse width
TCLKA
(TCLKC)
TCLKB
(TCLKD)
Pulse width
Pulse width
Notes: Phase difference and overlap : 1.5 states or more
Pulse width
: 2.5 states or more
Figure 9.44 Phase Difference, Overlap, and Pulse Width in Phase Counting Mode
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.3
Caution on Cycle Setting
When counter clearing by compare match is set, TCNT is cleared in the final state in which it
matches the TGR value (the point at which the count value matched by TCNT is updated).
Consequently, the actual counter frequency is given by the following formula:
φ
f=
(N + 1)
Where f: Counter frequency
φ: Operating frequency
N: TGR set value
9.9.4
Contention between TCNT Write and Clear Operations
If the counter clearing signal is generated in the T2 state of a TCNT write cycle, TCNT clearing
takes precedence and the TCNT write is not performed. Figure 9.45 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
Counter clearing
signal
TCNT
N
H'0000
Figure 9.45 Contention between TCNT Write and Clear Operations
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.5
Contention between TCNT Write and Increment Operations
If incrementing occurs in the T2 state of a TCNT write cycle, the TCNT write takes precedence
and TCNT is not incremented. Figure 9.46 shows the timing in this case.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
TCNT input
clock
TCNT
N
M
TCNT write data
Figure 9.46 Contention between TCNT Write and Increment Operations
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.6
Contention between TGR Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the TGR write takes precedence
and the compare match signal is disabled. A compare match also does not occur when the same
value as before is written.
Figure 9.47 shows the timing in this case.
TGR write cycle
T1
T2
φ
TGR address
Address
Write signal
Compare
match signal
Disabled
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 9.47 Contention between TGR Write and Compare Match
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.7
Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data transferred to TGR by the
buffer operation will be the data prior to the write.
Figure 9.48 shows the timing in this case.
TGR write cycle
T1
T2
φ
Buffer register
address
Address
Write signal
Compare
match signal
Buffer register write data
Buffer
register
TGR
N
M
N
Figure 9.48 Contention between Buffer Register Write and Compare Match
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.8
Contention between TGR Read and Input Capture
If the input capture signal is generated in the T1 state of a TGR read cycle, the data that is read
will be the data after input capture transfer.
Figure 9.49 shows the timing in this case.
TGR read cycle
T1
T2
φ
TGR address
Address
Read signal
Input capture
signal
TGR
X
Internal
data bus
M
M
Figure 9.49 Contention between TGR Read and Input Capture
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.9
Contention between TGR Write and Input Capture
If the input capture signal is generated in the T2 state of a TGR write cycle, the input capture
operation takes precedence and the write to TGR is not performed.
Figure 9.50 shows the timing in this case.
TGR write cycle
T1
T2
φ
Address
TGR address
Write signal
Input capture
signal
TCNT
M
M
TGR
Figure 9.50 Contention between TGR Write and Input Capture
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.10
Contention between Buffer Register Write and Input Capture
If the input capture signal is generated in the T2 state of a buffer register write cycle, the buffer
operation takes precedence and the write to the buffer register is not performed.
Figure 9.51 shows the timing in this case.
Buffer register write cycle
T1
T2
φ
Buffer register
address
Address
Write signal
Input capture
signal
TCNT
TGR
Buffer
register
N
M
N
M
Figure 9.51 Contention between Buffer Register Write and Input Capture
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.11
Contention between Overflow/Underflow and Counter Clearing
If overflow/underflow and counter clearing occur simultaneously, the TCFV/TCFU flag in TSR is
not set and TCNT clearing takes precedence.
Figure 9.52 shows the operation timing when a TGR compare match is specified as the clearing
source, and H'FFFF is set in TGR.
φ
TCNT input
clock
TCNT
H'FFFF
H'0000
Counter
clearing signal
TGF
Disabled
TCFV
Figure 9.52 Contention between Overflow and Counter Clearing
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Section 9 16-Bit Timer Pulse Unit (TPU)
9.9.12
Contention between TCNT Write and Overflow/Underflow
If there is an up-count or down-count in the T2 state of a TCNT write cycle, when
overflow/underflow occurs, the TCNT write takes precedence and the TCFV/TCFU flag in TSR is
not set.
Figure 9.53 shows the operation timing when there is contention between TCNT write and
overflow.
TCNT write cycle
T1
T2
φ
TCNT address
Address
Write signal
TCNT
TCNT write data
H'FFFF
M
TCFV flag
Figure 9.53 Contention between TCNT Write and Overflow
9.9.13
Multiplexing of I/O Pins
In this LSI, the TCLKA input pin is multiplexed with the TIOCC0 I/O pin, the TCLKB input pin
with the TIOCD0 I/O pin, the TCLKC input pin with the TIOCB1 I/O pin, and the TCLKD input
pin with the TIOCB2 I/O pin. When an external clock is input, compare match output should not
be performed from a multiplexed pin.
9.9.14
Interrupts and Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be
disabled before entering module stop mode.
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Section 9 16-Bit Timer Pulse Unit (TPU)
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Section 10 Programmable Pulse Generator (PPG)
Section 10 Programmable Pulse Generator (PPG)
The programmable pulse generator (PPG) provides pulse outputs by using the 16-bit timer pulse
unit (TPU) as a time base. The PPG pulse outputs are divided into 4-bit groups (groups 3 to 0) that
can operate both simultaneously and independently. The block diagram of PPG is shown in figure
10.1
10.1
Features
• 16-bit output data
• Four output groups
• Selectable output trigger signals
• Non-overlap mode
• Can operate together with the data transfer controller (DTC)
• Settable inverted output
• Module stop mode can be set
PPG0001A_000020020400
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Section 10 Programmable Pulse Generator (PPG)
Compare match signals
Control logic
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
PO7
PO6
PO5
PO4
PO3
PO2
PO1
PO0
Legend:
PMR:
PCR:
NDERH:
NDERL:
NDRH:
NDRL:
PODRH:
PODRL:
NDERH
NDERL
PMR
PCR
Pulse output
pins, group 3
PODRH
NDRH
PODRL
NDRL
Pulse output
pins, group 2
Pulse output
pins, group 1
Pulse output
pins, group 0
PPG output mode register
PPG output control register
Next data enable register H
Next data enable register L
Next data register H
Next data register L
Output data register H
Output data register L
Figure 10.1 Block Diagram of PPG
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Internal
data bus
Section 10 Programmable Pulse Generator (PPG)
10.2
Input/Output Pins
Table 10.1 shows the PPG pin configuration.
Table 10.1 Pin Configuration
Pin Name
I/O
Function
PO15
Output
Group 3 pulse output
PO14
Output
PO13
Output
PO12
Output
PO11
Output
PO10
Output
PO9
Output
PO8
Output
PO7
Output
PO6
Output
PO5
Output
PO4
Output
PO3
Output
PO2
Output
PO1
Output
PO0
Output
10.3
Group 2 pulse output
Group 1 pulse output
Group 0 pulse output
Register Descriptions
The PPG has the following registers.
• Next data enable register H (NDERH)
• Next data enable register L (NDERL)
• Output data register H (PODRH)
• Output data register L (PODRL)
• Next data register H (NDRH)
• Next data register L (NDRL)
• PPG output control register (PCR)
• PPG output mode register (PMR)
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Section 10 Programmable Pulse Generator (PPG)
10.3.1
Next Data Enable Registers H, L (NDERH, NDERL)
NDERH, NDERL enable or disable pulse output on a bit-by-bit basis. For outputting pulse by the
PPG, set the corresponding DDR to 1.
NDERH
Bit
Bit Name
Initial Value
R/W
Description
7
NDER15
0
R/W
Next Data Enable 15 to 8
6
NDER14
0
R/W
5
NDER13
0
R/W
4
NDER12
0
R/W
3
NDER11
0
R/W
When a bit is set to 1, the value in the
corresponding NDRH bit is transferred to the
PODRH bit by the selected output trigger. Values
are not transferred from NDRH to PODRH for
cleared bits.
2
NDER10
0
R/W
1
NDER9
0
R/W
0
NDER8
0
R/W
NDERL
Bit
Bit Name
Initial Value
R/W
Description
7
NDER7
0
R/W
Next Data Enable 7 to 0
6
NDER6
0
R/W
5
NDER5
0
R/W
4
NDER4
0
R/W
3
NDER3
0
R/W
When a bit is set to 1, the value in the
corresponding NDRL bit is transferred to the
PODRL bit by the selected output trigger. Values
are not transferred from NDRL to PODRL for
cleared bits.
2
NDER2
0
R/W
1
NDER1
0
R/W
0
NDER0
0
R/W
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Section 10 Programmable Pulse Generator (PPG)
10.3.2
Output Data Registers H, L (PODRH, PODRL)
PODRH and PODRL store output data for use in pulse output. A bit that has been set for pulse
output by NDER is read-only and cannot be modified.
PODRH
Bit
Bit Name
Initial Value
R/W
Description
7
POD15
0
R/W
Output Data Register 15 to 8
6
POD14
0
R/W
5
POD13
0
R/W
4
POD12
0
R/W
3
POD11
0
R/W
2
POD10
0
R/W
For bits which have been set to pulse output by
NDERH, the output trigger transfers NDRH values
to this register during PPG operation. While
NDERH is set to 1, the CPU cannot write to this
register. While NDERH is cleared, the initial output
value of the pulse can be set.
1
POD9
0
R/W
0
POD8
0
R/W
PODRL
Bit
Bit Name
Initial Value
R/W
Description
7
POD7
0
R/W
Output Data Register 7 to 0
6
POD6
0
R/W
5
POD5
0
R/W
4
POD4
0
R/W
3
POD3
0
R/W
2
POD2
0
R/W
For bits which have been set to pulse output by
NDERL, the output trigger transfers NDRL values
to this register during PPG operation. While
NDERL is set to 1, the CPU cannot write to this
register. While NDERL is cleared, the initial output
value of the pulse can be set.
1
POD1
0
R/W
0
POD0
0
R/W
10.3.3
Next Data Registers H, L (NDRH, NDRL)
NDRH, NDRL store the next data for pulse output. The NDR addresses differ depending on
whether pulse output groups have the same output trigger or different output triggers.
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Section 10 Programmable Pulse Generator (PPG)
NDRH
If pulse output groups 2 and 3 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 15 to 8
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3
NDR11
0
R/W
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
If pulse output groups 2 and 3 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR15
0
R/W
Next Data Register 15 to 12
6
NDR14
0
R/W
5
NDR13
0
R/W
4
NDR12
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
3
to
0
—
All 1
—
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 1
—
Reserved
3
NDR11
0
R/W
Next Data Register 11 to 8
2
NDR10
0
R/W
1
NDR9
0
R/W
0
NDR8
0
R/W
The register contents are transferred to the
corresponding PODRH bits by the output trigger
specified with PCR.
Reserved
Always read as 1 and cannot be modified.
Always read as 1 and cannot be modified.
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Section 10 Programmable Pulse Generator (PPG)
NDRL
If pulse output groups 0 and 1 have the same output trigger, all eight bits are mapped to the same
address and can be accessed at one time, as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 7 to 0
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
NDR3
0
R/W
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
If pulse output groups 0 and 1 have different output triggers, upper 4 bits and lower 4 bits are
mapped to the different addresses as shown below.
Bit
Bit Name
Initial Value
R/W
Description
7
NDR7
0
R/W
Next Data Register 7 to 4
6
NDR6
0
R/W
5
NDR5
0
R/W
4
NDR4
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
3
to
0
—
All 1
—
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 1
—
Reserved
3
NDR3
0
R/W
Next Data Register 3 to 0
2
NDR2
0
R/W
1
NDR1
0
R/W
0
NDR0
0
R/W
The register contents are transferred to the
corresponding PODRL bits by the output trigger
specified with PCR.
Reserved
Always read as 1 and cannot be modified.
Always read as 1 and cannot be modified.
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Section 10 Programmable Pulse Generator (PPG)
10.3.4
PPG Output Control Register (PCR)
PCR selects output trigger signals on a group-by-group basis. For details on output trigger
selection, refer to section 10.3.5, PPG Output Mode Register (PMR).
Bit
Bit Name
Initial Value
R/W
Description
7
G3CMS1
1
R/W
Group 3 Compare Match Select 1 and 0
6
G3CMS0
1
R/W
Select output trigger of pulse output group 3.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
5
4
G2CMS1
1
R/W
Group 2 Compare Match Select 1 and 0
G2CMS0
1
R/W
Select output trigger of pulse output group 2.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
3
G1CMS1
1
R/W
Group 1 Compare Match Select 1 and 0
2
G1CMS0
1
R/W
Select output trigger of pulse output group 1.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
1
G0CMS1
1
R/W
Group 0 Compare Match Select 1 and 0
0
G0CMS0
1
R/W
Select output trigger of pulse output group 0.
00: Compare match in TPU channel 0
01: Compare match in TPU channel 1
10: Compare match in TPU channel 2
11: Compare match in TPU channel 3
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Section 10 Programmable Pulse Generator (PPG)
10.3.5
PPG Output Mode Register (PMR)
PMR selects the pulse output mode of the PPG for each group. If inverted output is selected, a
low-level pulse is output when PODRH is 1 and a high-level pulse is output when PODRH is 0. If
non-overlapping operation is selected, PPG updates its output values at compare match A or B of
the TPU that becomes the output trigger. For details, refer to section 10.4.4, Non-Overlapping
Pulse Output.
Bit
Bit Name
Initial Value
R/W
Description
7
G3INV
1
R/W
Group 3 Inversion
Selects direct output or inverted output for pulse
output group 3.
0: Inverted output
1: Direct output
6
G2INV
1
R/W
Group 2 Inversion
Selects direct output or inverted output for pulse
output group 2.
0: Inverted output
1: Direct output
5
G1INV
1
R/W
Group 1 Inversion
Selects direct output or inverted output for pulse
output group 1.
0: Inverted output
1: Direct output
4
G0INV
1
R/W
Group 0 Inversion
Selects direct output or inverted output for pulse
output group 0.
0: Inverted output
1: Direct output
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Section 10 Programmable Pulse Generator (PPG)
Bit
Bit Name
Initial Value
R/W
Description
3
G3NOV
0
R/W
Group 3 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 3.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the selected
TPU channel)
2
G2NOV
0
R/W
Group 2 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 2.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the selected
TPU channel)
1
G1NOV
0
R/W
Group 1 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 1.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the selected
TPU channel)
0
G0NOV
0
R/W
Group 0 Non-Overlap
Selects normal or non-overlapping operation for
pulse output group 0.
0: Normal operation (output values updated at
compare match A in the selected TPU channel)
1: Non-overlapping operation (output values
updated at compare match A or B in the selected
TPU channel)
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Section 10 Programmable Pulse Generator (PPG)
10.4
Operation
Figure 10.2 shows an overview diagram of the PPG. PPG pulse output is enabled when the
corresponding bits in P1DDR, P2DDR, and NDER are set to 1. An initial output value is
determined by its corresponding PODR initial setting. When the compare match event specified
by PCR occurs, the corresponding NDR bit contents are transferred to PODR to update the output
values. Sequential output of data of up to 16 bits is possible by writing new output data to NDR
before the next compare match.
DDR
NDER
Q
Output trigger signal
C
Q PODR D
Q NDR D
Internal data bus
Pulse output pin
Normal output/inverted output
Figure 10.2 Overview Diagram of PPG
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Section 10 Programmable Pulse Generator (PPG)
10.4.1
Output Timing
If pulse output is enabled, NDR contents are transferred to PODR and output when the specified
compare match event occurs. Figure 10.3 shows the timing of these operations for the case of
normal output in groups 2 and 3, triggered by compare match A.
φ
N
TCNT
TGRA
N+1
N
Compare match
A signal
n
NDRH
PODRH
PO8 to PO15
m
n
m
n
Figure 10.3 Timing of Transfer and Output of NDR Contents (Example)
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Section 10 Programmable Pulse Generator (PPG)
10.4.2
Sample Setup Procedure for Normal Pulse Output
Figure 10.4 shows a sample procedure for setting up normal pulse output.
Normal PPG output
Select TGR functions
[1]
Set TGRA value
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
[1] Set TIOR to make TGRA an output
compare register (with output
disabled)
[2] Set the PPG output trigger period
TPU setup
Port and
PPG setup
TPU setup
Set next pulse
output data
[8]
Start counter
[9]
Compare match?
No
[3] Select the counter clock source with
bits TPSC2 to TPSC0 in TCR.
Select the counter clear source with
bits CCLR2 to CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC can also be set up to
transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to 1.
[7] Select the TPU compare match
event to be used as the output
trigger in PCR.
[8] Set the next pulse output values in
NDR.
Yes
Set next pulse
output data
[10]
[9] Set the CST bit in TSTR to 1 to start
the TCNT counter.
[10] At each TGIA interrupt, set the next
output values in NDR.
Figure 10.4 Setup Procedure for Normal Pulse Output (Example)
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Section 10 Programmable Pulse Generator (PPG)
10.4.3
Example of Normal Pulse Output (Example of Five-Phase Pulse Output)
Figure 10.5 shows an example in which pulse output is used for cyclic five-phase pulse output.
TCNT value
Compare match
TCNT
TGRA
H'0000
Time
80
NDRH
PODRH
00
C0
80
40
C0
60
40
20
60
30
20
10
30
18
10
08
18
88
08
80
88
C0
80
40
C0
PO15
PO14
PO13
PO12
PO11
Figure 10.5 Normal Pulse Output Example (Five-Phase Pulse Output)
1. Set up TGRA in TPU which is used as the output trigger to be an output compare register. Set
a cycle in TGRA so the counter will be cleared by compare match A. Set the TGIEA bit in
TIER to 1 to enable the compare match/input capture A (TGIA) interrupt.
2. Write H'F8 in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Write output data H'80 in NDRH.
3. The timer counter in the TPU channel starts. When compare match A occurs, the NDRH
contents are transferred to PODRH and output. The TGIA interrupt handling routine writes the
next output data (H'C0) in NDRH.
4. Five-phase pulse output (one or two phases active at a time) can be obtained subsequently by
writing H'40, H'60, H'20, H'30, H'10, H'18, H'08, H'88... at successive TGIA interrupts.
If the DTC is set for activation by the TGIA interrupt, pulse output can be obtained without
imposing a load on the CPU.
Rev. 3.00 Feb 22, 2006 page 348 of 624
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Section 10 Programmable Pulse Generator (PPG)
10.4.4
Non-Overlapping Pulse Output
During non-overlapping operation, transfer from NDR to PODR is performed as follows:
• NDR bits are always transferred to PODR bits at compare match A.
• At compare match B, NDR bits are transferred only if their value is 0. Bits are not transferred
if their value is 1.
Figure 10.6 illustrates the non-overlapping pulse output operation.
DDR
NDER
Q
Compare match A
Compare match B
Pulse
output
pin
C
Q PODR D
Q NDR D
Internal data bus
Normal output/inverted output
Figure 10.6 Non-Overlapping Pulse Output
Therefore, 0 data can be transferred ahead of 1 data by making compare match B occur before
compare match A.
The NDR contents should not be altered during the interval from compare match B to compare
match A (the non-overlap margin).
This can be accomplished by having the TGIA interrupt handling routine write the next data in
NDR, or by having the TGIA interrupt activate the DTC. Note, however, that the next data must
be written before the next compare match B occurs.
Figure 10.7 shows the timing of this operation.
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Section 10 Programmable Pulse Generator (PPG)
Compare match A
Compare match B
Write to NDR
Write to NDR
NDR
PODR
0 output
0/1 output
Write to NDR
Do not write here
to NDR here
0 output 0/1 output
Do not write
to NDR here
Write to NDR
here
Figure 10.7 Non-Overlapping Operation and NDR Write Timing
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Section 10 Programmable Pulse Generator (PPG)
10.4.5
Sample Setup Procedure for Non-Overlapping Pulse Output
Figure 10.8 shows a sample procedure for setting up non-overlapping pulse output.
Non-overlapping
pulse output
Select TGR functions
[1]
Set TGR values
[2]
Set counting operation
[3]
Select interrupt request
[4]
Set initial output data
[5]
Enable pulse output
[6]
Select output trigger
[7]
Set non-overlapping groups
[8]
Set next pulse
output data
[9]
Start counter
[10]
TPU setup
PPG setup
TPU setup
Compare match A?
[2] Set the pulse output trigger period
in TGRB and the non-overlap
period in TGRA.
[3] Select the counter clock source
with bits TPSC2 to TPSC0 in TCR.
Select the counter clear source
with bits CCLR2 to CCLR0.
[4] Enable the TGIA interrupt in TIER.
The DTC can also be set up to
transfer data to NDR.
[5] Set the initial output values in
PODR.
[6] Set the DDR and NDER bits for the
pins to be used for pulse output to
1.
[7] Select the TPU compare match
event to be used as the pulse
output trigger in PCR.
No
[8] In PMR, select the groups that will
operate in non-overlap mode.
Yes
Set next pulse
output data
[1] Set TIOR to make TGRA and
TGRB an output compare registers
(with output disabled)
[11]
[9] Set the next pulse output values in
NDR.
[10] Set the CST bit in TSTR to 1 to
start the TCNT counter.
[11] At each TGIA interrupt, set the next
output values in NDR.
Figure 10.8 Setup Procedure for Non-Overlapping Pulse Output (Example)
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Section 10 Programmable Pulse Generator (PPG)
10.4.6
Example of Non-Overlapping Pulse Output (Example of Four-Phase
Complementary Non-Overlapping Output)
Figure 10.9 shows an example in which pulse output is used for four-phase complementary nonoverlapping pulse output.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRH
Time
95
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
65
Non-overlap margin
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 10.9 Non-Overlapping Pulse Output Example (Four-Phase Complementary)
Rev. 3.00 Feb 22, 2006 page 352 of 624
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Section 10 Programmable Pulse Generator (PPG)
1. Set up the TPU channel to be used as the output trigger channel so that TGRA and TGRB are
output compare registers. Set the trigger period in TGRB and the non-overlap margin in
TGRA, and set the counter to be cleared by compare match B. Set the TGIEA bit in TIER to 1
to enable the TGIA interrupt.
2. Write H'FF in P1DDR and NDERH, and set the G3CMS1, G3CMS0, G2CMS1, and G2CMS0
bits in PCR to select compare match in the TPU channel set up in the previous step to be the
output trigger. Set the G3NOV and G2NOV bits in PMR to 1 to select non-overlapping output.
Write output data H'95 in NDRH.
3. The timer counter in the TPU channel starts. When a compare match with TGRB occurs,
outputs change from 1 to 0. When a compare match with TGRA occurs, outputs change from 0
to 1 (the change from 0 to 1 is delayed by the value set in TGRA). The TGIA interrupt
handling routine writes the next output data (H'65) in NDRH.
4. Four-phase complementary non-overlapping pulse output can be obtained subsequently by
writing H'59, H'56, H'95... at successive TGIA interrupts.
If the DTC is set for activation by the TGIA interrupt, pulse output can be obtained without
imposing a load on the CPU.
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Section 10 Programmable Pulse Generator (PPG)
10.4.7
Inverted Pulse Output
If the G3INV, G2INV, G1INV, and G0INV bits in PMR are cleared to 0, values that are the
inverse of the PODR contents can be output.
Figure 10.10 shows the outputs when G3INV and G2INV are cleared to 0, in addition to the
settings of figure 10.9.
TCNT value
TGRB
TCNT
TGRA
H'0000
NDRH
PODRL
Time
95
00
65
95
59
05
65
56
41
59
95
50
56
65
14
95
05
PO15
PO14
PO13
PO12
PO11
PO10
PO9
PO8
Figure 10.10 Inverted Pulse Output (Example)
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65
Section 10 Programmable Pulse Generator (PPG)
10.4.8
Pulse Output Triggered by Input Capture
Pulse output can be triggered by TPU input capture as well as by compare match. If TGRA
functions as an input capture register in the TPU channel selected by PCR, pulse output will be
triggered by the input capture signal.
Figure 10.11 shows the timing of this output.
φ
TIOC pin
Input capture
signal
NDR
N
PODR
M
PO
M
N
N
Figure 10.11 Pulse Output Triggered by Input Capture (Example)
10.5
Usage Notes
10.5.1
Module Stop Mode Setting
PPG operation can be disabled or enabled using the module stop control register. The initial value
is for PPG operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 19, Power-Down Modes.
10.5.2
Operation of Pulse Output Pins
Pins PO0 to PO15 are also used for other peripheral functions such as the TPU. When output by
another peripheral function is enabled, the corresponding pins cannot be used for pulse output.
Note, however, that data transfer from NDR bits to PODR bits takes place, regardless of the usage
of the pins.
Pin functions should be changed only under conditions in which the output trigger event will not
occur.
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Section 10 Programmable Pulse Generator (PPG)
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Section 11 8-Bit Timers (TMR)
Section 11 8-Bit Timers (TMR)
This LSI has an on-chip 8-bit timer module with two channels operating on the basis of an 8-bit
counter. The 8-bit timer module can be used to count external events and be used as a
multifunction timer in a variety of applications, such as generation of counter reset, interrupt
requests, and pulse output with an arbitrary duty cycle using a compare-match signal with two
registers.
11.1
Features
• Selection of four clock sources
The counters can be driven by one of three internal clock signals (φ/8, φ/64, or φ/8192) or an
external clock input
• Selection of three ways to clear the counters
The counters can be cleared on compare match A or B, or by an external reset signal
• Timer output control by a combination of two compare match signals
The timer output signal in each channel is controlled by a combination of two independent
compare match signals, enabling the timer to generate output waveforms with an arbitrary duty
cycle or PWM output
• Provision for cascading of two channels (TMR_0 and TMR_1)
Operation as a 16-bit timer is possible, using TMR_0 for the upper 8 bits and TMR_1 for the
lower 8 bits (16-bit count mode)
TMR_1 can be used to count TMR_0 compare matches (compare match count mode)
• Three independent interrupts
Compare match A and B and overflow interrupts can be requested independently
• A/D converter conversion start trigger can be generated
Figure 11.1 shows a block diagram of the 8-bit timer module (TMR_0 and TMR_1).
TIMH262A_000020020400
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Section 11 8-Bit Timers (TMR)
External clock source
TMCI0
TMCI1
Internal clock sources
TMR_0 TMR_1
φ/8
φ/8
φ/64
φ/64
φ/8192
φ/8192
Clock 1
Clock 0
Clock select
TCORA_0
Compare match A1
Compare match A0 Comparator A_0
Overflow 1
Overflow 0
TMO0
TMRI0
TCNT_0
TCORA_1
Comparator A_1
TCNT_1
Clear 1
TMO1
TMRI1
Control logic
Compare match B1
Compare match B0 Comparator B_0
Comparator B_1
TCORB_0
TCORB_1
TCSR_0
TCSR_1
TCR_0
TCR_1
A/D
conversion
start request
signal
CMIA0
CMIB0
OVI0
CMIA1
CMIB1
OVI1
Interrupt signals
Legend:
TCORA_0:
TCORB_0:
TCNT_0:
TCSR_0:
TCR_0:
Time constant register A_0
Time constant register B_0
Timer counter_0
Timer control/status register_0
Timer control register_0
TCORA_1:
TCORB_1:
TCNT_1:
TCSR_1:
TCR_1:
Time constant register A_1
Time constant register B_1
Timer counter_1
Timer control/status register_1
Timer control register_1
Figure 11.1 Block Diagram of 8-Bit Timer Module
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Internal bus
Clear 0
Section 11 8-Bit Timers (TMR)
11.2
Input/Output Pins
Table 11.1 shows the pin configuration of the 8-bit timer module.
Table 11.1 Pin Configuration
Channel
Name
Symbol
I/O
Function
0
Timer output pin
TMO0
Output
Outputs at compare match
Timer clock input pin
TMCI0
Input
Inputs external clock for counter
Timer reset input pin
TMRI0
Input
Inputs external reset to counter
Timer output pin
TMO1
Output
Outputs at compare match
Timer clock input pin
TMCI1
Input
Inputs external clock for counter
Timer reset input pin
TMRI1
Input
Inputs external reset to counter
1
11.3
Register Descriptions
The 8-bit timer module has the following registers. For details on the module stop control register,
refer to section 19.1.2 Module Stop Control Registers H, L (MSTPCRH, MSTPCRL).
• Timer counter_0 (TCNT_0)
• Time constant register A_0 (TCORA_0)
• Time constant register B_0 (TCORB_0)
• Timer control register_0 (TCR_0)
• Timer control/status register_0 (TCSR_0)
• Timer counter_1 (TCNT_1)
• Time constant register A_1 (TCORA_1)
• Time constant register B_1 (TCORB_1)
• Timer control register_1 (TCR_1)
• Timer control/status register_1 (TCSR_1)
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Section 11 8-Bit Timers (TMR)
11.3.1
Timer Counter (TCNT)
TCNT is 8-bit up-counter. TCNT_0 and TCNT_1 comprise a single 16-bit register so they can be
accessed together by a word transfer instruction. Bits CKS2 to CKS0 in TCR are used to select a
clock. TCNT can be cleared by an external reset input or by a compare match signal A or B.
Which signal is to be used for clearing is selected by bits CCLR1 and CCLR0 in TCR. When
TCNT overflows from H'FF to H'00, OVF in TCSR is set to 1. TCNT is initialized to H'00.
11.3.2
Time Constant Register A (TCORA)
TCORA is 8-bit readable/writable register. TCORA_0 and TCORA_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
The value in TCORA is continually compared with the value in TCNT. When a match is detected,
the corresponding CMFA flag in TCSR is set to 1. Note, however, that comparison is disabled
during the T2 state of a TCORA write cycle.
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match A) and the settings of bits OS1 and OS0 in TCSR.
TCORA is initialized to H'FF.
11.3.3
Time Constant Register B (TCORB)
TCORB is 8-bit readable/writable register. TCORB_0 and TCORB_1 comprise a single 16-bit
register so they can be accessed together by a word transfer instruction.
TCORB is continually compared with the value in TCNT. When a match is detected, the
corresponding CMFB flag in TCSR is set to 1. Note, however, that comparison is disabled during
the T2 state of a TCOBR write cycle.
The timer output from the TMO pin can be freely controlled by this compare match signal
(compare match B) and the settings of bits OS3 and OS2 in TCSR.
TCORB is initialized to H'FF.
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Section 11 8-Bit Timers (TMR)
11.3.4
Timer Control Register (TCR)
TCR selects the clock source and the time at which TCNT is cleared, and controls interrupts.
Bit
Bit Name
Initial Value
R/W
Description
7
CMIEB
0
R/W
Compare Match Interrupt Enable B
Selects whether CMFB interrupt requests
(CMIB) are enabled or disabled when the
CMFB flag in TCSR is set to 1.
0: CMFB interrupt requests (CMIB) are disabled
1: CMFB interrupt requests (CMIB) are enabled
6
CMIEA
0
R/W
Compare Match Interrupt Enable A
Selects whether CMFA interrupt requests
(CMIA) are enabled or disabled when the
CMFA flag in TCSR is set to 1.
0: CMFA interrupt requests (CMIA) are disabled
1: CMFA interrupt requests (CMIA) are enabled
5
OVIE
0
R/W
Timer Overflow Interrupt Enable
Selects whether OVF interrupt requests (OVI)
are enabled or disabled when the OVF flag in
TCSR is set to 1.
0: OVF interrupt requests (OVI) are disabled
1: OVF interrupt requests (OVI) are enabled
4
CCLR1
0
R/W
Counter Clear 1 and 0
3
CCLR0
0
R/W
These bits select the method by which TCNT is
cleared
00: Clearing is disabled
01: Clear by compare match A
10: Clear by compare match B
11: Clear by rising edge of external reset input
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
These bits select the clock input to TCNT and
count condition. See table 11.2.
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Section 11 8-Bit Timers (TMR)
Table 11.2 Clock Input to TCNT and Count Condition
TCR
Channel
TMR_0
Bit 2
CKS2
Bit 1
CKS1
Bit 0
CKS0
Description
0
0
0
Clock input disabled
1
Internal clock, counted at falling edge of φ/8
0
Internal clock, counted at falling edge of φ/64
1
Internal clock, counted at falling edge of φ/8192
1
TMR_1
1
0
0
Count at TCNT_1 overflow signal*
0
0
0
Clock input disabled
1
Internal clock, counted at falling edge of φ/8
0
Internal clock, counted at falling edge of φ/64
1
1
All
Note:
*
1
0
0
Internal clock, counted at falling edge of φ/8192
Count at TCNT_0 compare match A*
1
0
1
External clock, counted at rising edge
1
0
External clock, counted at falling edge
1
1
External clock, counted at both rising and falling edges
If the count input of TMR_0 is the TCNT_1 overflow signal and that of TMR_1 is the
TCNT_0 compare match signal, no incrementing clock is generated. Do not use this
setting.
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Section 11 8-Bit Timers (TMR)
11.3.5
Timer Control/Status Register (TCSR)
TCSR displays status flags, and controls compare match output.
TCSR_0
Bit
7
Bit Name
CMFB
Initial Value
R/W
Description
0
R/(W)*
Compare Match Flag B
[Setting condition]
•
Set when TCNT matches TCORB
[Clearing conditions]
6
CMFA
0
R/(W)*
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0
Compare Match Flag A
[Setting condition]
•
Set when TCNT matches TCORA
[Clearing conditions]
5
OVF
0
R/(W)*
•
Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt
while DISEL bit of MRB in DTC is 0
Timer Overflow Flag
[Setting condition]
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
4
ADTE
0
R/W
A/D Trigger Enable
Selects enabling or disabling of A/D converter
start requests by compare match A.
0: A/D converter start requests by compare
match A are disabled
1: A/D converter start requests by compare
match A are enabled
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Section 11 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
3
OS3
0
R/W
Output Select 3 and 2
2
OS2
0
R/W
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
1
OS1
0
R/W
Output Select 1 and 0
0
OS0
0
R/W
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note:
*
Only 0 can be written to bits 7 to 5, to clear these flags.
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Section 11 8-Bit Timers (TMR)
TCSR_1
Bit
7
Bit Name
CMFB
Initial Value
R/W
Description
0
R/(W)*
Compare Match Flag B
[Setting condition]
•
Set when TCNT matches TCORB
[Clearing conditions]
6
CMFA
0
R/(W)*
•
Cleared by reading CMFB when CMFB = 1,
then writing 0 to CMFB
•
When DTC is activated by CMIB interrupt
while DISEL bit of MRB in DTC is 0
Compare Match Flag A
[Setting condition]
•
Set when TCNT matches TCORA
[Clearing conditions]
5
OVF
0
R/(W)*
•
Cleared by reading CMFA when CMFA = 1,
then writing 0 to CMFA
•
When DTC is activated by CMIA interrupt
while DISEL bit of MRB in DTC is 0
Timer Overflow Flag
[Setting condition]
Set when TCNT overflows from H'FF to H'00
[Clearing condition]
Cleared by reading OVF when OVF = 1, then
writing 0 to OVF
4
—
1
R
Reserved
This bit is always read as 1 and cannot be
modified.
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Section 11 8-Bit Timers (TMR)
Bit
Bit Name
Initial Value
R/W
Description
3
OS3
0
R/W
Output Select 3 and 2
2
OS2
0
R/W
These bits select a method of TMO pin output
when compare match B of TCORB and TCNT
occurs.
00: No change when compare match B occurs
01: 0 is output when compare match B occurs
10: 1 is output when compare match B occurs
11: Output is inverted when compare match B
occurs (toggle output)
1
OS1
0
R/W
Output Select 1 and 0
0
OS0
0
R/W
These bits select a method of TMO pin output
when compare match A of TCORA and TCNT
occurs.
00: No change when compare match A occurs
01: 0 is output when compare match A occurs
10: 1 is output when compare match A occurs
11: Output is inverted when compare match A
occurs (toggle output)
Note:
*
Only 0 can be written to bits 7 to 5, to clear these flags.
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Section 11 8-Bit Timers (TMR)
11.4
Operation
11.4.1
Pulse Output
Figure 11.2 shows an example that the 8-bit timer is used to generate a pulse output with a
selected duty cycle. The control bits are set as follows:
[1] In TCR, bit CCLR1 is cleared to 0 and bit CCLR0 is set to 1 so that the timer counter is
cleared at a TCORA compare match.
[2] In TCSR, bits OS3 to OS0 are set to B'0110, causing the output to change to 1 at a TCORA
compare match and to 0 at a TCORB compare match.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA with
a pulse width determined by TCORB. No software intervention is required.
TCNT
H'FF
Counter clear
TCORA
TCORB
H'00
TMO
Figure 11.2 Example of Pulse Output
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Section 11 8-Bit Timers (TMR)
11.5
Operation Timing
11.5.1
TCNT Incrementation Timing
Figure 11.3 shows the count timing for internal clock input. Figure 11.4 shows the count timing
for external clock signal. Note that the external clock pulse width must be at least 1.5 states for
incrementation at a single edge, and at least 2.5 states for incrementation at both edges. The
counter will not increment correctly if the pulse width is less than these values.
φ
Internal clock
Clock input
to TCNT
TCNT
N–1
N
N+1
Figure 11.3 Count Timing for Internal Clock Input
φ
External clock
input pin
Clock input
to TCNT
TCNT
N–1
N
Figure 11.4 Count Timing for External Clock Input
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Section 11 8-Bit Timers (TMR)
11.5.2
Timing of CMFA and CMFB Setting when Compare-Match Occurs
The CMFA and CMFB flags in TCSR are set to 1 by a compare match signal generated when the
TCOR and TCNT values match. The compare match signal is generated at the last state in which
the match is true, just before the timer counter is updated. Therefore, when TCOR and TCNT
match, the compare match signal is not generated until the next incrementation clock input.
Figure 11.5 shows this timing.
φ
TCNT
N
TCOR
N
N+1
Compare match
signal
CMF
Figure 11.5 Timing of CMF Setting
11.5.3
Timing of Timer Output when Compare-Match Occurs
When compare match A or B occurs, the timer output changes as specified by bits OS3 to OS0 in
TCSR.
Figure 11.6 shows the timing when the output is set to toggle at compare match A.
φ
Compare match A
signal
Timer output pin
Figure 11.6 Timing of Timer Output
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Section 11 8-Bit Timers (TMR)
11.5.4
Timing of Compare Match Clear
TCNT is cleared when compare match A or B occurs, depending on the setting of the CCLR1 and
CCLR0 bits in TCR. Figure 11.7 shows the timing of this operation.
φ
Compare match
signal
TCNT
N
H'00
Figure 11.7 Timing of Compare Match Clear
11.5.5
Timing of TCNT External Reset
TCNT is cleared at the rising edge of an external reset input, depending on the settings of the
CCLR1 and CCLR0 bits in TCR. The clear pulse width must be at least 1.5 states. Figure 11.8
shows the timing of this operation.
φ
External reset
input pin
Clear signal
TCNT
N–1
N
Figure 11.8 Timing of Clearance by External Reset
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H'00
Section 11 8-Bit Timers (TMR)
11.5.6
Timing of Overflow Flag (OVF) Setting
The OVF in TCSR is set to 1 when TCNT overflows (changes from H'FF to H'00). Figure 11.9
shows the timing of this operation.
φ
TCNT
H'FF
H'00
Overflow signal
OVF
Figure 11.9 Timing of OVF Setting
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Section 11 8-Bit Timers (TMR)
11.6
Operation with Cascaded Connection
If bits CKS2 to CKS0 in either TCR_0 or TCR_1 are set to B'100, the 8-bit timers of the two
channels are cascaded. With this configuration, a single 16-bit timer could be used (16-bit counter
mode) or compare matches of the 8-bit channel 0 could be counted by the timer of channel 1
(compare match count mode). In this case, the timer operates as below.
11.6.1
16-Bit Counter Mode
When bits CKS2 to CKS0 in TCR_0 are set to B'100, the timer functions as a single 16-bit timer
with channel 0 occupying the upper 8 bits and channel 1 occupying the lower 8 bits.
[1] Setting of compare match flags
• The CMF flag in TCSR_0 is set to 1 when a 16-bit compare match event occurs.
• The CMF flag in TCSR_1 is set to 1 when a lower 8-bit compare match event occurs.
[2] Counter clear specification
• If the CCLR1 and CCLR0 bits in TCR_0 have been set for counter clear at compare match, the
16-bit counters (TCNT_0 and TCNT_1 together) are cleared when a 16-bit compare match
event occurs. The 16-bit counters (TCNT0 and TCNT1 together) are cleared even if counter
clear by the TMRI0 pin has also been set.
• The settings of the CCLR1 and CCLR0 bits in TCR_1 are ignored. The lower 8 bits cannot be
cleared independently.
[3] Pin output
• Control of output from the TMO0 pin by bits OS3 to OS0 in TCSR_0 is in accordance with the
16-bit compare match conditions.
• Control of output from the TMO1 pin by bits OS3 to OS0 in TCSR_1 is in accordance with the
lower 8-bit compare match conditions.
11.6.2
Compare Match Count Mode
When bits CKS2 to CKS0 in TCR_1 are B'100, TCNT_1 counts compare match A’s for channel
0.
Channels 0 and 1 are controlled independently. Conditions such as setting of the CMF flag,
generation of interrupts, output from the TMO pin, and counter clear are in accordance with the
settings for each channel.
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Section 11 8-Bit Timers (TMR)
11.7
Interrupt Sources
11.7.1
Interrupt Sources and DTC Activation
There are three 8-bit timer interrupt sources: CMIA, CMIB, and OVI. Their relative priorities are
shown in table 11.3. Each interrupt source is set as enabled or disabled by the corresponding
interrupt enable bit in TCR or TCSR, and independent interrupt requests are sent for each to the
interrupt controller. It is also possible to activate the DTC by means of CMIA and CMIB
interrupts.
Table 11.3 8-Bit Timer Interrupt Sources
Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
CMIA0
TCORA_0 compare match
CMFA
Possible
High
CMIB0
TCORB_0 compare match
CMFB
Possible
OVI0
TCNT_0 overflow
OVF
Not possible
Low
CMIA1
TCORA_1 compare match
CMFA
Possible
High
CMIB1
TCORB_1 compare match
CMFB
Possible
OVI1
TCNT_1 overflow
OVF
Not possible
11.7.2
Low
A/D Converter Activation
The A/D converter can be activated only by TMR_0 compare match A.
If the ADTE bit in TCSR0 is set to 1 when the CMFA flag is set to 1 by the occurrence of TMR_0
compare match A, a request to start A/D conversion is sent to the A/D converter. If the 8-bit timer
conversion start trigger has been selected on the A/D converter side at this time, A/D conversion is
started.
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Section 11 8-Bit Timers (TMR)
11.8
Usage Notes
11.8.1
Contention between TCNT Write and Clear
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the clear
takes priority, so that the counter is cleared and the write is not performed.
Figure 11.10 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
TCNT address
Address
Internal write signal
Counter clear signal
N
TCNT
H'00
Figure 11.10 Contention between TCNT Write and Clear
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Section 11 8-Bit Timers (TMR)
11.8.2
Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T2 state of a TCNT write cycle, the write
takes priority and the counter is not incremented.
Figure 11.11 shows this operation.
TCNT write cycle by CPU
T1
T2
φ
Address
TCNT address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 11.11 Contention between TCNT Write and Increment
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Section 11 8-Bit Timers (TMR)
11.8.3
Contention between TCOR Write and Compare Match
During the T2 state of a TCOR write cycle, the TCOR write has priority and the compare match
signal is inhibited even if a compare match event occurs as shown in figure 11.12.
TCOR write cycle by CPU
T1
T2
φ
TCOR address
Address
Internal write signal
TCNT
N
N+1
TCOR
N
M
TCOR write data
Compare match signal
Inhibited
Figure 11.12 Contention between TCOR Write and Compare Match
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Section 11 8-Bit Timers (TMR)
11.8.4
Contention between Compare Matches A and B
If compare match events A and B occur at the same time, the 8-bit timer operates in accordance
with the priorities for the output statuses set for compare match A and compare match B, as shown
in table 11.4.
Table 11.4 Timer Output Priorities
Output Setting
Priority
Toggle output
High
1 output
0 output
No change
11.8.5
Low
Switching of Internal Clocks and TCNT Operation
TCNT may increment erroneously when the internal clock is switched over. Table 11.5 shows the
relationship between the timing at which the internal clock is switched (by writing to the CKS1
and CKS0 bits) and the TCNT operation.
When the TCNT clock is generated from an internal clock, the falling edge of the internal clock
pulse is detected. If clock switching causes a change from high to low level, as shown in case 3 in
table 11.5, a TCNT clock pulse is generated on the assumption that the switchover is a falling
edge. This increments TCNT.
The erroneous incrementation can also happen when switching between internal and external
clocks.
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Section 11 8-Bit Timers (TMR)
Table 11.5 Switching of Internal Clock and TCNT Operation
No.
1
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from
1
low to low*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
CKS bit write
2
Switching from
2
low to high*
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
3
Switching from
3
high to low*
Clock before
swichover
Clock after
swichover
*4
TCNT clock
TCNT
N
N+1
CKS bit write
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Section 11 8-Bit Timers (TMR)
No.
4
Timing of Switchover
by Means of CKS1
and CKS0 Bits
TCNT Clock Operation
Switching from high
to high
Clock before
switchover
Clock after
switchover
TCNT clock
TCNT
N
N+1
N+2
CKS bit write
Notes: 1.
2.
3.
4.
11.8.6
Includes switching from low to stop, and from stop to low.
Includes switching from stop to high.
Includes switching from high to stop.
Generated on the assumption that the switchover is a falling edge; TCNT is
incremented.
Mode Setting with Cascaded Connection
If 16-bit counter mode and compare match count mode are specified at the same time, input clocks
for TCNT_0 and TCNT_1 are not generated, and the counter stops. Do not specify 16-bit counter
and compare match count modes simultaneously.
11.8.7
Interrupts in Module Stop Mode
If module stop mode is entered when an interrupt has been requested, it will not be possible to
clear the CPU interrupt source or the DTC activation source. Interrupts should therefore be
disabled before entering module stop mode.
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Section 11 8-Bit Timers (TMR)
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Section 12 Watchdog Timer
Section 12 Watchdog Timer
The watchdog timer (WDT) is an 8-bit timer that outputs an overflow signal (WDTOVF) if a
system crash prevents the CPU from writing to the timer counter, thus allowing it to overflow.
At the same time, the WDT can also generate an internal reset signal.
When this watchdog function is not needed, the WDT can be used as an interval timer. In interval
timer operation, an interval timer interrupt is generated each time the counter overflows.
The block diagram of the WDT is shown in figure 12.1.
12.1
Features
• Selectable from eight counter input clocks
• Switchable between watchdog timer mode and interval timer mode
In watchdog timer mode
• If the counter overflows, the WDT outputs WDTOVF. It is possible to select whether or not
the entire chip is reset at the same time.
In interval timer mode
• If the counter overflows, the WDT generates an interval timer interrupt (WOVI).
WDT0101A_010020020400
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Section 12 Watchdog Timer
Clock
WDTOVF
Internal reset signal*
Clock
select
Reset
control
RSTCSR
TCNT
φ/2
φ/64
φ/128
φ/512
φ/2048
φ/8192
φ/32768
φ/131072
Internal clock
sources
TSCR
Module bus
Bus
interface
Internal bus
Overflow
Interrupt
control
WOVI
(interrupt request
signal)
WDT
Legend:
TCSR:
Timer control/status register
TCNT:
Timer counter
RSTCSR: Reset control/status register
Note: * An internal reset signal can be generated by the register setting.
Figure 12.1 Block Diagram of WDT
12.2
Input/Output Pin
Table 12.1 shows the WDT pin configuration.
Table 12.1 Pin Configuration
Name
Symbol
I/O
Function
Watchdog timer overflow
WDTOVF
Output
Outputs counter overflow signal in watchdog
timer mode
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Section 12 Watchdog Timer
12.3
Register Descriptions
The WDT has the following three registers. To prevent accidental overwriting, TCSR, TCNT, and
RSTCSR have to be written to in a method different from normal registers. For details, refer to
section 12.6.1, Notes on Register Access.
• Timer counter (TCNT)
• Timer control/status register (TCSR)
• Reset control/status register (RSTCSR)
12.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
TCSR is cleared to 0.
12.3.2
Timer Control/Status Register (TCSR)
TCSR selects the clock source to be input to TCNT, and the timer mode.
Bit
7
Bit Name
OVF
Initial Value
R/W
Description
0
R/(W)*
Overflow Flag
Indicates that TCNT has overflowed in interval
timer mode. Only a write of 0 is permitted, to
clear the flag.
[Setting condition]
When TCNT overflows in interval timer mode
(changes from H’FF to H’00)
When internal reset request generation is selected
in watchdog timer mode, OVF is cleared
automatically by the internal reset.
[Clearing conditions]
Cleared by reading TCSR when OVF = 1, then
writing 0 to OVF
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Section 12 Watchdog Timer
Bit
Bit Name
Initial Value
R/W
Description
6
WT/IT
0
R/W
Timer Mode Select
Selects whether the WDT is used as a watchdog
timer or interval timer.
0: Interval timer mode
When TCNT overflows, an interval timer interrupt
(WOVI) is requested.
1: Watchdog timer mode
When TCNT overflows, the WDTOVF signal is
output.
5
TME
0
R/W
Timer Enable
When this bit is set to 1, TCNT starts counting.
When this bit is cleared, TCNT stops counting and
is initialized to H'00.
4, 3
—
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
2
CKS2
0
R/W
Clock Select 2 to 0
1
CKS1
0
R/W
0
CKS0
0
R/W
Selects the clock source to be input to TCNT. The
overflow frequency for φ = 20 MHz is enclosed in
parentheses.
000: Clock φ/2 (frequency: 25.6 µs)
001: Clock φ/64 (frequency: 819.2 µs)
010: Clock φ/128 (frequency: 1.6 ms)
011: Clock φ/512 (frequency: 6.6 ms)
100: Clock φ/2048 (frequency: 26.2 ms)
101: Clock φ/8192 (frequency: 104.9 ms)
110: Clock φ/32768 (frequency: 419.4 ms)
111: Clock φ/131072 (frequency: 1.68 s)
Note:
*
Only a write of 0 is permitted, to clear the flag.
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Section 12 Watchdog Timer
12.3.3
Reset Control/Status Register (RSTCSR)
RSTCSR controls the generation of the internal reset signal when TCNT overflows, and selects
the type of internal reset signal. RSTCSR is initialized to H'1F by a reset signal from the RES pin,
but not by the WDT internal reset signal caused by overflows.
Bit
Bit Name
Initial Value
R/W
Description
7
WOVF
0
R/(W)*
Watchdog Timer Overflow Flag
This bit is set when TCNT overflows in watchdog
timer mode. This bit cannot be set in interval
timer mode, and only 0 can be written.
[Setting condition]
Set when TCNT overflows (changed from H'FF to
H'00) in watchdog timer mode
[Clearing condition]
Cleared by reading RSTCSR when WOVF = 1,
and then writing 0 to WOVF
6
RSTE
0
R/W
Reset Enable
Specifies whether or not a reset signal is
generated in the chip if TCNT overflows during
watchdog timer operation.
0: Reset signal is not generated even if TCNT
overflows
(Though this LSI is not reset, TCNT and TCSR
in WDT are reset)
1: Reset signal is generated if TCNT overflows
5
—
0
R/W
Reserved
Can be read and written, but does not affect
operation.
4
to
0
Note:
—
All 1
—
Reserved
These bits are always read as 1 and cannot be
modified.
*
Only a write of 0 is permitted, to clear the flag.
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Section 12 Watchdog Timer
12.4
Operation
12.4.1
Watchdog Timer Mode
To use the WDT as a watchdog timer mode, set the WT/IT and TME bits in TCSR to 1.
If TCNT overflows without being rewritten because of a system crash or other error, the
WDTOVF signal is output. This ensures that TCNT does not overflow while the system is
operating normally. Software must prevent TCNT overflows by rewriting the TCNT value
(normally be writing H'00) before overflow occurs. This WDTOVF signal can be used to reset the
chip internally in watchdog timer mode.
If TCNT overflows when 1 is set in the RSTE bit in RSTCSR, a signal that resets this LSI
internally is generated at the same time as the WDTOVF signal. If a reset caused by a signal input
to the RES pin occurs at the same time as a reset caused by a WDT overflow, the RES pin reset
has priority and the WOVF bit in RSTCSR is cleared to 0.
The WDTOVF signal is output for 132 states when RSTE = 1, and for 130 states when RSTE = 0.
The internal reset signal is output for 518 states.
When TCNT overflows in watchdog timer mode, the WOVF bit in RSTCSR is set to 1. If TCNT
overflows when 1 is set in the RSTE bit in RSTCSR, an internal reset signal is generated to the
entire chip.
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Section 12 Watchdog Timer
TCNT count
Overflow
H'FF
Time
H'00
WT/IT=1
TME=1
H'00 written
to TCNT
WOVF=1
WDTOVF and
internal reset are
generated
WT/IT=1
TME=1
H'00 written
to TCNT
WDTOVF signal
132 states*2
Internal reset
signal*1
518 states
Legend:
WT/IT: Timer mode select bit
TME: Timer enable bit
Notes: 1. If TCNT overflows when the RSTE bit is set to 1, an internal reset signal is generated.
2. 130 states when the RSTE bit is cleared to 0.
Figure 12.2 Operation in Watchdog Timer Mode
12.4.2
Interval Timer Mode
To use the WDT as an interval timer, set the WT/IT bit to 0 and TME bit in TCSR to 1.
When the WDT is used as an interval timer, an interval timer interrupt (WOVI) is generated each
time the TCNT overflows. Therefore, an interrupt can be generated at intervals.
When the TCNT overflows in interval timer mode, an interval timer interrupt (WOVI) is requested
at the same time the OVF bit in the TCSR is set to 1.
Rev. 3.00 Feb 22, 2006 page 387 of 624
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Section 12 Watchdog Timer
TCNT count
Overflow
H'FF
Overflow
Overflow
Overflow
Time
H'00
WT/IT=0
TME=1
WOVI
WOVI
WOVI
WOVI
Legend:
WOVI: Interval timer interrupt request generation
Figure 12.3 Operation in Interval Timer Mode
12.5
Interrupt Source
During interval timer mode operation, an overflow generates an interval timer interrupt (WOVI).
The interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 12.2 WDT Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
WOVI
TCNT overflow
OVF
Impossible
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Section 12 Watchdog Timer
12.6
Usage Notes
12.6.1
Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT, TCSR, and RSTCSR
TCNT and TCSR must be written to by a word transfer instruction. They cannot be written to by a
byte transfer instruction.
TCNT and TCSR both have the same write address. Therefore, satisfy the relative condition
shown in figure 12.4 to write to TCNT or TCSR. The transfer instruction writes the lower byte
data to TCNT or TCSR according to the satisfied condition.
To write to RSTCSR, execute a word transfer instruction for address H'FFBE. A byte transfer
instruction cannot perform writing to RSTCSR.
The method of writing 0 to the WOVF bit differs from that of writing to the RSTE bit. To write 0
to the WOVF bit, satisfy the lower condition shown in figure 12.4.
If satisfied, the transfer instruction clears the WOVF bit to 0, but has no effect on the RSTE bit.
To write to the RSTE bit, satisfy the above condition shown in figure 12.4. If satisfied, the transfer
instruction writes the value in bit 6 of the lower byte into the RSTE bit, but has no effect on the
WOVF bit.
TCNT write or
Writing to RSTE bit in RSTCSR
15
Address: H'FFBC (TCNT)
H'FFBE (RSTCSR)
8
7
H'5A
0
Write data
TCSR write
Address: H'FFBC (TCSR)
15
8
7
H'A5
0
Write data
Writing 0 to WOVF bit in RSTCSR
Address: H'FFBE (RSTCSR)
Figure 12.4
15
8
H'A5
7
0
H'00
Writing to TCNT, TCSR, and RSTCSR
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Section 12 Watchdog Timer
Reading TCNT, TCSR, and RSTCSR
These registers are read in the same way as other registers. The read addresses are H'FFBC for
TCSR, H'FFBD for TCNT, and H'FFBF for RSTCSR.
12.6.2
Contention between Timer Counter (TCNT) Write and Increment
If a timer counter clock pulse is generated during the next cycle after the T2 state of a TCNT write
cycle, the write takes priority and the timer counter is not incremented. Figure 12.5 shows this
operation.
TCNT write cycle
T1
T2
Next cycle
φ
Address
Internal write signal
TCNT input clock
TCNT
N
M
Counter write data
Figure 12.5 Contention between TCNT Write and Increment
12.6.3
Changing Value of CKS2 to CKS0
If bits CKS2 to CKS0 in TCSR are written to while the WDT is operating, errors could occur in
the incrementation. Software must stop the watchdog timer (by clearing the TME bit to 0) before
changing the value of bits CKS2 to CKS0.
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Section 12 Watchdog Timer
12.6.4
Switching between Watchdog Timer Mode and Interval Timer Mode
If the mode is switched from watchdog timer to interval timer, while the WDT is operating, errors
could occur in the incrementation. Software must stop the watchdog timer (by clearing the TME
bit to 0) before switching the mode.
12.6.5
Internal Reset in Watchdog Timer Mode
This LSI is not reset internally if TCNT overflows while the RSTE bit is cleared to 0 during
watchdog timer mode operation, but TCNT and TCSR of the WDT are reset.
TCNT, TCSR, and RSTCR cannot be written to while the WDTOVF signal is low. Also note that
a read of the WOVF flag is not recognized during this period. To clear the WOVF flag, therefore,
read TCSR after the WDTOVF signal goes high, then write 0 to the WOVF flag.
12.6.6
System Reset by WDTOVF Signal
If the WDTOVF output signal is input to the RES pin, the chip will not be initialized correctly.
Make sure that the WDTOVF signal is not input logically to the RES pin.
To reset the entire system by means of the WDTOVF signal, use the circuit shown in figure 12.6.
This LSI
Reset input
Reset signal to entire system
RES
WDTOVF
Figure 12.6 Circuit for System Reset by WDTOVF Signal (Example)
Rev. 3.00 Feb 22, 2006 page 391 of 624
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Section 12 Watchdog Timer
Rev. 3.00 Feb 22, 2006 page 392 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Section 13 Serial Communication Interface (SCI, IrDA)
This LSI has three independent serial communication interface (SCI) channels. The SCI can
handle both asynchronous and clocked synchronous serial communication. Serial data
communication can be carried out with standard asynchronous communication chips such as a
Universal Asynchronous Receiver/Transmitter (UART) or Asynchronous Communication
Interface Adapter (ACIA). A function is also provided for serial communication between
processors (multiprocessor communication function) in asynchronous mode. The SCI also
supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification Card) as
an asynchronous serial communication interface extension function. One of the three SCI channels
(SCI_0) can generate an IrDA communication waveform conforming to IrDA specification
version 1.0.
Figure 13.1 shows a block diagram of the SCI.
13.1
Features
• Choice of asynchronous or clocked synchronous serial communication mode
• Full-duplex communication capability
The transmitter and receiver are mutually independent, enabling transmission and reception to
be executed simultaneously. Double-buffering is used in both the transmitter and the receiver,
enabling continuous transmission and continuous reception of serial data.
• On-chip baud rate generator allows any bit rate to be selected
External clock can be selected as a transfer clock source (except for in Smart Card interface
mode).
• Choice of LSB-first or MSB-first transfer (except in the case of asynchronous mode 7-bit data)
• Four interrupt sources
Four interrupt sources — transmit-end, transmit-data-empty, receive-data-full, and receive
error — that can issue requests. The transmit-data-empty interrupt and receive data full
interrupts can activate the data transfer controller (DTC).
• Module stop mode can be set
Asynchronous mode
• Data length: 7 or 8 bits
• Stop bit length: 1 or 2 bits
• Parity: Even, odd, or none
SCI0026A_000020020400
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Section 13 Serial Communication Interface (SCI, IrDA)
• Receive error detection: Parity, overrun, and framing errors
• Break detection: Break can be detected by reading the RxD pin level directly in case of a
framing error
• Average transfer rate generator (only for SCI_2)
115.152 or 460.606 kbps at 10.667 MHz operation
115.196, 460.784 or 720 kbps at 16 MHz operation
720 kbps at 32 MHz operation
Clocked Synchronous mode
• Data length: 8 bits
• Receive error detection: Overrun errors detected
Smart Card Interface
• Automatic transmission of error signal (parity error) in receive mode
• Error signal detection and automatic data retransmission in transmit mode
• Direct convention and inverse convention both supported
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Bus interface
Section 13 Serial Communication Interface (SCI, IrDA)
Module data bus
RDR
RxD
RSR
SCMR
SSR
SCR
SMR
SEMR
TDR
TSR
BRR
φ
Baud rate
generator
Transmission/
reception control
TxD
Parity generation
φ/4
φ/16
φ/64
Clock
Parity check
External clock
SCK
Internal
data bus
TEI
TXI
RXI
ERI
Legend:
RSR: Receive shift register
RDR: Receive data register
TSR:
Transmit shift register
TDR:
Transmit data register
SMR: Serial mode register
SCR: Serial control register
SSR:
Serial status register
SCMR: Smart card mode register
BRR: Bit rate register
SEMR: Serial extension mode register (only in SCI_2)
Average transfer
rate generator
(SCI_2)
10.667 MHz operation
• 115.152 kbps
• 460.606 kbps
16 MHz operation
• 115.196 kbps
• 460.784 kbps
• 720 kbps
32 MHz operation
• 720 kbps
Figure 13.1 Block Diagram of SCI
Rev. 3.00 Feb 22, 2006 page 395 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.2
Input/Output Pins
Table 13.1 shows the pin configuration of the serial communication interface.
Table 13.1 Pin Configuration
Channel
Pin Name*
I/O
Function
0
SCK0
I/O
Channel 0 clock input/output
RxD0/IrRxD
Input
Channel 0 receive data input (normal/IrDA)
TxD0/IrTxD
Output
Channel 0 transmit data output (normal/IrDA)
SCK1
I/O
Channel 1 clock input/output
RxD1
Input
Channel 1 receive data input
TxD1
Output
Channel 1 transmit data output
1
2
Note:
*
SCK2
I/O
Channel 2 clock input/output
RxD2
Input
Channel 2 receive data input
TxD2
Output
Channel 2 transmit data output
Pin names SCK, RxD, and TxD are used in the text for all channels, omitting the
channel designation.
Rev. 3.00 Feb 22, 2006 page 396 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.3
Register Descriptions
The SCI has the following registers. The serial mode register (SMR), serial status register (SSR),
and serial control register (SCR) are described separately for normal serial communication
interface mode and Smart Card interface mode because their bit functions partially differ.
• Receive shift register_0 (RSR_0)
• Transmit shift register_0 (TSR_0)
• Receive data register_0 (RDR_0)
• Transmit data register_0 (TDR_0)
• Serial mode register_0 (SMR_0)
• Serial control register_0 (SCR_0)
• Serial status register_0 (SSR_0)
• Smart card mode register_0 (SCMR_0)
• Bit rate register_0 (BRR_0)
• IrDA control register_0 (IrCR_0)
• Receive shift register_1 (RSR_1)
• Transmit shift register_1 (TSR_1)
• Receive data register_1 (RDR_1)
• Transmit data register_1 (TDR_1)
• Serial mode register_1 (SMR_1)
• Serial control register_1 (SCR_1)
• Serial status register_1 (SSR_1)
• Smart card mode register_1 (SCMR_1)
• Bit rate register_1 (BRR_1)
• Receive shift register_2 (RSR_2)
• Transmit shift register_2 (TSR_2)
• Receive data register_2 (RDR_2)
• Transmit data register_2 (TDR_2)
• Serial mode register_2 (SMR_2)
• Serial control register_2 (SCR_2)
• Serial status register_2 (SSR_2)
• Smart card mode register_2 (SCMR_2)
• Bit rate register_2 (BRR_2)
• Serial extension mode register (SEMR)
Rev. 3.00 Feb 22, 2006 page 397 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.3.1
Receive Shift Register (RSR)
RSR is a shift register used to receive serial data that is input to the RxD pin and convert it into
parallel data. When one byte of data has been received, it is transferred to RDR automatically.
RSR cannot be directly accessed by the CPU.
13.3.2
Receive Data Register (RDR)
RDR is an 8-bit register that stores receive data. When the SCI has received one byte of serial
data, it transfers the received serial data from RSR to RDR where it is stored. After this, RSR is
receive-enabled. Since RSR and RDR function as a double buffer in this way, enables continuous
receive operations to be performed. After confirming that the RDRF bit in SSR is set to 1, read
RDR for only once. RDR cannot be written to by the CPU.
13.3.3
Transmit Data Register (TDR)
TDR is an 8-bit register that stores transmit data. When the SCI detects that TSR is empty, it
transfers the transmit data written in TDR to TSR and starts transmission. The double-buffered
structures of TDR and TSR enable continuous serial transmission. If the next transmit data has
already been written to TDR during serial transmission, the SCI transfers the written data to TSR
to continue transmission. Although TDR can be read or written to by the CPU at all times, to
achieve reliable serial transmission, write transmit data to TDR for only once after confirming that
the TDRE bit in SSR is set to 1.
13.3.4
Transmit Shift Register (TSR)
TSR is a shift register that transmits serial data. To perform serial data transmission, the SCI first
transfers transmit data from TDR to TSR, then sends the data to the TxD pin starting. TSR cannot
be directly accessed by the CPU.
13.3.5
Serial Mode Register (SMR)
SMR is used to set the SCI’s serial transfer format and select the on-chip baud rate generator clock
source.
Some bit functions of SMR differ in normal serial communication interface mode and Smart Card
interface mode.
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Section 13 Serial Communication Interface (SCI, IrDA)
Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)
Bit
Bit Name
Initial Value
R/W
Description
7
C/A
0
R/W
Communication Mode
0: Asynchronous mode
1: Clocked synchronous mode
6
CHR
0
R/W
Character Length (enabled only in asynchronous
mode)
0: Selects 8 bits as the data length.
1: Selects 7 bits as the data length. LSB-first is
fixed and the MSB (bit 7) of TDR is not
transmitted in transmission.
In clocked synchronous mode, a fixed data length
of 8 bits is used.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. For a multiprocessor
format, parity bit addition and checking are not
performed regardless of the PE bit setting.
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
3
STOP
0
R/W
Stop Bit Length (enabled only in asynchronous
mode)
Selects the stop bit length in transmission.
0: 1 stop bit
1: 2 stop bits
In reception, only the first stop bit is checked
regardless of the STOP bit setting. If the second
stop bit is 0, it is treated as the start bit of the next
transmit character.
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Section 13 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
MP
0
R/W
Multiprocessor Mode (enabled only in
asynchronous mode)
When this bit is set to 1, the multiprocessor
communication function is enabled. The PE bit
and O/E bit settings are invalid in multiprocessor
mode.
1
CKS1
0
R/W
Clock Select 1 and 0:
0
CKS0
0
R/W
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 13.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 13.3.9, Bit Rate
Register (BRR)).
Rev. 3.00 Feb 22, 2006 page 400 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF in SCMR Is 1)
Bit
Bit Name
Initial Value
R/W
Description
7
GM
0
R/W
GSM Mode
When this bit is set to 1, the SCI operates in GSM
mode. In GSM mode, the timing of the TEND
setting is advanced by 11.0 etu (Elementary Time
Unit: the time for transfer of one bit), and clock
output control mode addition is performed. For
details, refer to section 13.7.8, Clock Output
Control.
6
BLK
0
R/W
When this bit is set to 1, the SCI operates in block
transfer mode. For details on block transfer mode,
refer to section 13.7.3, Block Transfer Mode.
5
PE
0
R/W
Parity Enable (enabled only in asynchronous
mode)
When this bit is set to 1, the parity bit is added to
transmit data before transmission, and the parity
bit is checked in reception. In Smart Card
interface mode, this bit must be set to 1.
4
O/E
0
R/W
Parity Mode (enabled only when the PE bit is 1 in
asynchronous mode)
0: Selects even parity.
1: Selects odd parity.
For details on setting this bit in Smart Card
interface mode, refer to section 13.7.2, Data
Format (Except for Block Transfer Mode).
3
BCP1
0
R/W
Basic Clock Pulse 1 and 0
2
BCP0
0
R/W
These bits select the number of basic clock
periods in a 1-bit transfer interval on the Smart
Card interface.
00: 32 clock (S = 32)
01: 64 clock (S = 64)
10: 372 clock (S = 372)
11: 256 clock (S = 256)
For details, refer to section 13.7.4, Receive Data
Sampling Timing and Reception Margin. S stands
for the value of S in BRR (see section 13.3.9, Bit
Rate Register (BRR)).
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Section 13 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
1
CKS1
0
R/W
Clock Select 1 and 0:
0
CKS0
0
R/W
These bits select the clock source for the on-chip
baud rate generator.
00: φ clock (n = 0)
01: φ/4 clock (n = 1)
10: φ/16 clock (n = 2)
11: φ/64 clock (n = 3)
For the relation between the bit rate register
setting and the baud rate, see section 13.3.9, Bit
Rate Register (BRR). n is the decimal display of
the value of n in BRR (see section 13.3.9, Bit Rate
Register (BRR)).
13.3.6
Serial Control Register (SCR)
SCR performs enabling or disabling of SCI transfer operations and interrupt requests, and
selection of the transfer/receive clock source. For details on interrupt requests, refer to section
13.9, Interrupts Sources. Some bit functions of SCR differ in normal serial communication
interface mode and Smart Card interface mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)
Bit
Bit Name
Initial Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
5
TE
0
R/W
Transmit Enable
When this bit s set to 1, transmission is enabled.
4
RE
0
R/W
Receive Enable:
When this bit is set to 1, reception is enabled.
Rev. 3.00 Feb 22, 2006 page 402 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
When this bit is set to 1, receive data in which the
multiprocessor bit is 0 is skipped, and setting of
the RDRF, FER, and ORER status flags in SSR is
prohibited. On receiving data in which the
multiprocessor bit is 1, this bit is automatically
cleared and normal reception is resumed. For
details, refer to section 13.5, Multiprocessor
Communication Function.
2
TEIE
0
R/W
Transmit End Interrupt Enable
When this bit is set to 1, TEI interrupt request is
enabled.
1
CKE1
0
R/W
0
CKE0
0
R/W
Clock Enable 1 and 0
Selects the clock source and SCK pin function.
Asynchronous mode
00: On-chip baud rate generator
SCK pin functions as I/O port
01: On-chip baud rate generator
(Outputs a clock of the same frequency as the bit
rate from the SCK pin.)
1X: External clock
(Inputs a clock with a frequency 16 times the bit
rate from the SCK pin.)
Clocked synchronous mode
0X: Internal clock (SCK pin functions as clock
output)
1X: External clock (SCK pin functions as clock
input)
Note: X: Don’t care
Rev. 3.00 Feb 22, 2006 page 403 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Smart Card Interface Mode (When SMIF in SCMR Is 1)
Bit
Bit Name
Initial Value
R/W
Description
7
TIE
0
R/W
Transmit Interrupt Enable
When this bit is set to 1, TXI interrupt request is
enabled.
6
RIE
0
R/W
Receive Interrupt Enable
When this bit is set to 1, RXI and ERI interrupt
requests are enabled.
5
TE
0
R/W
Transmit Enable
When this bit is set to 1, transmission is enabled.
4
RE
0
R/W
Receive Enable
When this bit is set to 1, reception is enabled.
3
MPIE
0
R/W
Multiprocessor Interrupt Enable (enabled only
when the MP bit in SMR is 1 in asynchronous
mode)
Write 0 to this bit in Smart Card interface mode.
2
TEIE
0
R/W
Transmit End Interrupt Enable
Write 0 to this bit in Smart Card interface mode.
1
CKE1
0
0
CKE0
0
R/W
Clock Enable 1 and 0
Enables or disables clock output from the SCK
pin. The clock output can be dynamically switched
in GSM mode. For details, refer to section 13.7.8,
Clock Output Control.
When the GM bit in SMR is 0:
00: Output disabled (SCK pin can be used as an
I/O port pin)
01: Clock output
1X: Reserved
When the GM bit in SMR is 1:
00: Output fixed low
01: Clock output
10: Output fixed high
11: Clock output
Note: X: Don’t care
Rev. 3.00 Feb 22, 2006 page 404 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.3.7
Serial Status Register (SSR)
SSR is a register containing status flags of the SCI and multiprocessor bits for transfer. 1 cannot
be written to flags TDRE, RDRF, ORER, PER, and FER; they can only be cleared. Some bit
functions of SSR differ in normal serial communication interface mode and Smart Card interface
mode.
Normal Serial Communication Interface Mode (When SMIF in SCMR Is 0)
Bit
Bit Name
Initial Value
R/W
Description
7
TDRE
1
R/(W)*
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR
[Clearing conditions]
6
RDRF
0
R/(W)*
•
When 0 is written to TDRE after reading TDRE
=1
•
When the DTC is activated by a TXI interrupt
request and transfers data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading
RDRF = 1
•
When the DTC is activated by an RXI interrupt
and transferred data from RDR
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared
to 0.
Rev. 3.00 Feb 22, 2006 page 405 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
5
ORER
0
R/(W)*
Overrun Error
[Setting condition]
•
When the next serial reception is completed
while RDRF = 1
[Clearing condition]
•
4
FER
0
R/(W)*
When 0 is written to ORER after reading
ORER = 1
Framing Error
[Setting condition]
•
When the stop bit is 0
[Clearing condition]
•
When 0 is written to FER after reading FER =
1
In 2-stop-bit mode, only the first stop bit is
checked.
3
PER
0
R/(W)*
Parity Error
[Setting condition]
•
When a parity error is detected during
reception
[Clearing condition]
•
2
TEND
1
R
When 0 is written to PER after reading PER =
1
Transmit End
[Setting conditions]
•
When the TE bit in SCR is 0
•
When TDRE = 1 at transmission of the last bit
of a 1-byte serial transmit character
[Clearing conditions]
Rev. 3.00 Feb 22, 2006 page 406 of 624
REJ09B0281-0300
•
When 0 is written to TDRE after reading TDRE
=1
•
When the DTC is activated by a TXI interrupt
and writes data to TDR
Section 13 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
1
MPB
0
R
Multiprocessor Bit
MPB stores the multiprocessor bit in the receive
data. When the RE bit in SCR is cleared to 0 its
previous state is retained.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
MPBT sets the multiprocessor bit to be added to
the transmit data.
Note:
*
Only 0 can be written, to clear the flag.
Smart Card Interface Mode (When SMIF in SCMR Is 1)
Bit
Bit Name
Initial Value
R/W
Description
7
TDRE
1
R/(W)*
Transmit Data Register Empty
Indicates whether TDR contains transmit data.
[Setting conditions]
•
When the TE bit in SCR is 0
•
When data is transferred from TDR to TSR
[Clearing conditions]
6
RDRF
0
R/(W)*
•
When 0 is written to TDRE after reading TDRE
=1
•
When the DTC is activated by a TXI interrupt
request and transfers data to TDR
Receive Data Register Full
Indicates that the received data is stored in RDR.
[Setting condition]
•
When serial reception ends normally and
receive data is transferred from RSR to RDR
[Clearing conditions]
•
When 0 is written to RDRF after reading
RDRF = 1
•
When the DTC is activated by an RXI interrupt
and transferred data from RDR
The RDRF flag is not affected and retains their
previous values when the RE bit in SCR is cleared
to 0.
Rev. 3.00 Feb 22, 2006 page 407 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
5
ORER
0
R/(W)*
Overrun Error
[Setting condition]
•
When the next serial reception is completed
while RDRF = 1
[Clearing condition]
•
4
ERS
0
R/(W)*
When 0 is written to ORER after reading
ORER = 1
Error Signal Status
[Setting condition]
•
When the low level of the error signal is
sampled
[Clearing conditions]
•
3
PER
0
R/(W)*
When 0 is written to ERS after reading ERS =
1
Parity Error
[Setting condition]
•
When a parity error is detected during
reception
[Clearing condition]
•
Rev. 3.00 Feb 22, 2006 page 408 of 624
REJ09B0281-0300
When 0 is written to PER after reading PER =
1
Section 13 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
TEND
1
R
Transmit End
This bit is set to 1 when no error signal has been
sent back from the receiving end and the next
transmit data is ready to be transferred to TDR.
[Setting conditions]
•
When the TE bit in SCR is 0 and the ERS bit
is also 0
•
If the ERS bit is 0 and the TDRE bit is 1 after
the specified interval after transmission of 1byte data
Timing to set this bit differs according to the
register settings.
GM = 0, BLK = 0: 2.5 etu after transmission
GM = 0, BLK = 1: 1.5 etu after transmission
GM = 1, BLK = 0: 1.0 etu after transmission
GM = 1, BLK = 1: 1.0 etu after transmission
[Clearing conditions]
1
MPB
0
R
•
When 0 is written to TEND after reading TEND
=1
•
When the DTC is activated by a TXI interrupt
and writes data to TDR
Multiprocessor Bit
This bit is not used in Smart Card interface mode.
0
MPBT
0
R/W
Multiprocessor Bit Transfer
Write 0 to this bit in Smart Card interface mode.
Note:
*
Only 0 can be written, to clear the flag.
Rev. 3.00 Feb 22, 2006 page 409 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
13.3.8
Smart Card Mode Register (SCMR)
SCMR selects Smart Card interface mode and its format.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 1
—
Reserved
3
SDIR
These bits are always read as 1.
0
R/W
Smart Card Data Transfer Direction
Selects the serial/parallel conversion format.
0: LSB-first in transfer
1: MSB-first in transfer
The bit setting is valid only when the transfer data
format is 8 bits. For 7-bit data, LSB-first is fixed.
2
SINV
0
R/W
Smart Card Data Invert
Specifies inversion of the data logic level. The
SINV bit does not affect the logic level of the
parity bit. To invert the parity bit, invert the O/E bit
in SMR.
0: TDR contents are transmitted as they are.
Receive data is stored as it is in RDR.
1: TDR contents are inverted before being
transmitted. Receive data is stored in inverted
form in RDR.
1
—
1
—
Reserved
This bit is always read as 1.
0
SMIF
0
R/W
Smart Card Interface Mode Select
This bit is set to 1 to make the SCI operate in
Smart Card interface mode.
0: Normal asynchronous mode or clocked
synchronous mode
1: Smart card interface mode
Rev. 3.00 Feb 22, 2006 page 410 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
13.3.9
Bit Rate Register (BRR)
BRR is an 8-bit register that adjusts the bit rate. As the SCI performs baud rate generator control
independently for each channel, different bit rates can be set for each channel. Table 13.2 shows
the relationships between the N setting in BRR and bit rate B for normal asynchronous mode,
clocked synchronous mode, and Smart Card interface mode. The initial value of BRR is H'FF, and
it can be read or written to by the CPU at all times.
Table 13.2 Relationships between N Setting in BRR and Bit Rate B
Mode
Bit Rate
Asynchronous
Mode
B=
Clocked
Synchronous
Mode
B=
Smart Card
Interface Mode
B=
Error
φ × 106
64 × 22n–1 × (N + 1)
{ B × 64 ×φ2× 10× (N + 1) – 1} × 100
6
Error (%) =
2n–1
φ × 106
8 × 22n–1 × (N + 1)
φ × 106
S × 22n+1 × (N + 1)
Error (%) =
φ × 106
{ B×S×2
2n+1
× (N + 1)
}
– 1 × 100
Note: B: Bit rate (bit/s)
N: BRR setting for baud rate generator (0 ≤ N ≤ 255)
φ: Operating frequency (MHz)
n and S: Determined by the SMR settings shown in the following tables.
SMR Setting
SMR Setting
CKS1
CKS0
n
BCP1
BCP0
S
0
0
0
0
0
32
0
1
1
0
1
64
1
0
2
1
0
372
1
1
3
1
1
256
Rev. 3.00 Feb 22, 2006 page 411 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.3 shows sample N settings in BRR in normal asynchronous mode. Table 13.4 shows the
maximum bit rate for each frequency in normal asynchronous mode. Table 13.6 shows sample N
settings in BRR in clocked synchronous mode. Table 13.8 shows sample N settings in BRR in
Smart Card interface mode. In Smart Card interface mode, S (the number of basic clock periods in
a 1-bit transfer interval) can be selected. For details, refer to section 13.7.4, Receive Data
Sampling Timing and Reception Margin. Tables 13.5 and 13.7 show the maximum bit rates with
external clock input.
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (1)
Operating Frequency φ (MHz)
2
2.097152
2.4576
3
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
1
141
0.03
1
148
–0.04
1
174
–0.26
1
212
0.03
150
1
103
0.16
1
108
0.21
1
127
0.00
1
155
0.16
300
0
207
0.16
0
217
0.21
0
255
0.00
1
77
0.16
600
0
103
0.16
0
108
0.21
0
127
0.00
0
155
0.16
1200
0
51
0.16
0
54
–0.70
0
63
0.00
0
77
0.16
2400
0
25
0.16
0
26
1.14
0
31
0.00
0
38
0.16
4800
0
12
0.16
0
13
–2.48
0
15
0.00
0
19
–2.34
9600
—
—
—
0
6
–2.48
0
7
0.00
0
9
–2.34
19200
—
—
—
—
—
—
0
3
0.00
0
4
–2.34
31250
0
1
0.00
—
—
—
—
—
—
0
2
0.00
38400
—
—
—
—
—
—
0
1
0.00
—
—
—
Rev. 3.00 Feb 22, 2006 page 412 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (2)
Operating Frequency φ (MHz)
3.6864
4
4.9152
5
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
64
0.70
2
70
0.03
2
86
0.31
2
88
–0.25
150
1
191
0.00
1
207
0.16
1
255
0.00
2
64
0.16
300
1
95
0.00
1
103
0.16
1
127
0.00
1
129
0.16
600
0
191
0.00
0
207
0.16
0
255
0.00
1
64
0.16
1200
0
95
0.00
0
103
0.16
0
127
0.00
0
129
0.16
2400
0
47
0.00
0
51
0.16
0
63
0.00
0
64
0.16
4800
0
23
0.00
0
25
0.16
0
31
0.00
0
32
–1.36
9600
0
11
0.00
0
12
0.16
0
15
0.00
0
15
1.73
19200
0
5
0.00
—
—
—
0
7
0.00
0
7
1.73
31250
—
—
—
0
3
0.00
0
4
–1.70
0
4
0.00
38400
0
2
0.00
—
—
—
0
3
0.00
0
3
1.73
Operating Frequency φ (MHz)
6
6.144
7.3728
8
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
106
–0.44
2
108
0.08
2
130
–0.07
2
141
0.03
150
2
77
0.16
2
79
0.00
2
95
0.00
2
103
0.16
300
1
155
0.16
1
159
0.00
1
191
0.00
1
207
0.16
600
1
77
0.16
1
79
0.00
1
95
0.00
1
103
0.16
1200
0
155
0.16
0
159
0.00
0
191
0.00
0
207
0.16
2400
0
77
0.16
0
79
0.00
0
95
0.00
0
103
0.16
4800
0
38
0.16
0
39
0.00
0
47
0.00
0
51
0.16
9600
0
19
–2.34
0
19
0.00
0
23
0.00
0
25
0.16
19200
0
9
–2.34
0
9
0.00
0
11
0.00
0
12
0.16
31250
0
5
0.00
0
5
2.40
—
—
—
0
7
0.00
38400
0
4
–2.34
0
4
0.00
0
5
0.00
—
—
—
Rev. 3.00 Feb 22, 2006 page 413 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (3)
Operating Frequency φ (MHz)
9.8304
10
12
12.288
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
174
–0.26
2
177
–0.25
2
212
0.03
2
217
0.08
150
2
127
0.00
2
129
0.16
2
155
0.16
2
159
0.00
300
1
255
0.00
2
64
0.16
2
77
0.16
2
79
0.00
600
1
127
0.00
1
129
0.16
1
155
0.16
1
159
0.00
1200
0
255
0.00
1
64
0.16
1
77
0.16
1
79
0.00
2400
0
127
0.00
0
129
0.16
0
155
0.16
0
159
0.00
4800
0
63
0.00
0
64
0.16
0
77
0.16
0
79
0.00
9600
0
31
0.00
0
32
–1.36
0
38
0.16
0
39
0.00
19200
0
15
0.00
0
15
1.73
0
19
–2.34
0
19
0.00
31250
0
9
–1.70
0
9
0.00
0
11
0.00
0
11
2.40
38400
0
7
0.00
0
7
1.73
0
9
–2.34
0
9
0.00
Operating Frequency φ (MHz)
14
14.7456
16
17.2032
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
2
248
–0.17
3
64
0.70
3
70
0.03
3
75
0.48
150
2
181
0.16
2
191
0.00
2
207
0.16
2
223
0.00
300
2
90
0.16
2
95
0.00
2
103
0.16
2
111
0.00
600
1
181
0.16
1
191
0.00
1
207
0.16
1
223
0.00
1200
1
90
0.16
1
95
0.00
1
103
0.16
1
111
0.00
2400
0
181
0.16
0
191
0.00
0
207
0.16
0
223
0.00
4800
0
90
0.16
0
95
0.00
0
103
0.16
0
111
0.00
9600
0
45
–0.93
0
47
0.00
0
51
0.16
0
55
0.00
19200
0
22
–0.93
0
23
0.00
0
25
0.16
0
27
0.00
31250
0
13
0.00
0
14
–1.70
0
15
0.00
0
16
1.20
38400
—
—
—
0
11
0.00
0
12
0.16
0
13
0.00
Rev. 3.00 Feb 22, 2006 page 414 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.3 BRR Settings for Various Bit Rates (Asynchronous Mode) (4)
Operating Frequency φ (MHz)
18
19.6608
20
25
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
110
3
79
–0.12
3
86
0.31
3
88
–0.25
3
110
–0.02
150
2
233
0.16
2
255
0.00
3
64
0.16
3
80
–0.47
300
2
116
0.16
2
127
0.00
2
129
0.16
2
162
0.15
600
1
233
0.16
1
255
0.00
2
64
0.16
2
80
–0.47
1200
1
116
0.16
1
127
0.00
1
129
0.16
1
162
0.15
2400
0
233
0.16
0
255
0.00
1
64
0.16
1
80
–0.47
4800
0
116
0.16
0
127
0.00
0
129
0.16
0
162
0.15
9600
0
58
–0.69
0
63
0.00
0
64
0.16
0
80
–0.47
19200
0
28
1.02
0
31
0.00
0
32
–1.36
0
40
–0.76
31250
0
17
0.00
0
19
–1.70
0
19
0.00
0
24
0.00
38400
0
14
–2.34
0
15
0.00
0
15
1.73
0
19
1.73
Operating Frequency φ (MHz)
30
33
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
110
3
132
0.13
3
145
0.33
150
3
97
–0.35
3
106
0.39
300
2
194
0.16
2
214
–0.07
600
2
97
–0.35
2
106
0.39
1200
1
194
0.16
1
214
–0.07
2400
1
97
–0.35
1
106
0.39
4800
0
194
0.16
0
214
–0.07
9600
0
97
–0.35
0
106
0.39
19200
0
48
–0.35
0
53
–0.54
31250
0
29
0
0
32
0
38400
0
23
1.73
0
26
–0.54
Rev. 3.00 Feb 22, 2006 page 415 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.4 Maximum Bit Rate for Each Frequency (Asynchronous Mode)
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
2
62500
0
0
10
312500
0
0
2.097152
65536
0
0
12
375000
0
0
2.4576
76800
0
0
12.288
384000
0
0
3
93750
0
0
14
437500
0
0
3.6864
115200
0
0
14.7456
460800
0
0
4
125000
0
0
16
500000
0
0
4.9152
153600
0
0
17.2032
537600
0
0
5
156250
0
0
18
562500
0
0
6
187500
0
0
19.6608
614400
0
0
6.144
192000
0
0
20
625000
0
0
7.3728
230400
0
0
25
781250
0
0
8
250000
0
0
30
937500
0
0
9.8304
307200
0
0
33
1031250
0
0
Table 13.5 Maximum Bit Rate with External Clock Input (Asynchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
2
0.5000
31250
10
2.5000
156250
2.097152
0.5243
32768
12
3.0000
187500
2.4576
0.6144
38400
12.288
3.0720
192000
3
0.7500
46875
14
3.5000
218750
3.6864
0.9216
57600
14.7456
3.6864
230400
4
1.0000
62500
16
4.0000
250000
4.9152
1.2288
76800
17.2032
4.3008
268800
5
1.2500
78125
18
4.5000
281250
6
1.5000
93750
19.6608
4.9152
307200
6.144
1.5360
96000
20
5.0000
312500
7.3728
1.8432
115200
25
6.2500
390625
8
2.0000
125000
30
7.5000
468750
9.8304
2.4576
153600
33
8.2500
515625
Rev. 3.00 Feb 22, 2006 page 416 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.6 BRR Settings for Various Bit Rates (Clocked Synchronous Mode)
Operating Frequency φ (MHz)
Bit Rate
(bit/s) n
2
4
N
n
N
8
10
16
n
N
n
N
n
N
20
n
N
25
n
N
110
3
70
—
—
250
2
124
2
249
3
124
—
—
3
249
500
1
249
2
124
2
249
—
—
3
124
—
—
1k
1
124
1
249
2
124
—
—
2
249
—
—
3
97
2.5 k
0
199
1
99
1
199
1
249
2
99
2
124
2
155
5k
0
99
0
199
1
99
1
124
1
199
1
249
2
77
10 k
0
49
0
99
0
199
0
249
1
99
1
124
1
155
25 k
0
19
0
39
0
79
0
99
0
159
0
199
0
249
50 k
0
9
0
19
0
39
0
49
0
79
0
99
0
124
100 k
0
4
0
9
0
19
0
24
0
39
0
49
0
62
250 k
0
1
0
3
0
7
0
9
0
15
0
19
0
24
0
0*
0
1
0
3
0
4
0
7
0
9
—
—
0
0*
0
1
0
3
0
4
—
—
0
0*
0
1
—
—
0
0*
—
—
500 k
1M
2.5 M
5M
Rev. 3.00 Feb 22, 2006 page 417 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Operating Frequency φ
(MHz)
Bit Rate
(bit/s) n
30
N
33
n
N
110
250
500
3
233
1k
3
116
3
128
2.5 k
2
187
2
205
5k
2
93
2
102
10 k
1
187
1
205
25 k
1
74
1
82
50 k
0
149
0
164
100 k
0
74
0
82
250 k
0
29
0
32
500 k
0
14
—
—
1M
—
—
—
—
2.5 M
0
2
—
—
5M
—
—
—
—
Legend:
Blank: Cannot be set.
—:
Can be set, but there will be a degree of error.
*:
Continuous transfer is not possible.
Table 13.7 Maximum Bit Rate with External Clock Input (Clocked Synchronous Mode)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
φ (MHz)
External Input
Clock (MHz)
Maximum Bit
Rate (bit/s)
2
0.3333
333333.3
16
2.6667
2666666.7
4
0.6667
666666.7
18
3.0000
3000000.0
6
1.0000
1000000.0
20
3.3333
3333333.3
8
1.3333
1333333.3
25
4.1667
4166666.7
10
1.6667
1666666.7
30
5.0000
5000000.0
12
2.0000
2000000.0
33
5.5000
5500000.0
14
2.3333
2333333.3
Rev. 3.00 Feb 22, 2006 page 418 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.8 Examples of Bit Rate for Various BRR Settings (Smart Card Interface Mode)
(when n = 0 and S = 372)
Operating Frequency φ (MHz)
7.1424
10.00
10.7136
13.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
1
1
0.00
0
1
30
0
1
25
0
1
8.99
Operating Frequency φ (MHz)
14.2848
16.00
18.00
20.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
0
1
0.00
0
1
12.01
0
2
15.99
0
2
6.60
Operating Frequency φ (MHz)
25.00
30.00
33.00
Bit Rate
(bit/s)
n
N
Error
(%)
n
N
Error
(%)
n
N
Error
(%)
9600
0
3
12.49
0
3
5.01
0
4
7.59
Table 13.9 Maximum Bit Rate at Various Frequencies (Smart Card Interface Mode)
(when S = 372)
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
φ (MHz)
Maximum Bit
Rate (bit/s)
n
N
7.1424
9600
0
0
18.00
24194
0
0
10.00
13441
0
0
20.00
26882
0
0
10.7136
14400
0
0
25.00
33602
0
0
13.00
17473
0
0
30.00
40323
0
0
14.2848
19200
0
0
33.00
44355
0
0
16.00
21505
0
0
Rev. 3.00 Feb 22, 2006 page 419 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.3.10 IrDA Control Register (IrCR)
IrCR selects the function of SCI_0.
Bit
Bit Name
Initial Value
R/W
Description
7
IrE
0
R/W
IrDA Enable
Specifies normal SCI mode or IrDA mode for
SCI_0 input/output.
0: Pins TxD0/IrTxD and RxD0/IrRxD function as
TxD0 and RxD0
1: Pins TxD0/IrTxD and RxD0/IrRxD function as
IrTxD and IrRxD
6
IrCKS2
0
R/W
IrDA Clock Select 2 to 0
5
IrCKS1
0
R/W
4
IrCKS0
0
R/W
Specifies the high pulse width in IrTxD output
pulse encoding when the IrDA function is enabled.
000: Pulse width = B × 3/16 (3/16 of bit rate)
001: Pulse width = φ/2
010: Pulse width = φ/4
011: Pulse width = φ/8
100: Pulse width = φ/16
101: Pulse width = φ/32
110: Pulse width = φ/64
111: Pulse width = φ/128
3
to
0
—
All 0
—
Rev. 3.00 Feb 22, 2006 page 420 of 624
REJ09B0281-0300
Reserved
These bits are always read as 0 and cannot be
modified.
Section 13 Serial Communication Interface (SCI, IrDA)
13.3.11 Serial Extension Mode Register (SEMR)
SEMR selects the clock source in asynchronous mode. The basic clock can be automatically set by
selecting the average transfer rate. SEMR is supported only in SCI_2.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
Undefined
—
Reserved
3
ABCS
If these bits are read, an undefined value will be
returned and cannot be modified.
0
R/W
Asynchronous basic clock selection (valid only in
asynchronous mode)
Selects the basic clock for 1-bit period in
asynchronous mode.
0: Operates on a basic clock with a frequency of
16 times the transfer rate.
1: Operates on a basic clock with a frequency of
8 times the transfer rate.
Rev. 3.00 Feb 22, 2006 page 421 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Bit
Bit Name
Initial Value
R/W
Description
2
ACS2
0
R/W
1
ACS1
0
R/W
Asynchronous clock source selection (valid when
CKS1 = 1 in asynchronous mode)
0
ACS0
0
R/W
Selects the clock source for the average transfer
rate.
The basic clock can be automatically set by
selecting the average transfer rate in spite of the
value of ABCS.
000: External clock input
001: Selects 115.152 kbps which is the average
transfer rate dedicated for φ= 10.667 MHz.
(Operates on a basic clock with a frequency
of 16 times the transfer rate.)
010: Selects 460.606 kbps which is the average
transfer rate dedicated for φ= 10.667 MHz.
(Operates on a basic clock with a frequency
of 8 times the transfer rate.)
011: Selects 720 kbps which is the average
transfer rate dedicated for φ = 32 MHz.
(Operates on a basic clock with a frequency
of 16 times the transfer rate.)
100: Reserved
101: Selects 115.196 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a frequency
of 16 times the transfer rate.)
110: Selects 460.784 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a frequency
of 16 times the transfer rate.)
111: Selects 720 kbps which is the average
transfer rate dedicated for φ = 16 MHz
(Operates on a basic clock with a frequency
of 8 times the transfer rate.)
Note that the average transfer rate does not
correspond to the frequency other than 10.667,
16, or 32 MHz.
Rev. 3.00 Feb 22, 2006 page 422 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.4
Operation in Asynchronous Mode
Figure 13.2 shows the general format for asynchronous serial communication. One frame consists
of a start bit (low level), followed by transfer data, a parity bit, and finally stop bits (high level). In
asynchronous serial communication, the transmission line is usually held in the mark state (high
level). The SCI monitors the transmission line, and when it goes to the space state (low level),
recognizes a start bit and starts serial communication. In asynchronous serial communication, the
communication line is usually held in the mark state (high level). The SCI monitors the
communication line, and when it goes to the space state (low level), recognizes a start bit and
starts serial communication. Inside the SCI, the transmitter and receiver are independent units,
enabling full-duplex communication. Both the transmitter and the receiver also have a doublebuffered structure, so that data can be read or written during transmission or reception, enabling
continuous data transfer.
Idle state
(mark state)
1
MSB
LSB
Serial
data
0
D0
D1
D2
D3
D4
D5
Start
bit
Transmit/receive data
1 bit
7 or 8 bits
D6
D7
1
0/1
1
1
Parity Stop bit(s)
bit
1 bit,
or none
1 or
2 bits
One unit of transfer data (character or frame)
Figure 13.2 Data Format in Asynchronous Communication
(Example with 8-Bit Data, Parity, Two Stop Bits)
13.4.1
Data Transfer Format
Table 13.10 shows the data transfer formats that can be used in asynchronous mode. Any of 12
transfer formats can be selected according to the SMR setting. For details on the multiprocessor
bit, refer to section 13.5, Multiprocessor Communication Function.
Rev. 3.00 Feb 22, 2006 page 423 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.10 Serial Transfer Formats (Asynchronous Mode)
SMR Settings
Serial Transfer Format and Frame Length
CHR
PE
MP
STOP
1
0
0
0
0
S
8-bit data
STOP
0
0
0
1
S
8-bit data
STOP STOP
0
1
0
0
S
8-bit data
P STOP
0
1
0
1
S
8-bit data
P STOP STOP
1
0
0
0
S
7-bit data
STOP
1
0
0
1
S
7-bit data
STOP STOP
1
1
0
0
S
7-bit data
P
STOP
1
1
0
1
S
7-bit data
P
STOP STOP
0
—
1
0
S
8-bit data
MPB STOP
0
—
1
1
S
8-bit data
MPB STOP STOP
1
—
1
0
S
7-bit data
MPB STOP
1
—
1
1
S
7-bit data
MPB STOP STOP
Legend:
S
: Start bit
STOP : Stop bit
P
: Parity bit
MPB : Multiprocessor bit
Rev. 3.00 Feb 22, 2006 page 424 of 624
REJ09B0281-0300
2
3
4
5
6
7
8
9
10
11
12
Section 13 Serial Communication Interface (SCI, IrDA)
13.4.2
Receive Data Sampling Timing and Reception Margin in Asynchronous Mode
In asynchronous mode, the SCI operates on a basic clock with a frequency of 16 times the bit rate.
In reception, the SCI samples the falling edge of the start bit using the basic clock, and performs
internal synchronization. Receive data is latched at the middle of each bit by sampling the data at
the rising edge of the 8th pulse of the basic clock as shown in figure 13.3. Thus the reception
margin in asynchronous mode is given by formula (1) below.
{
M = (0.5 –
1
D – 0.5
) – (L – 0.5) F –
(1 + F)
2N
N
} × 100 [%]
... Formula (1)
Where M: Reception Margin
N: Ratio of bit rate to clock (N = 16)
D: Clock duty cycle (D = 0.5 to 1.0)
L: Frame length (L = 9 to 12)
F: Absolute value of clock rate deviation
Assuming values of F = 0 and D = 0.5 in formula (1), a reception margin is given by formula
below.
M = {0.5 – 1/(2 × 16)} × 100 [%] = 46.875%
However, this is only the computed value, and a margin of 20% to 30% should be allowed in
system design.
16 clocks
8 clocks
0
7
15 0
7
15 0
Internal base
clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.3 Receive Data Sampling Timing in Asynchronous Mode
Rev. 3.00 Feb 22, 2006 page 425 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
13.4.3
Clock
Either an internal clock generated by the on-chip baud rate generator or an external clock input at
the SCK pin can be selected as the SCI’s serial clock, according to the setting of the C/A bit in
SMR and the CKE1 and CKE0 bits in SCR. When an external clock is input at the SCK pin, the
clock frequency should be 16 times the bit rate used.
When the SCI is operated on an internal clock, the clock can be output from the SCK pin. The
frequency of the clock output in this case is equal to the bit rate, and the phase is such that the
rising edge of the clock is in the middle of the transmit data, as shown in figure 13.4.
SCK
TxD
0
D0
D1
D2
D3
D4
D5
D6
D7
0/1
1
1
1 frame
Figure 13.4 Relation between Output Clock and Transfer Data Phase
(Asynchronous Mode)
Rev. 3.00 Feb 22, 2006 page 426 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
13.4.4
SCI Initialization (Asynchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as shown in figure 13.5. When the operating mode, transfer format, etc., is
changed, the TE and RE bits must be cleared to 0 before making the change. When the TE bit is
cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit to 0 does not initialize the
contents of the RDRF, PER, FER, and ORER flags, or the contents of RDR. When the external
clock is used in asynchronous mode, the clock must be supplied even during initialization.
[1] Set the clock selection in SCR.
Be sure to clear bits RIE, TIE,
TEIE, and MPIE, and bits TE and
RE, to 0.
Start of initialization
Clear TE and RE bits in SCR to 0
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
When the clock is selected in
asynchronous mode, it is output
immediately after SCR settings are
made.
[2] Set the data transfer format in SMR
and SCMR.
[3] Write a value corresponding to the
bit rate to BRR. (Not necessary if
an external clock is used.)
Wait
No
1-bit interval elapsed?
Yes
Set TE and RE bits in
SCR to 1, and set RIE, TIE, TEIE,
and MPIE bits
[4] Wait at least one bit interval, then
set the TE bit or RE bit in SCR to 1.
Also set the RIE, TIE, TEIE, and
MPIE bits.
Setting the TE and RE bits enables
the TxD and RxD pins to be used.
[4]
<Initialization completed>
Figure 13.5 Sample SCI Initialization Flowchart
Rev. 3.00 Feb 22, 2006 page 427 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
13.4.5
Data Transmission (Asynchronous Mode)
Figure 13.6 shows an example of the operation for transmission in asynchronous mode. In
transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is cleared to 0, recognizes that data has been
written to TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit is set to 1 at this time, a transmit data empty interrupt request
(TXI) is generated. Because the TXI interrupt routine writes the next transmit data to TDR
before transmission of the current transmit data has finished, continuous transmission can be
enabled.
3. Data is sent from the TxD pin in the following order: start bit, transmit data, parity bit or
multiprocessor bit (may be omitted depending on the format), and stop bit.
4. The SCI checks the TDRE flag at the timing for sending the stop bit.
5. If the TDRE flag is 0, the data is transferred from TDR to TSR, the stop bit is sent, and then
serial transmission of the next frame is started.
6. If the TDRE flag is 1, the TEND flag in SSR is set to 1, the stop bit is sent, and then the “mark
state” is entered in which 1 is output. If the TEIE bit in SCR is set to 1 at this time, a TEI
interrupt request is generated.
Figure 13.7 shows a sample flowchart for transmission in asynchronous mode.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
1
1
Idle state
(mark state)
TDRE
TEND
TXI interrupt
Data written to TDR and
TXI interrupt
request generated TDRE flag cleared to 0 in
request generated
TXI interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 13.6 Example of Operation in Transmission in Asynchronous Mode
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 3.00 Feb 22, 2006 page 428 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
Start of transmission
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
No
TDRE = 1?
Yes
Write transmit data to TDR
and clear TDRE flag in SSR to 0
No
All data transmitted?
Yes
[3]
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
Yes
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1, a frame
of 1s is output, and transmission is
enabled.
[4]
[3] Serial transmission continuation
procedure:
To continue serial transmission,
read 1 from the TDRE flag to
confirm that writing is possible,
then write data to TDR, and then
clear the TDRE flag to 0. Checking
and clearing of the TDRE flag is
automatic when the DTC is
activated by a transmit-dataempty interrupt (TXI) request, and
data is written to TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set DDR for the port
corresponding to the TxD pin to 1,
clear DR to 0, then clear the TE bit
in SCR to 0.
Clear DR to 0 and
set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 13.7 Sample Serial Transmission Flowchart
Rev. 3.00 Feb 22, 2006 page 429 of 624
REJ09B0281-0300
Section 13 Serial Communication Interface (SCI, IrDA)
13.4.6
Serial Data Reception (Asynchronous Mode)
Figure 13.8 shows an example of the operation for reception in asynchronous mode. In serial
reception, the SCI operates as described below.
1. The SCI monitors the communication line, and if a start bit is detected, performs internal
synchronization, receives receive data in RSR, and checks the parity bit and stop bit.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If a parity error is detected, the PER bit in SSR is set to 1 and receive data is transferred to
RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt request is generated.
4. If a framing error (when the stop bit is 0) is detected, the FER bit in SSR is set to 1 and receive
data is transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an ERI interrupt
request is generated.
5. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
1
Start
bit
0
Data
D0
D1
Parity Stop Start
bit
bit
bit
D7
0/1
1
0
Data
D0
D1
Parity Stop
bit
bit
D7
0/1
0
1
Idle state
(mark state)
RDRF
FER
RXI interrupt
request
generated
RDR data read and RDRF
flag cleared to 0 in RXI
interrupt handling routine
ERI interrupt request
generated by framing
error
1 frame
Figure 13.8 Example of SCI Operation in Reception
(Example with 8-Bit Data, Parity, One Stop Bit)
Rev. 3.00 Feb 22, 2006 page 430 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.11 shows the states of the SSR status flags and receive data handling when a receive
error is detected. If a receive error is detected, the RDRF flag retains its state before receiving
data. Reception cannot be resumed while a receive error flag is set to 1. Accordingly, clear the
ORER, FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.9 shows a sample
flowchart for serial data reception.
Table 13.11 SSR Status Flags and Receive Data Handling
SSR Status Flag
RDRF*
ORER
FER
PER
Receive Data
Receive Error Type
1
1
0
0
Lost
Overrun error
0
0
1
0
Transferred to RDR
Framing error
0
0
0
1
Transferred to RDR
Parity error
1
1
1
0
Lost
Overrun error + framing error
1
1
0
1
Lost
Overrun error + parity error
0
0
1
1
Transferred to RDR
Framing error + parity error
1
1
1
1
Lost
Overrun error + framing error +
parity error
Note:
*
The RDRF flag retains its state before data reception.
Rev. 3.00 Feb 22, 2006 page 431 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
Start of reception
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling and
break detection:
Read ORER, PER, and
If a receive error occurs, read the
[2]
FER flags in SSR
ORER, PER, and FER flags in
SSR to identify the error. After
performing the appropriate error
Yes
processing, ensure that the
PER ∨ FER ∨ ORER = 1?
ORER, PER, and FER flags are
[3]
all cleared to 0. Reception cannot
No
Error handling
be resumed if any of these flags
(Continued on next page) are set to 1. In the case of a
framing error, a break can be
detected by reading the value of
[4]
Read RDRF flag in SSR
the input port corresponding to
the RxD pin.
No
RDRF = 1?
[4] SCI status check and receive
data read :
Read SSR and check that RDRF
= 1, then read the receive data in
RDR and clear the RDRF flag to
0. Transition of the RDRF flag
from 0 to 1 can also be identified
by an RXI interrupt.
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
<End>
[5]
[5] Serial reception continuation
procedure:
To continue serial reception,
before the stop bit for the current
frame is received, read the
RDRF flag, read RDR, and clear
the RDRF flag to 0. The RDRF
flag is cleared automatically
when the DTC is activated by an
RXI interrupt and the RDR value
is read.
Figure 13.9 Sample Serial Reception Data Flowchart (1)
Rev. 3.00 Feb 22, 2006 page 432 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
[3]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
No
PER = 1?
Yes
Parity error handling
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 13.9 Sample Serial Reception Data Flowchart (2)
Rev. 3.00 Feb 22, 2006 page 433 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.5
Multiprocessor Communication Function
Use of the multiprocessor communication function enables data transfer to be performed among a
number of processors sharing communication lines by means of asynchronous serial
communication using the multiprocessor format, in which a multiprocessor bit is added to the
transfer data. When multiprocessor communication is carried out, each receiving station is
addressed by a unique ID code. The serial communication cycle consists of two component
cycles: an ID transmission cycle which specifies the receiving station, and a data transmission
cycle to the specified receiving station. The multiprocessor bit is used to differentiate between the
ID transmission cycle and the data transmission cycle. If the multiprocessor bit is 1, the cycle is
an ID transmission cycle, and if the multiprocessor bit is 0, the cycle is a data transmission cycle.
Figure 13.10 shows an example of inter-processor communication using the multiprocessor
format. The transmitting station first sends communication data with a 1 multiprocessor bit added
to the ID code of the receiving station. It then sends transmit data as data with a 0 multiprocessor
bit added. When data with a 1 multiprocessor bit is received, the receiving station compares that
data with its own ID. The station whose ID matches then receives the data sent next. Stations
whose ID does not match continue to skip data until data with a 1 multiprocessor bit is again
received.
The SCI uses the MPIE bit in SCR to implement this function. When the MPIE bit is set to 1,
transfer of receive data from RSR to RDR, error flag detection, and setting the SSR status flags,
RDRF, FER, and ORER to 1 are inhibited until data with a 1 multiprocessor bit is received. On
reception of receive character with a 1 multiprocessor bit, the MPBR bit in SSR is set to 1 and the
MPIE bit is automatically cleared, thus normal reception is resumed. If the RIE bit in SCR is set to
1 at this time, an RXI interrupt is generated.
When the multiprocessor format is selected, the parity bit setting is invalid. All other bit settings
are the same as those in normal asynchronous mode. The clock used for multiprocessor
communication is the same as that in normal asynchronous mode.
Rev. 3.00 Feb 22, 2006 page 434 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Transmitting
station
Serial communication line
Receiving
station A
Receiving
station B
Receiving
station C
Receiving
station D
(ID = 01)
(ID = 02)
(ID = 03)
(ID = 04)
Serial
data
H'AA
H'01
(MPB= 1)
ID transmission cycle =
receiving station
specification
(MPB= 0)
Data transmission cycle =
data transmission to
receiving station specified by ID
Legend:
MPB: Multiprocessor bit
Figure 13.10 Example of Communication Using Multiprocessor Format
(Transmission of Data H'AA to Receiving Station A)
13.5.1
Multiprocessor Serial Data Transmission
Figure 13.11 shows a sample flowchart for multiprocessor serial data transmission. For an ID
transmission cycle, set the MPBT bit in SSR to 1 before transmission. For a data transmission
cycle, clear the MPBT bit in SSR to 0 before transmission. All other SCI operations are the same
as those in asynchronous mode.
Rev. 3.00 Feb 22, 2006 page 435 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
[1] [1] SCI initialization:
Initialization
Start of transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
set MPBT bit in SSR
Clear TDRE flag to 0
No
All data transmitted?
Yes
Read TEND flag in SSR
No
TEND = 1?
Yes
No
Break output?
The TxD pin is automatically
designated as the transmit data
output pin.
After the TE bit is set to 1,
a frame of 1s is output, and
transmission is enabled.
[2] SCI status check and transmit
data write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR. Set the
MPBT bit in SSR to 0 or 1.
Finally, clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission,
be sure to read 1 from the TDRE
flag to confirm that writing is
[3]
possible, then write data to TDR,
and then clear the TDRE flag to
0. Checking and clearing of the
TDRE flag is automatic when the
DTC is activated by a transmitdata-empty interrupt (TXI)
request, and data is written to
TDR.
[4] Break output at the end of serial
transmission:
To output a break in serial
transmission, set the port DDR to
[4]
1, clear DR to 0, then clear the
TE bit in SCR to 0.
Yes
Clear DR to 0 and set DDR to 1
Clear TE bit in SCR to 0
<End>
Figure 13.11 Sample Multiprocessor Serial Transmission Flowchart
Rev. 3.00 Feb 22, 2006 page 436 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.5.2
Multiprocessor Serial Data Reception
Figure 13.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is received. On receiving
data with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request
is generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
13.12 shows an example of SCI operation for multiprocessor format reception.
1
Start
bit
0
Data (ID1)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data1)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
RXI interrupt
request
(multiprocessor
interrupt)
generated
MPIE = 0
If not this station’s ID, RXI interrupt request is
MPIE bit is set to 1
not generated, and RDR
again
retains its state
RDR data read
and RDRF flag
cleared to 0 in
RXI interrupt
handling routine
(a) Data does not match station’s ID
1
Start
bit
0
Data (ID2)
MPB
D0
D1
D7
1
Stop
bit
Start
bit
1
0
Data (Data2)
MPB
D0
D1
D7
0
Stop
bit
1
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
Data2
ID2
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
handling routine
Matches this station’s ID,
so reception continues, and
data is received in RXI
interrupt handling routine
MPIE bit set to 1
again
(b) Data matches station’s ID
Figure 13.12 Example of SCI Operation in Reception
(Example with 8-Bit Data, Multiprocessor Bit, One Stop Bit)
Rev. 3.00 Feb 22, 2006 page 437 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Initialization
[1]
[1] SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2]
[2] ID reception cycle:
Set the MPIE bit in SCR to 1.
Start of reception
Set MPIE bit in SCR to 1
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
[3] SCI status check, ID reception
and comparison:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
compare it with this station’s ID.
If the data is not this station’s ID,
set the MPIE bit to 1 again, and
clear the RDRF flag to 0.
If the data is this station’s ID,
clear the RDRF flag to 0.
Yes
No
Read RDRF flag in SSR
[3]
No
RDRF = 1?
Yes
[4] SCI status check and data
reception:
Read SSR and check that the
RDRF flag is set to 1, then read
the data in RDR.
Read receive data in RDR
No
This station's ID?
Yes
[5] Receive error handling and break
detection:
If a receive error occurs, read the
ORER and FER flags in SSR to
identify the error. After
performing the appropriate error
handling, ensure that the ORER
and FER flags are both cleared
to 0.
Reception cannot be resumed if
either of these flags is set to 1.
In the case of a framing error, a
break can be detected by reading
the RxD pin value.
Read ORER and FER flags in SSR
FER ∨ ORER = 1?
Yes
No
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR
No
All data received?
[5]
Error handling
Yes
Clear RE bit in SCR to 0
(Continued on
next page)
<End>
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (1)
Rev. 3.00 Feb 22, 2006 page 438 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
[5]
Error handling
No
ORER = 1?
Yes
Overrun error handling
No
FER = 1?
Yes
Yes
Break?
No
Framing error handling
Clear RE bit in SCR to 0
Clear ORER, PER, and
FER flags in SSR to 0
<End>
Figure 13.13 Sample Multiprocessor Serial Reception Flowchart (2)
Rev. 3.00 Feb 22, 2006 page 439 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.6
Operation in Clocked Synchronous Mode
Figure 13.14 shows the general format for clocked synchronous communication. In clocked
synchronous mode, data is transmitted or received in synchronization with clock pulses. One
character of communication data consists of 8-bit data. In clocked synchronous serial
communication, data on the transmission line is output from one falling edge of the serial clock to
the next. In clocked synchronous mode, the SCI receives data in synchronization with the rising
edge of the serial clock. After 8-bit data is output, the transmission line holds the MSB state. In
clocked synchronous mode, no parity or multiprocessor bit is added. Inside the SCI, the
transmitter and receiver are independent units, enabling full-duplex communication by use of a
common clock. Both the transmitter and the receiver also have a double-buffered structure, so that
data can be read or written during transmission or reception, enabling continuous data transfer.
One unit of transfer data (character or frame)
*
*
Serial
clock
LSB
Serial
data
Bit 0
MSB
Bit 1
Bit 2
Don’t care
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Don’t care
Note: * High except in continuous transfer
Figure 13.14 Data Format in Clocked Synchronous Communication (For LSB-First)
13.6.1
Clock
Either an internal clock generated by the on-chip baud rate generator or an external
synchronization clock input at the SCK pin can be selected, according to the setting of CKE1 and
CKE0 bits in SCR. When the SCI is operated on an internal clock, the serial clock is output from
the SCK pin. Eight serial clock pulses are output in the transfer of one character, and when no
transfer is performed the clock is fixed high.
Rev. 3.00 Feb 22, 2006 page 440 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.6.2
SCI Initialization (Clocked Synchronous Mode)
Before transmitting and receiving data, you should first clear the TE and RE bits in SCR to 0, then
initialize the SCI as described in a sample flowchart in figure 13.15. When the operating mode,
transfer format, etc., is changed, the TE and RE bits must be cleared to 0 before making the
change. When the TE bit is cleared to 0, the TDRE flag is set to 1. Note that clearing the RE bit
to 0 does not change the contents of the RDRF, PER, FER, and ORER flags, or the contents of
RDR.
[1] Set the clock selection in SCR. Be sure
to clear bits RIE, TIE, TEIE, and MPIE,
TE and RE, to 0.
Start of initialization
Clear TE and RE bits in SCR to 0
[2] Set the data transfer format in SMR
and SCMR.
Set CKE1 and CKE0 bits in SCR
(TE, RE bits 0)
[1]
Set data transfer format in
SMR and SCMR
[2]
Set value in BRR
[3]
Wait
[3] Write a value corresponding to the bit
rate to BRR. (Not necessary if an
external clock is used.)
[4] Wait at least one bit interval, then set
the TE and RE bits in SCR to 1.
Also set the RIE, TIE, TEIE, and MPIE
bits.
Setting the TE and RE bits enable the
TxD and RxD pins to be used.
No
1-bit interval elapsed?
Yes
Set TE and RE bits in SCR to 1, and
set RIE, TIE, TEIE, and MPIE bits
[4]
<Transfer start>
Note: In simultaneous transmit and receive operations, the TE and RE bits should
both be cleared to 0 or set to 1 simultaneously.
Figure 13.15 Sample SCI Initialization Flowchart
Rev. 3.00 Feb 22, 2006 page 441 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.6.3
Serial Data Transmission (Clocked Synchronous Mode)
Figure 13.16 shows an example of SCI operation for transmission in clocked synchronous mode.
In serial transmission, the SCI operates as described below.
1. The SCI monitors the TDRE flag in SSR, and if is 0, recognizes that data has been written to
TDR, and transfers the data from TDR to TSR.
2. After transferring data from TDR to TSR, the SCI sets the TDRE flag to 1 and starts
transmission. If the TIE bit in SCR is set to 1 at this time, a TXI interrupt request is generated.
Because the TXI interrupt routine writes the next transmit data to TDR before transmission of
the current transmit data has finished, continuous transmission can be enabled.
3. 8-bit data is sent from the TxD pin synchronized with the output clock when output clock
mode has been specified and synchronized with the input clock when use of an external clock
has been specified.
4. The SCI checks the TDRE flag at the timing for sending the MSB.
5. If the TDRE flag is cleared to 0, data is transferred from TDR to TSR, and serial transmission
of the next frame is started.
6. If the TDRE flag is set to 1, the TEND flag in SSR is set to 1, and the TxD pin maintains the
output state of the last bit. If the TEIE bit in SCR is set to 1 at this time, a TEI interrupt
request is generated. The SCK pin is fixed high.
Figure 13.17 shows a sample flowchart for serial data transmission. Even if the TDRE flag is
cleared to 0, transmission will not start while a receive error flag (ORER, FER, or PER) is set to 1.
Make sure to clear the receive error flags to 0 before starting transmission. Note that clearing the
RE bit to 0 does not clear the receive error flags.
Rev. 3.00 Feb 22, 2006 page 442 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Transfer direction
Serial clock
Serial data
Bit 0
Bit 1
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
TDRE
TEND
TXI interrupt
request generated
Data written to TDR
TXI interrupt
and TDRE flag
request generated
cleared to 0 in TXI
interrupt handling routine
TEI interrupt
request generated
1 frame
Figure 13.16 Sample SCI Transmission Operation in Clocked Synchronous Mode
Rev. 3.00 Feb 22, 2006 page 443 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
[1]
Initialization
Start of transmission
Read TDRE flag in SSR
[2]
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
No
All data transmitted?
[3]
Yes
Read TEND flag in SSR
[1] SCI initialization:
The TxD pin is automatically
designated as the transmit data output
pin.
[2] SCI status check and transmit data
write:
Read SSR and check that the TDRE
flag is set to 1, then write transmit data
to TDR and clear the TDRE flag to 0.
[3] Serial transmission continuation
procedure:
To continue serial transmission, be
sure to read 1 from the TDRE flag to
confirm that writing is possible, then
write data to TDR, and then clear the
TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request and data is
written to TDR.
No
TEND = 1?
Yes
Clear TE bit in SCR to 0
<End>
Figure 13.17 Sample Serial Transmission Flowchart
Rev. 3.00 Feb 22, 2006 page 444 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.6.4
Serial Data Reception (Clocked Synchronous Mode)
Figure 13.18 shows an example of SCI operation for reception in clocked synchronous mode. In
serial reception, the SCI operates as described below.
1. The SCI performs internal initialization in synchronization with a synchronization clock input
or output, starts receiving data, and stores the received data in RSR.
2. If an overrun error (when reception of the next data is completed while the RDRF flag is still
set to 1) occurs, the ORER bit in SSR is set to 1. If the RIE bit in SCR is set to 1 at this time,
an ERI interrupt request is generated. Receive data is not transferred to RDR. The RDRF flag
remains to be set to 1.
3. If reception finishes successfully, the RDRF bit in SSR is set to 1, and receive data is
transferred to RDR. If the RIE bit in SCR is set to 1 at this time, an RXI interrupt request is
generated. Because the RXI interrupt routine reads the receive data transferred to RDR before
reception of the next receive data has finished, continuous reception can be enabled.
Serial
clock
Serial
data
Bit 7
Bit 0
Bit 7
Bit 0
Bit 1
Bit 6
Bit 7
RDRF
ORER
RXI interrupt request
generated
RDR data read and
RDRF flag cleared to 0
in RXI interrupt handling
routine
RXI interrupt request
generated
ERI interrupt request
generated by overrun
error
1 frame
Figure 13.18 Example of SCI Operation in Reception
Transfer cannot be resumed while a receive error flag is set to 1. Accordingly, clear the ORER,
FER, PER, and RDRF bits to 0 before resuming reception. Figure 13.19 shows a sample
flowchart for serial data reception.
Rev. 3.00 Feb 22, 2006 page 445 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
[1]
Initialization
Start of reception
[2]
Read ORER flag in SSR
Yes
[3]
ORER = 1?
No
Error processing
(Continued below)
Read RDRF flag in SSR
[4]
No
RDRF = 1?
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit in SCR to 0
[5]
[1]
SCI initialization:
The RxD pin is automatically
designated as the receive data
input pin.
[2] [3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
handling, clear the ORER flag to
0. Transfer cannot be resumed if
the ORER flag is set to 1.
[4] SCI status check and receive
data read:
Read SSR and check that the
RDRF flag is set to 1, then read
the receive data in RDR and
clear the RDRF flag to 0.
Transition of the RDRF flag from
0 to 1 can also be identified by
an RXI interrupt.
[5] Serial reception continuation
procedure:
To continue serial reception,
before the MSB (bit 7) of the
current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag
to 0. The RDRF flag is cleared
automatically when the DTC is
activated by a receive-data-full
interrupt (RXI) request and the
RDR value is read.
<End>
[3]
Error handling
Overrun error handling
Clear ORER flag in SSR to 0
<End>
Figure 13.19 Sample Serial Reception Flowchart
Rev. 3.00 Feb 22, 2006 page 446 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
13.6.5
Simultaneous Serial Data Transmission and Reception (Clocked Synchronous
Mode)
Figure 13.20 shows a sample flowchart for simultaneous serial transmit and receive operations.
The following procedure should be used for simultaneous serial data transmit and receive
operations after the SCI is initialized. To switch from transmit mode to simultaneous transmit and
receive mode, after checking that the SCI has finished transmission and the TDRE and TEND
flags are set to 1, clear TE to 0. Then simultaneously set TE and RE to 1 with a single instruction.
To switch from receive mode to simultaneous transmit and receive mode, after checking that the
SCI has finished reception, clear RE to 0. Then after checking that the RDRF and receive error
flags (ORER, FER, and PER) are cleared to 0, simultaneously set TE and RE to 1 with a single
instruction.
Rev. 3.00 Feb 22, 2006 page 447 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
Initialization
[1] SCI initialization:
[1]
The TxD pin is designated as the
transmit data output pin, and the
RxD pin is designated as the
receive data input pin, enabling
simultaneous transmit and receive
operations.
Start of transmission/reception
Read TDRE flag in SSR
[2]
[2] SCI status check and transmit data
write:
Read SSR and check that the
TDRE flag is set to 1, then write
transmit data to TDR and clear the
TDRE flag to 0.
Transition of the TDRE flag from 0 to
1 can also be identified by a TXI
interrupt.
No
TDRE = 1?
Yes
Write transmit data to TDR and
clear TDRE flag in SSR to 0
[3] Receive error handling:
If a receive error occurs, read the
ORER flag in SSR, and after
performing the appropriate error
handling, clear the ORER flag to 0.
Transmission/reception cannot be
resumed if the ORER flag is set to 1.
Read ORER flag in SSR
ORER = 1?
No
Read RDRF flag in SSR
Yes
[3]
Error handling
[4] SCI status check and receive data
read:
Read SSR and check that the
RDRF flag is set to 1, then read the
receive data in RDR and clear the
RDRF flag to 0. Transition of the
RDRF flag from 0 to 1 can also be
identified by an RXI interrupt.
[4]
No
RDRF = 1?
[5] Serial transmission/reception
Yes
Read receive data in RDR, and
clear RDRF flag in SSR to 0
No
All data received?
[5]
Yes
Clear TE and RE bits in SCR to 0
<End>
Note: When switching from transmit or receive operation to simultaneous
transmit and receive operations, first clear the TE and RE bits to 0,
then set both these bits to 1 simultaneously.
continuation procedure:
To continue serial transmission/
reception, before the MSB (bit 7) of
the current frame is received, finish
reading the RDRF flag, reading
RDR, and clearing the RDRF flag to
0. Also, before the MSB (bit 7) of
the current frame is transmitted,
read 1 from the TDRE flag to
confirm that writing is possible.
Then write data to TDR and clear
the TDRE flag to 0.
Checking and clearing of the TDRE
flag is automatic when the DTC is
activated by a transmit-data-empty
interrupt (TXI) request and data is
written to TDR. Also, the RDRF flag
is cleared automatically when the
DTC is activated by a receive-datafull interrupt (RXI) request and the
RDR value is read.
Figure 13.20 Sample Flowchart of Simultaneous Serial Transmit and Receive Operations
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Section 13 Serial Communication Interface (SCI, IrDA)
13.7
Operation in Smart Card Interface Mode
The SCI supports an IC card (Smart Card) interface conforming to ISO/IEC 7816-3 (Identification
Card) as a serial communication interface extension function. Switching between the normal
serial communication interface and the Smart Card interface is carried out by means of a register
setting.
13.7.1
Pin Connection Example
Figure 13.21 shows an example of connection with the Smart Card. In communication with an IC
card, since both transmission and reception are carried out on a single data transmission line, the
TxD pin and RxD pin should be connected with the LSI pin. The data transmission line should be
pulled up to the VCC power supply with a resistor. If an IC card is not connected, and the TE and
RE bits are both set to 1, closed transmission/reception is possible, enabling self-diagnosis to be
carried out. When the clock generated on the SCI is used by an IC card, the SCK pin output is
input to the CLK pin of the IC card. This LSI port output is used as the reset signal.
VCC
TxD
RxD
SCK
Rx (port)
This LSI
Data line
Clock line
Reset line
I/O
CLK
RST
IC card
Connected equipment
Figure 13.21 Schematic Diagram of Smart Card Interface Pin Connections
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Section 13 Serial Communication Interface (SCI, IrDA)
13.7.2
Data Format (Except for Block Transfer Mode)
Figure 13.22 shows the transfer data format in Smart Card interface mode.
• One frame consists of 8-bit data plus a parity bit in asynchronous mode.
• In transmission, a guard time of at least 2 etu (Elementary Time Unit: the time for transfer of
one bit) is left between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for one etu
period, 10.5 etu after the start bit.
• If an error signal is sampled during transmission, the same data is retransmitted automatically
after the elapse of 2 etu or longer.
When there is no parity error
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
D6
D7
Dp
Transmitting station output
When a parity error occurs
Ds
D0
D1
D2
D3
D4
D5
DE
Transmitting station output
Legend:
Ds:
D0 to D7:
Dp:
DE:
Receiving station
output
Start bit
Data bits
Parity bit
Error signal
Figure 13.22 Normal Smart Card Interface Data Format
Data transfer with the types of IC cards (direct convention and inverse convention) are performed
as described in the following.
(Z)
A
Z
Z
A
Z
Z
Z
A
A
Z
Ds
D0
D1
D2
D3
D4
D5
D6
D7
Dp
(Z)
State
Figure 13.23 Direct Convention (SDIR = SINV = O/E
E = 0)
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Section 13 Serial Communication Interface (SCI, IrDA)
As in the above sample start character, with the direct convention type, the logic 1 level
corresponds to state Z and the logic 0 level to state A, and transfer is performed in LSB-first order.
The start character data above is H'3B. For the direct convention type, clear the SDIR and SINV
bits in SCMR to 0. According to the Smart Card regulations, clear the O/E bit in SMR to 0 to
select even parity mode.
(Z)
A
Z
Z
A
A
A
A
A
A
Z
Ds
D7
D6
D5
D4
D3
D2
D1
D0
Dp
(Z)
State
Figure 13.24 Inverse Convention (SDIR = SINV = O/E
E = 1)
With the inverse convention type, the logic 1 level corresponds to state A and the logic 0 level to
state Z, and transfer is performed in MSB-first order. The start character data above is H'3F. For
the inverse convention type, set the SDIR and SINV bits in SCMR to 1. According to the Smart
Card regulations, even parity mode is the logic 0 level of the parity bit, and corresponds to state Z.
In this LSI, the SINV bit inverts only data bits D7 to D0. Therefore, set the O/E bit in SMR to 1
to invert the parity bit for both transmission and reception.
13.7.3
Block Transfer Mode
Operation in block transfer mode is the same as that in normal Smart Card interface, except for the
following points.
• In reception, though the parity check is performed, no error signal is output even if an error is
detected. However, the PER bit in SSR is set to 1 and must be cleared before receiving the
parity bit of the next frame.
• In transmission, a guard time of at least 1 etu is left between the end of the parity bit and the
start of the next frame.
• In transmission, because retransmission is not performed, the TEND flag is set to 1, 11.5 etu
after transmission start.
• As with the normal Smart Card interface, the ERS flag indicates the error signal status, but
since error signal transfer is not performed, this flag is always cleared to 0.
13.7.4
Receive Data Sampling Timing and Reception Margin
Only the internal clock generated by the on-chip baud rate generator is used as transmit/receive
clock in Smart Card interface. In Smart Card interface mode, the SCI operates on a basic clock
with a frequency of 32, 64, 372, or 256 times the bit rate (fixed at 16 times in normal
asynchronous mode) as determined by bits BCP1 and BCP0. In reception, the SCI samples the
Rev. 3.00 Feb 22, 2006 page 451 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
falling edge of the start bit using the basic clock, and performs internal synchronization. As
shown in figure 13.25, by sampling receive data at the rising-edge of the 16th, 32nd, 186th, or
128th pulse of the basic clock, data can be latched at the middle of the bit. The reception margin is
given by the following formula.
M = (0.5 –
Where M:
N:
D:
L:
F:
1
D – 0.5
) – (L – 0.5) F –
(1 + F) × 100 [%]
2N
N
Reception margin (%)
Ratio of bit rate to clock (N = 32, 64, 372, and 256)
Clock duty cycle (D = 0 to 1.0)
Frame length (L = 10)
Absolute value of clock frequency deviation
Assuming values of F = 0, D = 0.5 and N = 372 in the above formula, the reception margin
formula is as follows.
M = (0.5 – 1/2 × 372) × 100%
= 49.866%
372 clocks
186 clocks
0
185
185
371 0
371 0
Internal
basic clock
Receive data
(RxD)
Start bit
D0
D1
Synchronization
sampling timing
Data sampling
timing
Figure 13.25 Receive Data Sampling Timing in Smart Card Mode
(Using Clock of 372 Times the Bit Rate)
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Section 13 Serial Communication Interface (SCI, IrDA)
13.7.5
Initialization
Before transmitting and receiving data, initialize the SCI as described below. Initialization is also
necessary when switching from transmit mode to receive mode, or vice versa.
1. Clear the TE and RE bits in SCR to 0.
2. Clear the error flags ERS, PER, and ORER in SSR to 0.
3. Set the GM, BLK, O/E, BCP1, BCP0, CKS1, and CKS0 bits in SMR. Set the PE bit to 1.
4. Set the SMIF, SDIR, and SINV bits in SCMR.
When the SMIF bit is set to 1, the TxD and RxD pins are both switched from ports to SCI pins,
and are placed in the high-impedance state.
5. Set the value corresponding to the bit rate in BRR.
6. Set the CKE0 and CKE1 bits in SCR. Clear the TIE, RIE, TE, RE, MPIE, and TEIE bits to 0.
If the CKE0 bit is set to 1, the clock is output from the SCK pin.
7. Wait at least one bit interval, then set the TIE, RIE, TE, and RE bits in SCR. Do not set the TE
bit and RE bit at the same time, except for self-diagnosis.
To switch from receive mode to transmit mode, after checking that the SCI has finished reception,
initialize the SCI, and clear RE to 0 and set TE to 1. Whether SCI has finished reception can be
checked with the RDRF, PER, or ORER flag. To switch from transmit mode to receive mode,
after checking that the SCI has finished transmission, initialize the SCI, and clear TE to 0 and set
RE to 1. Whether SCI has finished transmission can be checked with the TEND flag.
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Section 13 Serial Communication Interface (SCI, IrDA)
13.7.6
Data Transmission (Except for Block Transfer Mode)
As data transmission in Smart Card interface mode involves error signal sampling and
retransmission processing, the operations are different from those in normal serial communication
interface mode (except for block transfer mode). Figure 13.26 illustrates the retransfer operation
when the SCI is in transmit mode.
1. If an error signal is sampled from the receiving end after transmission of one frame is
completed, the ERS bit in SSR is set to 1. If the RIE bit in SCR is set at this time, an ERI
interrupt request is generated. The ERS bit in SSR should be cleared to 0 before the next
parity bit is sampled.
2. The TEND bit in SSR is not set for a frame for which an error signal is received. Data is
retransferred from TDR to TSR, and retransmitted automatically.
3. If an error signal is not sent back from the receiving end, the ERS bit in SSR is not set.
Transmission of one frame, including a retransfer, is judged to have been completed, and the
TEND bit in SSR is set to 1. If the TIE bit in SCR is set at this time, a TXI interrupt request is
generated. Writing transmit data to TDR transfers the next transmit data.
Figure 13.28 shows a flowchart for transmission. The sequence of transmit operations can be
performed automatically by specifying the DTC to be activated with a TXI interrupt source. In a
transmit operation, the TDRE flag is also set to 1 at the same time as the TEND flag in SSR, and a
TXI interrupt will be generated if the TIE bit in SCR has been set to 1. If the TXI request is
designated beforehand as a DTC activation source, the DTC will be activated by the TXI request,
and transfer of the transmit data will be carried out. The TDRE and TEND flags are automatically
cleared to 0 when data transfer is performed by the DTC. In the event of an error, the SCI
retransmits the same data automatically. During this period, the TEND flag remains cleared to 0
and the DTC is not activated. Therefore, the SCI and DTC will automatically transmit the
specified number of bytes in the event of an error, including retransmission. However, the ERS
flag is not cleared automatically when an error occurs, and so the RIE bit should be set to 1
beforehand so that an ERI request will be generated in the event of an error, and the ERS flag will
be cleared.
When performing transfer using the DTC, it is essential to set and enable the DTC before carrying
out SCI setting. For details on the DTC setting procedures, refer to section 7, Data Transfer
Controller (DTC).
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Section 13 Serial Communication Interface (SCI, IrDA)
nth transfer frame
Transfer
frame n+1
Retransferred frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
TDRE
Transfer to TSR from TDR
Transfer to TSR
from TDR
Transfer to TSR from TDR
TEND
[7]
[9]
FER/ERS
[6]
[8]
Figure 13.26 Retransfer Operation in SCI Transmit Mode
The timing for setting the TEND flag depends on the value of the GM bit in SMR. The TEND
flag generation timing is shown in figure 13.27.
I/O data
Ds
TXI
(TEND interrupt)
D0
D1
D2
D3
D4
D5
D6
D7
Dp
DE
Guard
time
12.5etu
When GM = 0
11.0etu
When GM = 1
Legend:
Ds:
D0 to D7:
Dp:
DE:
Start bit
Data bits
Parity bit
Error signal
Figure 13.27 TEND Flag Generation Timing in Transmission Operation
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Section 13 Serial Communication Interface (SCI, IrDA)
Start
Initialization
Start transmission
ERS = 0?
No
Yes
Error processing
No
TEND = 1?
Yes
Write data to TDR,
and clear TDRE flag
in SSR to 0
No
All data transmitted ?
Yes
No
ERS = 0?
Yes
Error processing
No
TEND = 1?
Yes
Clear TE bit to 0
End
Figure 13.28 Example of Transmission Processing Flow
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Section 13 Serial Communication Interface (SCI, IrDA)
13.7.7
Serial Data Reception (Except for Block Transfer Mode)
Data reception in Smart Card interface mode uses the same operation procedure as for normal
serial communication interface mode. Figure 13.29 illustrates the retransfer operation when the
SCI is in receive mode.
1. If an error is found when the received parity bit is checked, the PER bit in SSR is
automatically set to 1. If the RIE bit in SCR is set at this time, an ERI interrupt request is
generated. The PER bit in SSR should be cleared to 0 before the next parity bit is sampled.
2. The RDRF bit in SSR is not set for a frame in which an error has occurred.
3. If no error is found when the received parity bit is checked, the PER bit in SSR is not set to 1.
The receive operation is judged to have been completed normally, and the RDRF flag in SSR
is automatically set to 1. If the RIE bit in SCR is set at this time, an RXI interrupt request is
generated.
Figure 13.30 shows a flowchart for reception. The sequence of receive operations can be
performed automatically by specifying the DTC to be activated with an RXI interrupt source. In a
receive operation, an RXI interrupt request is generated when the RDRF flag in SSR is set to 1. If
the RXI request is designated beforehand as a DTC activation source, the DTC will be activated
by the RXI request, and transfer of the receive data will be carried out. The RDRF flag is cleared
to 0 automatically when data transfer is performed by the DTC. If an error occurs in receive mode
and the ORER or PER flag is set to 1, a transfer error interrupt (ERI) request will be generated,
and so the error flag must be cleared to 0. In the event of an error, the DTC is not activated and
receive data is skipped. Therefore, receive data is transferred for only the specified number of
bytes in the event of an error. Even when a parity error occurs in receive mode and the PER flag
is set to 1, the data that has been received is transferred to RDR and can be read from there.
Note: For details on receive operations in block transfer mode, refer to section 13.4, Operation in
Asynchronous Mode.
nth transfer frame
Transfer
frame n+1
Retransferred frame
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp DE
Ds D0 D1 D2 D3 D4 D5 D6 D7 Dp
(DE)
Ds D0 D1 D2 D3 D4
RDRF
[2]
[4]
[1]
[3]
PER
Figure 13.29 Retransfer Operation in SCI Receive Mode
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Section 13 Serial Communication Interface (SCI, IrDA)
Start
Initialization
Start reception
ORER = 0 and
PER = 0
No
Yes
Error processing
No
RDRF = 1?
Yes
Read RDR and clear
RDRF flag in SSR to 0
No
All data received?
Yes
Clear RE bit to 0
Figure 13.30 Example of Reception Processing Flow
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Section 13 Serial Communication Interface (SCI, IrDA)
13.7.8
Clock Output Control
When the GM bit in SMR is set to 1, the clock output level can be fixed with bits CKE1 and
CKE0 in SCR. At this time, the minimum clock pulse width can be made the specified width.
Figure 13.31 shows the timing for fixing the clock output level. In this example, GM is set to 1,
CKE1 is cleared to 0, and the CKE0 bit is controlled.
CKE0
SCK
Specified pulse width
Specified pulse width
Figure 13.31 Timing for Fixing Clock Output Level
When turning on the power or switching between Smart Card interface mode and software standby
mode, the following procedures should be followed in order to maintain the clock duty cycle.
Powering On: To secure the clock duty cycle from power-on, the following switching procedure
should be followed.
1. The initial state is port input and high impedance. Use a pull-up resistor or pull-down resistor
to fix the potential.
2. Fix the SCK pin to the specified output level with the CKE1 bit in SCR.
3. Set SMR and SCMR, and switch to smart card mode operation.
4. Set the CKE0 bit in SCR to 1 to start clock output.
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Section 13 Serial Communication Interface (SCI, IrDA)
When changing from smart card interface mode to software standby mode:
1. Set the data register (DR) and data direction register (DDR) corresponding to the SCK pin to
the value for the fixed output state in software standby mode.
2. Write 0 to the TE bit and RE bit in the serial control register (SCR) to halt transmit/receive
operation. At the same time, set the CKE1 bit to the value for the fixed output state in
software standby mode.
3. Write 0 to the CKE0 bit in SCR to halt the clock.
4. Wait for one serial clock period.
During this interval, clock output is fixed at the specified level, with the duty cycle preserved.
5. Make the transition to the software standby state.
When returning to smart card interface mode from software standby mode:
1. Exit the software standby state.
2. Write 1 to the CKE0 bit in SCR and output the clock. Signal generation is started with the
normal duty cycle.
Software
standby
Normal operation
[1] [2] [3]
[4] [5]
Normal operation
[6] [7]
Figure 13.32 Clock Halt and Restart Procedure
13.8
IrDA Operation
When the IrDA function is enabled with bit IrE in IrCR, the SCI_0 TxD0 and RxD0 signals are
subjected to waveform encoding/decoding conforming to IrDA specification version 1.0 (IrTxD
and IrRxD pins). By connecting these pins to an infrared transceiver/receiver, it is possible to
implement infrared transmission/reception conforming to the IrDA specification version 1.0
system.
In the IrDA specification version 1.0 system, communication is started at a transfer rate of 9600
bps, and subsequently the transfer rate can be varied as necessary. As the IrDA interface in this
Rev. 3.00 Feb 22, 2006 page 460 of 624
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Section 13 Serial Communication Interface (SCI, IrDA)
LSI does not include a function for varying the transfer rate automatically, the transfer rate setting
must be changed by software.
Figure 13.33 shows a block diagram of the IrDA function.
IrDA
TxD0/IrTxD
Pulse encoder
RxD0/IrRxD
Pulse decoder
SCI0
TxD
RxD
IrCR
Figure 13.33 Block Diagram of IrDA
Transmission: In transmission, the output signal (UART frame) from the SCI is converted to an
IR frame by the IrDA interface (see figure 13.34).
When the serial data is 0, a high pulse of 3/16 the bit rate (interval equivalent to the width of one
bit) is output (initial value). The high-level pulse can be varied according to the setting of bits
IrCKS2 to IrCKS0 in IrCR.
In the specification, the high pulse width is fixed at a minimum of 1.41 µs, and a maximum of
(3/16 + 2.5%) × bit rate or (3/16 × bit rate) + 1.08 µs. When system clock φ is 20 MHz, 1.6 µs can
be set for a high pulse width with a minimum value of 1.41 µs.
When the serial data is 1, no pulse is output.
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Section 13 Serial Communication Interface (SCI, IrDA)
UART frame
Stop
bit
Data
Start
bit
0
1
0
1
0
0
1
Transmit
1
0
1
Receive
IR frame
Data
Start
bit
0
1
0
Bit
cycle
1
0
Stop
bit
0
1
1
0
1
Pulse width
1.6 µs to 3/16 bit cycle
Figure 13.34 IrDA Transmit/Receive Operations
Reception: In reception, IR frame data is converted to a UART frame by the IrDA interface, and
input to the SCI.
When a high pulse is detected, 0 data is output, and if there is no pulse during a one-bit interval, 1
data is output. Note that a pulse shorter than the minimum pulse width of 1.41 µs will be identified
as a 0 signal.
High Pulse Width Selection: Table 13.12 shows possible settings for bits IrCKS2 to IrCKS0
(minimum pulse width), and operating frequencies of this LSI and bit rates, for making the pulse
width shorter than 3/16 times the bit rate in transmission.
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Section 13 Serial Communication Interface (SCI, IrDA)
Table 13.12 Settings of Bits IrCKS2 to IrCKS0
Bit Rate (bps) (Above) /Bit Period × 3/16 (µs) (Below)
Operating
Frequency
φ (MHz)
2400
9600
19200
38400
57600
115200
78.13
19.53
9.77
4.88
3.26
1.63
2
010
010
010
010
010
—
2.097152
010
010
010
010
010
—
2.4576
010
010
010
010
010
—
3
011
011
011
011
011
—
3.6864
011
011
011
011
011
011
4.9152
011
011
011
011
011
011
5
011
011
011
011
011
011
6
100
100
100
100
100
100
6.144
100
100
100
100
100
100
7.3728
100
100
100
100
100
100
8
100
100
100
100
100
100
9.8304
100
100
100
100
100
100
10
100
100
100
100
100
100
12
101
101
101
101
101
101
12.288
101
101
101
101
101
101
14
101
101
101
101
101
101
14.7456
101
101
101
101
101
101
16
101
101
101
101
101
101
16.9344
101
101
101
101
101
101
17.2032
101
101
101
101
101
101
18
101
101
101
101
101
101
19.6608
101
101
101
101
101
101
20
101
101
101
101
101
101
25
110
110
110
110
110
110
Legend:
—: A bit rate setting cannot be made on the SCI side.
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Section 13 Serial Communication Interface (SCI, IrDA)
13.9
Interrupt Sources
13.9.1
Interrupts in Normal Serial Communication Interface Mode
Table 13.13 shows the interrupt sources in normal serial communication interface mode. A
different interrupt vector is assigned to each interrupt source, and individual interrupt sources can
be enabled or disabled using the enable bits in SCR.
When the TDRE flag in SSR is set to 1, a TXI interrupt request is generated. When the TEND
flag in SSR is set to 1, a TEI interrupt request is generated. A TXI interrupt can activate the DTC
to perform data transfer. The TDRE flag is cleared to 0 automatically when data transfer is
performed by the DTC.
When the RDRF flag in SSR is set to 1, an RXI interrupt request is generated. When the ORER,
PER, or FER flag in SSR is set to 1, an ERI interrupt request is generated. An RXI interrupt
request can activate the DTC to perform data transfer. The RDRF flag is cleared to 0
automatically when data transfer is performed by the DTC.
A TEI interrupt is generated when the TEND flag is set to 1 while the TEIE bit is set to 1. If a TEI
interrupt and a TXI interrupt are generated simultaneously, the TXI interrupt has priority for
acceptance. However, note that if the TDRE and TEND flags are cleared simultaneously by the
TXI interrupt routine, the SCI cannot branch to the TEI interrupt routine later.
Table 13.13 SCI Interrupt Sources
Channel
Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
0
ERI0
Receive Error
ORER, FER, PER
Not possible
High
RXI0
Receive Data Full
RDRF
Possible
TXI0
Transmit Data Empty
TDRE
Possible
TEI0
Transmission End
TEND
Not possible
ERI1
Receive Error
ORER, FER, PER
Not possible
RXI1
Receive Data Full
RDRF
Possible
TXI1
Transmit Data Empty
TDRE
Possible
TEI1
Transmission End
TEND
Not possible
ERI2
Receive Error
ORER, FER, PER
Not possible
RXI2
Receive Data Full
RDRF
Possible
TXI2
Transmit Data Empty
TDRE
Possible
TEI2
Transmission End
TEND
Not possible
1
2
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Low
Section 13 Serial Communication Interface (SCI, IrDA)
13.9.2
Interrupts in Smart Card Interface Mode
Table 13.14 shows the interrupt sources in Smart Card interface mode. The transmit end interrupt
(TEI) request cannot be used in this mode.
Table 13.14 SCI Interrupt Sources
Channel
Name
Interrupt Source
Interrupt Flag
DTC Activation
Priority
0
ERI0
Receive Error, detection
ORER, PER, ERS
Not possible
High
RXI0
Receive Data Full
RDRF
Possible
TXI0
Transmit Data Empty
TEND
Possible
ERI1
Receive Error, detection
ORER, PER, ERS
Not possible
RXI1
Receive Data Full
RDRF
Possible
TXI1
Transmit Data Empty
TEND
Possible
ERI2
Receive Error, detection
ORER, PER, ERS
Not possible
RXI2
Receive Data Full
RDRF
Possible
TXI2
Transmit Data Empty
TEND
Possible
1
2
Low
In Smart Card interface mode, as in normal serial communication interface mode, transfer can be
carried out using the DTC. In transmit operations, the TDRE flag is also set to 1 at the same time
as the TEND flag in SSR, and a TXI interrupt is generated. If the TXI request is designated
beforehand as a DTC activation source, the DTC will be activated by the TXI request, and transfer
of the transmit data will be carried out. The TDRE and TEND flags are automatically cleared to 0
when data transfer is performed by the DTC. In the event of an error, the SCI retransmits the
same data automatically. During this period, the TEND flag remains cleared to 0 and the DTC is
not activated. Therefore, the SCI and DTC will automatically transmit the specified number of
bytes in the event of an error, including retransmission. However, the ERS flag is not cleared
automatically when an error occurs, and so the RIE bit should be set to 1 beforehand so that an
ERI request will be generated in the event of an error, and the ERS flag will be cleared.
When performing transfer using the DTC, it is essential to set and enable the DTC before carrying
out SCI setting. For details on the DTC setting procedures, refer to section 7, Data Transfer
Controller (DTC).
In receive operations, an RXI interrupt request is generated when the RDRF flag in SSR is set to
1. If the RXI request is designated beforehand as a DTC activation source, the DTC will be
activated by the RXI request, and transfer of the receive data will be carried out. The RDRF flag
is cleared to 0 automatically when data transfer is performed by the DTC. If an error occurs, an
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Section 13 Serial Communication Interface (SCI, IrDA)
error flag is set but the RDRF flag is not. Consequently, the DTC is not activated, but instead, an
ERI interrupt request is sent to the CPU. Therefore, the error flag should be cleared.
13.10
Usage Notes
13.10.1 Module Stop Mode Setting
SCI operation can be disabled or enabled using the module stop control register. The initial setting
is for SCI operation to be halted. Register access is enabled by clearing module stop mode. For
details, refer to section 19, Power-Down Modes.
13.10.2 Break Detection and Processing
When framing error detection is performed, a break can be detected by reading the RxD pin value
directly. In a break, the input from the RxD pin becomes all 0s, and so the FER flag is set, and the
PER flag may also be set. Note that, since the SCI continues the receive operation after receiving
a break, even if the FER flag is cleared to 0, it will be set to 1 again.
13.10.3 Mark State and Break Sending
When TE is 0, the TxD pin is used as an I/O port whose direction (input or output) and level are
determined by DR and DDR. This can be used to set the TxD pin to mark state or send a break
during serial data transmission. To maintain the communication line at mark state until TE is set
to 1, set both PCR and PDR to 1. Since TE is cleared to 0 at this point, the TxD pin becomes an
I/O port, and 1 is output from the TxD pin. To send a break during serial transmission, first set
PCR to 1 and clear PDR to 0, and then clear TE to 0. When TE is cleared to 0, the transmitter is
initialized regardless of the current transmission state, the TxD pin becomes an I/O port, and 0 is
output from the TxD pin.
13.10.4 Receive Error Flags and Transmit Operations (Clocked Synchronous Mode Only)
Transmission cannot be started when a receive error flag (ORER, PER, or FER) is set to 1, even if
the TDRE flag is cleared to 0. Be sure to clear the receive error flags to 0 before starting
transmission. Note also that receive error flags cannot be cleared to 0 even if the RE bit is cleared
to 0.
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Section 13 Serial Communication Interface (SCI, IrDA)
13.10.5 Relation between Writes to TDR and the TDRE Flag
The TDRE flag in SSR is a status flag that indicates that transmit data has been transferred from
TDR to TSR. When the SCI transfers data from TDR to TSR, the TDRE flag is set to 1.
Data can be written to TDR regardless of the state of the TDRE flag. However, if new data is
written to TDR when the TDRE flag is cleared to 0, the data stored in TDR will be lost since it has
not yet been transferred to TSR. It is therefore essential to check that the TDRE flag is set to 1
before writing transmit data to TDR.
13.10.6 Restrictions on Use of DTC
• When an external clock source is used as the serial clock, the transmit clock should not be
input until at least 5 φ clock cycles after TDR is updated by the DTC. Misoperation may occur
if the transmit clock is input within 4 φ clocks after TDR is updated. (Figure 13.35)
• When RDR is read by the DTC, be sure to set the activation source to the relevant SCI receivedata-full interrupt (RXI).
SCK
t
TDRE
LSB
Serial data
D0
D1
D2
D3
D4
D5
D6
D7
Note: When operating on an external clock, set t > 4 clocks.
Figure 13.35 Example of Synchronous Transmission Using DTC
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Section 13 Serial Communication Interface (SCI, IrDA)
13.10.7 Operation in Case of Mode Transition
• Transmission
Operation should be stopped (by clearing TE, TIE, and TEIE to 0) before making a module
stop mode or software standby mode transition. TSR, TDR, and SSR are reset. The output pin
states in module stop mode or software standby mode depend on the port settings, and become
high-level output after the relevant mode is cleared. If a transition is made during
transmission, the data being transmitted will be undefined.
When transmitting without changing the transmit mode after the relevant mode is cleared,
transmission can be started by setting TE to 1 again, and performing the following sequence:
SSR read → TDR write → TDRE clearance. To transmit with a different transmit mode after
clearing the relevant mode, the procedure must be started again from initialization.
Figure 13.36 shows a sample flowchart for mode transition during transmission. Port pin states
during mode transition are shown in figures 13.37 and 13.38.
Operation should also be stopped (by clearing TE, TIE, and TEIE to 0) before making a
transition from transmission by DTC transfer to module stop mode or software standby mode
transition. To perform transmission with the DTC after the relevant mode is cleared, setting
TE and TIE to 1 will set the TXI flag and start DTC transmission.
• Reception
Receive operation should be stopped (by clearing RE to 0) before making a module stop mode
or software standby mode transition. RSR, RDR, and SSR are reset. If a transition is made
during reception, the data being received will be invalid.
To continue receiving without changing the reception mode after the relevant mode is cleared,
set RE to 1 before starting reception. To receive with a different receive mode, the procedure
must be started again from initialization.
Figure 13.39 shows a sample flowchart for mode transition during reception.
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Section 13 Serial Communication Interface (SCI, IrDA)
<Transmission>
All data
transmitted?
No
[1]
Yes
Read TEND flag in SSR
TEND = 1
No
Yes
TE = 0
[2]
Transition to software
standby mode
[3]
[1] Data being transmitted is interrupted.
After exiting software standby mode,
normal CPU transmission is possible
by setting TE to 1, reading SSR,
writing TDR, and clearing TDRE to 0,
but note that if the DTC has been
activated, the remaining data in
DTCRAM will be transmitted when
TE and TIE are set to 1.
[2] If TIE and TEIE are set to 1, clear
them to 0 in the same way.
[3] Includes module stop mode.
Exit from software
standby mode
Change
operating mode?
No
Yes
Initialization
TE = 1
<Start of transmission>
Figure 13.36 Sample Flowchart for Mode Transition during Transmission
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Section 13 Serial Communication Interface (SCI, IrDA)
End of
transmission
Start of transmission
Transition
to software
standby
Exit from
software
standby
TE bit
Port input/output
SCK output pin
TxD output pin
Port input/output
High output
Port
Start
Stop
Port input/output
Port
SCI TxD output
High output
SCI TxD
output
Figure 13.37 Port Pin States during Mode Transition
(Internal Clock, Asynchronous Transmission)
Start of transmission
End of
transmission
Transition
to software
standby
Exit from
software
standby
TE bit
Port input/output
SCK output pin
TxD output pin Port input/output
Last TxD bit held
Marking output
Port
SCI TxD output
Port input/output
Port
Note: * Initialized by software standby.
Figure 13.38 Port Pin States during Mode Transition
(Internal Clock, Synchronous Transmission)
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High output*
SCI TxD
output
Section 13 Serial Communication Interface (SCI, IrDA)
<Reception>
Read RDRF flag in SSR
RDRF = 1
No
[1]
[1] Receive data being received
becomes invalid.
[2]
[2] Includes module stop mode.
Yes
Read receive data in RDR
RE = 0
Transition to software
standby mode
Exit from software
standby mode
Change
operating mode?
No
Yes
Initialization
RE = 1
<Start of reception>
Figure 13.39 Sample Flowchart for Mode Transition during Reception
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Section 13 Serial Communication Interface (SCI, IrDA)
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Section 14 A/D Converter
Section 14 A/D Converter
This LSI includes a successive approximation type 10-bit A/D converter that allows up to twelve
analog input channels to be selected. The block diagram of A/D converter is shown in figure 14.1.
14.1
Features
• 10-bit resolution
• Twelve input channels
• Conversion time: 6.7 µs per channel (at 20 MHz operation)
• Two kinds of operating modes
 Single mode: Single-channel A/D conversion
 Scan mode: Continuous A/D conversion on 1 to 4 channels, or 1 to 8 channels
• Eight data registers
 Conversion results are held in a 16-bit data register for each channel
• Sample and hold function
• Three kinds of conversion start
 Conversion can be started by software, 16-bit timer pulse unit (TPU), conversion start
trigger by 8-bit timer (TMR), or external trigger signal.
• Interrupt request
 A/D conversion end interrupt (ADI) request can be generated
• Module stop mode can be set
ADCMS02A_010020020400
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Section 14 A/D Converter
Module data bus
Vref
10-bit D/A
AVSS
AN0
AN1
AN7
AN12
A
D
D
R
A
A
D
D
R
B
A
D
D
R
C
A
D
D
R
D
A
D
D
R
E
A
D
D
R
F
A
D
D
R
G
A
D
D
R
H
A
D
C
S
R
A
D
C
R
+
–
Multiplexer
AN2
AN3
AN4
AN5
AN6
Bus interface
Successive approximations
register
AVCC
Internal data bus
Comparator
Control circuit
Sample-andhold circuit
AN13
AN14
AN15
ADI interrupt
signal
ADTRG
Legend:
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
Conversion start
trigger from 8-bit
timer or TPU
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
ADDRD:
ADDRE:
ADDRF:
ADDRG:
ADDRH:
A/D data register D
A/D data register E
A/D data register F
A/D data register G
A/D data register H
Figure 14.1 Block Diagram of A/D Converter
14.2
Input/Output Pins
Table 14.1 shows the pin configuration of the A/D converter.
The twelve analog input pins are divided into two channel sets: channel set 0 (AN0 to AN7) and
channel set 1 (AN12 to AN15).
The AVCC and AVSS pins are the power supply pins for the analog block in the A/D converter. The
Vref pin is the A/D conversion reference voltage pin.
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Section 14 A/D Converter
Table 14.1 A/D Converter Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power supply pin
AVCC
Input
Analog block power supply
Analog ground pin
AVSS
Input
Analog block ground
Reference voltage pin
Vref
Input
A/D conversion reference voltage
Analog input pin 0
AN0
Input
Channel set 0 analog inputs
Analog input pin 1
AN1
Input
Analog input pin 2
AN2
Input
Analog input pin 3
AN3
Input
Analog input pin 4
AN4
Input
Analog input pin 5
AN5
Input
Analog input pin 6
AN6
Input
Analog input pin 7
AN7
Input
Analog input pin 12
AN12
Input
Analog input pin 13
AN13
Input
Analog input pin 14
AN14
Input
Analog input pin 15
AN15
Input
A/D external trigger input
pin
ADTRG
Input
14.3
Channel set 1 analog inputs
External trigger input for starting A/D conversion
Register Descriptions
The A/D converter has the following registers.
• A/D data register A (ADDRA)
• A/D data register B (ADDRB)
• A/D data register C (ADDRC)
• A/D data register D (ADDRD)
• A/D data register E (ADDRE)
• A/D data register F (ADDRF)
• A/D data register G (ADDRG)
• A/D data register H (ADDRH)
• A/D control/status register (ADCSR)
• A/D control register (ADCR)
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Section 14 A/D Converter
14.3.1
A/D Data Registers A to H (ADDRA to ADDRH)
There are eight 16-bit read-only ADDR registers, ADDRA to ADDRH, used to store the results of
A/D conversion. The ADDR registers, which store a conversion result for each channel, are
shown in table 14.2.
The converted 10-bit data is stored to bits 15 to 6. The lower 6-bit data is always read as 0.
ADDR must not be accessed in 8-bit units and must be accessed in 16-bit units.
The data bus between the CPU and the A/D converter is 16-bit width. The data can be read
directly from the CPU.
Table 14.2 Analog Input Channels and Corresponding ADDR Registers
Analog Input Channel
Channel Set 0 (CH3 = 0)
Channel Set 1 (CH3 = 1)
A/D Data Register which stores
conversion result
AN0
Nothing
ADDRA
AN1
Nothing
ADDRB
AN2
Nothing
ADDRC
AN3
Nothing
ADDRD
AN4
AN12
ADDRE
AN5
AN13
ADDRF
AN6
AN14
ADDRG
AN7
AN15
ADDRH
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Section 14 A/D Converter
14.3.2
A/D Control/Status Register (ADCSR)
ADCSR controls A/D conversion operations.
Bit
Bit Name
Initial Value
R/W
Description
7
ADF
0
R/(W)*
A/D End Flag
A status flag that indicates the end of A/D
conversion.
[Setting conditions]
•
When A/D conversion ends in single mode
•
When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
6
ADIE
0
R/W
•
When 0 is written after reading ADF = 1
•
When the DTC is activated by an ADI interrupt
and ADDR is read
A/D Interrupt Enable
A/D conversion end interrupt (ADI) request
enabled when 1 is set
5
ADST
0
R/W
A/D Start
Clearing this bit to 0 stops A/D conversion, and
the A/D converter enters wait state. When this bit
is set to 1 by software, TPU (trigger), TMR
(trigger), or the ADTRG pin, A/D conversion
starts. This bit remains set to 1 during A/D
conversion. In single mode, cleared to 0
automatically when conversion on the specified
channel ends. In scan mode, conversion
continues sequentially on the specified channels
until this bit is cleared to 0 by a reset, or a
transition to hardware standby mode or software.
4
—
0
—
Reserved
This bit is always read as 0 and cannot be
modified.
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Section 14 A/D Converter
Bit
Bit Name
Initial Value
R/W
Description
3
CH3
0
R/W
Channel select 3 to 0
2
CH2
0
R/W
1
CH1
0
R/W
Selects analog input together with bits SCANE
and SCANS in ADCR.
0
CH0
0
R/W
When SCANE = 0 and SCANS = X
0000: AN0
1000: Setting prohibited
0001: AN1
1001: Setting prohibited
0010: AN2
1010: Setting prohibited
0011: AN3
1011: Setting prohibited
0100: AN4
1100: AN12
0101: AN5
1101: AN13
0110: AN6
1110: AN14
0111: AN7
1111: AN15
When SCANE = 1 and SCANS = 0
0000: AN0
1000: Setting prohibited
0001: AN0 and AN1
1001: Setting prohibited
0010: AN0 to AN2
1010: Setting prohibited
0011: AN0 to AN3
1011: Setting prohibited
0100: AN4
1100: AN12
0101: AN4 and AN5
1101: AN12 and AN13
0110: AN4 to AN6
1110: AN12 to AN14
0111: AN4 to AN7
1111: AN12 to AN15
When SCANE = 1 and SCANS = 1
Note: *
Legend:
0000: AN0
1000: Setting prohibited
0001: AN0 and AN1
1001: Setting prohibited
0010: AN0 to AN2
1010: Setting prohibited
0011: AN0 to AN3
1011: Setting prohibited
0100: AN0 to AN4
1100: Setting prohibited
0101: AN0 to AN5
1101: Setting prohibited
0110: AN0 to AN6
1110: Setting prohibited
0111: AN0 to AN7
1111: Setting prohibited
Only 0 can be written in bit 7, to clear the flag.
X: Don’t care.
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Section 14 A/D Converter
14.3.3
A/D Control Register (ADCR)
ADCR enables A/D conversion start by an external trigger input.
Bit
Bit Name
Initial Value
R/W
Description
7
TRGS1
0
R/W
Timer Trigger Select 1 and 0
6
TRGS0
0
R/W
These bits select enabling or disabling of the start
of A/D conversion by a trigger signal.
00: A/D conversion start by external trigger is
disabled
01: A/D conversion start by external trigger (TPU)
is enabled
10: A/D conversion start by external trigger (TMR)
is enabled
11: A/D conversion start by external trigger pin
(ADTRG) is enabled
5
SCANE
0
R/W
Scan Mode
4
SCANS
0
R/W
Selects single mode or scan mode as the A/D
conversion operating mode.
0x: Single mode
10: Scan mode. A/D conversion is performed
continuously for channels 1 to 4
11: Scan mode. A/D conversion is performed
continuously for channels 1 to 8.
3
CKS1
0
R/W
Clock Select 1 to 0
2
CKS0
0
R/W
Sets the A/D conversion time.
Only set bits CKS1 and CKS0 while conversion is
stopped (ADST = 0).
00: A/D conversion time = 530 states (max)
01: A/D conversion time = 266 states (max)
10: A/D conversion time = 134 states (max)
11: A/D conversion time = 68 states (max)
1, 0
—
All 0
—
Reserved
These bits are always read as 0 and cannot be
modified.
Legend:
X: Don’t care.
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Section 14 A/D Converter
14.4
Operation
The A/D converter operates by successive approximation with 10-bit resolution. It has two
operating modes: single mode and scan mode. When changing the operating mode or analog input
channel, to prevent incorrect operation, first clear the bit ADST to 0 in ADCSR to halt A/D
conversion. The ADST bit can be set at the same time as the operating mode or analog input
channel is changed.
14.4.1
Single Mode
In single mode, A/D conversion is to be performed only once on the specified single channel.
Operations are as follows.
1. A/D conversion is started when the ADST bit in ADCSR is set to 1, according to the software
or external trigger input.
2. When A/D conversion is completed, the result is transferred to the corresponding A/D data
register to the channel.
3. On completion of conversion, the ADF bit in ADCSR is set to 1. If the ADIE bit is set to 1 at
this time, an ADI interrupt request is generated.
4. The ADST bit remains set to 1 during A/D conversion, and is automatically cleared to 0 when
conversion ends. When the ADST bit is cleared to 0 during A/D conversion, A/D conversion
stops and the A/D converter enters wait state.
14.4.2
Scan Mode
In scan mode, A/D conversion is to be performed sequentially on the specified channels:
maximum four channels or maximum eight channels. Operations are as follows.
1. When the ADST bit in ADCSR is set to 1 by a software, TPU or external trigger input, A/D
conversion starts on the first channel in the group.
The consecutive A/D conversion on maximum four channels (SCANE and SCANS = 10) or on
maximum eight channels (SCANE and SCANS = 11) can be selected. When the consecutive
A/D conversion is performed on the four channels, the A/D conversion starts on AN0 when
CH3 and CH2 =00, AN4 when CH3 and CH2 = 01, or AN12 when CH3 and CH2 = 11. When
the consecutive A/D conversion is performed on the eight channels, the A/D conversion starts
on AN0 when SH3 and SH2 =00.
2. When A/D conversion for each channel is completed, the result is sequentially transferred to
the corresponding A/D data register to each channel.
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Section 14 A/D Converter
3. When conversion of all the selected channels is completed, the ADF bit in ADCSR is set to 1.
If the ADIE bit is set to 1 at this time, an ADI interrupt is requested. Conversion of the first
channel in the group starts again.
4. The ADST bit is not cleared automatically, and steps [2] to [3] are repeated as long as the
ADST bit remains set to 1. When the ADST bit is cleared to 0, A/D conversion stops and the
A/D converter enters wait state. If the ADST bit is later set to 1, A/D conversion starts again
from the first channel in the group.
14.4.3
Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input when A/D conversion start delay time (tD) passes after the ADST bit is set to 1, then starts
conversion. Figure 14.2 shows the A/D conversion timing. Table 14.3 indicates the A/D
conversion time.
As indicated in figure 14.2, the A/D conversion time (tCONV) includes tD and the input sampling time
(tSPL). The length of tD varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in tables 14.3.
In scan mode, the values given in tables 14.3 apply to the first conversion time. The values given
in tables 14.4 apply to the second and subsequent conversions. The conversion time must be
within the ranges indicated in the descriptions, A/D Conversion Characteristics in section 21,
Electrical Characteristics. Therefore the CKS1 and CKS0 bits must be set to satisfy this condition.
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Section 14 A/D Converter
(1)
φ
Address
(2)
Write signal
Input sampling
timing
ADF
tSPL
tD
tCONV
Legend:
(1):
ADCSR write cycle
(2):
ADCSR address
A/D conversion start delay time
tD:
tSPL: Input sampling time
tCONV: A/D conversion time
Figure 14.2 A/D Conversion Timing
Table 14.3 A/D Conversion Time (Single Mode)
CKS1 = 0
CKS1 = 1
CKS0 = 0
CKS0 = 1
CKS0 = 0
CKS0 = 1
Item
Symbol
Min Typ Max
Min Typ Max
Min Typ Max
Min Typ Max
A/D conversion
start delay time
tD
18
—
33
10
—
17
6
—
9
4
—
5
Input sampling
time
tSPL
—
127 —
—
63
—
—
31
—
—
15
—
A/D conversion
time
tCONV
515 —
266
131 —
134
67
—
68
530
259 —
Note: Values in the table are the number of states.
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Section 14 A/D Converter
Table 14.4 A/D Conversion Time (Scan Mode)
CKS1
CKS0
Conversion Time (State)
0
0
512 (Fixed)
1
256 (Fixed)
0
128 (Fixed)
1
64 (Fixed)
1
14.4.4
External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGS1 and TRGS0 bits are set to 11 in
ADCR, external trigger input is enabled at the ADTRG pin. A falling edge at the ADTRG pin sets
the ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as when the bit ADST has been set to 1 by software. Figure 14.3 shows the
timing.
φ
ADTRG
Internal trigger signal
ADST
A/D conversion
Figure 14.3 External Trigger Input Timing
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Section 14 A/D Converter
14.5
Interrupt Source
The A/D converter generates an A/D conversion end interrupt (ADI) at the end of A/D conversion.
Setting the ADIE bit to 1 enables an ADI interrupt requests while the bit ADF in ADCSR is set to
1 after A/D conversion is completed. The DTC can be activated by an ADI interrupt. Having the
converted data read by the DTC in response to an ADI interrupt enables continuous conversion to
be achieved without imposing a load on software.
Table 14.5 A/D Converter Interrupt Source
Name
Interrupt Source
Interrupt Flag
DTC Activation
ADI
End of conversion
ADF
Possible
14.6
A/D Conversion Accuracy Definitions
This LSI’s A/D conversion accuracy definitions are given below.
• Resolution
The number of A/D converter digital output codes
• Quantization error
The deviation inherent in the A/D converter, given by 1/2 LSB (see figure 14.4).
• Offset error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from the minimum voltage value B'0000000000 (H'000) to
B'0000000001 (H'001) (see figure 14.5).
• Full-scale error
The deviation of the analog input voltage value from the ideal A/D conversion characteristic
when the digital output changes from B'1111111110 (H'3FE) to B'1111111111 (H'3FF) (see
figure 14.5).
• Nonlinearity error
The error with respect to the ideal A/D conversion characteristic between the zero voltage and
the full-scale voltage. Does not include the offset error, full-scale error, or quantization error
(see figure 14.5).
• Absolute precision
The deviation between the digital value and the analog input value. Includes the offset error,
full-scale error, quantization error, and nonlinearity error.
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Section 14 A/D Converter
Digital output
Ideal A/D conversion
characteristic
111
110
101
100
011
010
Quantization error
001
000
1
2
1024 1024
1022 1023 FS
1024 1024
Analog
input voltage
Figure 14.4 A/D Conversion Accuracy Definitions
Full-scale error
Digital output
Ideal A/D conversion
characteristic
Nonlinearity
error
Actual A/D conversion
characteristic
Offset error
FS
Analog
input voltage
Figure 14.5 A/D Conversion Accuracy Definitions
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Section 14 A/D Converter
14.7
Usage Notes
14.7.1
Module Stop Mode Setting
Operation of the A/D converter can be disabled or enabled using the module stop control register.
The initial setting is for operation of the A/D converter to be halted. Register access is enabled by
clearing module stop mode. For details, refer to section 19, Power-Down Modes.
14.7.2
Permissible Signal Source Impedance
This LSI’s analog input is designed so that conversion precision is guaranteed for an input signal
for which the signal source impedance is 10 kΩ or less. This specification is provided to enable
the A/D converter’s sample-and-hold circuit input capacitance to be charged within the sampling
time; if the sensor output impedance exceeds 10 kΩ, charging may be insufficient and it may not
be possible to guarantee the A/D conversion accuracy. However, if a large capacitance is
provided externally for conversion in single mode, the input load will essentially comprise only
the internal input resistance of 10 kΩ, and the signal source impedance becomes unnecessary.
However, since a low-pass filter effect is obtained in this case, it may not be possible to follow an
analog signal with a large differential coefficient (e.g., 5 mV/µs or greater) (see figure 14.6).
When converting a high-speed analog signal or conversion in scan mode, a low-impedance buffer
should be inserted.
This LSI
Equivalent circuit of A/D converter
Sensor output
impedance
10 kΩ
Up to 10 kΩ
Sensor input
Low-pass
filter
C to 0.1 µF
Cin =
15 pF
Figure 14.6 Example of Analog Input Circuit
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20 pF
Section 14 A/D Converter
14.7.3
Influences on Absolute Precision
Adding capacitance results in coupling with GND, and therefore noise in GND may adversely
affect absolute precision. Be sure to make the connection to an electrically stable GND such as
AVss.
Care is also required to insure that filter circuits do not communicate with digital signals on the
mounting board, so acting as antennas.
14.7.4
Setting Range of Analog Power Supply and Other Pins
If conditions shown below are not met, the reliability of the device may be adversely affected.
• Analog input voltage range
The voltage applied to analog input pin ANn during A/D conversion should be in the range
AVss ≤ VAn ≤ Vref.
• Relation between AVcc, AVss and Vcc, Vss
As the relationship between AVcc, AVss and Vcc, Vss, set AVcc ≥ Vcc and AVss = Vss. If
the A/D converter is not used, the AVcc and AVss pins must not be left open.
• Vref setting range
The reference voltage at the Vref pin should be set in the range Vref ≤ AVcc.
14.7.5
Notes on Board Design
In board design, digital circuitry and analog circuitry should be as mutually isolated as possible,
and layout in which digital circuit signal lines and analog circuit signal lines cross or are in close
proximity should be avoided as far as possible. Failure to do so may result in incorrect operation
of the analog circuitry due to inductance, adversely affecting A/D conversion values.
Also, digital circuitry must be isolated from the analog input signals (AN0 to AN7 and AN12 to
AN15), analog reference power supply (Vref), and analog power supply (AVcc) by the analog
ground (AVss). Also, the analog ground (AVss) should be connected at one point to a stable
digital ground (Vss) on the board.
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Section 14 A/D Converter
14.7.6
Notes on Noise Countermeasures
A protection circuit connected to prevent damage due to an abnormal voltage such as an excessive
surge at the analog input pins (AN0 to AN7 and AN12 to AN15) should be connected between
AVcc and AVss as shown in figure 14.7. Also, the bypass capacitors connected to AVcc and the
filter capacitor connected to AN0 to AN7 and AN12 to AN15 must be connected to AVss.
If a filter capacitor is connected, the input currents at the analog input pins (AN0 to AN7 and
AN12 to AN15) are averaged, and so an error may arise. Also, when A/D conversion is
performed frequently, as in scan mode, if the current charged and discharged by the capacitance of
the sample-and-hold circuit in the A/D converter exceeds the current input via the input impedance
(Rin), an error will arise in the analog input pin voltage. Careful consideration is therefore required
when deciding the circuit constants.
AVCC
Vref
Rin*2
*1
100Ω
AN0 to AN7, AN12 to AN15
*1
0.1 µF
AVSS
Notes:
Values are reference values.
1.
10 µF
0.01 µF
2. Rin: Input impedance
Figure 14.7 Example of Analog Input Protection Circuit
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Section 14 A/D Converter
Table 14.6 Analog Pin Specifications
Item
Min
Max
Unit
Analog input capacitance
—
20
pF
Permissible signal source impedance
—
10
kΩ
10 kΩ
AN0 to AN7,
AN12 to AN15
To A/D
converter
20 pF
Note: Values are reference values.
Figure 14.8 Analog Input Pin Equivalent Circuit
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Section 14 A/D Converter
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Section 15 D/A Converter
Section 15 D/A Converter
15.1
Features
D/A converter features are listed below.
• 8-bit resolution
• Four output channels
• Maximum conversion time of 10 µs (with 20 pF load)
• Output voltage of 0 V to Vref
• D/A output hold function in software standby mode
• Setting the module stop mode
DAC0001A_010020020400
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Bus interface
Section 15 D/A Converter
Module data bus
Vref
DACR23
DACR01
D/A
DADR3
DA1
DADR2
8-bit
DA2
DADR1
DA3
DADR0
AVCC
DA0
AVSS
Control circuit
Legend:
DADR0:
DADR1:
DADR2:
DADR3:
DACR01:
DACR23:
D/A data register 0
D/A data register 1
D/A data register 2
D/A data register 3
D/A control register 01
D/A control register 23
Figure 15.1 Block Diagram of D/A Converter
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Internal data bus
Section 15 D/A Converter
15.2
Input/Output Pins
Table 15.1 shows the pin configuration of the D/A converter.
Table 15.1 Pin Configuration
Pin Name
Symbol
I/O
Function
Analog power pin
AVCC
Input
Analog power
Analog ground pin
AVSS
Input
Analog ground
Reference voltage pin
Vref
Input
Reference voltage of D/A converter
Analog output pin 0
DA0
Output
Channel 0 analog output
Analog output pin 1
DA1
Output
Channel 1 analog output
Analog output pin 2
DA2
Output
Channel 2 analog output
Analog output pin 3
DA3
Output
Channel 3 analog output
15.3
Register Descriptions
The D/A converter has the following registers.
• D/A data register 0 (DADR0)
• D/A data register 1 (DADR1)
• D/A data register 2 (DADR2)
• D/A data register 3 (DADR3)
• D/A control register 01 (DACR01)
• D/A control register 23 (DACR23)
15.3.1
D/A Data Registers 0 to 3 (DADR0 to DADR3)
DADR0 to DADR3 are 8-bit readable/writable registers that store data for conversion.
Whenever output is enabled, the values in DADR are converted and output to the analog output
pins.
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Section 15 D/A Converter
15.3.2
D/A Control Registers 01 and 23 (DACR01, DACR23)
DACR01 and DACR23 control the operation of the D/A converter.
DACR01
Bit
Bit Name
Initial Value
R/W
Description
7
DAOE1
0
R/W
D/A Output Enable 1
Controls D/A conversion and analog output.
0: Analog output (DA1) is disabled
1: Channel 1 D/A conversion is enabled; analog
output (DA1) is enabled
6
DAOE0
0
R/W
D/A Output Enable 0
Controls D/A conversion and analog output.
0: Analog output (DA0) is disabled
1: Channel 0 D/A conversion is enabled; analog
output (DA0) is enabled
5
DAE
0
R/W
D/A Enable
Used together with the DAOE0 and DAOE1 bits to
control D/A conversion. When the DAE bit is
cleared to 0, channel 0 and 1 D/A conversions are
controlled independently. When the DAE bit is set
to 1, channel 0 and 1 D/A conversions are
controlled together.
Output of conversion results is always controlled
independently by the DAOE0 and DAOE1 bits. For
details, see table 15.2 Control of D/A Conversion.
4
to
0
—
All 1
—
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Reserved
These bits are always read as 1 and cannot be
modified.
Section 15 D/A Converter
Table 15.2 Control of D/A Conversion
Bit 5
DAE
Bit 7
DAOE1
Bit 6
DAOE0
Description
0
0
0
D/A conversion disabled
1
Channel 0 D/A conversion enabled, channel1 D/A conversion
disabled
0
Channel 1 D/A conversion enabled, channel0 D/A conversion
disabled
1
Channel 0 and 1 D/A conversions enabled
0
D/A conversion disabled
1
Channel 0 and 1 D/A conversions enabled
1
1
0
1
0
1
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Section 15 D/A Converter
DACR23
Bit
Bit Name
Initial Value
R/W
Description
7
DAOE3
0
R/W
D/A Output Enable 3
Controls D/A conversion and analog output.
0: Analog output (DA3) is disabled
1: Channel 3 D/A conversion is enabled; analog
output (DA3) is enabled
6
DAOE2
0
R/W
D/A Output Enable 2
Controls D/A conversion and analog output.
0: Analog output (DA2) is disabled
1: Channel 2 D/A conversion is enabled; analog
output (DA2) is enabled
5
DAE
0
R/W
D/A Enable
Used together with the DAOE2 and DAOE3 bits to
control D/A conversion. When the DAE bit is
cleared to 0, channel 2 and 3 D/A conversions are
controlled independently. When the DAE bit is set
to 1, channel 2 and 3 D/A conversions are
controlled together.
Output of conversion results is always controlled
independently by the DAOE2 and DAOE3 bits. For
details, see table 15.3 Control of D/A Conversion.
4
to
0
—
All 1
—
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Reserved
These bits are always read as 1 and cannot be
modified.
Section 15 D/A Converter
Table 15.3 Control of D/A Conversion
Bit 5
DAE
Bit 7
DAOE3
Bit 6
DAOE2
Description
0
0
0
D/A conversion disabled
1
Channel 2 D/A conversion enabled, channel3 D/A conversion
disabled
0
Channel 3 D/A conversion enabled, channel2 D/A conversion
disabled
1
Channel 2 and 3 D/A conversions enabled
0
D/A conversion disabled
1
Channel 2 and 3 D/A conversions enabled
1
1
0
1
0
1
15.4
Operation
The D/A converter includes D/A conversion circuits for four channels, each of which can operate
independently.
When DAOE bit in DACR01 or DACR23 is set to 1, D/A conversion is enabled and the
conversion result is output.
The operation example concerns D/A conversion on channel 0. Figure 15.2 shows the timing of
this operation.
[1] Write the conversion data to DADR0.
[2] Set the DAOE0 bit in DACR01 to 1. D/A conversion is started. The conversion result is output
from the analog output pin DA0 after the conversion time tDCONV has elapsed. The conversion
result is continued to output until DADR0 is written to again or the DAOE0 bit is cleared to 0.
The output value is expressed by the following formula:
DADR contents
× Vref
256
[3] If DADR0 is written to again, the conversion is immediately started. The conversion result is
output after the conversion time tDCONV has elapsed.
[4] If the DAOE0 bit is cleared to 0, analog output is disabled.
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Section 15 D/A Converter
DADR0
write cycle
DADR0
write cycle
DACR01
write cycle
DACR01
write cycle
φ
Address
Conversion data 1
DADR0
Conversion data 2
DAOE0
DA0
Conversion
result 2
Conversion
result 1
High-impedance state
tDCONV
tDCONV
Legend:
tDCONV: D/A conversion time
Figure 15.2 Example of D/A Converter Operation
15.5
Usage Notes
15.5.1
Setting for Module Stop Mode
It is possible to enable/disable the D/A converter operation using the module stop control register,
the D/A converter does not operate by the initial value of the register. The register can be accessed
by releasing the module stop mode. For details, see section 19, Power-Down Modes.
15.5.2
D/A Output Hold Function in Software Standby Mode
If D/A conversion is enabled and this LSI enters software standby mode, D/A output is held and
analog power supply current remains at the same level during D/A conversion. When the analog
power supply current is required to go low in software standby mode, bits DAOE0 to DAOE3 and
DAE should be cleared to 0, and D/A output should be disabled.
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Section 16 RAM
Section 16 RAM
This LSI has an on-chip high-speed static RAM. The RAM is connected to the CPU by a 16-bit
data bus, enabling one-state access by the CPU to both byte data and word data.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), refer to section 3.2.2,
System Control Register (SYSCR).
Product Type
H8S/2668
Group
HD64F2667
ROM Type
RAM
Capacitance
RAM Address
Flash memory version
16 kbytes
H'FF8000 to H'FFBFFF
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Section 16 RAM
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Section 17 Flash Memory (F-ZTAT Version)
Section 17 Flash Memory (F-ZTAT Version)
The features of the flash memory included in the flash memory version are summarized below.
The block diagram of the flash memory is shown in figure 17.1.
17.1
Features
• Size
Product Classification
ROM Size
ROM Address
H8S/2668 Group
384 kbytes
H'000000 to H'05FFFF (Modes 3, 4, and 7)
H'100000 to H'15FFFF (Modes 5 and 6)
HD64F2667
• Programming/erase methods
The flash memory is programmed 128 bytes at a time. Erase is performed in single-block
units. The flash memory of 384 kbytes is configured as follows: 64 kbytes × 5 blocks, 32
kbytes × 1 block, and 4 kbytes × 8 block. To erase the entire flash memory, each block must be
erased in turn.
• Reprogramming capability
The flash memory can be reprogrammed up to 100 times.
• Two on-board programming modes
Boot mode
User program mode
On-board programming/erasing can be done in boot mode in which the on-chip boot program
is started for erase or programming of the entire flash memory. In normal user program mode,
individual blocks can be erased or programmed.
• Programmer mode
Flash memory can be programmed/erased in programmer mode, using a PROM programmer,
as well as in on-board programming mode.
• Automatic bit rate adjustment
With data transfer in boot mode, the bit rate of this LSI can be automatically adjusted to match
the transfer bit rate of the host.
• Flash memory emulation by RAM
Part of the RAM area can be overlapped onto flash memory, to emulate flash memory updates
in real time.
• Programming/erasing protection
There are three protect modes, hardware, software, and error protect, which allow protected
status to be designated for flash memory program/erase operations.
ROMF380A_010020020400
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Section 17 Flash Memory (F-ZTAT Version)
Internal address bus
Module bus
Internal data bus (16 bits)
FLMCR1
FLMCR2
Bus interface/controller
EBR1
Operating
mode
Mode pins
EBR2
RAMER
SYSCR
Flash memory
Legend:
FLMCR1:
FLMCR2:
EBR1:
EBR2:
RAMER:
SYSCR:
Flash memory control register 1
Flash memory control register 2
Erase block register 1
Erase block register 2
RAM emulation register
System control register
Figure 17.1
17.2
Block Diagram of Flash Memory
Mode Transitions
When the mode pins are set in the reset state and a reset-start is executed, this LSI enters an
operating mode as shown in figure 17.2. In user mode, flash memory can be read but not
programmed or erased.
The boot, user program and programmer modes are provided as modes to write and erase the flash
memory.
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Section 17 Flash Memory (F-ZTAT Version)
The differences between boot mode and user program mode are shown in table 17.1. Figure 17.3
shows boot mode. Figure 17.4 shows user program mode.
Reset state
MD2 = 1
User mode
(on-chip ROM
enabled)
RES = 0
RES = 0
RES = 0
SWE = 0
SWE = 1
MD0 = 1,
MD1 = 1,
MD2 = 0
RES = 0
MD0 = 0,
MD1 = 0,
MD2 = 0,
P50 = 0,
P51 = 0,
P52 = 1
User
program mode
Programmer
mode
Boot mode
On-board programming mode
Note: Only make a transition between user mode and user program mode when the CPU is
not accessing the flash memory.
Figure 17.2 Flash Memory State Transitions
Table 17.1 Differences between Boot Mode and User Program Mode
Boot Mode
User Program Mode
Total erase
Yes
Yes
Block erase
No
Yes
Programming control program*
Program/program-verify
Erase/erase-verify/program/
program-verify emulation
Note:
*
To be provided by the user, in accordance with the recommended algorithm.
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Section 17 Flash Memory (F-ZTAT Version)
1. Initial state
The old program version or data remains written
in the flash memory. The user should prepare the
programming control program and new
application program beforehand in the host.
2. Programming control program transfer
When boot mode is entered, the boot program in
the chip (originally incorporated in the chip) is
started and the programming control program in
the host is transferred to RAM via SCI
communication. The boot program required for
flash memory erasing is automatically transferred
to the RAM boot program area.
Host
Host
Programming control
program
New application
program
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
SCI
Boot program
Flash memory
RAM
RAM
Boot program area
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The erase program in the boot program area (in
RAM) is executed, and the flash memory is
initialized (to H'FF). In boot mode, entire flash
memory erasure is performed, without regard to
blocks.
Host
Programming control
program
4. Writing new application program
The programming control program transferred
from the host to RAM is executed, and the new
application program in the host is written into the
flash memory.
Host
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
Flash memory
Boot program area
Flash memory
prewrite-erase
Programming control
program
SCI
Boot program
RAM
Boot program area
New application
program
Programming control
program
Program execution state
Figure 17.3 Boot Mode
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Section 17 Flash Memory (F-ZTAT Version)
1. Initial state
(1) The program that will transfer the
programming/ erase control program to on-chip
RAM should be written into the flash memory by
the user beforehand. (2) The programming/erase
control program should be prepared in the host
or in the flash memory.
2. Programming/erase control program transfer
When user program mode is entered, user
software confirms this fact, executes the transfer
program in the flash memory, and transfers the
programming/erase control program to RAM.
Host
Host
Programming/
erase control program
New application
program
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
SCI
Boot program
Flash memory
RAM
Transfer program
Transfer program
Programming/
erase control program
Application program
(old version)
Application program
(old version)
3. Flash memory initialization
The programming/erase program in RAM is
executed, and the flash memory is initialized (to
H'FF). Erasing can be performed in block units,
but not in byte units.
4. Writing new application program
Next, the new application program in the host is
written into the erased flash memory blocks. Do
not write to unerased blocks.
Host
Host
New application
program
This LSI
This LSI
SCI
Boot program
Flash memory
RAM
Flash memory
RAM
Transfer program
Transfer program
Programming/
erase control program
Flash memory
erase
SCI
Boot program
Programming/
erase control program
New application
program
Program execution state
Figure 17.4 User Program Mode
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Section 17 Flash Memory (F-ZTAT Version)
17.3
Block Configuration
Figure 17.5 shows the block configuration of 384-kbyte flash memory. The thick lines indicate
erasing units, the narrow lines indicate programming units, and the values are addresses. The 384kbyte flash memory is divided into 64 kbytes (5 blocks), 32 kbytes (1 block), and 4 kbytes (8
blocks). Erasing is performed in these divided units. Programming is performed in 128-byte units
starting from an address whose lower eight bits are H'00 or H'80.
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Section 17 Flash Memory (F-ZTAT Version)
EB0
Erase unit
4 kbytes
H'000000
H'000001
H'000002
Programming unit: 128 bytes
EB1
Erase unit
4 kbytes
H'001000
H'001001
H'001002
Programming unit: 128 bytes
EB2
Erase unit
4 kbytes
H'002000
H'002001
H'002002
Programming unit: 128 bytes
EB3
Erase unit
4 kbytes
H'003000
H'003001
H'003002
Programming unit: 128 bytes
H'00407F
H'00707F
H'00007F
H'000FFF
H'00107F
H'001FFF
H'00207F
H'002FFF
H'00307F
H'003FFF
EB4
Erase unit
4 kbytes
H'004000
H'004001
H'004002
Programming unit: 128 bytes
EB7
Erase unit
4 kbytes
H'007000
H'007001
H'007002
Programming unit: 128 bytes
EB8
Erase unit
32 kbytes
H'008000
H'008001
H'008002
Programming unit: 128 bytes
EB9
Erase unit
64 kbytes
H'010000
H'010001
H'010002
Programming unit: 128 bytes
EB10
Erase unit
64 kbytes
H'020000
H'020001
H'020002
Programming unit: 128 bytes
EB11
Erase unit
64 kbytes
H'030000
H'030001
H'030002
Programming unit: 128 bytes
H'03007F
EB12
Erase unit
64 kbytes
H'040000
H'040001
H'040002
Programming unit: 128 bytes
H'04007F
EB13
Erase unit
64 kbytes
H'050000
H'050001
H'050002
Programming unit: 128 bytes
H'007FFF
H'00807F
H'00FFFF
H'01007F
H'01FFFF
H'02007F
H'02FFFF
H'03FFFF
H'04FFFF
H'05007F
H'05FFFF
Note: Addresses H'100000 to H'15FFFF are allocated in modes 5 and 6.
Figure 17.5 384-Kbyte Flash Memory Block Configuration (Modes 3, 4, and 7)
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Section 17 Flash Memory (F-ZTAT Version)
17.4
Input/Output Pins
Table 17.2 shows the pin configuration of the flash memory.
Table 17.2 Pin Configuration
Pin Name
I/O
Function
RES
Input
Reset
MD2
Input
Sets this LSI’s operating mode
MD1
Input
Sets this LSI’s operating mode
MD0
Input
Sets this LSI’s operating mode
P52
Input
Sets operating mode in programmer mode
P51
Input
Sets operating mode in programmer mode
P50
Input
Sets operating mode in programmer mode
TxD1
Output
Serial transmit data output
RxD1
Input
Serial receive data input
17.5
Register Descriptions
The flash memory has the following registers. For details on the system control register, refer to
section 3.2.2, System Control Register (SYSCR).
• Flash memory control register 1 (FLMCR1)
• Flash memory control register 2 (FLMCR2)
• Erase block register 1 (EBR1)
• Erase block register 2 (EBR2)
• RAM emulation register (RAMER)
17.5.1
Flash Memory Control Register 1 (FLMCR1)
FLMCR1 is a register that makes the flash memory transit to program mode, program-verify
mode, erase mode, or erase-verify mode. For details on register setting, refer to section 17.8,
Flash Memory Programming/Erasing.
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Section 17 Flash Memory (F-ZTAT Version)
Bit
Bit Name
Initial Value
R/W
Description
7
—
0/1
R
This bit is reserved. This bit is always read as 0 in
modes 1 and 2. This bit is always read as 1 in
modes 3 to 7. The initial value should not be
changed.
6
SWE
0
R/W
Software Write Enable
When this bit is set to 1, flash memory
programming/erasing is enabled. When this bit is
cleared to 0, other FLMCR1 register bits and all
EBR1 and EBR2 bits cannot be set.
5
ESU
0
R/W
Erase Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the erase setup state. When it
is cleared to 0, the erase setup state is cancelled.
4
PSU
0
R/W
Program Setup
When this bit is set to 1 while SWE = 1, the flash
memory transits to the program setup state. When
it is cleared to 0, the program setup state is
cancelled.
3
EV
0
R/W
Erase-Verify
When this bit is set to 1 while SWE = 1, the flash
memory transits to erase-verify mode. When it is
cleared to 0, erase-verify mode is cancelled.
2
PV
0
R/W
Program-Verify
When this bit is set to 1 while SWE = 1, the flash
memory transits to program-verify mode. When it
is cleared to 0, program-verify mode is cancelled.
1
E
0
R/W
Erase
When this bit is set to 1 while SWE = 1, and ESU =
1, the flash memory transits to erase mode. When
it is cleared to 0, erase mode is cancelled.
0
P
0
R/W
Program
When this bit is set to 1 while SWE = 1, and PSU =
1, the flash memory transits to program mode.
When it is cleared to 0, program mode is
cancelled.
Rev. 3.00 Feb 22, 2006 page 509 of 624
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Section 17 Flash Memory (F-ZTAT Version)
17.5.2
Flash Memory Control Register 2 (FLMCR2)
FLMCR2 is a register that displays the state of flash memory programming/erasing. FLMCR2 is a
read-only register, and should not be written to. When the on-chip flash memory is disabled, the
contents of FLMCR2 are always read as H’00.
Bit
Bit Name
Initial Value
R/W
Description
7
FLER
0
R
Indicates that an error has occurred during an
operation on flash memory (programming or
erasing). When FLER is set to 1, flash memory
goes to the error-protection state.
6
to
0
—
All 0
R
Reserved
See 17.9.3 Error Protection, for details.
Rev. 3.00 Feb 22, 2006 page 510 of 624
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These bits are always read 0.
Section 17 Flash Memory (F-ZTAT Version)
17.5.3
Erase Block Register 1 (EBR1)
EBR1 specifies the flash memory erase area block. EBR1 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Set only one bit in EBR1 and EBR2 together (do not set more than one bit at the
same time). Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0. For
details, see table 17.3, Erase Blocks.
Bit
Bit Name
Initial Value
R/W
Description
7
EB7
0
R/W
When this bit is set to 1, 4 kbytes of EB7 are to be
erased.
6
EB6
0
R/W
When this bit is set to 1, 4 kbytes of EB6 are to be
erased.
5
EB5
0
R/W
When this bit is set to 1, 4 kbytes of EB5 are to be
erased.
4
EB4
0
R/W
When this bit is set to 1, 4 kbytes of EB4 are to be
erased.
3
EB3
0
R/W
When this bit is set to 1, 4 kbytes of EB3 is to be
erased.
2
EB2
0
R/W
When this bit is set to 1, 4 kbytes of EB2 is to be
erased.
1
EB1
0
R/W
When this bit is set to 1, 4 kbytes of EB1 is to be
erased.
0
EB0
0
R/W
When this bit is set to 1, 4 kbytes of EB0 is to be
erased.
Rev. 3.00 Feb 22, 2006 page 511 of 624
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Section 17 Flash Memory (F-ZTAT Version)
17.5.4
Erase Block Register 2 (EBR2)
EBR2 specifies the flash memory erase area block. EBR2 is initialized to H'00 when the SWE bit
in FLMCR1 is 0. Set only one bit in EBR2 and EBR1 together (do not set more than one bit at the
same time). Setting more than one bit will automatically clear all EBR1 and EBR2 bits to 0. For
details, see table 17.3, Erase Blocks.
Bit
Bit Name
Initial Value
R/W
Description
7, 6
—
All 0
R/W
Reserved
5
EB13
0
R/W
When this bit is set to 1, 64 kbytes of EB13 are to
be erased.
4
EB12
0
R/W
When this bit is set to 1, 64 kbytes of EB12 are to
be erased.
3
EB11
0
R/W
When this bit is set to 1, 64 kbytes of EB11 are to
be erased.
2
EB10
0
R/W
When this bit is set to 1, 64 kbytes of EB10 are to
be erased.
1
EB9
0
R/W
When this bit is set to 1, 64 kbytes of EB9 are to be
erased.
0
EB8
0
R/W
When this bit is set to 1, 32 kbytes of EB8 are to be
erased.
The initial value should not be changed.
Rev. 3.00 Feb 22, 2006 page 512 of 624
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Section 17 Flash Memory (F-ZTAT Version)
Table 17.3 Erase Blocks
Address
Block (Size)
Modes 3, 4, and 7
Modes 5 and 6
EB0 (4 kbytes)
H'000000 to H'000FFF
H'100000 to H'100FFF
EB1 (4 kbytes)
H'001000 to H'001FFF
H'101000 to H'101FFF
EB2 (4 kbytes)
H'002000 to H'002FFF
H'102000 to H'102FFF
EB3 (4 kbytes)
H'003000 to H'003FFF
H'103000 to H'103FFF
EB4 (4 kbytes)
H'004000 to H'004FFF
H'104000 to H'104FFF
EB5 (4 kbytes)
H'005000 to H'005FFF
H'105000 to H'105FFF
EB6 (4 kbytes)
H'006000 to H'006FFF
H'106000 to H'106FFF
EB7 (4 kbytes)
H'007000 to H'007FFF
H'107000 to H'107FFF
EB8 (32 kbytes)
H'008000 to H'00FFFF
H'108000 to H'10FFFF
EB9 (64 kbytes)
H'010000 to H'01FFFF
H'110000 to H'11FFFF
EB10 (64 kbytes)
H'020000 to H'02FFFF
H'120000 to H'12FFFF
EB11 (64 kbytes)
H'030000 to H'03FFFF
H'130000 to H'13FFFF
EB12 (64 kbytes)
H'040000 to H'04FFFF
H'140000 to H'14FFFF
EB13 (64 kbytes)
H'050000 to H'05FFFF
H'150000 to H'15FFFF
17.5.5
RAM Emulation Register (RAMER)
RAMER specifies the area of flash memory to be overlapped with part of RAM when emulating
real-time flash memory programming. RAMER settings should be made in user mode or user
program mode. To ensure correct operation of the emulation function, the ROM for which RAM
emulation is performed should not be accessed immediately after this register has been modified.
Normal execution of an access immediately after register modification is not guaranteed.
Rev. 3.00 Feb 22, 2006 page 513 of 624
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Section 17 Flash Memory (F-ZTAT Version)
Bit
Bit Name
Initial Value
R/W
Description
7
to
5
—
All 0
R
Reserved
4
—
These bits always read 0.
0
R/W
Reserved
The initial value should not be changed.
3
RAMS
0
R/W
RAM Select
Specifies selection or non-selection of flash
memory emulation in RAM. When RAMS = 1, the
flash memory is overlapped with part of RAM, and
all flash memory block are in the program/eraseprotect state. When this bit is cleared to 0, the
RAM emulation function is invalid.
2
RAM2
0
R/W
Flash Memory Area Selection
1
RAM1
0
R/W
0
RAM0
0
R/W
When the RAMS bit is set to 1, selects one of the
following flash memory areas to overlap the RAM
area. The areas correspond with 4-kbyte erase
blocks.
Modes 3, 4, and 7
000: H'000000 to H'000FFF (EB0)
001: H'001000 to H'001FFF (EB1)
010: H'002000 to H'002FFF (EB2)
011: H'003000 to H'003FFF (EB3)
100: H'004000 to H'004FFF (EB4)
101: H'005000 to H'005FFF (EB5)
110: H'006000 to H'006FFF (EB6)
111: H'007000 to H'007FFF (EB7)
Modes 5 and 6
000: H'100000 to H'100FFF (EB0)
001: H'101000 to H'101FFF (EB1)
010: H'102000 to H'102FFF (EB2)
011: H'103000 to H'103FFF (EB3)
100: H'104000 to H'104FFF (EB4)
101: H'105000 to H'105FFF (EB5)
110: H'106000 to H'106FFF (EB6)
111: H'107000 to H'107FFF (EB7)
Rev. 3.00 Feb 22, 2006 page 514 of 624
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Section 17 Flash Memory (F-ZTAT Version)
17.6
On-Board Programming Modes
In an on-board programming mode, programming, erasing, and verification for the on-chip flash
memory can be performed. There are two on-board programming modes: boot mode and user
program mode. Table 17.4 shows how to select boot mode. User program mode can be selected by
setting the control bits by software. For a diagram that shows mode transitions of flash memory,
see figure 17.2.
Table 17.4 Setting On-Board Programming Modes
Mode Setting
Boot mode
17.6.1
Single-chip activation expanded mode
with on-chip ROM enabled
MD2
MD1
MD0
0
1
1
Boot Mode
When this LSI enters boot mode, the embedded boot program is started. The boot program
transfers the programming control program from the externally connected host to the on-chip
RAM via the SCI_1. When the flash memory is all erased, the programming control program is
executed.
Table 17.5 shows the boot mode operations between reset end and branching to the programming
control program.
1. When the boot program is initiated, the SCI_1 should be set to asynchronous mode, the chip
measures the low-level period of asynchronous SCI communication data (H’00) transmitted
continuously from the host. The chip then calculates the bit rate of transmission from the host,
and adjusts the SCI_1 bit rate to match that of the host. The transfer format is 8-bit data, 1 stop
bit, and no parity. The reset should end with the RxD pin high. The RxD and TxD pins should
be pulled up on the board if necessary. After the reset ends, it takes approximately 100 states
before the chip is ready to measure the low-level period.
2. After matching the bit rates, the chip transmits one H’00 byte to the host to indicate the end of
bit rate adjustment. The host should confirm that this adjustment end indication (H’00) has
been received normally, and transmit one H’55 byte to the chip. If reception could not be
performed normally, initiate boot mode again by a reset. Depending on the host’s transfer bit
rate and system clock frequency of this LSI, there will be a discrepancy between the bit rates
of the host and the chip. To operate the SCI properly, set the host’s transfer bit rate and system
clock frequency of this LSI within the ranges listed in table 17.6.
Rev. 3.00 Feb 22, 2006 page 515 of 624
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Section 17 Flash Memory (F-ZTAT Version)
3. When boot mode is used, the flash memory programming control program must be prepared in
the host beforehand. Prepare a programming control program in accordance with the
description in section 17.8, Flash Memory Programming/Erasing.
4. Before branching to the programming control program, the chip terminates transfer operations
by the SCI_1 (by clearing the RE and TE bits in SCR to 0), but the adjusted bit rate value
remains set in BRR. Therefore, the programming control program can still use it for transfer
of program data or verify data with the host. The TxD pin is high. The contents of the CPU
general registers are undefined immediately after branching to the programming control
program. These registers must be initialized at the beginning of the programming control
program, since the stack pointer (SP), in particular, is used implicitly in subroutine calls, etc.
5. In boot mode, if flash memory contains data (all data is not 1), all blocks of flash memory are
erased. Boot mode is used for the initial programming in the on-board state or for a forcible
return when a program that is to be initiated in user program mode was accidentally erased and
could not be executed in user program mode.
Notes: 1. In boot mode, a part of the on-chip RAM area (H’FF8000 to H’FF87FF) is used by the
boot program. Addresses H’FF8800 to H’FFBFFF is the area to which the
programming control program is transferred from the host. The boot program area
cannot be used until the execution state in boot mode switches to the programming
control program.
2. Boot mode can be cleared by a reset. Release the reset by setting the MD pins, after
waiting at least 20 states since driving the reset pin low. Boot mode is also cleared
when the WDT overflow reset occurs.
3. Do not change the MD pin input levels in boot mode.
4. All interrupts are disabled during programming or erasing of the flash memory.
Rev. 3.00 Feb 22, 2006 page 516 of 624
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Section 17 Flash Memory (F-ZTAT Version)
Host Operation
Communication Contents
Processing Contents
Bit rate adjustment
Boot mode initiation
Item
Table 17.5 Boot Mode Operation
LSI Operation
Processing Contents
Branches to boot program at reset-start.
Boot program initiation
Continuously transmits data H'00
at specified bit rate.
Transmits data H'55 when data H'00
is received error-free.
H'00, H'00 . . . H'00
• Measures low-level period of receive data H'00.
• Calculates bit rate and sets BRR in SCI_1.
• Transmits data H'00 to host as adjustment end
indication.
H'00
H'55
H'AA
Transmits data H'AA to host when data H'55 is
received.
Flash memory erase
Transfer of number of bytes of
programming control program
H'AA reception
Transmits number of bytes (N) of
programming control program to be
transferred as 2-byte data
(low-order byte following high-order
byte)
Transmits 1-byte of programming
control program (repeated for N times)
Boot program
erase error
H'AA reception.
Upper bytes, lower bytes
Echoback
H'XX
Echoback
H'FF
H'AA
Echobacks the 2-byte data
received to host.
Echobacks received data to host and also
transfers it to RAM.
(repeated for N times)
Checks flash memory data, erases all flash
memory blocks in case of written data
existing, and transmits data H'AA to host.
(If erase could not be done, transmits data
H'FF to host and aborts operation.)
Branches to programming control program
transferred to on-chip RAM and starts
execution.
Rev. 3.00 Feb 22, 2006 page 517 of 624
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Section 17 Flash Memory (F-ZTAT Version)
Table 17.6 System Clock Frequencies for which Automatic Adjustment of LSI Bit Rate Is
Possible
Host Bit Rate
System Clock Frequency Range of LSI
19,200 bps
8 to 25 MHz
9,600 bps
8 to 25 MHz
17.6.2
User Program Mode
On-board programming/erasing of an individual flash memory block can also be performed in user
program mode by branching to a user program/erase program. The user must set branching
conditions and provide on-board means of supplying programming data. The flash memory must
contain the program/erase program or a program which provides the program/erase program from
external memory. Because the flash memory itself cannot be read during programming/erasing,
transfer the program/erase program to on-chip RAM, as like in boot mode. Figure 17.6 shows a
sample procedure for programming/erasing in user program mode. Prepare a program/erase
program in accordance with the description in section 17.8, Flash Memory Programming/Erasing.
Reset-start
No
Program/erase?
Yes
Transfer user program/erase control
program to RAM
Branch to flash memory application
program
Branch to user program/erase control
program in RAM
Execute user program/erase control
program (flash memory programming)
Branch to flash memory application
program
Figure 17.6 Programming/Erasing Flowchart Example in User Program Mode
Rev. 3.00 Feb 22, 2006 page 518 of 624
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Section 17 Flash Memory (F-ZTAT Version)
17.7
Flash Memory Emulation in RAM
Making a setting in the RAM emulation register (RAMER) enables RAM to be overlapped onto
the part of flash memory area so that data to be programmed to flash memory can be emulated in
the on-chip RAM in real time. Emulation can be performed in user mode or user program mode.
Figure 17.7 shows an example of emulation of real-time flash memory programming.
1. Set RAMER to overlap RAM onto the area for which real-time programming is required.
2. Emulation is performed using the overlapping RAM.
3. After the program data has been confirmed, the RAMS bit is cleared, thus releasing RAM
overlap.
4. The data written in the overlapping RAM is written into the flash memory space (EB0).
Start of emulation program
Set RAMER
Write tuning data to overlap
RAM
Execute application program
No
Tuning OK?
Yes
Clear RAMER
Write to flash memory
emulation block
End of emulation program
Figure 17.7 Flowchart for Flash Memory Emulation in RAM
Rev. 3.00 Feb 22, 2006 page 519 of 624
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Section 17 Flash Memory (F-ZTAT Version)
Example in which flash memory block is overlapped is shown in figure 17.8.
1. The RAM area to be overlapped is fixed at a 4-kbyte area in the range of H'FFA000 to
H'FFAFFF.
2. The flash memory area to overlap is selected by RAMER from a 4-kbyte area among one of
the EB0 to EB7 blocks.
3. The overlapped RAM area can be accessed from both the flash memory addresses and RAM
addresses.
Note: 1. When the RAMS bit in RAMER is set to 1, program/erase protection is enabled for all
flash memory blocks (emulation protection). In this state, setting the P or E bit in
FLMCR1 to 1 does not cause a transition to program mode or erase mode.
2. A RAM area cannot be erased by execution of software in accordance with the erase
algorithm.
3. Block area EB0 contains the vector table. When performing RAM emulation, the
vector table is needed in the overlap RAM.
Rev. 3.00 Feb 22, 2006 page 520 of 624
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Section 17 Flash Memory (F-ZTAT Version)
This area can be accessed
from both the RAM area
and flash memory area
H'00000
EB0
H'01000
EB1
H'02000
EB2
H'03000
EB3
H'04000
EB4
H'05000
EB5
H'06000
EB6
H'07000
EB7
H'08000
H'FFA000
H'FFAFFF
Flash memory
EB8 to EB13
On-chip RAM
H'FFBFFF
H'5FFFF
384-kbyte flash memory
Figure 17.8 Example of RAM Overlap Operation
17.8
Flash Memory Programming/Erasing
A software method, using the CPU, is employed to program and erase flash memory in the onboard programming modes. Depending on the FLMCR1 and FLMCR2 setting, the flash memory
operates in one of the following four modes: program mode, erase mode, program-verify mode,
and erase-verify mode. The programming control program in boot mode and the user
program/erase program in user mode use these operating modes in combination to perform
programming/erasing. Flash memory programming and erasing should be performed in
accordance with the descriptions in section 17.8.1, Program/Program-Verify and section 17.8.2,
Erase/Erase-Verify, respectively.
Rev. 3.00 Feb 22, 2006 page 521 of 624
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Section 17 Flash Memory (F-ZTAT Version)
17.8.1
Program/Program-Verify
When programming data or programs to the flash memory, the program/program-verify flowchart
shown in figure 17.9 should be followed. Performing programming operations according to this
flowchart will enable data or programs to be programmed to the flash memory without subjecting
the chip to voltage stress or sacrificing program data reliability.
1. Programming must be done to an empty address. Do not reprogram an address to which
programming has already been performed.
2. Programming should be carried out 128 bytes at a time. A 128-byte data transfer must be
performed even if programming fewer than 128 bytes. In this case, H'FF data must be written
to the extra addresses.
3. Prepare the following data storage areas in RAM: a 128-byte programming data area, a 128byte reprogramming data area, and a 128-byte additional-programming data area. Perform
reprogramming data computation and additional programming data computation according to
figure 17.9.
4. Consecutively transfer 128 bytes of data in byte units from the programming data area,
reprogramming data area, or additional-programming data area to the flash memory. The
program address and 128-byte data are latched in the flash memory. The lower 8 bits of the
start address in the flash memory destination area must be H'00 or H'80.
5. The time during which the P bit is set to 1 is the programming time. Figure 17.9 shows the
allowable programming times.
6. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (y + z2 + α + β) µs as the WDT overflow period.
7. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower 2 bits
are B’00. Verify data can be read in words from the address to which a dummy write was
performed.
8. The maximum number of repetitions of the program/program-verify sequence to the same bit
(N) must not be exceeded.
Rev. 3.00 Feb 22, 2006 page 522 of 624
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Section 17 Flash Memory (F-ZTAT Version)
Start of programming
Write pulse application subroutine
Write pulse application
Start
Enable WDT
Set SWE bit in FLMCR1
Wait (x) µs
*6
Store 128-byte program data in program
data area and reprogram data area
*4
Set PSU bit in FLMCR1
Wait (y) µs
*6
Perform programming in the erased state.
Do not perform additional programming
on previously programmed addresses.
Set P bit in FLMCR1
n=1
Wait (z1) µs or (z2) µs or (z3) µs
*5 *6
m=0
Clear P bit in FLMCR1
Write 128-byte data in RAM reprogram *1
data area consecutively to flash memory
Wait (α) µs
Sub-routine-call
Clear PSU bit in FLMCR1
Wait (β) ms
Write pulse application
(z1) µs or (z2) µs
Disable WDT
Set PV bit in FLMCR1
See note 7 for pulse width
Wait (γ) µs
End sub
Note: 7. Write Pulse Width
Number of Writes (n)
Write Time (z) ms
1
z1
2
z1
3
z1
4
z1
5
z1
6
z1
7
z2
8
z2
9
z2
10
z2
11
z2
12
z2
13
z2
.
.
.
.
.
.
998
z2
999
z2
1000
z2
*6
H'FF dummy write to verify address
Wait (ε) µs
Increment address
Note: Use a z3 µs write pulse for additional
programming.
Read verify data
Transfer additional program data to
additional program data area
Reprogram data computation
*3
*4
128-byte
data verification
completed?
OK
Clear PV bit in FLMCR1
Wait (η) µs
6≥n?
Additional program data
storage area (128 bytes)
*4
Transfer reprogram data to reprogram
data area
NG
Reprogram data storage
area (128 bytes)
m=1
NG
OK
Additional program data computation
RAM
Program data storage
area (128 bytes)
NG
Write data = verify
data?
OK
6≥n?
n←n+1
*2
*6
NG
OK
Sequentially write 128-byte data in
additional program data area in RAM to *1
flash memory
Sub-routine-call
Write pulse application
(z3) µs
*6
(additional programming)
Notes: 1. Data transfer is performed by byte transfer. The lower 8 bits of the first address written
to must be H'00 or H'80. A 128-byte data transfer must be performed even if writing
fewer than 128 bytes; in this case, H'FF data must be written to the extra addresses.
2. Verify data is read in 16-bit (W) units.
3. The reprogram data is given by the operation of the following tables (comparison
NG
between stored data in the program data area and verify data). Programming is
m = 0?
executed for the bits of reprogram data 0 in the next reprogram loop. Even bits for
OK
which programming has been completed will be subjected to additional programming
Clear SWE bit in FLMCR1
if they fail the subsequent verify operation.
4. A 128-byte areas for storing program data, reprogram data, and additional program
Wait (θ) µs
data must be provided in the RAM. The contents of the reprogram and additional
program data are modified as programming proceeds.
End of programming
5. A write pulse of (z1) or (z2) µs should be applied according to the progress of the
programming operation. See note 7 for the pulse widths. When writing of additionalprogramming data is executed, a (z3) µs write pulse should be applied.
Reprogram data X' means reprogram data when the write pulse is applied.
6. For the values of x, y, z1, z2, z3, α, β, γ, ε, η, θ, and N, see section 21.1.6, Flash Memory Characteristics.
Program Data Operation Chart
Original Data Verify Data Reprogram Data
Comments
(D)
(V)
(X)
0
0
1
Programming completed
1
0
Programming incomplete; reprogram
1
0
1
1
Still in erased state; no action
n ≥ (N)?
*6
NG
OK
Clear SWE bit in FLMCR1
Wait (θ) µs
*6
Additional Program Data Operation Chart
Reprogram Data Verify Data Additional Program
(X')
(V)
Data (Y)
0
0
0
1
1
1
0
1
*6
Programming failure
Comments
Additional programming executed
Additional programming not executed
Additional programming not executed
Additional programming not executed
Figure 17.9 Program/Program-Verify Flowchart
Rev. 3.00 Feb 22, 2006 page 523 of 624
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Section 17 Flash Memory (F-ZTAT Version)
17.8.2
Erase/Erase-Verify
When erasing flash memory, the erase/erase-verify flowchart shown in figure 17.10 should be
followed.
1. Prewriting (setting erase block data to all 0s) is not necessary.
2. Erasing is performed in block units. Make only a single-bit specification in the erase block
registers (EBR1 and EBR2). To erase multiple blocks, each block must be erased in turn.
3. The time during which the E bit is set to 1 is the flash memory erase time.
4. The watchdog timer (WDT) is set to prevent overprogramming due to program runaway, etc.
Set a value greater than (y + z + α + β) ms as the WDT overflow period.
5. For a dummy write to a verify address, write 1-byte data H'FF to an address whose lower two
bits are B’00. Verify data can be read in longwords from the address to which a dummy write
was performed.
6. If the read data is unerased, set erase mode again, and repeat the erase/erase-verify sequence as
before. The maximum number of repetitions of the erase/erase-verify sequence (N) must not
be exceeded.
17.8.3
Interrupt Handling when Programming/Erasing Flash Memory
All interrupts, including NMI input, are disabled when flash memory is being programmed or
erased, and while the boot program is executing in boot mode. There are three reasons for this:
1. Interrupt during programming or erasing might cause a violation of the programming or
erasing algorithm, with the result that normal operation could not be assured.
2. If the interrupt exception handling is started when the vector address has not been programmed
yet or the flash memory is being programmed or erased, the vector would not be read correctly,
possibly resulting in CPU runaway.
3. If an interrupt occurred during boot program execution, it would not be possible to execute the
normal boot mode sequence.
Rev. 3.00 Feb 22, 2006 page 524 of 624
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Section 17 Flash Memory (F-ZTAT Version)
Start
∗1
Set SWE bit in FLMCR1
Wait (x) µs
∗2
n=1
∗4
Set EBR1, EBR2
Enable WDT
Set ESU bit in FLMCR1
Wait (y) µs
∗2
Start of erase
Set E bit in FLMCR1
∗2
Wait (z) ms
Clear E bit in FLMCR1
n←n+1
Halt erase
Wait (α) µs
∗2
Clear ESU bit in FLMCR1
Wait (β) µs
∗2
Disable WDT
Set EV bit in FLMCR1
∗2
Wait (γ) µs
Set block start address to verify address
H'FF dummy write to verify address
∗2
Wait (ε) ms
∗3
Read verify data
Increment
address
Verify data = all 1?
NG
OK
NG
Last address of block?
OK
Clear EV bit in FLMCR1
Clear EV bit in FLMCR1
Wait (η) µs
Wait (η) µs
∗2
NG
∗5
∗2
End of
erasing of all erase
blocks?
OK
n ≥ N?
OK
Clear SWE bit in FLMCR1
Clear SWE bit in FLMCR1
Wait (θ) µs
End of erasing
Notes: 1.
2.
3.
4.
5.
∗2
NG
∗2
Wait (θ) µs
∗2
Erase failure
Prewriting (setting erase block data to all 0) is not necessary.
The values of x, y, z, α, β, γ, ε, η, θ, and N are shown in section 21.1.6, Flash Memory Characteristics.
Verify data is read in 16-bit (W) units.
Set only one bit in EBR1or EBR2. More than one bit cannot be set.
Erasing is performed in block units. To erase a number of blocks, the individual blocks must be erased sequentially.
Figure 17.10 Erase/Erase-Verify Flowchart
Rev. 3.00 Feb 22, 2006 page 525 of 624
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Section 17 Flash Memory (F-ZTAT Version)
17.9
Program/Erase Protection
There are three kinds of flash memory program/erase protection: hardware protection, software
protection, and error protection.
17.9.1
Hardware Protection
Hardware protection refers to a state in which programming/erasing of flash memory is forcibly
disabled or aborted because of a transition to reset (including an overflow reset by the WDT) or
standby mode. Flash memory control register 1 (FLMCR1), flash memory control register 2
(FLMCR2), erase block register 1 (EBR1), and erase block register 2 (EBR2) are initialized. In a
reset via the RES pin, the reset state is not entered unless the RES pin is held low until oscillation
stabilizes after powering on. In the case of a reset during operation, hold the RES pin low for the
RES pulse width specified in the AC Characteristics section.
17.9.2
Software Protection
Software protection can be implemented against programming/erasing of all flash memory blocks
by clearing the SWE bit in FLMCR1 (this operation must be executed in the on-chip RAM or
external memory). When software protection is in effect, setting the P or E bit in FLMCR1 does
not cause a transition to program mode or erase mode. By setting the erase block register 1
(EBR1) and erase block register 2 (EBR2), erase protection can be set for individual blocks.
When EBR1 and EBR2 are set to H'00, erase protection is set for all blocks.
17.9.3
Error Protection
In error protection, an error is detected when the CPU’s runaway occurs during flash memory
programming/erasing, or operation is not performed in accordance with the program/erase
algorithm, and the program/erase operation is forcibly aborted. Aborting the program/erase
operation prevents damage to the flash memory due to overprogramming or overerasing.
When the following errors are detected during programming/erasing of flash memory, the FLER
bit in FLMCR2 is set to 1, and the error protection state is entered.
• When flash memory is read during programming/erasing (including a vector read or instruction
fetch)
• When an exception handling (excluding a reset) is started during programming/erasing
• When a SLEEP instruction is executed during programming/erasing
• When the CPU releases the bus mastership during programming/erasing
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Section 17 Flash Memory (F-ZTAT Version)
The FLMCR1, FLMCR2, EBR1, and EBR2 settings are retained, but program mode or erase
mode is forcibly aborted at the point at which the error occurred. Program mode or erase mode
cannot be re-entered by re-setting the P or E bit. However, PV and EV bit setting is enabled, and a
transition can be made to verify mode. The error protection state can be canceled by a power-on
reset or in hardware standby mode.
17.10
Programmer Mode
In programmer mode, a PROM programmer can perform programming/erasing via a socket
adapter, just like for a discrete flash memory. Use a PROM programmer which supports the
Renesas Technology 512-kbyte flash memory on-chip MCU device type (FZTAT512V3A). A 12MHz input clock is needed.
17.11
Power-Down States for Flash Memory
In user mode, the flash memory will operate in either of the following states:
• Normal operating mode
The flash memory can be read.
• Standby mode
All flash memory circuits are halted.
Table 17.7 shows the correspondence between the operating modes of this LSI and the flash
memory. When the flash memory returns to normal operation from a standby state, a power
supply circuit stabilization period is needed. When the flash memory returns to its normal
operating state, bits STS3 to STS0 in SBYCR must be set to provide a wait time of at least 100 µs,
even when the external clock is being used.
Table 17.7 Flash Memory Operating States
Operating Mode
Flash Memory Operating State
Active mode
Normal operating state
Sleep mode
Normal operating state
Standby mode
Standby state
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Section 17 Flash Memory (F-ZTAT Version)
17.12
Usage Notes
Precautions concerning the use of on-board programming mode, the RAM emulation function, and
programmer mode are summarized below.
1. Use the specified voltages and timing for programming and erasing.
Applied voltages in excess of the rating can permanently damage the device. Use a PROM
programmer that supports the Renesas Technology microcomputer device type with 512-kbyte
on-chip flash memory (FZTAT512V3A).
Do not select the HN27C4096 setting for the PROM programmer, and only use the specified
socket adapter.
2. Reset the flash memory before turning on/off the power.
When applying or disconnecting Vcc power, fix the RES pin low and place the flash memory
in the hardware protection state. The power-on and power-off timing requirements should also
be satisfied in the event of a power failure and subsequent recovery.
3. Use the recommended algorithm when programming and erasing flash memory.
The recommended algorithm enables programming and erasing to be carried out without
subjecting the device to voltage stress or sacrificing program data reliability. When setting the
P or E bit in FLMCR1, the watchdog timer should be set beforehand as a precaution against
program runaway, etc.
4. Do not set or clear the SWE bit during execution of a program in flash memory.
Wait for at least 100 µs after clearing the SWE bit before executing a program or reading data
in flash memory.
When the SWE bit is set, data in flash memory can be rewritten. When the SWE bit is set to 1,
data in flash memory can be read only in program-verify/erase-verify mode. Access flash
memory only for verify operations (verification during programming/erasing). Also, do not
clear the SWE bit during programming, erasing, or verifying. Similarly, when using the RAM
emulation function, the SWE bit must be cleared before executing a program or reading data in
flash memory.
However, the RAM area overlapping flash memory space can be read and written to regardless
of whether the SWE bit is set or cleared.
5. Do not use interrupts while flash memory is being programmed or erased.
All interrupt requests, including NMI, should be disabled during programming/erasing the
flash memory to give priority to program/erase operations.
6. Do not perform additional programming. Erase the memory before reprogramming.
In on-board programming, perform only one programming operation on a 128-byte
programming unit block. In programmer mode, too, perform only one programming operation
on a 128-byte programming unit block. Programming should be carried out with the entire
programming unit block erased.
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Section 17 Flash Memory (F-ZTAT Version)
7. Before programming, check that the chip is correctly mounted in the PROM programmer.
Overcurrent damage to the device can result if the index marks on the PROM programmer
socket, socket adapter, and chip are not correctly aligned.
8. Do not touch the socket adapter or chip during programming.
Touching either of these can cause contact faults and write errors.
9. Apply the reset signal after the SWE, bit is cleared during its operation.
The reset signal is applied at least 100 µs after the SWE bit has been cleared.
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Section 17 Flash Memory (F-ZTAT Version)
Wait time: x
Programming/
erasing
possible Wait time: 100 µs
φ
Min 0 µs
tOSC1
VCC
MD2 to MD0*1
tMDS*3
RES
SWE set
SWE cleared
SWE bit
(1) Boot Mode
Wait time: x
Programming/
erasing
possible Wait time: 100 µs
φ
Min 0 µs
tOSC1
VCC
MD2 to MD0*1
tMDS*3
RES
SWE set
SWE cleared
SWE bit
(2) User Program Mode
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*2
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations
prohibited)
Notes: 1. Except when switching modes, the level of the mode pins (MD2 to MD0) must be fixed until
power-off by pulling the pins up or down.
2. See section 21.1.6, Flash Memory Characteristics.
3. Mode programming setup time tMDS (min) = 200 ns
Figure 17.11 Power-On/Off Timing
Rev. 3.00 Feb 22, 2006 page 530 of 624
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Section 17 Flash Memory (F-ZTAT Version)
Wait time: x
Programming/erasing Programming/erasing
possible
possible
*4
Wait time: x
Programming/erasing
possible
*4
Programming/erasing
possible
*4
φ
tOSC1
VCC
2
tMDS*
MD2 to MD0
tMDS
tRESW
RES
SWE
set
SWE bit
Mode
change*1
SWE
cleared
Boot
mode
Mode
change*1
User
mode
User
User
program mode
mode
User
program
mode
User mode
User
program
mode
Period during which flash memory access is prohibited
(x: Wait time after setting SWE bit)*3
Period during which flash memory can be programmed
(Execution of program in flash memory prohibited, and data reads other than verify operations prohibited)
Notes: 1.
When entering boot mode or making a transition from boot mode to another mode, mode switching must be
carried out by means of RES input. The state of ports with multiplexed address functions and bus control
output pins (AS, RD, HWR, LWR) will change during this switchover interval (the interval during which the RES
pin input is low), and therefore these pins should not be used as output signals during this time.
2. When making a transition from boot mode to another mode, a mode programming setup time tMDS (min) of 200
ns is necessary with respect to RES clearance timing.
3. See section 21.1.6, Flash Memory Characteristics.
4. Wait time: 100 ms
Figure 17.12 Mode Transition Timing
(Example: Boot Mode → User Mode ↔ User Program Mode)
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Section 17 Flash Memory (F-ZTAT Version)
Rev. 3.00 Feb 22, 2006 page 532 of 624
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Section 18 Clock Pulse Generator
Section 18 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and
internal clocks.
The clock pulse generator consists of an oscillator circuit, PLL circuit, and divider.
Figure 18.1 shows a block diagram of the clock pulse generator.
PLLCR
STC0, STC1
SCKCR
SCK2 to SCK0
EXTAL
Oscillator
PLL circuit
(×1, ×2, ×4)
Divider
XTAL
Legend:
PLLCR: PLL system control register
SCKCR: System clock control register
System clock
to φ pin
Internal clock
to peripheral
modules
Figure 18.1 Block Diagram of Clock Pulse Generator
The frequency can be changed by means of the PLL circuit. Frequency changes are made by
software by means of settings in the PLL control register (PLLCR) and the system clock control
register (SCKCR).
18.1
Register Descriptions
The clock pulse generator has the following registers.
• System clock control register (SCKCR)
• PLL control register (PLLCR)
CPG0400A_010020020400
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Section 18 Clock Pulse Generator
18.1.1
System Clock Control Register (SCKCR)
SCKCR controls φ clock output and selects operation when the frequency multiplication factor
used by the PLL circuit is changed, and the division ratio used by the divider.
Bit
Bit Name
Initial Value
R/W
Description
7
PSTOP
0
R/W
φ Clock Output Disable
Controls φ output.
Normal Operation
0: φ output
1: Fixed high
Sleep Mode
0: φ output
1: Fixed high
Software Standby Mode
0: Fixed high
1: Fixed high
Hardware Standby Mode
0: High impedance
1: High impedance
All module clock stop mode
0: φ output
1: Fixed high
6
—
0
R/W
Reserved
This bit can be read from or written to. However, the
write value should always be 0.
5, 4
—
All 0
—
Reserved
These bits are always read as 0 and cannot be
modified.
3
STCS
0
R/W
Frequency Multiplication Factor Switching Mode Select
Selects the operation when the PLL circuit frequency
multiplication factor is changed.
0: Specified multiplication factor is valid after transition
to software standby mode
1: Specified multiplication factor is valid immediately
after STC1 and STC0 bits are rewritten
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Section 18 Clock Pulse Generator
Bit
Bit Name
Initial Value
R/W
Description
2
SCK2
0
R/W
System Clock Select 2 to 0
1
SCK1
0
R/W
Select the division ratio.
0
SCK0
0
R/W
000: 1/1
001: 1/2
010: 1/4
011: 1/8
100: 1/16
101: 1/32
11X: Setting prohibited
X: Don’t care
18.1.2
PLL Control Register (PLLCR)
PLLCR sets the frequency multiplication factor used by the PLL circuit.
Bit
Bit Name
Initial Value
R/W
Description
7
to
4
—
All 0
—
Reserved
3
—
These bits are always read as 0 and cannot be
modified.
0
R/W
Reserved
This bit can be read from or written to. However,
the write value should always be 0.
2
—
0
—
Reserved
This bit is always read as 0 and cannot be
modified.
1
STC1
0
R/W
Frequency Multiplication Factor
0
STC0
0
R/W
The STC bits specify the frequency multiplication
factor used by the PLL circuit.
00: × 1
01: × 2
10: × 4
11: Setting prohibited
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Section 18 Clock Pulse Generator
18.2
Oscillator
Clock pulses can be supplied by connecting a crystal resonator, or by input of an external clock.
18.2.1
Connecting a Crystal resonator
A crystal resonator can be connected as shown in the example in figure 18.2. Select the damping
resistance Rd according to table 18.1. An AT-cut parallel-resonance type should be used.
Figure 18.3 shows the equivalent circuit of the crystal resonator. Use a crystal resonator that has
the characteristics shown in table 18.2.
CL1
EXTAL
XTAL
Rd
CL2
CL1 = CL2 = 10 to 22 pF
Figure 18.2 Connection of Crystal Resonator (Example)
Table 18.1 Damping Resistance Value
Frequency (MHz)
8
12
16
20
25
Rd (Ω)
200
0
0
0
0
CL
L
Rs
XTAL
EXTAL
C0
AT-cut parallel-resonance type
Figure 18.3 Crystal Resonator Equivalent Circuit
Rev. 3.00 Feb 22, 2006 page 536 of 624
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Section 18 Clock Pulse Generator
Table 18.2 Crystal Resonator Characteristics
Frequency (MHz)
8
12
16
20
25
RS max (Ω)
80
60
50
40
40
C0 max (pF)
7
7
7
7
7
18.2.2
External Clock Input
An external clock signal can be input as shown in the examples in figure 18.4. If the XTAL pin is
left open, make sure that parasitic capacitance is no more than 10 pF. When the counter clock is
input to the XTAL pin, make sure that the external clock is held high in standby mode.
Table 18.3 shows the input conditions for the external clock
EXTAL
XTAL
External clock input
Open
(a) XTAL pin left open
EXTAL
External clock input
XTAL
(b) Counter clock input at XTAL pin
Figure 18.4 External Clock Input (Examples)
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Section 18 Clock Pulse Generator
Table 18.3 External Clock Input Conditions
VCC = 3.0 V to 3.6 V
Item
Symbol
Min
Max
Unit
Test Conditions
External clock input low pulse
width
tEXL
15
—
ns
Figure 18.5
External clock input high pulse
width
tEXH
15
—
ns
External clock rise time
tEXr
—
5
ns
External clock fall time
tEXf
—
5
ns
Clock low pulse width
tCL
0.4
0.6
tcyc
Clock high pulse width
tCH
0.4
0.6
tcyc
tEXH
tEXL
EXTAL
VCC × 0.5
tEXr
tEXf
Figure 18.5 External Clock Input Timing
Rev. 3.00 Feb 22, 2006 page 538 of 624
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Section 18 Clock Pulse Generator
18.3
PLL Circuit
The PLL circuit has the function of multiplying the frequency of the clock from the oscillator by a
factor of 1, 2, or 4. The multiplication factor is set with the STC1 and the STC0 bits in PLLCR.
The phase of the rising edge of the internal clock is controlled so as to match that of the rising
edge of the EXTAL pin.
When the multiplication factor of the PLL circuit is changed, the operation varies according to the
setting of the STCS bit in SCKCR.
When STCS = 0, the setting becomes valid after a transition to software standby mode. The
transition time count is performed in accordance with the setting of bits STS3 to STS0 in SBYCR.
For details on SBYCR, refer to section 19.1.1, Standby Control Register (SBYCR).
1. The initial PLL circuit multiplication factor is 1.
2. A value is set in bits STS3 to STS0 to give the specified transition time.
3. The target value is set in bits STC1 and STC0, and a transition is made to software standby
mode.
4. The clock pulse generator stops and the value set in STC1 and STC0 becomes valid.
5. Software standby mode is cleared, and a transition time is secured in accordance with the
setting in STS3 to STS0.
6. After the set transition time has elapsed, this LSI resumes operation using the target
multiplication factor.
When STCS = 1, this LSI operates using the new multiplication factor immediately after bits
STC1 and STC0 are rewritten.
18.4
Frequency Divider
The frequency divider divides the PLL output clock to generate a 1/2, 1/4, 1/8, 1/16, or 1/32 clock.
Rev. 3.00 Feb 22, 2006 page 539 of 624
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Section 18 Clock Pulse Generator
18.5
Usage Notes
18.5.1
Notes on Clock Pulse Generator
1. The following points should be noted since the frequency of φ changes according to the setting
of SCKCR and PLLCR.
Select the clock division ratio that is within the operation guaranteed range of clock cycle time
tcyc shown in the AC timing of Electrical Characteristics. In other words, the range of φ must
be specified from 8 MHz (min) to 33 MHz (max); outside of this range must be prevented.
2. All the on-chip peripheral modules operate on the φ. Therefore, note that the time processing
of modules such as a timer and SCI differ before and after changing the clock division ratio. In
addition, wait time for clearing software standby mode differs by changing the clock division
ratio. See the description, Setting Oscillation Stabilization Time after Clearing Software
Standby Mode in section 19.2.3, Software Standby Mode, for details.
3. Note that the frequency of φ will be changed when setting SCKCR or PLLCR while executing
the external bus cycle with the write-data-buffer function.
18.5.2
Notes on Resonator
Since various characteristics related to the resonator are closely linked to the user’s board design,
thorough evaluation is necessary on the user’s part, using the resonator connection examples
shown in this section as a guide. As the parameters for the oscillation circuit will depend on the
floating capacitance of the resonator and the user board, the parameters should be determined in
consultation with the resonator manufacturer. The design must ensure that a voltage exceeding the
maximum rating is not applied to the resonator pin.
Rev. 3.00 Feb 22, 2006 page 540 of 624
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Section 18 Clock Pulse Generator
18.5.3
Notes on Board Designs
When using the crystal resonator, place the crystal resonator and its load capacitors as close as
possible to the XTAL and EXTAL pins. Other signal lines should be routed away from the
oscillator circuit to prevent induction from interfering with correct oscillation. See figure 18.6.
Avoid
Signal A Signal B
This LSI
CL2
XTAL
EXTAL
CL1
Figure 18.6 Note on Oscillator Board Design
Figure 18.7 shows the external circuitry recommended for the PLL circuit. Separate PLLVcc and
PLLVss from the other Vcc and Vss lines at the board power supply source, and be sure to insert
bypass capacitors CPB and CB close to the pins.
Rp: 200Ω
PLLVCC
CPB: 0.1 µF*
PLLVSS
VCC
CB: 0.1 µF*
VSS
Note: * CB and CPB are laminated ceramic capacitors.
Figure 18.7 Recommended External Circuitry for PLL Circuit
Rev. 3.00 Feb 22, 2006 page 541 of 624
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Section 18 Clock Pulse Generator
Rev. 3.00 Feb 22, 2006 page 542 of 624
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Section 19 Power-Down Modes
Section 19 Power-Down Modes
In addition to the normal program execution state, this LSI has power-down modes in which
operation of the CPU and oscillator is halted and power dissipation is reduced. Low-power
operation can be achieved by individually controlling the CPU, on-chip peripheral modules, and
so on.
This LSI’s operating modes are high-speed mode and six power down modes:
• Clock division mode
• Sleep mode
• Module stop mode
• All module clock stop mode
• Software standby mode
• Hardware standby mode
Sleep mode is a CPU state, clock division mode is a CPU and bus master state, and module stop
mode is an on-chip peripheral function (including bus masters other than the CPU) state. A
combination of these modes can be set.
After a reset, this LSI is in high-speed mode.
Table 19.1 shows the internal states of this LSI in each mode. Figure 19.1 shows the mode
transition diagram.
LPWS262A_010020020400
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Section 19 Power-Down Modes
Table 19.1 Operating Modes
Clock
Division
Mode
Sleep
Mode
All Module Software
Clock Stop Standby
Module
Mode
Stop Mode Mode
Hardware
Standby
Mode
Clock pulse generator Functions
Functions
Functions
Functions
Functions
Halted
Halted
CPU
Functions
Halted
Functions
Halted
Halted
Halted
Retained
Undefined
Operating State
High
Speed
Mode
Instruction Functions
execution
Register
External
interrupts
NMI
Retained
Functions
Functions
Functions
Functions
Functions
Functions
Halted
Peripheral WDT
functions
Functions
Functions
Functions
Functions
Functions
Halted
(Retained)
Halted
(Reset)
TMR
Functions
Functions
Functions
Halted
(Retained)
Functions/ Halted
Halted
(Retained)
(Retained)*
Halted
(Reset)
DTC
Functions
Functions
Functions
Halted
(Retained)
Halted
(Retained)
Halted
(Retained)
Halted
(Reset)
TPU
Functions
Functions
Functions
Halted
(Retained)
Halted
(Retained)
Halted
(Retained)
Halted
(Reset)
PPG
Functions
Functions
Functions
Halted
(Retained)
Halted
(Retained)
Halted
(Retained)
Halted
(Reset)
D/A
Functions
Functions
Functions
Halted
(Retained)
Halted
(Retained)
Halted
(Retained)
Halted
(Reset)
A/D
Functions
Functions
Functions
Halted
(Retained)
Halted
(Retained)
Halted
(Reset)
Halted
(Reset)
SCI
Functions
Functions
Functions
Halted
(Reset)
Halted
(Reset)
Halted
(Reset)
Halted
(Reset)
RAM
Functions
Functions
Functions
Functions
Functions
Retained
Retained
I/O
Functions
Functions
Functions
Functions
Retained
Retained
High
impedance
IRQ0 to 15
Notes: “Halted (Retained)” in the table means that internal register values are retained and internal
operations are suspended.
“Halted (Reset)” in the table means that internal register values and internal states are
initialized.
In module stop mode, only modules for which a stop setting has been made are halted
(reset or retained).
* The active or halted state can be selected by means of the MSTP0 bit in MSTPCR.
Rev. 3.00 Feb 22, 2006 page 544 of 624
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Section 19 Power-Down Modes
STBY pin = low
Reset state
STBY pin = high
RES pin = low
Hardware
standby mode
RES pin = high
SSBY = 0
SLEEP
instruction
High-speel mode
(Internal clock is PLL
circuit output clock)
SCK2 to
SCK0 = 0
SCK2 to
SCK0 ≠ 0
Clock division
mode
Sleep mode
Any interrupt
SLEEP
instruction
Interrupt*1
All
module-clocks-stop
mode
SLEEP
instruction
SSBY = 1
Software
standby mode
External
interrupt*2
Program execution state
: Transition after exception handling
MSTPCR =
H'FFFF (H'FFFE),
SSBY = 0
Program-halted state
: Power- down mode
Notes: When a transition is made between modes by means of an interrupt, the transition cannot
be made on interrupt source generation alone. Ensure that interrupt handling is performed
after accepting the interrupt request.
From any state, a transition to hardware standby mode occurs when STBY is driven low.
From any state except hardware standby mode, a transition to the reset state occurs when
RES is driven low.
1. NMI, IRQ0 to IRQ7, 8-bit timer interrupts, watchdog timer interrupts.
(8-bit timer interrupts are valid when MSTP0 = 0.)
2. NMI, IRQ0 to IRQ7
(IRQ0 to IRQ7 are valid when the corresponding bit in SSIER is 1.)
Figure 19.1 Mode Transitions
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Section 19 Power-Down Modes
19.1
Register Descriptions
The registers relating to the power-down mode are shown below. For details on the system clock
control register (SCKCR), refer to section 18.1.1, System Clock Control Register (SCKCR).
• System clock control register (SCKCR)
• Standby control register (SBYCR)
• Module stop control register H (MSTPCRH)
• Module stop control register L (MSTPCRL)
19.1.1
Standby Control Register (SBYCR)
SBYCR performs software standby mode control.
Bit
Bit Name
Initial Value
R/W
Description
7
SSBY
0
R/W
Software Standby
This bit specifies the transition mode after
executing the SLEEP instruction
0: Shifts to sleep mode after the SLEEP instruction
is executed
1: Shifts to software standby mode after the
SLEEP instruction is executed
This bit does not change when clearing the
software standby mode by using external interrupts
and shifting to normal operation. This bit should be
written 0 when clearing.
6
OPE
1
R/W
Output Port Enable
Specifies whether the output of the address bus
and bus control signals (CS0 to CS7, AS, RD,
HWR, LWR, UCAS, LCAS) is retained or set to the
high-impedance state in software standby mode.
0: In software standby mode, address bus and bus
control signals are high-impedance
1: In software standby mode, address bus and bus
control signals retain output state
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Section 19 Power-Down Modes
Bit
Bit Name
Initial Value
R/W
Description
5, 4
—
All 0
—
Reserved
These bits are always read as 0. The initial value
should not be changed.
3
STS3
1
R/W
Standby Timer Select 3 to 0
2
STS2
1
1
STS1
1
0
STS0
1
R/W
R/W
R/W
These bits select the time the MCU waits for the
clock to stabilize when software standby mode is
cleared by an external interrupt. With crystal
oscillation, refer to table 19.2 and make a selection
according to the operating frequency so that the
standby time is at least the oscillation stabilization
time. With an external clock, a PLL circuit
stabilization time is necessary. Refer to table 19.2
to set the wait time.
0000: Setting prohibited
0001: Setting prohibited
0010: Setting prohibited
0011: Setting prohibited
0100: Setting prohibited
0101: Standby time = 64 states
0110: Standby time = 512 states
0111: Standby time = 1024 states
1000: Standby time = 2048 states
1001: Standby time = 4096 states
1010: Standby time = 16384 states
1011: Standby time = 32768 states
1100: Standby time = 65536 states
1101: Standby time = 131072 states
1110: Standby time = 262144 states
1111: Standby time = 524288 states
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Section 19 Power-Down Modes
19.1.2
Module Stop Control Registers H and L (MSTPCRH, MSTPCRL)
MSTPCR performs module stop mode control.
Setting a bit to 1, the corresponding module enters module stop mode, while clearing the bit to 0
clears the module stop mode.
MSTPCRH
Bit
Bit Name
Initial Value
R/W
Module
15
ACSE
0
R/W
All-Module-Clocks-Stop Mode Enable
Enables or disables all-module-clocks-stop mode, in
which, when the CPU executes a SLEEP instruction
after module stop mode has been set for all the onchip peripheral functions controlled by MSTPCR or
the on-chip peripheral functions except the TMR.
0: All-module-clocks-stop mode disabled
1: All-module-clocks-stop mode enabled
14
MSTP14
0
R/W
—
13
MSTP13
0
R/W
—
12
MSTP12
0
R/W
Data transfer controller (DTC)
11
MSTP11
1
R/W
16-bit timer-pulse unit (TPU)
10
MSTP10
1
R/W
Programmable pulse generator (PPG)
9
MSTP9
1
R/W
D/A converter (channels 0 and 1)
8
MSTP8
1
R/W
D/A converter (channels 2 and 3)
MSTPCRL
Bit
Bit Name
Initial Value
R/W
Module
7
MSTP7
1
R/W
—
6
MSTP6
1
R/W
A/D converter
5
MSTP5
1
R/W
—
4
MSTP4
1
R/W
—
3
MSTP3
1
R/W
Serial communication interface 2 (SCI_2)
2
MSTP2
1
R/W
Serial communication interface 1 (SCI_1)
1
MSTP1
1
R/W
Serial communication interface 0 (SCI_0)
0
MSTP0
1
R/W
8-bit timer (TMR)
Rev. 3.00 Feb 22, 2006 page 548 of 624
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Section 19 Power-Down Modes
19.2
Operation
19.2.1
Clock Division Mode
When bits SCK2 to SCK0 in SCKCR are set to a value from 001 to 101, a transition is made to
clock division mode at the end of the bus cycle. In clock division mode, the CPU, bus masters, and
on-chip peripheral functions all operate on the operating clock (1/2, 1/4, 1/8, 1/16, or 1/32)
specified by bits SCK2 to SCK0.
Clock division mode is cleared by clearing all of bits SCK2 to SCK0 to 0. A transition is made to
high-speed mode at the end of the bus cycle, and clock division mode is cleared.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is cleared to 0, the chip enters
sleep mode. When sleep mode is cleared by an interrupt, clock division mode is restored.
If a SLEEP instruction is executed while the SSBY bit in SBYCR is set to 1, the chip enters
software standby mode. When software standby mode is cleared by an external interrupt, clock
division mode is restored.
When the RES pin is driven low, the reset state is entered and clock division mode is cleared. The
same applies to a reset caused by watchdog timer overflow.
When the STBY pin is driven low, a transition is made to hardware standby mode.
19.2.2
Sleep Mode
Transition to Sleep Mode: When the SLEEP instruction is executed when the SSBY bit is 0 in
SBYCR, the CPU enters the sleep mode. In sleep mode, CPU operation stops but the contents of
the CPU’s internal registers are retained. Other peripheral functions do not stop.
Exiting Sleep Mode: Sleep mode is exited by any interrupt, or signals at the RES, or STBY pins.
• Exiting Sleep Mode by Interrupts:
When an interrupt occurs, sleep mode is exited and interrupt exception processing starts. Sleep
mode is not exited if the interrupt is disabled, or interrupts other than NMI are masked by the
CPU.
• Exiting Sleep Mode by RES pin:
Setting the RES pin level low selects the reset state. After the stipulated reset input duration,
driving the RES pin high starts the CPU performing reset exception processing.
• Exiting Sleep Mode by STBY Pin:
When the STBY pin level is driven low, a transition is made to hardware standby mode.
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Section 19 Power-Down Modes
19.2.3
Software Standby Mode
Transition to Software Standby Mode: If a SLEEP instruction is executed when the SSBY bit in
SBYCR is set to 1, software standby mode is entered. In this mode, the CPU, on-chip peripheral
functions, and oscillator all stop. However, the contents of the CPU’s internal registers, RAM
data, and the states of on-chip peripheral functions other than the SCI and A/D converter, and I/O
ports, are retained. Whether the address bus and bus control signals are placed in the highimpedance state or retain the output state can be specified by the OPE bit in SBYCR.
In this mode the oscillator stops, and therefore power dissipation is significantly reduced.
Clearing Software Standby Mode: Software standby mode is cleared by an external interrupt
(NMI pin, or pins IRQ0 to IRQ7), or by means of the RES pin or STBY pin. Setting the SSI bit in
SSIER to 1 enables IRQ0 to IRQ7 to be used as software standby mode clearing sources.
• Clearing with an Interrupt
When an NMI or IRQ0 to IRQ7 interrupt request signal is input, clock oscillation starts, and
after the elapse of the time set in bits STS2 to STS0 in SBYCR, stable clocks are supplied to
the entire LSI, software standby mode is cleared, and interrupt exception handling is started.
When clearing software standby mode with an IRQ0 to IRQ7 interrupt, set the corresponding
enable bit to 1 and ensure that no interrupt with a higher priority than interrupts IRQ0 to IRQ7
is generated. Software standby mode cannot be cleared if the interrupt has been masked on the
CPU side or has been designated as a DTC activation source.
• Clearing with the RES Pin
When the RES pin is driven low, clock oscillation is started. At the same time as clock
oscillation starts, clocks are supplied to the entire LSI. Note that the RES pin must be held low
until clock oscillation stabilizes. When the RES pin goes high, the CPU begins reset exception
handling.
• Clearing with the STBY Pin
When the STBY pin is driven low, a transition is made to hardware standby mode.
Setting Oscillation Stabilization Time after Clearing Software Standby Mode: Bits STS3 to
STS0 in SBYCR should be set as described below.
• Using a Crystal Oscillator
Set bits STS3 to STS0 so that the standby time is more than the oscillation stabilization time.
Table 19.2 shows the standby times for operating frequencies and settings of bits STS3 to
STS0.
• Using an External Clock
A PLL circuit stabilization time is necessary. Refer to table 19.2 to set the wait time.
Rev. 3.00 Feb 22, 2006 page 550 of 624
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Section 19 Power-Down Modes
Table 19.2 Oscillation Stabilization Time Settings
φ* [MHz]
STS3
STS2
STS1
STS0
Standby
Time
0
0
0
0
Reserved
—
—
—
—
—
—
1
Reserved
—
—
—
—
—
—
0
Reserved
—
—
—
—
—
—
1
Reserved
—
—
—
—
—
—
0
Reserved
—
—
—
—
—
—
1
64
1.9
2.6
3.2
4.9
6.4
8.0
0
512
15.5
20.5
25.6
39.4
51.2
64.0
1
1024
31.0
41.0
51.2
78.8
102.4
128.0
0
2048
62.1
81.9
102.4
157.5
204.8
256.0
1
4096
0.12
0.16
0.20
0.32
0.41
0.51
0
16384
0.50
0.66
0.82
1.26
1.64
2.05
1
32765
0.99
1.31
1.64
2.52
3.28
4.10
0
65536
1.99
2.62
3.28
5.04
6.55
8.19
1
131072
3.97
5.24
6.55
10.08
13.11
16.38
0
262144
7.94
10.49
13.11
20.16
26.21
32.77
1
524288
15.89
20.97
26.21
40.33
52.43
65.54
1
1
0
1
1
0
0
1
1
0
1
33
25
20
13
10
8
Unit
µs
ms
: Recommended time setting
Note: * φ is the frequency divider output.
Software Standby Mode Application Example: Figure 19.2 shows an example in which a
transition is made to software standby mode at the falling edge on the NMI pin, and software
standby mode is cleared at the rising edge on the NMI pin.
In this example, an NMI interrupt is accepted with the NMIEG bit in INTCR cleared to 0 (falling
edge specification), then the NMIEG bit is set to 1 (rising edge specification), the SSBY bit is set
to 1, and a SLEEP instruction is executed, causing a transition to software standby mode.
Software standby mode is then cleared at the rising edge on the NMI pin.
Rev. 3.00 Feb 22, 2006 page 551 of 624
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Section 19 Power-Down Modes
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception
handling
NMIEG=1
SSBY=1
Software standby mode
(power-down mode)
Oscillation
stabilization
time tOSC2
NMI exception
handling
SLEEP instruction
Figure 19.2 Software Standby Mode Application Example
19.2.4
Hardware Standby Mode
Transition to Hardware Standby Mode: When the STBY pin is driven low, a transition is made
to hardware standby mode from any mode.
In hardware standby mode, all functions enter the reset state and stop operation, resulting in a
significant reduction in power dissipation. As long as the prescribed voltage is supplied, on-chip
RAM data is retained. I/O ports are set to the high-impedance state.
In order to retain on-chip RAM data, the RAME bit in SYSCR should be cleared to 0 before
driving the STBY pin low. Do not change the state of the mode pins (MD2 to MD0) while this
LSI is in hardware standby mode.
Clearing Hardware Standby Mode: Hardware standby mode is cleared by means of the STBY
pin and the RES pin. When the STBY pin is driven high while the RES pin is low, the reset state is
set and clock oscillation is started. Ensure that the RES pin is held low until the clock oscillator
stabilizes (for details on the oscillation stabilization time, refer to table 19.2). When the RES pin is
Rev. 3.00 Feb 22, 2006 page 552 of 624
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Section 19 Power-Down Modes
subsequently driven high, a transition is made to the program execution state via the reset
exception handling state.
Hardware Standby Mode Timing: Figure 19.3 shows an example of hardware standby mode
timing.
When the STBY pin is driven low after the RES pin has been driven low, a transition is made to
hardware standby mode. Hardware standby mode is cleared by driving the STBY pin high, waiting
for the oscillation stabilization time, then changing the RES pin from low to high.
Oscillator
RES
STBY
Oscillation
stabilization
time
Reset
exception
handling
Figure 19.3 Hardware Standby Mode Timing
19.2.5
Module Stop Mode
Module stop mode can be set for individual on-chip peripheral modules.
When the corresponding MSTP bit in MSTPCR is set to 1, module operation stops at the end of
the bus cycle and a transition is made to module stop mode. The CPU continues operating
independently.
When the corresponding MSTP bit is cleared to 0, module stop mode is cleared and the module
starts operating at the end of the bus cycle. In module stop mode, the internal states of modules
other than the SCI are retained.
After reset clearance, all modules other than the DTC are in module stop mode.
The module registers which are set in module stop mode cannot be read or written to.
Rev. 3.00 Feb 22, 2006 page 553 of 624
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Section 19 Power-Down Modes
19.2.6
All-Module-Clocks-Stop Mode
When the ACSE bit in MSTPCRH is set to 1 and module stop mode is set for all the on-chip
peripheral functions controlled by MSTPCR (MSTPCR = H'FFFF), or for all the on-chip
peripheral functions except the 8-bit timer (MSTPCR = H'FFFE), executing a SLEEP instruction
while the SSBY bit in SBYCR is cleared to 0 will cause all the on-chip peripheral functions
(except the 8-bit timer and watchdog timer), the bus controller, and the I/O ports to stop operating,
and a transition to be made to all-module-clocks-stop mode, at the end of the bus cycle.
Operation or halting of the 8-bit timer can be selected by means of the MSTP0 bit.
All-module-clocks-stop mode is cleared by an external interrupt (NMI, IRQ0 to IRQ7 pins), RES
pin input, or an internal interrupt (8-bit timer, watchdog timer), and the CPU returns to the normal
program execution state via the exception handling state. All-module-clocks-stop mode is not
cleared if interrupts are disabled, if interrupts other than NMI are masked by the CPU, or if the
relevant interrupt is designated as a DTC activation source.
When the STBY pin is driven low, a transition is made to hardware standby mode.
φ Clock Output Control
19.3
Output of the φ clock can be controlled by means of the PSTOP bit in SCKCR, and DDR for the
corresponding port. When the PSTOP bit is set to 1, the φ clock stops at the end of the bus cycle,
and φ output goes high. φ clock output is enabled when the PSTOP bit is cleared to 0. When DDR
for the corresponding port is cleared to 0, φ clock output is disabled and input port mode is set.
Table 19.3 shows the state of the φ pin in each processing state.
Table 19.3 φ Pin State in Each Processing State
Register Setting
All-ModuleClocks-Stop
Mode
DDR
PSTOP
Normal
Operating
State
0
X
High impedance High impedance High impedance High impedance High impedance
1
0
φ output
φ output
Fixed high
High impedance φ output
1
1
Fixed high
Fixed high
Fixed high
High impedance Fixed high
Sleep Mode
Rev. 3.00 Feb 22, 2006 page 554 of 624
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Software
Standby Mode
Hardware
Standby Mode
Section 19 Power-Down Modes
19.4
Usage Notes
19.4.1
I/O Port Status
In software standby mode, I/O port states are retained. Therefore, there is no reduction in current
dissipation for the output current when a high-level signal is output.
19.4.2
Current Dissipation during Oscillation Stabilization Standby Period
Current dissipation increases during the oscillation stabilization standby period.
19.4.3
DTC Module Stop
Depending on the operating status of the DTC, the MSTP14 to MSTP12 bits may not be set to 1.
Setting of the DTC module stop mode should be carried out only when the respective module is
not activated.
For details, refer to section 7, Data Transfer Controller (DTC).
19.4.4
On-Chip Peripheral Module Interrupts
Relevant interrupt operations cannot be performed in module stop mode. Consequently, if module
stop mode is entered when an interrupt has been requested, it will not be possible to clear the CPU
interrupt source or the DTC activation source.
Interrupts should therefore be disabled before entering module stop mode.
19.4.5
Writing to MSTPCR
MSTPCR should only be written to by the CPU.
Rev. 3.00 Feb 22, 2006 page 555 of 624
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Section 19 Power-Down Modes
Rev. 3.00 Feb 22, 2006 page 556 of 624
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Section 20 List of Registers
Section 20 List of Registers
The address list gives information on the on-chip I/O register addresses, how the register bits are
configured, and the register states in each operating mode. The information is given as shown
below.
1. Register addresses (address order)
• Registers are listed from the lower allocation addresses.
• Registers are classified by functional modules.
• Reserved addresses are indicated by — in the register name column.
Do not access the reserved addresses.
• For 16-bit and 32-bit addresses, the MSB address is shown in the table.
• The access size is indicated.
2. Register bits
• Bit configurations of the registers are described in the same order as the register addresses.
• Reserved bits are indicated by  in the bit name column.
• No entry in the bit-name column indicates that the whole register is allocated as a counter or
for holding data.
• For 16-bit and 32-bit registers, the bits are aligned from the MSB.
3. Register states in each operating mode
• Register states are described in the same order as the register addresses.
• The register states described here are for the basic operating modes. If there is a specific reset
for an on-chip peripheral module, refer to the section on that on-chip peripheral module.
Rev. 3.00 Feb 22, 2006 page 557 of 624
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Section 20 List of Registers
20.1
Register Addresses (Address Order)
The data bus width indicates the numbers of bits by which the register is accessed.
The number of access states indicates the number of states based on the specified reference clock.
Register Name
Abbreviation
DTC mode register A
DTC source address register
Access
States
Address
MRA
8
2
24
H'BC00 to DTC
H'BFFF
DTC
16/32
SAR
16/32
2
DTC mode register B
MRB
8
DTC
16/32
2
DTC destination address register
DAR
24
DTC
16/32
2
DTC transfer count register A
CRA
16
DTC
16/32
2
DTC transfer count register B
CRB
16
DTC
16/32
2
Serial expansion mode register
SEMR
8
H'FDA8
SCI_2
8
2
Interrupt priority register A
IPRA
16
H'FE00
INT
16
2
Interrupt priority register B
IPRB
16
H'FE02
INT
16
2
Interrupt priority register C
IPRC
16
H'FE04
INT
16
2
Interrupt priority register D
IPRD
16
H'FE06
INT
16
2
Interrupt priority register E
IPRE
16
H'FE08
INT
16
2
Interrupt priority register F
IPRF
16
H'FE0A
INT
16
2
Interrupt priority register G
IPRG
16
H'FE0C
INT
16
2
Interrupt priority register H
IPRH
16
H'FE0E
INT
16
2
Interrupt priority register I
IPRI
16
H'FE10
INT
16
2
Interrupt priority register J
IPRJ
16
H'FE12
INT
16
2
Interrupt priority register K
IPRK
16
H'FE14
INT
16
2
IRQ pin select register
ITSR
16
H'FE16
INT
16
2
Software standby release IRQ enable
register
SSIER
16
H'FE18
INT
16
2
IRQ sense control register
ISCR
16
H'FE1C
INT
16
2
IrDA control register_0
IrCR_0
8
H'FE1E
IrDA_0
8
2
Port 1 data direction register
P1DDR
8
H'FE20
PORT
8
2
Port 2 data direction register
P2DDR
8
H'FE21
PORT
8
2
Port 3 data direction register
P3DDR
8
H'FE22
PORT
8
2
Port 5 data direction register
P5DDR
8
H'FE24
PORT
8
2
Rev. 3.00 Feb 22, 2006 page 558 of 624
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Module
Data
Width
Bit No.
Section 20 List of Registers
Register Name
Abbreviation
Bit No.
Address
Module
Data
Width
Access
States
Port 6 data direction register
P6DDR
8
H'FE25
PORT
8
2
Port 7 data direction register
P7DDR
8
H'FE26
PORT
8
2
Port 8 data direction register
P8DDR
8
H'FE27
PORT
8
2
Port A data direction register
PADDR
8
H'FE29
PORT
8
2
Port B data direction register
PBDDR
8
H'FE2A
PORT
8
2
Port C data direction register
PCDDR
8
H'FE2B
PORT
8
2
Port D data direction register
PDDDR
8
H'FE2C
PORT
8
2
Port E data direction register
PEDDR
8
H'FE2D
PORT
8
2
Port F data direction register
PFDDR
8
H'FE2E
PORT
8
2
Port G data direction register
PGDDR
8
H'FE2F
PORT
8
2
Port function control register 0
PFCR0
8
H'FE32
PORT
8
2
Port function control register 1
PFCR1
8
H'FE33
PORT
8
2
Port function control register 2
PFCR2
8
H'FE34
PORT
8
2
Port A MOS pull-up control register
PAPCR
8
H'FE36
PORT
8
2
Port B MOS pull-up control register
PBPCR
8
H'FE37
PORT
8
2
Port C MOS pull-up control register
PCPCR
8
H'FE38
PORT
8
2
Port D MOS pull-up control register
PDPCR
8
H'FE39
PORT
8
2
Port E MOS pull-up control register
PEPCR
8
H'FE3A
PORT
8
2
Port 3 open drain control register
P3ODR
8
H'FE3C
PORT
8
2
Port A open drain control register
PAODR
8
H'FE3D
PORT
8
2
Timer control register_3
TCR_3
8
H'FE80
TPU_3
16
2
Timer mode register_3
TMDR_3
8
H'FE81
TPU_3
16
2
Timer I/O control register H_3
TIORH_3
8
H'FE82
TPU_3
16
2
Timer I/O control register L_3
TIORL_3
8
H'FE83
TPU_3
16
2
Timer interrupt enable register_3
TIER_3
8
H'FE84
TPU_3
16
2
Timer status register_3
TSR_3
8
H'FE85
TPU_3
16
2
Timer counter_3
TCNT_3
16
H'FE86
TPU_3
16
2
Timer general register A_3
TGRA_3
16
H'FE88
TPU_3
16
2
Timer general register B_3
TGRB_3
16
H'FE8A
TPU_3
16
2
Timer general register C_3
TGRC_3
16
H'FE8C
TPU_3
16
2
Timer general register D_3
TGRD_3
16
H'FE8E
TPU_3
16
2
Rev. 3.00 Feb 22, 2006 page 559 of 624
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Section 20 List of Registers
Register Name
Abbreviation
Bit No.
Address
Module
Data
Width
Access
States
Timer control register_4
TCR_4
8
H'FE90
TPU_4
16
2
Timer mode register_4
TMDR_4
8
H'FE91
TPU_4
16
2
Timer I/O control register_4
TIOR_4
8
H'FE92
TPU_4
16
2
Timer interrupt enable register_4
TIER_4
8
H'FE94
TPU_4
16
2
Timer status register_4
TSR_4
8
H'FE95
TPU_4
16
2
Timer counter_4
TCNT_4
16
H'FE96
TPU_4
16
2
Timer general register A_4
TGRA_4
16
H'FE98
TPU_4
16
2
Timer general register B_4
TGRB_4
16
H'FE9A
TPU_4
16
2
Timer control register_5
TCR_5
8
H'FEA0
TPU_5
16
2
Timer mode register_5
TMDR_5
8
H'FEA1
TPU_5
16
2
Timer I/O control register_5
TIOR_5
8
H'FEA2
TPU_5
16
2
Timer interrupt enable register_5
TIER_5
8
H'FEA4
TPU_5
16
2
Timer status register_5
TSR_5
8
H'FEA5
TPU_5
16
2
Timer counter_5
TCNT_5
16
H'FEA6
TPU_5
16
2
Timer general register A_5
TGRA_5
16
H'FEA8
TPU_5
16
2
Timer general register B_5
TGRB_5
16
H'FEAA
TPU_5
16
2
Bus width control register
ABWCR
8
H'FEC0
BSC
16
2
Access state control register
ASTCR
8
H'FEC1
BSC
16
2
Wait control register AH
WTCRAH
8
H'FEC2
BSC
16
2
Wait control register AL
WTCRAL
8
H'FEC3
BSC
16
2
Wait control register BH
WTCRBH
8
H'FEC4
BSC
16
2
Wait control register BL
WTCRBL
8
H'FEC5
BSC
16
2
Read strobe timing control register
RDNCR
8
H'FEC6
BSC
16
2
Chip select assertion period control
registers H
CSACRH
8
H'FEC8
BSC
16
2
Chip select assertion period control
register L
CSACRL
8
H'FEC9
BSC
16
2
Bus control register
BCR
16
H'FECC
BSC
16
2
RAMER
8
H'FECE
FLASH
16
2
DTC enable register A
DTCERA
8
H'FF28
DTC
16
2
DTC enable register B
DTCERB
8
H'FF29
DTC
16
2
DTC enable register C
DTCERC
8
H'FF2A
DTC
16
2
RAM emulation register*
1
Rev. 3.00 Feb 22, 2006 page 560 of 624
REJ09B0281-0300
Section 20 List of Registers
Register Name
Abbreviation
Bit No.
Address
Module
Data
Width
Access
States
DTC enable register D
DTCERD
8
H'FF2B
DTC
16
2
DTC enable register E
DTCERE
8
H'FF2C
DTC
16
2
DTC enable register F
DTCERF
8
H'FF2D
DTC
16
2
DTC enable register G
DTCERG
8
H'FF2E
DTC
16
2
DTC vector register
DTVECR
8
H'FF30
DTC
16
2
Interrupt control register
INTCR
8
H'FF31
INT
16
2
IRQ enable register
IER
16
H'FF32
INT
16
2
IRQ status register
ISR
16
H'FF34
INT
16
2
Standby control register
SBYCR
8
H'FF3A
SYSTEM
8
2
System clock control register
SCKCR
8
H'FF3B
SYSTEM
8
2
System control register
SYSCR
8
H'FF3D
SYSTEM
8
2
Mode control register
MDCR
8
H'FF3E
SYSTEM
8
2
Module stop control register H
MSTPCRH
8
H'FF40
SYSTEM
8
2
Module stop control register L
MSTPCRL
8
H'FF41
SYSTEM
8
2
PLL control register
PLLCR
8
H'FF45
SYSTEM
8
2
PPG output control register
PCR
8
H'FF46
PPG
8
2
PPG output mode register
PMR
8
H'FF47
PPG
8
2
Next data enable register H
NDERH
8
H'FF48
PPG
8
2
Next data enable register L
NDERL
8
H'FF49
PPG
8
2
Output data register H
PODRH
8
H'FF4A
PPG
8
2
Output data register L
PODRL
8
H'FF4B
PPG
8
2
Next data register H*
NDRH
8
H'FF4C
PPG
8
2
Next data register L*
2
2
NDRL
8
H'FF4D
PPG
8
2
Next data register H*2
NDRH
8
H'FF4E
PPG
8
2
Next data register L*2
NDRL
8
H'FF4F
PPG
8
2
Port 1 register
PORT1
8
H'FF50
PORT
8
2
Port 2 register
PORT2
8
H'FF51
PORT
8
2
Port 3 register
PORT3
8
H'FF52
PORT
8
2
Port 4 register
PORT4
8
H'FF53
PORT
8
2
Port 5 register
PORT5
8
H'FF54
PORT
8
2
Port 6 register
PORT6
8
H'FF55
PORT
8
2
Rev. 3.00 Feb 22, 2006 page 561 of 624
REJ09B0281-0300
Section 20 List of Registers
Register Name
Abbreviation
Bit No.
Address
Module
Data
Width
Access
States
Port 7 register
PORT7
8
H'FF56
PORT
8
2
Port 8 register
PORT8
8
H'FF57
PORT
8
2
Port A register
PORTA
8
H'FF59
PORT
8
2
Port B register
PORTB
8
H'FF5A
PORT
8
2
Port C register
PORTC
8
H'FF5B
PORT
8
2
Port D register
PORTD
8
H'FF5C
PORT
8
2
Port E register
PORTE
8
H'FF5D
PORT
8
2
Port F register
PORTF
8
H'FF5E
PORT
8
2
Port G register
PORTG
8
H'FF5F
PORT
8
2
Port 1 data register
P1DR
8
H'FF60
PORT
8
2
Port 2 data register
P2DR
8
H'FF61
PORT
8
2
Port 3 data register
P3DR
8
H'FF62
PORT
8
2
Port 5 data register
P5DR
8
H'FF64
PORT
8
2
Port 6 data register
P6DR
8
H'FF65
PORT
8
2
Port 7 data register
P7DR
8
H'FF66
PORT
8
2
Port 8 data register
P8DR
8
H'FF67
PORT
8
2
Port A data register
PADR
8
H'FF69
PORT
8
2
Port B data register
PBDR
8
H'FF6A
PORT
8
2
Port C data register
PCDR
8
H'FF6B
PORT
8
2
Port D data register
PDDR
8
H'FF6C
PORT
8
2
Port E data register
PEDR
8
H'FF6D
PORT
8
2
Port F data register
PFDR
8
H'FF6E
PORT
8
2
Port G data register
PGDR
8
H'FF6F
PORT
8
2
Port H register
PORTH
8
H'FF70
PORT
8
2
Port H data register
PHDR
8
H'FF72
PORT
8
2
Port H data direction register
PHDDR
8
H'FF74
PORT
8
2
Serial mode register_0
SMR_0
8
H'FF78
SCI_0
8
2
Bit rate register_0
BRR_0
8
H'FF79
SCI_0
8
2
Serial control register_0
SCR_0
8
H'FF7A
SCI_0
8
2
Transmit data register_0
TDR_0
8
H'FF7B
SCI_0
8
2
Serial status register_0
SSR_0
8
H'FF7C
SCI_0
8
2
Rev. 3.00 Feb 22, 2006 page 562 of 624
REJ09B0281-0300
Section 20 List of Registers
Register Name
Abbreviation
Bit No.
Address
Module
Data
Width
Access
States
Receive data register_0
RDR_0
8
H'FF7D
SCI_0
8
2
Smart card mode register_0
SCMR_0
8
H'FF7E
SCI_0
8
2
Serial mode register_1
SMR_1
8
H'FF80
SCI_1
8
2
Bit rate register_1
BRR_1
8
H'FF81
SCI_1
8
2
Serial control register_1
SCR_1
8
H'FF82
SCI_1
8
2
Transmit data register_1
TDR_1
8
H'FF83
SCI_1
8
2
Serial status register_1
SSR_1
8
H'FF84
SCI_1
8
2
Receive data register_1
RDR_1
8
H'FF85
SCI_1
8
2
Smart card mode register_1
SCMR_1
8
H'FF86
SCI_1
8
2
Serial mode register_2
SMR_2
8
H'FF88
SCI_2
8
2
Bit rate register_2
BRR_2
8
H'FF89
SCI_2
8
2
Serial control register_2
SCR_2
8
H'FF8A
SCI_2
8
2
Transmit data register_2
TDR_2
8
H'FF8B
SCI_2
8
2
Serial status register_2
SSR_2
8
H'FF8C
SCI_2
8
2
Receive data register_2
RDR_2
8
H'FF8D
SCI_2
8
2
Smart card mode register_2
SCMR_2
8
H'FF8E
SCI_2
8
2
A/D data register A
ADDRA
16
H'FF90
A/D
16
2
A/D data register B
ADDRB
16
H'FF92
A/D
16
2
A/D data register C
ADDRC
16
H'FF94
A/D
16
2
A/D data register D
ADDRD
16
H'FF96
A/D
16
2
A/D data register E
ADDRE
16
H'FF98
A/D
16
2
A/D data register F
ADDRF
16
H'FF9A
A/D
16
2
A/D data register G
ADDRG
16
H'FF9C
A/D
16
2
A/D data register H
ADDRH
16
H'FF9E
A/D
16
2
A/D control/status register
ADCSR
8
H'FFA0
A/D
16
2
A/D control register
ADCR
8
H'FFA1
A/D
16
2
D/A data register 0
DADR0
8
H'FFA4
D/A
8
2
D/A data register 1
DADR1
8
H'FFA5
D/A
8
2
D/A control register 01
DACR01
8
H'FFA6
D/A
8
2
D/A data register 2
DADR2
8
H'FFA8
D/A
8
2
D/A data register 3
DADR3
8
H'FFA9
D/A
8
2
Rev. 3.00 Feb 22, 2006 page 563 of 624
REJ09B0281-0300
Section 20 List of Registers
Register Name
Abbreviation
Bit No.
Address
Module
Data
Width
Access
States
D/A control register 23
DACR23
8
H'FFAA
D/A
8
2
Timer control register 0
TCR_0
8
H'FFB0
TMR_0
16
2
Timer control register 1
TCR_1
8
H'FFB1
TMR_1
16
2
Timer control/status register 0
TCSR_0
8
H'FFB2
TMR_0
16
2
Timer control/status register 1
TCSR_1
8
H'FFB3
TMR_1
16
2
Time constant register A0
TCORA_0
8
H'FFB4
TMR_0
16
2
Time constant register A1
TCORA_1
8
H'FFB5
TMR_1
16
2
Time constant register B0
TCORB_0
8
H'FFB6
TMR_0
16
2
Time constant register B1
TCORB_1
8
H'FFB7
TMR_1
16
2
Timer counter 0
TCNT_0
8
H'FFB8
TMR_0
16
2
Timer counter 1
TCNT_1
8
H'FFB9
TMR_1
16
2
Timer control/status register
TCSR
8
H'FFBC*3 WDT
(Write)
16
2
16
2
16
2
H'FFBC
(Read)
Timer counter
TCNT
8
H'FFBC*3 WDT
(Write)
H'FFBD
(Read)
Reset control/status register
RSTCSR
8
H'FFBE*3 WDT
(Write)
H'FFBF
(Read)
Timer start register
TSTR
8
H'FFC0
TPU
16
2
Timer synchronous register
TSYR
8
H'FFC1
TPU
16
2
Flash memory control register 1*1
FLMCR1
8
H'FFC8
FLASH
8
2
Flash memory control register 2*1
FLMCR2
8
H'FFC9
FLASH
8
2
Erase block register 1*1
EBR1
8
H'FFCA
FLASH
8
2
Erase block register 2*1
EBR2
8
H'FFCB
FLASH
8
2
Timer control register_0
TCR_0
8
H'FFD0
TPU_0
16
2
Timer mode register_0
TMDR_0
8
H'FFD1
TPU_0
16
2
Timer I/O control register H_0
TIORH_0
8
H'FFD2
TPU_0
16
2
Timer I/O control register L_0
TIORL_0
8
H'FFD3
TPU_0
16
2
Rev. 3.00 Feb 22, 2006 page 564 of 624
REJ09B0281-0300
Section 20 List of Registers
Register Name
Abbreviation
Bit No.
Address
Module
Data
Width
Access
States
Timer interrupt enable register_0
TIER_0
8
H'FFD4
TPU_0
16
2
Timer status register_0
TSR_0
8
H'FFD5
TPU_0
16
2
Timer counter_0
TCNT_0
16
H'FFD6
TPU_0
16
2
Timer general register A_0
TGRA_0
16
H'FFD8
TPU_0
16
2
Timer general register B_0
TGRB_0
16
H'FFDA
TPU_0
16
2
Timer general register C_0
TGRC_0
16
H'FFDC
TPU_0
16
2
Timer general register D_0
TGRD_0
16
H'FFDE
TPU_0
16
2
Timer control register_1
TCR_1
8
H'FFE0
TPU_1
16
2
Timer mode register_1
TMDR_1
8
H'FFE1
TPU_1
16
2
Timer I/O control register_1
TIOR_1
8
H'FFE2
TPU_1
16
2
Timer interrupt enable register_1
TIER_1
8
H'FFE4
TPU_1
16
2
Timer status register_1
TSR_1
8
H'FFE5
TPU_1
16
2
Timer counter_1
TCNT_1
16
H'FFE6
TPU_1
16
2
Timer general register A_1
TGRA_1
16
H'FFE8
TPU_1
16
2
Timer general register B_1
TGRB_1
16
H'FFEA
TPU_1
16
2
Timer control register_2
TCR_2
8
H'FFF0
TPU_2
16
2
Timer mode register_2
TMDR_2
8
H'FFF1
TPU_2
16
2
Timer I/O control register_2
TIOR_2
8
H'FFF2
TPU_2
16
2
Timer interrupt enable register_2
TIER_2
8
H'FFF4
TPU_2
16
2
Timer status rgister_2
TSR_2
8
H'FFF5
TPU_2
16
2
Timer counter_2
TCNT_2
16
H'FFF6
TPU_2
16
2
Timer general register A_2
TGRA_2
16
H'FFF8
TPU_2
16
2
Timer general register B_2
TGRB_2
16
H'FFFA
TPU_2
16
2
Notes: 1. Register of the flash memory version. Not available in the masked ROM version and
ROM-less version.
2. If the pulse output group 2 and pulse output group 3 output triggers are the same
according to the PCR setting, the NDRH address will be H'FF4C, and if different, the
address of NDRH for group 2 will be H'FF4E, and that for group 3 will be H'FF4C.
Similarly, if the pulse output group 0 and pulse output group 1 output triggers are the
same according to the PCR setting, the NDRL address will be H'FF4D, and if different,
the address of NDRL for group 0 will be H'FF4F, and that for group 1 will be H'FF4D.
3. For writing, refer to section 12.6.1, Notes on register access.
Rev. 3.00 Feb 22, 2006 page 565 of 624
REJ09B0281-0300
Section 20 List of Registers
20.2
Register Bits
Register bit names of the on-chip peripheral modules are described below.
Each line covers eight bits, and 16- or 32-bit registers are shown as 2 or 4 lines.
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
MRA
SM1
SM0
DM1
DM0
MD1
MD0
DTS
Sz
DTC*7
SAR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
MRB
CHNE
DISEL
CHNS
—
—
—
—
—
DAR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRA
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
CRB
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
SEMR*7
—
—
—
—
ABCS
ACS2
ACS1
ACS0
SCI_2
Smart card
interface 2
IPRA
—
IPRA14
IPRA13
IPRA12
—
IPRA10
IPRA9
IPRA8
INT
—
IPRA6
IPRA5
IPRA4
—
IPRA2
IPRA1
IPRA0
IPRB
—
IPRB14
IPRB13
IPRB12
—
IPRB10
IPRB9
IPRB8
—
IPRB6
IPRB5
IPRB4
—
IPRB2
IPRB1
IPRB0
IPRC
—
IPRC14
IPRC13
IPRC12
—
IPRC10
IPRC9
IPRC8
—
IPRC6
IPRC5
IPRC4
—
IPRC2
IPRC1
IPRC0
—
IPRD14
IPRD13
IPRD12
—
IPRD10
IPRD9
IPRD8
—
IPRD6
IPRD5
IPRD4
—
IPRD2
IPRD1
IPRD0
—
IPRE14
IPRE13
IPRE12
—
IPRE10
IPRE9
IPRE8
—
IPRE6
IPRE5
IPRE4
—
IPRE2
IPRE1
IPRE0
IPRF
—
IPRF14
IPRF13
IPRF12
—
IPRF10
IPRF9
IPRF8
—
IPRF6
IPRF5
IPRF4
—
IPRF2
IPRF1
IPRF0
IPRG
—
IPRG14
IPRG13
IPRG12
—
IPRG10
IPRG9
IPRG8
—
IPRG6
IPRG5
IPRG4
—
IPRG2
IPRG1
IPRG0
IPRD
IPRE
Rev. 3.00 Feb 22, 2006 page 566 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
IPRH
—
IPRH14
IPRH13
IPRH12
—
IPRH10
IPRH9
IPRH8
INT
—
IPRH6
IPRH5
IPRH4
—
IPRH2
IPRH1
IPRH0
—
IPRI14
IPRI13
IPRI12
—
IPRI10
IPRI9
IPRI8
—
IPRI6
IPRI5
IPRI4
—
IPRI2
IPRI1
IPRI0
—
IPRJ14
IPRJ13
IPRJ12
—
IPRJ10
IPRJ9
IPRJ8
—
IPRJ6
IPRJ5
IPRJ4
—
IPRJ2
IPRJ1
IPRJ0
—
IPRK14
IPRK13
IPRK12
—
IPRK10
IPRK9
IPRK8
—
IPRK6
IPRK5
IPRK4
—
IPRK2
IPRK1
IPRK0
—
—
—
—
—
—
—
—
ITS7
ITS6
ITS5
ITS4
ITS3
ITS2
ITS1
ITS0
—
—
—
—
—
—
—
—
SSI7
SSI6
SSI5
SSI4
SSI3
SSI2
SSI1
SSI0
IRQ7SCB
IRQ7SCA
IRQ6SCB
IRQ6SCA
IRQ5SCB
IRQ5SCA
IRQ4SCB
IRQ4SCA
IRQ3SCB
IRQ3SCA
IRQ2SCB
IRQ2SCA
IRQ1SCB
IRQ1SCA
IRQ0SCB
IRQ0SCA
IrCR_0
IrE
IrCKS2
IrCKS1
IrCKS0
—
—
—
—
IrDA_0
P1DDR
P17DDR
P16DDR
P15DDR
P14DDR
P13DDR
P12DDR
P11DDR
P10DDR
PORT
P2DDR
P27DDR
P26DDR
P25DDR
P24DDR
P23DDR
P22DDR
P21DDR
P20DDR
P3DDR
—
—
P35DDR
P34DDR
P33DDR
P32DDR
P31DDR
P30DDR
P5DDR
—
—
—
—
P53DDR
P52DDR
P51DDR
P50DDR
P6DDR
—
—
P65DDR
P64DDR
P63DDR
P62DDR
P61DDR
P60DDR
P7DDR
—
—
P75DDR
P74DDR
P73DDR
P72DDR
P71DDR
P70DDR
P8DDR
—
—
P85DDR
P84DDR
P83DDR
P82DDR
P81DDR
P80DDR
PADDR
PA7DDR
PA6DDR
PA5DDR
PA4DDR
PA3DDR
PA2DDR
PA1DDR
PA0DDR
PBDDR
PB7DDR
PB6DDR
PB5DDR
PB4DDR
PB3DDR
PB2DDR
PB1DDR
PB0DDR
PCDDR
PC7DDR
PC6DDR
PC5DDR
PC4DDR
PC3DDR
PC2DDR
PC1DDR
PC0DDR
PDDDR
PD7DDR
PD6DDR
PD5DDR
PD4DDR
PD3DDR
PD2DDR
PD1DDR
PD0DDR
PEDDR
PE7DDR
PE6DDR
PE5DDR
PE4DDR
PE3DDR
PE2DDR
PE1DDR
PE0DDR
PFDDR
PF7DDR
PF6DDR
PF5DDR
PF4DDR
PF3DDR
PF2DDR
PF1DDR
PF0DDR
PGDDR
—
PG6DDR
PG5DDR
PG4DDR
PG3DDR
PG2DDR
PG1DDR
PG0DDR
PFCR0
CS7E
CS6E
CS5E
CS4E
CS3E
CS2E
CS1E
CS0E
PFCR1
A23E
A22E
A21E
A20E
A19E
A18E
A17E
A16E
IPRI
IPRJ
IPRK
ITSR
SSIER
ISCR
Rev. 3.00 Feb 22, 2006 page 567 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PFCR2
—
—
—
—
ASOE
LWROE
—
—
PORT
PAPCR
PA7PCR
PA6PCR
PA5PCR
PA4PCR
PA3PCR
PA2PCR
PA1PCR
PA0PCR
PBPCR
PB7PCR
PB6PCR
PB5PCR
PB4PCR
PB3PCR
PB2PCR
PB1PCR
PB0PCR
PCPCR
PC7PCR
PC6PCR
PC5PCR
PC4PCR
PC3PCR
PC2PCR
PC1PCR
PC0PCR
PDPCR
PD7PCR
PD6PCR
PD5PCR
PD4PCR
PD3PCR
PD2PCR
PD1PCR
PD0PCR
PEPCR
PE7PCR
PE6PCR
PE5PCR
PE4PCR
PE3PCR
PE2PCR
PE1PCR
PE0PCR
P3ODR
—
—
P35ODR
P34ODR
P33ODR
P32ODR
P31ODR
P30ODR
PAODR
PA7ODR
PA6ODR
PA5ODR
PA4ODR
PA3ODR
PA2ODR
PA1ODR
PA0ODR
TCR_3
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_3
—
—
BFB
BFA
MD3
MD2
MD1
MD0
TIORH_3
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIORL_3
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
TIER_3
TTGE
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_3
—
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
TCNT_3
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCR_4
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_4
—
—
—
—
MD3
MD2
MD1
MD0
TGRA_3
TGRB_3
TGRC_3
TGRD_3
TIOR_4
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_4
TTGE
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
TSR_4
TCFD
—
TCFU
TCFV
—
—
TGFB
TGFA
TCNT_4
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Rev. 3.00 Feb 22, 2006 page 568 of 624
REJ09B0281-0300
TPU_3
TPU_4
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TGRA_4
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TPU_4
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCR_5
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_5
—
—
—
—
MD3
MD2
MD1
MD0
TIOR_5
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_5
TTGE
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
TSR_5
TCFD
—
TCFU
TCFV
—
—
TGFB
TGFA
TCNT_5
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRA_5
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ABWCR
ABW7
ABW6
ABW5
ABW4
ABW3
ABW2
ABW1
ABW0
ASTCR
AST7
AST6
AST5
AST4
AST3
AST2
AST1
AST0
WTCRAH
—
W72
W71
W70
—
W62
W61
W60
WTCRAL
—
W52
W51
W50
—
W42
W41
W40
WTCRBH
—
W32
W31
W30
—
W22
W21
W20
WTCRBL
—
W12
W11
W10
—
W02
W01
W00
RDNCR
RDN7
RDN6
RDN5
RDN4
RDN3
RDN2
RDN1
RDN0
CSACRH
CSXH7
CSXH6
CSXH5
CSXH4
CSXH3
CSXH2
CSXH1
CSXH0
CSACRL
CSXT7
CSXT6
CSXT5
CSXT4
CSXT3
CSXT2
CSXT1
CSXT0
BCR
BRLE
BREQ0E
—
IDLC
ICIS1
ICIS0
WDBE
WAITE
—
—
—
—
—
ICIS2
—
—
—
—
—
—
RAMS
RAM2
RAM1
RAM0
TGRB_4
TGRB_5
RAMER
TPU_5
BSC
FLASH
(F-ZTAT
version)
Rev. 3.00 Feb 22, 2006 page 569 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
DTCERA
DTCEA7
DTCEA6
DTCEA5
DTCEA4
DTCEA3
DTCEA2
DTCEA1
DTCEA0
DTC
DTCERB
—
—
—
—
—
—
—
—
DTCERC
—
DTCEC6
DTCEC5
DTCEC4
DTCEC3
DTCEC2
DTCEC1
DTCEC0
DTCERD
DTCED7
DTCED6
DTCED5
DTCED4
DTCED3
DTCED2
DTCED1
DTCED0
DTCERE
DTCEE7
DTCEE6
—
—
DTCEE3
DTCEE2
DTCEE1
DTCEE0
DTCERF
—
—
—
—
DTCEF3
DTCEF2
DTCEF1
DTCEF0
DTCERG
DTCEG7
DTCEG6
—
—
—
—
—
—
DTVECR
SWDTE
DTVEC6
DTVEC5
DTVEC4
DTVEC3
DTVEC2
DTVEC1
DTVEC0
INTCR
—
—
INTM1
INTM0
NMIEG
—
—
—
IER
—
—
—
—
—
—
—
—
IRQ7E
IRQ6E
IRQ5E
IRQ4E
IRQ3E
IRQ2E
IRQ1E
IRQ0E
ISR
—
—
—
—
—
—
—
—
IRQ7F
IRQ6F
IRQ5F
IRQ4F
IRQ3F
IRQ2F
IRQ1F
IRQ0F
SBYCR
SSBY
OPE
—
—
STS3
STS2
STS1
STS0
SCKCR
PSTOP
—
—
—
STCS
SCK2
SCK1
SCK0
SYSCR
—
—
MACS
—
FLSHE
—
EXPE
RAME
MDCR
—
—
—
—
—
MDS2
MDS1
MDS0
MSTPCRH
ACSE
MSTP14
MSTP13
MSTP12
MSTP11
MSTP10
MSTP9
MSTP8
MSTPCRL
MSTP7
MSTP6
MSTP5
MSTP4
MSTP3
MSTP2
MSTP1
MSTP0
PLLCR
—
—
—
—
—
—
STC1
STC0
PCR
G3CMS1
G3CMS0
G2CMS1
G2CMS0
G1CMS1
G1CMS0
G0CMS1
G0CMS0
PMR
G3INV
G2INV
G1INV
G0INV
G3NOV
G2NOV
G1NOV
G0NOV
NDERH
NDER15
NDER14
NDER13
NDER12
NDER11
NDER10
NDER9
NDER8
NDERL
NDER7
NDER6
NDER5
NDER4
NDER3
NDER2
NDER1
NDER0
PODRH
POD15
POD14
POD13
POD12
POD11
POD10
POD9
POD8
PODRL
POD7
POD6
POD5
POD4
POD3
POD2
POD1
POD0
NDRH*1
NDR15
NDR14
NDR13
NDR12
NDR11
NDR10
NDR9
NDR8
NDRL*1
NDR7
NDR6
NDR5
NDR4
NDR3
NDR2
NDR1
NDR0
NDRH*
—
—
—
—
NDR11
NDR10
NDR9
NDR8
—
—
—
—
NDR3
NDR2
NDR1
NDR0
NDRL*
1
1
Rev. 3.00 Feb 22, 2006 page 570 of 624
REJ09B0281-0300
INT
SYSTEM
PPG
PPG
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PORT1
P17
P16
P15
P14
P13
P12
P11
P10
PORT
PORT2
P27
P26
P25
P24
P23
P22
P21
P20
PORT3
—
—
P35
P34
P33
P32
P31
P30
PORT4
P47
P46
P45
P44
P43
P42
P41
P40
PORT5
P57
P56
P55
P54
P53
P52
P51
P50
PORT6
—
—
P65
P64
P63
P62
P61
P60
PORT7
—
—
P75
P74
P73
P72
P71
P70
PORT8
—
—
P85
P84
P83
P82
P81
P80
PORTA
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
PORTB
PB7
PB6
PB5
PB4
PB3
PB2
PB1
PB0
PORTC
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
PORTD
PD7
PD6
PD5
PD4
PD3
PD2
PD1
PD0
PORTE
PE7
PE6
PE5
PE4
PE3
PE2
PE1
PE0
PORTF
PF7
PF6
PF5
PF4
PF3
PF2
PF1
PF0
PORTG
—
PG6
PG5
PG4
PG3
PG2
PG1
PG0
P1DR
P17DR
P16DR
P15DR
P14DR
P13DR
P12DR
P11DR
P10DR
P2DR
P27DR
P26DR
P25DR
P24DR
P23DR
P22DR
P21DR
P20DR
P3DR
—
—
P35DR
P34DR
P33DR
P32DR
P31DR
P30DR
P5DR
—
—
—
—
P53DR
P52DR
P51DR
P50DR
P6DR
—
—
P65DR
P64DR
P63DR
P62DR
P61DR
P60DR
P7DR
—
—
P75DR
P74DR
P73DR
P72DR
P71DR
P70DR
P8DR
—
—
P85DR
P84DR
P83DR
P82DR
P81RD
P80DR
PADR
PA7DR
PA6DR
PA5DR
PA4DR
PA3DR
PA2DR
PA1DR
PA0DR
PBDR
PB7DR
PB6DR
PB5DR
PB4DR
PB3DR
PB2DR
PB1DR
PB0DR
PCDR
PC7DR
PC6DR
PC5DR
PC4DR
PC3DR
PC2DR
PC1DR
PC0DR
PDDR
PD7DR
PD6DR
PD5DR
PD4DR
PD3DR
PD2DR
PD1DR
PD0DR
PEDR
PE7DR
PE6DR
PE5DR
PE4DR
PE3DR
PE2DR
PE1DR
PE0DR
PFDR
PF7DR
PF6DR
PF5DR
PF4DR
PF3DR
PF2DR
PF1DR
PF0DR
PGDR
—
PG6DR
PG5DR
PG4DR
PG3DR
PG2DR
PG1DR
PG0DR
PORTH
—
—
—
—
PH3
PH2
PH1
PH0
Rev. 3.00 Feb 22, 2006 page 571 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
PHDR
—
—
—
—
PH3DR
PH2DR
PH1DR
PH0DR
PORT
PHDDR
—
—
—
—
PH3DDR
PH2DDR
PH1DDR
PH0DDR
SMR_0
C/A/
2
GM*
CHR/
3
BLK*
PE
O/E
STOP/
4
BCP1*
MP/
CKS1
CKS0
BRR_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCR_0
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SSR_0
TDRE
RDRF
ORER
FER/
PER
TEND
MPB
MPBT
BCP0*
5
SCI_0,
Smart card
interface_0
ERS*6
RDR_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCMR_0
—
—
—
—
SDIR
SINV
—
SMIF
SMR_1
C/A/
GM*2
CHR/
BLK*3
PE
O/E
STOP/
BCP1*4
MP/
CKS1
CKS0
BRR_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCR_1
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SSR_1
TDRE
RDRF
ORER
PER
TEND
MPB
MPBT
FER/
BCP0*5
SCI_1,
Smart card
interface_1
ERS*
6
RDR_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCMR_1
—
—
—
—
SDIR
SINV
—
SMIF
SMR_2
C/A/
2
GM*
CHR/
3
BLK*
PE
O/E
STOP/
4
BCP1*
MP/
CKS1
CKS0
BRR_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCR_2
TIE
RIE
TE
RE
MPIE
TEIE
CKE1
CKE0
TDR_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SSR_2
TDRE
RDRF
ORER
FER/
PER
TEND
MPB
MPBT
5
BCP0*
SCI_2,
Smart card
interface_2
ERS*6
RDR_2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
SCMR_2
—
—
—
—
SDIR
SINV
—
SMIF
ADDRA
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
ADDRB
Rev. 3.00 Feb 22, 2006 page 572 of 624
REJ09B0281-0300
A/D
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
ADDRC
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
A/D
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
AD9
AD8
AD7
AD6
AD5
AD4
AD3
AD2
AD1
AD0
—
—
—
—
—
—
ADCSR
ADF
ADIE
ADST
—
CH3
CH2
CH1
CH0
ADCR
TRGS1
TRGS0
SCANE
SCANS
CKS1
CH3
—
—
DADR0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DADR1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DACR01
DAOE1
DAOE0
DAE
—
—
—
—
—
DADR2
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DADR3
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
DACR23
DAOE3
DAOE2
DAE
—
—
—
—
—
TCR_0
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
TMR_0
TCR_1
CMIEB
CMIEA
OVIE
CCLR1
CCLR0
CKS2
CKS1
CKS0
TMR_1
TCSR_0
CMFB
CMFA
OVF
ADTE
OS3
OS2
OS1
OS0
TCSR_1
CMFB
CMFA
OVF
—
OS3
OS2
OS1
OS0
TCORA_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCORA_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCORB_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCORB_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCNT_0
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCNT_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
ADDRD
ADDRE
ADDRF
ADDRG
ADDRH
D/A
Rev. 3.00 Feb 22, 2006 page 573 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TCSR
OVF
WT/IT
TME
—
—
CKS2
CKS1
CKS0
WDT
TCNT
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
RSTCSR
WOVF
RSTE
—
—
—
—
—
—
TSTR
—
—
CST5
CST4
CST3
CST2
CST1
CST0
TSYR
—
—
SYNC5
SYNC4
SYNC3
SYNC2
SYNC1
SYNC0
FLMCR1
—
SWE
ESU
PSU
EV
PV
E
P
FLMCR2
FLER
—
—
—
—
—
—
—
EBR1
EB7
EB6
EB5
EB4
EB3
EB2
EB1
EB0
EBR2
—
—
EB13
EB12
EB11
EB10
EB9
EB8
TCR_0
CCLR2
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TPU
FLASH
(F-ZTAT
version )
TMDR_0
—
—
BFB
BFA
MD3
MD2
MD1
MD0
TIORH_0
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIORL_0
IOD3
IOD2
IOD1
IOD0
IOC3
IOC2
IOC1
IOC0
TIER_0
TTGE
—
—
TCIEV
TGIED
TGIEC
TGIEB
TGIEA
TSR_0
—
—
—
TCFV
TGFD
TGFC
TGFB
TGFA
TCNT_0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRA_0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRB_0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCR_1
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_1
—
—
—
—
MD3
MD2
MD1
MD0
TIOR_1
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_1
TTGE
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
TSR_1
TCFD
—
TCFU
TCFV
—
—
TGFB
TGFA
TGRC_0
TGRD_0
Rev. 3.00 Feb 22, 2006 page 574 of 624
REJ09B0281-0300
TPU_0
TPU_1
Section 20 List of Registers
Register
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Module
TCNT_1
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
TPU_1
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TCR_2
—
CCLR1
CCLR0
CKEG1
CKEG0
TPSC2
TPSC1
TPSC0
TMDR_2
—
—
—
—
MD3
MD2
MD1
MD0
TIOR_2
IOB3
IOB2
IOB1
IOB0
IOA3
IOA2
IOA1
IOA0
TIER_2
TTGE
—
TCIEU
TCIEV
—
—
TGIEB
TGIEA
TSR_2
TCFD
—
TCFU
TCFV
—
—
TGFB
TGFA
TCNT_2
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
Bit15
Bit14
Bit13
Bit12
Bit11
Bit10
Bit9
Bit8
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
Bit0
TGRA_1
TGRB_1
TGRA_2
TGRB_2
Notes:
TPU_2
1. If the PCR setting specifies the same output trigger for pulse output group 2 and pulse output
group 3, the address is H'FF4C. If the triggers are different, the NDRH address corresponding to
pulse output group 2 is H'FF4E and the NDRH address corresponding to pulse output group 3 is
H'FF4C. In like manner, if the PCR setting specifies the same output trigger for pulse output group
0 and pulse output group 1, the address is H'FF4D. If the triggers are different, the NDRH address
corresponding to pulse output group 0 is H'FF4F and the NDRH address corresponding to pulse
output group 1 is H'FF4D.
2. Functions as C/A for SCI use, and as GM for smart card interface use.
3. Functions as CHR for SCI use, and as BLK for smart card interface use.
4. Functions as STOP for SCI use, and as BCP1 for smart card interface use.
5. Functions as MP for SCI use, and as BCP0 for smart card interface use.
6. Functions as FER for SCI use, and as ERS for smart card interface use.
7. Loaded in on-chip RAM. The bus width is 32 bits when the DTC accesses this area as register
information, and 16 bits otherwise.
Rev. 3.00 Feb 22, 2006 page 575 of 624
REJ09B0281-0300
Section 20 List of Registers
20.3
Register States in Each Operating Mode
Register
Name
Reset
Clock
High-Speed Division
Sleep
Module
Stop
All Module
Clock Stop
Software Hardware
Standby Standby
Module
MRA
Initialized
—
—
—
—
—
—
Initialized
DTC
SAR
Initialized
—
—
—
—
—
—
Initialized
MRB
Initialized
—
—
—
—
—
—
Initialized
DAR
Initialized
—
—
—
—
—
—
Initialized
CRA
Initialized
—
—
—
—
—
—
Initialized
CRB
Initialized
—
—
—
—
—
—
Initialized
SEMR
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SCI2
IPRA
Initialized
—
—
—
—
—
—
Initialized
INT
IPRB
Initialized
—
—
—
—
—
—
Initialized
IPRC
Initialized
—
—
—
—
—
—
Initialized
IPRD
Initialized
—
—
—
—
—
—
Initialized
IPRE
Initialized
—
—
—
—
—
—
Initialized
IPRF
Initialized
—
—
—
—
—
—
Initialized
IPRG
Initialized
—
—
—
—
—
—
Initialized
IPRH
Initialized
—
—
—
—
—
—
Initialized
IPRI
Initialized
—
—
—
—
—
—
Initialized
IPRJ
Initialized
—
—
—
—
—
—
Initialized
IPRK
Initialized
—
—
—
—
—
—
Initialized
ITSR
Initialized
—
—
—
—
—
—
Initialized
SSIER
Initialized
—
—
—
—
—
—
Initialized
ISCR
Initialized
—
—
—
—
—
—
Initialized
IrCR_0
Initialized
—
—
—
—
—
—
Initialized
IrDA_0
P1DDR
Initialized
—
—
—
—
—
—
—
PORT
P2DDR
Initialized
—
—
—
—
—
—
—
P3DDR
Initialized
—
—
—
—
—
—
—
P5DDR
Initialized
—
—
—
—
—
—
—
P6DDR
Initialized
—
—
—
—
—
—
—
P7DDR
Initialized
—
—
—
—
—
—
—
P8DDR
Initialized
—
—
—
—
—
—
—
PADDR
Initialized
—
—
—
—
—
—
—
PBDDR
Initialized
—
—
—
—
—
—
—
PCDDR
Initialized
—
—
—
—
—
—
—
Rev. 3.00 Feb 22, 2006 page 576 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Reset
Clock
High-Speed Division
Sleep
Module
Stop
All Module
Clock Stop
Software Hardware
Standby Standby
Module
PDDDR
Initialized
—
—
—
—
—
—
—
PORT
PEDDR
Initialized
—
—
—
—
—
—
—
PFDDR
Initialized
—
—
—
—
—
—
—
PGDDR
Initialized
—
—
—
—
—
—
—
PFCR0
Initialized
—
—
—
—
—
—
—
PFCR1
Initialized
—
—
—
—
—
—
—
PFCR2
Initialized
—
—
—
—
—
—
—
PAPCR
Initialized
—
—
—
—
—
—
—
PBPCR
Initialized
—
—
—
—
—
—
—
PCPCR
Initialized
—
—
—
—
—
—
—
PDPCR
Initialized
—
—
—
—
—
—
—
PEPCR
Initialized
—
—
—
—
—
—
—
P3ODR
Initialized
—
—
—
—
—
—
—
PAODR
Initialized
—
—
—
—
—
—
—
TCR_3
Initialized
—
—
—
—
—
—
Initialized
TMDR_3
Initialized
—
—
—
—
—
—
Initialized
TIORH_3
Initialized
—
—
—
—
—
—
Initialized
TIORL_3
Initialized
—
—
—
—
—
—
Initialized
TIER_3
Initialized
—
—
—
—
—
—
Initialized
TSR_3
Initialized
—
—
—
—
—
—
Initialized
TCNT_3
Initialized
—
—
—
—
—
—
Initialized
TGRA_3
Initialized
—
—
—
—
—
—
Initialized
TGRB_3
Initialized
—
—
—
—
—
—
Initialized
TGRC_3
Initialized
—
—
—
—
—
—
Initialized
TGRD_3
Initialized
—
—
—
—
—
—
Initialized
TCR_4
Initialized
—
—
—
—
—
—
Initialized
TMDR_4
Initialized
—
—
—
—
—
—
Initialized
TIOR_4
Initialized
—
—
—
—
—
—
Initialized
TIER_4
Initialized
—
—
—
—
—
—
Initialized
TSR_4
Initialized
—
—
—
—
—
—
Initialized
TCNT_4
Initialized
—
—
—
—
—
—
Initialized
TGRA_4
Initialized
—
—
—
—
—
—
Initialized
TGRB_4
Initialized
—
—
—
—
—
—
Initialized
TPU_3
TPU_4
Rev. 3.00 Feb 22, 2006 page 577 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Reset
Clock
High-Speed Division
Sleep
Module
Stop
All Module
Clock Stop
Software Hardware
Standby Standby
Module
TCR_5
Initialized
—
—
—
—
—
—
Initialized
TPU_5
TMDR_5
Initialized
—
—
—
—
—
—
Initialized
TIOR_5
Initialized
—
—
—
—
—
—
Initialized
TIER_5
Initialized
—
—
—
—
—
—
Initialized
TSR_5
Initialized
—
—
—
—
—
—
Initialized
TCNT_5
Initialized
—
—
—
—
—
—
Initialized
TGRA_5
Initialized
—
—
—
—
—
—
Initialized
TGRB_5
Initialized
—
—
—
—
—
—
Initialized
ABWCR
Initialized
—
—
—
—
—
—
Initialized
ASTCR
Initialized
—
—
—
—
—
—
Initialized
WTCRAH
Initialized
—
—
—
—
—
—
Initialized
WTCRAL
Initialized
—
—
—
—
—
—
Initialized
WTCRBH
Initialized
—
—
—
—
—
—
Initialized
WTCRBL
Initialized
—
—
—
—
—
—
Initialized
BSC
RDNCR
Initialized
—
—
—
—
—
—
Initialized
CSACRH
Initialized
—
—
—
—
—
—
Initialized
CSACRL
Initialized
—
—
—
—
—
—
Initialized
BCR
Initialized
—
—
—
—
—
—
Initialized
RAMER
Initialized
—
—
—
—
—
—
Initialized
FLASH
(F-ZTAT
version)
DTCERA
Initialized
—
—
—
—
—
—
Initialized
DTC
DTCERB
Initialized
—
—
—
—
—
—
Initialized
DTCERC
Initialized
—
—
—
—
—
—
Initialized
DTCERD
Initialized
—
—
—
—
—
—
Initialized
DTCERE
Initialized
—
—
—
—
—
—
Initialized
DTCERF
Initialized
—
—
—
—
—
—
Initialized
DTCERG
Initialized
—
—
—
—
—
—
Initialized
DTVECR
Initialized
—
—
—
—
—
—
Initialized
INTCR
Initialized
—
—
—
—
—
—
Initialized
IER
Initialized
—
—
—
—
—
—
Initialized
ISR
Initialized
—
—
—
—
—
—
Initialized
Rev. 3.00 Feb 22, 2006 page 578 of 624
REJ09B0281-0300
INT
Section 20 List of Registers
Register
Name
Reset
Clock
High-Speed Division
Sleep
Module
Stop
All Module
Clock Stop
Software Hardware
Standby Standby
Module
SBYCR
Initialized
—
—
—
—
—
—
Initialized
SYSTEM
SCKCR
Initialized
—
—
—
—
—
—
Initialized
SYSCR
Initialized
—
—
—
—
—
—
Initialized
MDCR
Initialized
—
—
—
—
—
—
Initialized
MSTPCRH
Initialized
—
—
—
—
—
—
Initialized
MSTPCRL
Initialized
—
—
—
—
—
—
Initialized
PLLCR
Initialized
—
—
—
—
—
—
Initialized
PCR
Initialized
—
—
—
—
—
—
Initialized
PMR
Initialized
—
—
—
—
—
—
Initialized
NDERH
Initialized
—
—
—
—
—
—
Initialized
NDERL
Initialized
—
—
—
—
—
—
Initialized
PODRH
Initialized
—
—
—
—
—
—
Initialized
PODRL
Initialized
—
—
—
—
—
—
Initialized
NDRH
Initialized
—
—
—
—
—
—
Initialized
NDRL
Initialized
—
—
—
—
—
—
Initialized
NDRH
Initialized
—
—
—
—
—
—
Initialized
NDRL
Initialized
—
—
—
—
—
—
Initialized
PORT1
—
—
—
—
—
—
—
—
PORT2
—
—
—
—
—
—
—
—
PORT3
—
—
—
—
—
—
—
—
PORT4
—
—
—
—
—
—
—
—
PORT5
—
—
—
—
—
—
—
—
PORT6
—
—
—
—
—
—
—
—
PORT7
—
—
—
—
—
—
—
—
PORT8
—
—
—
—
—
—
—
—
PORTA
—
—
—
—
—
—
—
—
PORTB
—
—
—
—
—
—
—
—
PORTC
—
—
—
—
—
—
—
—
PORTD
—
—
—
—
—
—
—
—
PORTE
—
—
—
—
—
—
—
—
PORTF
—
—
—
—
—
—
—
—
PORTG
—
—
—
—
—
—
—
—
PPG
PORT
Rev. 3.00 Feb 22, 2006 page 579 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Reset
Clock
High-Speed Division
Sleep
Module
Stop
All Module
Clock Stop
Software Hardware
Standby Standby
Module
P1DR
Initialized
—
—
—
—
—
—
—
PORT
P2DR
Initialized
—
—
—
—
—
—
—
P3DR
Initialized
—
—
—
—
—
—
—
P5DR
Initialized
—
—
—
—
—
—
—
P6DR
Initialized
—
—
—
—
—
—
—
P7DR
Initialized
—
—
—
—
—
—
—
P8DR
Initialized
—
—
—
—
—
—
—
PADR
Initialized
—
—
—
—
—
—
—
PBDR
Initialized
—
—
—
—
—
—
—
PCDR
Initialized
—
—
—
—
—
—
—
PDDR
Initialized
—
—
—
—
—
—
—
PEDR
Initialized
—
—
—
—
—
—
—
PFDR
Initialized
—
—
—
—
—
—
—
PGDR
Initialized
—
—
—
—
—
—
—
PORTH
—
—
—
—
—
—
—
—
PHDR
Initialized
—
—
—
—
—
—
—
PHDDR
Initialized
—
—
—
—
—
—
—
SMR_0
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
BRR_0
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SCR_0
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
TDR_0
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SSR_0
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
RDR_0
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SCMR_0
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SMR_1
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
BRR_1
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SCR_1
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
TDR_1
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SSR_1
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
RDR_1
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SCMR_1
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
Rev. 3.00 Feb 22, 2006 page 580 of 624
REJ09B0281-0300
SCI_0
SCI_1
Section 20 List of Registers
Register
Name
Reset
Clock
High-Speed Division
Sleep
Module
Stop
SMR_2
Initialized
—
—
—
BRR_2
Initialized
—
—
SCR_2
Initialized
—
—
TDR_2
Initialized
—
SSR_2
Initialized
RDR_2
Initialized
All Module
Clock Stop
Software Hardware
Standby Standby
Module
Initialized Initialized
Initialized Initialized
SCI_2
—
Initialized Initialized
Initialized Initialized
—
Initialized Initialized
Initialized Initialized
—
—
Initialized Initialized
Initialized Initialized
—
—
—
Initialized Initialized
Initialized Initialized
—
—
—
Initialized Initialized
Initialized Initialized
SCMR_2
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADDRA
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADDRB
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADDRC
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADDRD
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADDRE
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADDRF
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADDRG
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADDRH
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADCSR
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
ADCR
Initialized
—
—
—
Initialized Initialized
Initialized Initialized
DADR0
Initialized
—
—
—
—
—
—
Initialized
DADR1
Initialized
—
—
—
—
—
—
Initialized
DACR01
Initialized
—
—
—
—
—
—
Initialized
DADR2
Initialized
—
—
—
—
—
—
Initialized
DADR3
Initialized
—
—
—
—
—
—
Initialized
DACR23
Initialized
—
—
—
—
—
—
Initialized
TCR_0
Initialized
—
—
—
—
—
—
—
TCR_1
Initialized
—
—
—
—
—
—
—
TCSR_0
Initialized
—
—
—
—
—
—
—
TCSR_1
Initialized
—
—
—
—
—
—
—
TCORA_0
Initialized
—
—
—
—
—
—
—
TCORA_1
Initialized
—
—
—
—
—
—
—
TCORB_0
Initialized
—
—
—
—
—
—
—
TCORB_1
Initialized
—
—
—
—
—
—
—
TCNT_0
Initialized
—
—
—
—
—
—
—
TCNT_1
Initialized
—
—
—
—
—
—
—
A/D
D/A
TMR_0
TMR_1
Rev. 3.00 Feb 22, 2006 page 581 of 624
REJ09B0281-0300
Section 20 List of Registers
Register
Name
Reset
Clock
High-Speed Division
Sleep
Module
Stop
All Module
Clock Stop
Software Hardware
Standby Standby
Module
TCSR
Initialized
—
—
—
—
—
WDT
—
—
TCNT
Initialized
—
—
—
—
—
—
—
RSTCSR
Initialized
—
—
—
—
—
—
—
TSTR
Initialized
—
—
—
—
—
—
Initialized
TSYR
Initialized
—
—
—
—
—
—
Initialized
FLMCR1
Initialized
—
—
—
—
—
—
Initialized
FLMCR2
Initialized
—
—
—
—
—
—
Initialized
EBR1
Initialized
—
—
—
—
—
—
Initialized
EBR2
Initialized
—
—
—
—
—
—
Initialized
TCR_0
Initialized
—
—
—
—
—
—
Initialized
TMDR_0
Initialized
—
—
—
—
—
—
Initialized
TIORH_0
Initialized
—
—
—
—
—
—
Initialized
TIORL_0
Initialized
—
—
—
—
—
—
Initialized
TIER_0
Initialized
—
—
—
—
—
—
Initialized
TSR_0
Initialized
—
—
—
—
—
—
Initialized
TCNT_0
Initialized
—
—
—
—
—
—
Initialized
TGRA_0
Initialized
—
—
—
—
—
—
Initialized
TGRB_0
Initialized
—
—
—
—
—
—
Initialized
TGRC_0
Initialized
—
—
—
—
—
—
Initialized
TGRD_0
Initialized
—
—
—
—
—
—
Initialized
TCR_1
Initialized
—
—
—
—
—
—
Initialized
TMDR_1
Initialized
—
—
—
—
—
—
Initialized
TIOR_1
Initialized
—
—
—
—
—
—
Initialized
TIER_1
Initialized
—
—
—
—
—
—
Initialized
TSR_1
Initialized
—
—
—
—
—
—
Initialized
TCNT_1
Initialized
—
—
—
—
—
—
Initialized
TGRA_1
Initialized
—
—
—
—
—
—
Initialized
TGRB_1
Initialized
—
—
—
—
—
—
Initialized
Rev. 3.00 Feb 22, 2006 page 582 of 624
REJ09B0281-0300
TPU
FLASH
(F-ZTAT
version)
TPU_0
TPU_1
Section 20 List of Registers
Register
Name
Reset
Clock
High-Speed Division
Sleep
Module
Stop
All Module
Clock Stop
Software Hardware
Standby Standby
Module
TCR_2
Initialized
—
—
—
—
—
—
Initialized
TPU_2
TMDR_2
Initialized
—
—
—
—
—
—
Initialized
TIOR_2
Initialized
—
—
—
—
—
—
Initialized
TIER_2
Initialized
—
—
—
—
—
—
Initialized
TSR_2
Initialized
—
—
—
—
—
—
Initialized
TCNT_2
Initialized
—
—
—
—
—
—
Initialized
TGRA_2
Initialized
—
—
—
—
—
—
Initialized
TGRB_2
Initialized
—
—
—
—
—
—
Initialized
Rev. 3.00 Feb 22, 2006 page 583 of 624
REJ09B0281-0300
Section 20 List of Registers
Rev. 3.00 Feb 22, 2006 page 584 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Section 21 Electrical Characteristics
21.1
Electrical Characteristics of F-ZTAT Version (H8S/2667)
21.1.1
Absolute Maximum Ratings
Table 21.1 lists the absolute maximum ratings.
Table 21.1 Absolute Maximum Ratings
Item
Symbol
Value
Unit
Power supply voltage
VCC
–0.3 to +4.0
V
PLLVCC
Input voltage (except port 4, P54 to P57)
Vin
–0.3 to VCC +0.3
V
Input voltage (port 4, P54 to P57)
Vin
–0.3 to AVCC +0.3
V
Reference power supply voltage
Vref
–0.3 to AVCC +0.3
V
Analog power supply voltage
AVCC
–0.3 to +4.0
V
Analog input voltage
VAN
–0.3 to AVCC +0.3
V
Operating temperature
Topr
Regular specifications:
–20 to +75*
°C
Wide-range specifications:
–40 to +85*
°C
–55 to +125
°C
Storage temperature
Tstg
Caution: Permanent damage to the LSI may result if absolute maximum ratings are exceeded.
Note: * The operating temperature ranges for flash memory programming/erasing are as
follows:
Ta = 0°C to +75°C (regular specifications)
Ta = 0°C to +85°C (wide-range specifications)
Rev. 3.00 Feb 22, 2006 page 585 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
21.1.2
DC Characteristics
Table 21.2 DC Characteristics (1)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
1
VSS = AVSS = 0 V* , Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Min
Typ
Max
Test
Unit Conditions
–
VCC × 0.2
—
—
V
+
—
—
VCC × 0.7
V
VCC × 0.07
—
—
V
AVCC × 0.2
—
—
V
—
—
AVCC × 0.7
V
AVCC × 0.07 —
—
V
VCC × 0.9
—
VCC + 0.3
V
VCC × 0.9
—
VCC + 0.3
V
VCC × 0.7
—
VCC + 0.3
V
Port 3, 6 to 8* ,
3
P50 to P53* ,
3
*
ports A to H
VCC × 0.7
—
VCC + 0.3
V
Port 4,
3
P54 to P57*
AVCC × 0.7
—
AVCC + 0.3 V
–0.3
—
VCC × 0.1
V
NMI, EXTAL
–0.3
—
VCC × 0.2
V
Ports 3 to 8,
3
ports A to H*
–0.3
—
VCC × 0.2
V
VCC – 0.5
—
—
V
IOH = –200 µA
VCC – 1.0
—
—
V
IOH = –1 mA
—
—
0.4
V
IOL = 1.6 mA
Item
Symbol
2
Schmitt
Port 1, 2, 8* ,
2
trigger input P50 to P53* ,
2
2
*
*
PH2 , PH3
voltage
VT
VT
+
VT – VT
P54 to P57*
2
VT
–
VT
+
+
VT – VT
Input high
voltage
STBY,
MD2 to MD0
–
–
VIH
RES, NMI
EXTAL
3
Input low
voltage
RES, STBY,
MD2 to MD0
VIL
Output high All output pins
voltage
VOH
Output low
voltage
VOL
All output pins
Notes: 1. If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins
open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
2. When used as IRQ0 to IRQ7.
3. When used as other than IRQ0 to IRQ7.
Rev. 3.00 Feb 22, 2006 page 586 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Table 21.3 DC Characteristics (2)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
1
VSS = AVSS = 0 V* , Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Input
leakage
current
Three-state
leakage
current
(off state)
Test
Conditions
Symbol
Min
Typ
Max
Unit
|Iin|
—
—
10.0
µA
STBY, NMI,
MD2 to MD0
—
—
1.0
µA
Port 4,
P54 to P57
—
—
1.0
µA
Vin = 0.5 to
AVCC – 0.5 V
| ITSI |
—
—
1.0
µA
Vin = 0.5 to
VCC – 0.5 V
–Ip
10
—
300
µA
VCC = 3.0 to
3.6 V
RES
Ports 1 to 3,
6 to 8,
P50 to P53,
ports A to H
Input pull-up Ports A to E
MOS current
Vin = 0.5 to
VCC – 0.5 V
Vin = 0 V
Input
RES
capacitance
NMI
Cin
All input pins
except RES
and NMI
4
Current
Normal operation ICC*
2
*
dissipation
Sleep mode
Standby mode*
3
When all module
5
clocks stop*
Analog
power
supply
current
During A/D and
D/A conversion
Idle
AICC
—
—
30
pF
Vin = 0 V
—
—
30
pF
f = 1 MHz
—
—
15
pF
Ta = 25°C
—
80
(3.3 V)
150
mA
f = 33 MHz
—
70
(3.3 V)
125
mA
f = 33 MHz
—
0.01
10
µA
Ta ≤ 50°C
—
—
80
µA
50°C < Ta
—
50
(3.3 V)
125
mA
f = 33 MHz
—
0.2
(3.0 V)
2.0
mA
—
0.01
5.0
µA
Rev. 3.00 Feb 22, 2006 page 587 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Item
Reference
power
supply
current
During A/D and
D/A conversion
Symbol
Min
Typ
Max
Unit
AICC
—
1.4
(3.0 V)
4.0
mA
—
0.01
5.0
µA
2.0
—
—
V
Idle
RAM standby voltage
VRAM
Test
Conditions
Notes: 1. When the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS
pins open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
2. Current dissipation values are for VIHmin = VCC – 0.5 V and VILmax = 0.5 V with all output
pins unloaded and all MOS input pull-ups in the off state.
3. The values are for VRAM ≤ VCC < 3.0 V, VIHmin = VCC × 0.9, and VILmax = 0.3 V.
4. ICC depends on VCC and f as follows:
ICCmax = 1.0 (mA) + 1.2 (mA/(MHz × V)) × VCC × f (normal operation)
ICCmax = 1.0 (mA) + 1.0 (mA/(MHz × V)) × VCC × f (sleep mode)
5. The values are for reference.
Table 21.4 Permissible Output Currents
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V*, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Typ
Max
Unit
Permissible output low
current (per pin)
All output pins
IOL
—
—
2.0
mA
Permissible output low
current (total)
Total of all output
pins
ΣIOL
—
—
80
mA
Permissible output high
current (per pin)
All output pins
–IOH
—
—
2.0
mA
Permissible output high
current (total)
Total of all output
pins
Σ–IOH
—
—
40
mA
Caution: To protect the LSI’s reliability, do not exceed the output current values in table 21.4.
Note: * If the A/D and D/A converters are not used, do not leave the AVCC, Vref, and AVSS pins
open. Connect the AVCC and Vref pins to VCC, and the AVSS pin to VSS.
Rev. 3.00 Feb 22, 2006 page 588 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
21.1.3
AC Characteristics
3V
RL
C = 50 pF: ports A to H
C = 30 pF: ports 1 to 3,
P50 to P53,
ports 6 to 8
LSI output pin
C
RL = 2.4 kΩ
RH = 12 kΩ
Input/output timing
measurement level:
1.5 V (VCC = 3.0 V to 3.6 V)
RH
Figure 21.1 Output Load Circuit
Rev. 3.00 Feb 22, 2006 page 589 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Clock Timing
Table 21.5 Clock Timing
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Max
Unit
Test Conditions
Clock cycle time
tcyc
30.3
125
ns
Figure 21.2
Clock pulse high width
tCH
10
—
ns
Clock pulse low width
tCL
10
—
ns
Clock rise time
tCr
—
5
ns
Clock fall time
tCf
—
5
ns
Reset oscillation stabilization
time (crystal)
tOSC1
10
—
ms
Figure 21.3(1)
Software standby oscillation
stabilization time (crystal)
tOSC2
10
—
ms
Figure 21.3(2)
External clock output delay
stabilization time
tDEXT
500
—
µs
Figure 21.3(1)
tcyc
tCH
tCf
φ
tCL
tCr
Figure 21.2 System Clock Timing
Rev. 3.00 Feb 22, 2006 page 590 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
EXTAL
tDEXT
tDEXT
VCC
STBY
tOSC1
tOSC1
RES
φ
Figure 21.3(1) Oscillation Stabilization Timing
Oscillator
φ
NMI
NMIEG
SSBY
NMI exception handling
NMI exception
handling
NMIEG = 1
SSBY = 1
Software standby mode
(power-down mode)
Oscillation
stabilization time
tOSC2
SLEEP
instruction
Figure 21.3(2) Oscillation Stabilization Timing
Rev. 3.00 Feb 22, 2006 page 591 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Control Signal Timing
Table 21.6 Control Signal Timing
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Max
Unit
Test Conditions
RES setup time
tRESS
200
—
ns
Figure 21.4
RES pulse width
tRESW
20
—
tcyc
NMI setup time
tNMIS
150
—
ns
NMI hold time
tNMIH
10
—
NMI pulse width (in recovery from
software standby mode)
tNMIW
200
—
IRQ setup time
tIRQS
150
—
IRQ hold time
tIRQH
10
—
IRQ pulse width (in recovery from
software standby mode)
tIRQW
200
—
ns
φ
tRESS
tRESS
RES
tRESW
Figure 21.4 Reset Input Timing
Rev. 3.00 Feb 22, 2006 page 592 of 624
REJ09B0281-0300
Figure 21.5
Section 21 Electrical Characteristics
φ
tNMIS tNMIH
NMI
tNMIW
tIRQW
IRQi
(i = 0 to 7)*
tIRQS tIRQH
IRQ
(edge input)
tIRQS
IRQ
(level input)
Note: * Necessary for SSIER setting to clear software standby mode.
Figure 21.5 Interrupt Input Timing
Rev. 3.00 Feb 22, 2006 page 593 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Bus Timing
Table 21.7 Bus Timing (1)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Address delay time
TAD
—
Address setup time 1
TAS1
0.5 × tcyc – 13
Address setup time 2
TAS2
1.0 × tcyc – 13
—
ns
Address setup time 3
TAS3
1.5 × tcyc – 13
—
ns
Address setup time 4
TAS4
2.0 × tcyc – 13
—
ns
Address hold time 1
TAH1
0.5 × tcyc – 8
—
ns
Address hold time 2
TAH2
1.0 × tcyc – 8
—
ns
Address hold time 3
TAH3
1.5 × tcyc – 8
—
ns
CS delay time 1
tCSD1
—
15
ns
AS delay time
TASD
—
15
ns
RD delay time 1
tRSD1
—
15
ns
RD delay time 2
tRSD2
—
15
ns
Read data setup time 1
tRDS1
15
—
ns
Read data setup time 2
tRDS2
15
—
ns
Read data hold time 1
tRDH1
0
—
ns
Read data hold time 2
tRDH2
0
—
ns
Read data access time 2
TAC2
—
1.5 × tcyc – 20
ns
Read data access time 4
TAC4
—
2.5 × tcyc – 20
ns
Read data access time 5
TAC5
—
1.0 × tcyc – 20
ns
Read data access time 6
TAC6
—
2.0 × tcyc – 20
ns
Address read data access time 2
TAA2
—
1.5 × tcyc – 20
ns
Address read data access time 3
TAA3
—
2.0 × tcyc – 20
ns
Address read data access time 4
TAA4
—
2.5 × tcyc – 20
ns
Address read data access time 5
TAA5
—
3.0 × tcyc – 20
ns
Rev. 3.00 Feb 22, 2006 page 594 of 624
REJ09B0281-0300
Max
Unit
Test Conditions
20
ns
—
ns
Figures 21.6 to
21.10
Section 21 Electrical Characteristics
Table 21.8 Bus Timing (2)
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Max
Unit
Test Conditions
WR delay time 1
tWRD1
—
15
ns
WR delay time 2
tWRD2
—
15
ns
Figures 21.6 to
21.10
WR pulse width 1
tWSW1
1.0 × tcyc – 13
—
ns
WR pulse width 2
tWSW2
1.5 × tcyc – 13
—
ns
Write data delay time
tWDD
—
20
ns
Write data setup time 1
tWDS1
0.5 × tcyc – 13
—
ns
Write data setup time 2
tWDS2
1.0 × tcyc – 13
—
ns
Write data setup time 3
tWDS3
1.5 × tcyc – 13
—
ns
Write data hold time 1
tWDH1
0.5 × tcyc – 8
—
ns
Write data hold time 3
tWDH3
1.5 × tcyc – 8
—
ns
WAIT setup time
tWTS
25
—
ns
WAIT hold time
tWTH
5
—
ns
BREQ setup time
tBREQS
30
—
ns
BACK delay time
tBACD
—
15
ns
Bus floating time
tBZD
—
40
ns
BREQO delay time
tBRQOD
—
25
ns
Figure 21.8
Figure 21.11
Figure 21.12
Rev. 3.00 Feb 22, 2006 page 595 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
T1
T2
φ
tAD
A23 to A0
tCSD1
CS7 to CS0
tAS1
tASD tASD
tAH1
AS
tAS1
tRSD1
tRSD1
RD
Read
(RDNn = 1)
tRDS1 tRDH1
tAC5
tAA2
D15 to D0
tAS1
tRSD1
tRSD2
RD
Read
(RDNn = 0)
tAC2
tRDS2 tRDH2
tAA3
D15 to D0
tAS1
tWRD2 tWRD2
tAH1
HWR, LWR
tWDD
Write
tWSW1
tWDH1
D15 to D0
Figure 21.6 Basic Bus Timing: Two-State Access
Rev. 3.00 Feb 22, 2006 page 596 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
T1
T2
T3
φ
tAD
A23 to A0
tCSD1
CS7 to CS0
tAS1
tASD
tASD
tAH1
AS
tAS1
tRSD1
tRSD1
RD
Read
(RDNn = 1)
tRDS1 tRDH1
tAC6
tAA4
D15 to D0
tAS1
tRSD1
tRSD2
RD
Read
(RDNn = 0)
tRDS2
tAC4
tRDH2
tAA5
D15 to D0
tAS2
tAH1
tWRD1
HWR, LWR
tWDS1
tWDD
Write
tWRD2
tWSW2
tWDH1
D15 to D0
Figure 21.7 Basic Bus Timing: Three-State Access
Rev. 3.00 Feb 22, 2006 page 597 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
T1
T2
Tw
tWTS tWTH
tWTS tWTH
T3
φ
A23 to A0
CS7 to CS0
AS
RD
Read
(RDNn = 1)
D15 to D0
RD
Read
(RDNn = 0)
D15 to D0
HWR, LWR
Write
D15 to D0
WAIT
Figure 21.8 Basic Bus Timing: Three-State Access, One Wait
Rev. 3.00 Feb 22, 2006 page 598 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Th
T1
T2
Tt
φ
tAD
A23 to A0
tCSD1
CS7 to CS0
tAS1
tAH1
tASD
tASD
AS
tAS3
tAH3
tRSD1 tRSD1
RD
Read
(RDNn = 1)
tAC5
tRDS1 tRDH1
tRSD1
tRSD2
D15 to D0
tAS3
tAH2
RD
Read
(RDNn = 0)
tAC2
tRDS2 tRDH2
D15 to D0
tAS3
tWRD2 tWRD2
tAH3
HWR, LWR
tWDD
Write
tWDS2
tWSW1
tWDH3
D15 to D0
Figure 21.9 Basic Bus Timing: Two-State Access (CS
CS Assertion Period Extended)
Rev. 3.00 Feb 22, 2006 page 599 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Th
T1
T2
T3
Tt
φ
tAD
A23 to A0
tCSD1
CS7 to CS0
tAS1
tASD
tAH1
tASD
AS
tAS3
tRSD1
tAH3
tRSD1
RD
Read
(RDNn = 1)
tRDS1 tRDH1
tAC6
D15 to D0
tAS3
tAH2
tRSD2
tRSD1
RD
Read
(RDNn = 0)
tRDS2 tRDH2
tAC4
D15 to D0
tAS4
HWR, LWR
tWDD
Write
tWRD2
tAH3
tWRD1
tWDS3
tWSW2
tWDH3
D15 to D0
Figure 21.10 Basic Bus Timing: Three-State Access (CS
CS Assertion Period Extended)
Rev. 3.00 Feb 22, 2006 page 600 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
φ
tBREQS
tBREQS
BREQ
tBACD
tBACD
BACK
tBZD
tBZD
A23 to A0
CS7 to CS0
D15 to D0
AS, RD
HWR, LWR
Figure 21.11 External Bus Release Timing
φ
BACK
tBRQOD
tBRQOD
BREQO
Figure 21.12 External Bus Request Output Timing
Rev. 3.00 Feb 22, 2006 page 601 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Timing of On-Chip Peripheral Modules
Table 21.9 Timing of On-Chip Peripheral Modules
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Symbol
Min
Max
Output data delay time
tPWD
—
Input data setup time
tPRS
25
Input data hold time
tPRH
PPG
Pulse output delay time
TPU
Timer output delay time
I/O ports
8-bit timer
Unit
Test Conditions
40
ns
Figure 21.13
—
ns
25
—
ns
tPOD
—
40
ns
Figure 21.14
tTOCD
—
40
ns
Figure 21.15
Timer input setup time
tTICS
25
—
ns
Timer clock input setup time
tTCKS
25
—
ns
Timer clock
pulse width
Single-edge
specification
tTCKWH
1.5
—
tcyc
Both-edge
specification
tTCKWL
2.5
—
tcyc
Figure 21.16
Timer output delay time
tTMOD
—
40
ns
Figure 21.17
Timer reset input setup time
tTMRS
25
—
ns
Figure 21.19
Timer clock input setup time
tTMCS
25
—
ns
Figure 21.18
Timer clock
pulse width
Single-edge
specification
tTMCWH
1.5
—
tcyc
Both-edge
specification
tTMCWL
2.5
—
tcyc
WDT
Overflow output delay time
tWOVD
—
40
ns
Figure 21.20
SCI
Input clock
cycle
tScyc
4
—
tcyc
Figure 21.21
6
—
Input clock pulse width
tSCKW
0.4
0.6
tScyc
Input clock rise time
tSCKr
—
1.5
tcyc
Input clock fall time
tSCKf
—
1.5
Transmit data delay time
tTXD
—
40
ns
Receive data setup time
(synchronous)
tRXS
40
—
ns
Receive data hold time
(synchronous)
tRXH
40
—
ns
Trigger input setup time
tTRGS
30
—
ns
A/D
converter
Asynchronous
Synchronous
Rev. 3.00 Feb 22, 2006 page 602 of 624
REJ09B0281-0300
Figure 21.22
Figure 21.23
Section 21 Electrical Characteristics
T1
T2
φ
tPRS tPRH
Ports 1 to 8, A to H
(read)
tPWD
Ports 1 to 3, 6 to 8,
P53 to P50,
ports A to H
(write)
Figure 21.13 I/O Port Input/Output Timing
φ
tPOD
PO15 to PO0
Figure 21.14 PPG Output Timing
φ
tTOCD
Output compare
output*
tTICS
Input capture
input*
Note: * TIOCA0 to TIOCA5, TIOCB0 to TIOCB5, TIOCC0, TIOCC3, TIOCD0, TIOCD3
Figure 21.15 TPU Input/Output Timing
Rev. 3.00 Feb 22, 2006 page 603 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
φ
tTCKS
tTCKS
TCLKA to TCLKD
tTCKWH
tTCKWL
Figure 21.16 TPU Clock Input Timing
φ
tTMOD
TMO0, TMO1
Figure 21.17 8-Bit Timer Output Timing
φ
tTMCS
tTMCS
TMCI0, TMCI1
tTMCWL
tTMCWH
Figure 21.18 8-Bit Timer Clock Input Timing
φ
tTMRS
TMRI0, TMRI1
Figure 21.19 8-Bit Timer Reset Input Timing
Rev. 3.00 Feb 22, 2006 page 604 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
φ
tWOVD
tWOVD
WDTOVF
Figure 21.20 WDT Output Timing
tSCKW
tSCKr
tSCKf
SCK0 to SCK2
tScyc
Figure 21.21 SCK Clock Input Timing
SCK0 to SCK2
tTXD
TxD0 to TxD2
(transmit data)
tRXS tRXH
RxD0 to RxD2
(receive data)
Figure 21.22 SCI Input/Output Timing: Synchronous Mode
φ
tTRGS
ADTRG
Figure 21.23 A/D Converter External Trigger Input Timing
Rev. 3.00 Feb 22, 2006 page 605 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
21.1.4
A/D Conversion Characteristics
Table 21.10 A/D Conversion Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Min
Typ
Max
Unit
Resolution
10
10
10
Bit
Conversion time
—
—
8.1
µs
Analog input capacitance
—
—
20
pF
Permissible signal source impedance
—
—
5
kΩ
Nonlinearity error
—
—
±7.5
LSB
Offset error
—
—
±7.5
LSB
Full-scale error
—
—
±7.5
LSB
Quantization error
—
±0.5
—
LSB
Absolute accuracy
—
—
±8.0
LSB
21.1.5
D/A Conversion Characteristics
Table 21.11 D/A Conversion Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC, VSS = AVSS = 0 V,
φ = 8 MHz to 33 MHz, Ta = –20°C to +75°C (regular specifications),
Ta = –40°C to +85°C (wide-range specifications)
Item
Min
Typ
Max
Unit
Resolution
8
8
8
Bit
Conversion time
—
—
10
µs
20 pF capacitive load
Absolute accuracy
—
±2.0
±3.0
LSB
2 MΩ resistive load
—
—
±2.0
LSB
4 MΩ resistive load
Rev. 3.00 Feb 22, 2006 page 606 of 624
REJ09B0281-0300
Test Conditions
Section 21 Electrical Characteristics
21.1.6
Flash Memory Characteristics
Table 21.12 Flash Memory Characteristics
Conditions: VCC = 3.0 V to 3.6 V, AVCC = 3.0 V to 3.6 V, Vref = 3.0 V to AVCC,
VSS = AVSS = 0 V, Ta = 0°C to 75°C (program/erase operating temperature range:
regular specifications), Ta = 0°C to 85°C (program/erase operating temperature
range: wide-range specifications)
Item
Symbol
Min
Typ
Max
Unit
Programming time*1 *2 *4
tP
—
10
200
ms/
128 bytes
Erase time*1 *3 *6
tE
—
50
1000
ms/
128 bytes
Rewrite times
NWEC
100*1
10000*2 —
Times
Data retention time*3
tDRP
10
—
—
Years
Programming Wait time after SWE bit
setting*1
x
1
—
—
µs
Wait time after PSU bit
setting*1
y
50
—
—
µs
Wait time after P bit
setting*1 *4
z
Test
Conditions
z1
—
—
30
µs
1≤n≤6
z2
—
—
200
µs
7 ≤ n ≤ 1000
z3
—
—
10
µs
Additional
program-ming
wait
Wait time after P bit
clearing*1
α
5
—
—
µs
Wait time after PSU bit
clearing*1
β
5
—
—
µs
Wait time after PV bit
setting*1
γ
4
—
—
µs
Wait time after H'FF
dummy write*1
ε
2
—
—
µs
Wait time after PV bit
clearing*1
η
2
—
—
µs
Wait time after SWE bit
clearing*1
θ
100
—
—
µs
Maximum number of
writes*1 *4
N
—
—
1000*5
Times
Rev. 3.00 Feb 22, 2006 page 607 of 624
REJ09B0281-0300
Section 21 Electrical Characteristics
Item
Erasing
Symbol
Min
Typ
Max
Unit
Wait time after SWE bit
setting*1
x
1
—
—
µs
Wait time after ESU bit
setting*1
y
100
—
—
µs
Wait time after E bit
setting*1 *6
z
—
—
10
µs
Wait time after E bit
clearing*1
α
10
—
—
µs
Wait time after ESU bit
clearing*1
β
10
—
—
µs
Wait time after EV bit
setting*1
γ
20
—
—
µs
Wait time after H'FF
dummy write*1
ε
2
—
—
µs
Wait time after EV bit
clearing*1
η
4
—
—
µs
Wait time after SWE bit
clearing*1
θ
100
—
—
µs
Maximum number of
erases*1 *6
N
—
—
100
Times
Test
Conditions
Erase time
wait
Notes: 1. Follow the program/erase algorithms when making the time settings.
2. Programming time per 128 bytes. (Indicates the total time during which the P bit is set
in flash memory control register 1 (FLMCR1). Does not include the program-verify
time.)
3. Time to erase one block. (Indicates the time during which the E bit is set in FLMCR1.
Does not include the erase-verify time.)
4. Maximum programming time
N
tP(max) = Σ wait time after P bit setting (z)
i=1
5. The maximum number of writes (N) should be set as shown below according to the
actual set value of (z) so as not to exceed the maximum programming time (tP(max)).
The wait time after P bit setting (z) should be changed as follows according to the
number of writes (n).
Number of writes (n)
1≤n≤6
z = 30 µs
7 ≤ n ≤ 1000
z = 200 µs
(Additional programming)
Number of writes (n)
1≤n≤6
z = 10 µs
6. For the maximum erase time (tE(max)), the following relationship applies between the
wait time after E bit setting (z) and the maximum number of erases (N):
tE(max) = Wait time after E bit setting (z) × maximum number of erases (N)
Rev. 3.00 Feb 22, 2006 page 608 of 624
REJ09B0281-0300
Appendix
Appendix
A.
I/O Port States in Each Pin State
Reset
Hardware
Standby
Mode
Software
Standby Mode
Bus Release
State
Program
Execution
State Sleep
Mode
1 to 7
T
T
Keep
Keep
I/O port
1 to 7
T
T
Keep
Keep
I/O port
Port 3
1 to 7
T
T
Keep
Keep
I/O port
P47/DA1
1 to 7
T
T
[DAOE1 = 1]
Keep
Input port
Keep
Input port
Port Name
MCU
Operating
Mode*1
Port 1
Port 2
Keep
[DAOE1 = 0]
T
P46/DA0
1 to 7
T
T
[DAOE0 = 1]
Keep
[DAOE0 = 0]
T
P45 to P40
1 to 7
T
T
T
T
Input port
P57/DA3
1 to 7
T
T
[DAOE3 = 1]
Keep
Input port
Keep
Input port
Keep
[DAOE3 = 0]
T
P56/DA2
1 to 7
T
T
[DAOE2 = 1]
Keep
[DAOE2 = 0]
T
P55, P54
1 to 7
T
T
T
T
Input port
P53 to P50
1 to 7
T
T
Keep
Keep
I/O port
Port 6
1 to 7
T
T
Keep
Keep
I/O port
Port 7
1 to 7
T
T
Keep
Keep
I/O port
Port 8
1 to 7
T
T
Keep
Keep
I/O port
Rev. 3.00 Feb 22, 2006 page 609 of 624
REJ09B0281-0300
Appendix
Port Name
MCU
Operating
Mode*1
Reset
Hardware
Standby
Mode
PA7/A23
1 to 7
T
T
PA6/A22
PA5/A21
Software
Standby Mode
Bus Release
State
[OPE = 0,
address output]
[Address output]
T
[Other than the
above]
[OPE = 1,
address output]
T
Keep
Keep
Program
Execution
State Sleep
Mode
[Address
output]
A23 to A21
[Other than
the above]
I/O port
[Other than the
above]
Keep
PA4/A20
1, 2, 5, 6
L
T
[OPE = 0]
PA3/A19
T
PA2/A18
[OPE = 1]
PA1/A17
Keep
PA0/A16
3, 4, 7
T
T
[OPE = 0,
address output]
T
[OPE = 1,
address output]
T
Address
output
A20 to A16
[Address output]
T
[Other than the
above]
Keep
Keep
[Address
output]
A20 to A16
[Other than
the above]
I/O port
[Other than the
above]
Keep
Port B
1, 2, 5, 6
L
T
[OPE = 0]
T
[OPE = 1]
Keep
Rev. 3.00 Feb 22, 2006 page 610 of 624
REJ09B0281-0300
T
Address
output
A15 to A8
Appendix
Port Name
MCU
Operating
Mode*1
Reset
Hardware
Standby
Mode
Port B
4
T
T
Software
Standby Mode
Bus Release
State
[OPE = 0,
address output]
[Address output]
T
[Other than the
above]
[OPE = 1,
address output]
T
Keep
Keep
Program
Execution
State Sleep
Mode
[Address
output]
A15 to A8
[Other than
the above]
I/O port
[Other than the
above]
Keep
3, 7
T
T
[OPE = 0,
address output]
T
[OPE = 1,
address output]
[Address output]
T
[Other than the
above]
Keep
Keep
[Address
output]
A15 to A8
[Other than
the above]
I/O port
[Other than the
above]
Keep
Port C
1, 2, 5, 6
L
T
[OPE = 0]
T
T
Address
output
[OPE = 1]
A7 to A0
Keep
4
T
T
[OPE = 0,
address output]
T
[OPE = 1,
address output]
Keep
[Address output]
T
[Other than the
above]
Keep
[Address
output]
A7 to A0
[Other than
the above]
I/O port
[Other than the
above]
Keep
Rev. 3.00 Feb 22, 2006 page 611 of 624
REJ09B0281-0300
Appendix
Port Name
MCU
Operating
Mode*1
Reset
Hardware
Standby
Mode
Port C
3, 7
T
T
Software
Standby Mode
Bus Release
State
[OPE = 0,
address output]
[Address output]
T
[Other than the
above]
[OPE = 1,
address output]
T
Keep
Keep
Program
Execution
State Sleep
Mode
[Address
output]
A7 to A0
[Other than
the above]
I/O port
[Other than the
above]
Keep
Port D
Port E
1, 2, 4 to 6
T
T
T
T
D15 toD8
3, 7
T
T
[Data bus]
[Data bus]
[Data bus]
T
T
D15 to D8
[Other than the
above]
[Other than the
above]
[Other than
the above]
Keep
Keep
I/O port
1, 2, 4
to 6
3, 7
PF7/φ
8-bit
bus
T
T
Keep
Keep
I/O port
16-bit
bus
T
T
T
T
D7 to D0
8-bit
bus
T
T
Keep
Keep
I/O port
16-bit
bus
T
T
[Data bus]
[Data bus]
[Data bus]
T
T
D7 to D0
[Other than the
above]
[Other than the
above]
[Other than
the above]
Keep
Keep
I/O port
[Clock output]
[Clock output]
H
Clock output
[Clock
output]
[Other than the
above]
[Other than the
above]
Keep
Keep
1, 2, 4 to 6
3, 7
Clock
output
T
T
Clock output
[Other than
the above]
Input port
Rev. 3.00 Feb 22, 2006 page 612 of 624
REJ09B0281-0300
Appendix
Port Name
MCU
Operating
Mode*1
Reset
Hardware
Standby
Mode
PF6/AS
1, 2, 4 to 6
H
T
3, 7
Software
Standby Mode
Bus Release
State
Program
Execution
State Sleep
Mode
[OPE = 0,
AS output]
[AS output]
[AS output]
T
AS
T
[Other than the
above]
[Other than
the above]
Keep
I/O port
T
RD, HWR
[OPE = 1,
AS output]
T
H
[Other than the
above]
Keep
PF5/RD
1, 2, 4 to 6
H
T
PF4/HWR
[OPE = 0]
T
[OPE = 1]
H
3, 7
[OPE = 0, RD,
HWR output]
T
T
[OPE = 1, RD,
HWR output]
[RD, HWR output] [RD, HWR
output]
T
[Other than the
above]
Keep
H
RD, HWR
[Other than
the above]
I/O port
[Other than the
above]
Keep
PF3/LWR
1, 2, 4 to 6
3, 7
H
T
T
[OPE = 0,
LWR output]
[LWR output]
T
[Other than the
above]
[OPE = 1,
LWR output]
H
T
Keep
[LWR
output]
LWR
[Other than
the above]
I/O port
[Other than the
above]
Keep
Rev. 3.00 Feb 22, 2006 page 613 of 624
REJ09B0281-0300
Appendix
Reset
Hardware
Standby
Mode
Software
Standby Mode
Bus Release
State
Program
Execution
State Sleep
Mode
1 to 7
T
T
Keep
Keep
I/O port
PF1
1 to 7
T
T
Keep
Keep
I/O port
PF0/WAIT
1 to 7
T
T
[WAIT input]
[WAIT input]
[WAIT input]
T
T
WAIT
[Other than the
above]
[Other than the
above]
[Other than
the above]
Keep
Keep
I/O port
[BREQ input]
BREQ input
T
BREQ
[BREQ
input]
Port Name
MCU
Operating
Mode*1
PF2
PG6/BREQ
1 to 7
T
T
[Other than the
above]
BREQ
[Other than
the above]
Keep
I/O port
PG5/BACK
1 to 7
T
T
[BACK output]
BACK
T
[BACK
output]
BACK
[Other than the
above]
[Other than
the above]
Keep
I/O port
[BREQO
output]
[BREQO output]
[BREQO output]
T
BREQO
[Other than the
above]
[Other than the
above]
Keep
Keep
[CS output]
[CS output]
PG2/CS2
[OPE = 0,
CS output]
T
CS
PG1/CS1
T
[Other than the
above]
[Other than
the above]
Keep
I/O port
PG4/
BREQO
1 to 7
T
T
BREQO
[Other than
the above]
I/O port
PG3/CS3
1 to 7
T
T
[OPE = 1,
CS output]
H
[Other than the
above]
Keep
Rev. 3.00 Feb 22, 2006 page 614 of 624
REJ09B0281-0300
Appendix
Port Name
MCU
Operating
Mode*1
Reset
Hardware
Standby
Mode
PG0/CS0
1, 2, 5, 6
H
T
3, 4, 7
T
Software
Standby Mode
Bus Release
State
Program
Execution
State Sleep
Mode
[OPE = 0,
CS output]
[CS output]
[CS output]
T
CS
T
[Other than the
above]
[Other than
the above]
Keep
I/O port
[CS output]
[CS output]
T
CS
[Other than the
above]
[Other than
the above]
Keep
I/O port
[OPE = 1,
CS output]
H
[Other than the
above]
Keep
PH3/CS7
PH2/CS6
PH1/CS5
PH0/CS4
1 to 7
T
T
[OPE = 0,
CS output]
T
[OPE = 1,
CS output]
H
[Other than the
above]
Keep
Legend:
L:
Low level
H:
High level
Keep: Input port becomes high-impedance, output port retains state
T:
High impedance
DDR: Data direction register
OPE: Output port enable
Note: * Indicates the state after the currently executed bus cycle ends.
Rev. 3.00 Feb 22, 2006 page 615 of 624
REJ09B0281-0300
Appendix
B.
Product Lineup
Product
H8S/2667
F-ZTAT version
Type Name
Model Marking
Package (Code)
HD64F2667
HD64F2667
144-pin LQFP (FP-144H)
Rev. 3.00 Feb 22, 2006 page 616 of 624
REJ09B0281-0300
Appendix
C.
Package Dimensions
For package dimensions, dimensions described in Renesas Package data book have priority.
JEITA Package Code
P-LQFP144-20x20-0.50
RENESAS Code
PLQP0144KC-A
Previous Code
FP-144H/FP-144HV
MASS[Typ.]
1.4g
HD
*1
D
108
73
109
NOTE)
1. DIMENSIONS"*1"AND"*2"
DO NOT INCLUDE MOLD FLASH
2. DIMENSION"*3"DOES NOT
INCLUDE TRIM OFFSET.
72
bp
c
c1
HE
*2
E
b1
Reference Dimension in Millimeters
Symbol
Terminal cross section
ZE
Min
37
144
36
Index mark
c
A
ZD
A2
1
F
θ
A1
L
L1
e
*3
y
bp
Detail F
x
M
D
E
A2
HD
HE
A
A1
bp
b1
c
c1
θ
e
x
y
ZD
ZE
L
L1
Nom Max
20
20
1.45
21.7 22.0 22.3
21.7 22.0 22.3
1.70
0.04 0.12 0.20
0.17 0.22 0.27
0.20
0.12 0.17 0.22
0.15
0°
8°
0.5
0.08
0.10
1.25
1.25
0.4 0.5 0.6
1.0
Figure C.1 Package Dimensions (FP-144H)
Rev. 3.00 Feb 22, 2006 page 617 of 624
REJ09B0281-0300
Appendix
Rev. 3.00 Feb 22, 2006 page 618 of 624
REJ09B0281-0300
Index
Index
16-Bit Timer Pulse Unit.......................... 251
Buffer Operation ................................. 297
Cascaded Operation ............................ 300
Free-running count operation.............. 290
Input Capture Function ....................... 293
Phase Counting Mode......................... 307
PWM Modes....................................... 302
Synchronous Operation....................... 294
toggle output ....................................... 291
Waveform Output by Compare Match 291
8-Bit Timers............................................ 357
16-Bit Counter Mode .......................... 372
Cascaded Connection.......................... 372
Compare Match Count Mode.............. 372
Pulse Output........................................ 367
TCNT Incrementation Timing ............ 368
Toggle output...................................... 377
A/D Converter ........................................ 473
A/D Converter Activation................... 315
Conversion Time................................. 481
External Trigger .................................. 483
Scan Mode .......................................... 480
Single Mode........................................ 480
Address Space........................................... 22
Addressing Modes .................................... 42
Absolute Address.................................. 43
Immediate ............................................. 44
Memory Indirect ................................... 45
Program-Counter Relative .................... 44
Register Direct ...................................... 43
Register Indirect.................................... 43
Register Indirect with Displacement..... 43
Register indirect with post-increment ... 43
Register indirect with pre-decrement .... 43
Bcc ...................................................... 31, 39
Bus Controller ...........................................99
Basic Bus Interface .............................120
Basic Timing .......................................122
Bus Arbitration....................................142
Bus Release .........................................139
Chip Select (CS) Assertion Period
Extension States ..............................117
Data Size and Data Alignment ............120
Idle Cycle ............................................134
Read Strobe (RD) Timing ...................132
Valid Strobes.......................................121
Wait Control........................................130
Write Data Buffer Function.................138
Clock Pulse Generator.............................533
PLL Circuit .........................................539
Condition Field .........................................41
Condition-Code Register (CCR) ...............26
CPU Operating Modes ..............................18
Advanced Mode ....................................20
Normal Mode ..................................18, 19
D/A Converter.........................................491
data direction register..............................173
data register .............................................173
Data Transfer Controller .........................145
activated by software...........................163
Activation by Software .......................166
Block Transfer Mode ..........................161
Chain Transfer.............................162, 167
Chain Transfer when Counter = 0 .......168
DTC Vector Table...............................153
Normal Mode ..............................159, 167
Register Information ...........................153
Repeat Mode .......................................160
Software Activation ............................170
Effective Address ......................................46
Rev. 3.00 Feb 22, 2006 page 619 of 624
REJ09B0281-0300
Index
Effective Address Extension..................... 41
Exception Handling .................................. 59
Interrupts............................................... 65
Reset exception handling ...................... 62
Stack Status after Exception Handling.. 67
Traces ................................................... 64
Trap Instruction .................................... 66
Exception Vector Table ............................ 59
Extended Register (EXR) ......................... 25
Flash Memory......................................... 501
Boot Mode .......................................... 515
Erase/Erase-Verify.............................. 524
erasing unit.......................................... 506
Error Protection .................................. 526
Hardware Protection ........................... 526
Program/Program-Verify .................... 522
Programmer Mode .............................. 527
programming units.............................. 506
Software Protection ............................ 526
General Registers...................................... 24
input pull-up MOS.................................. 173
Instruction Set........................................... 31
Interrupt Control Modes ........................... 87
Interrupt Controller ................................... 69
Interrupt Exception Handling Vector Table
.............................................................. 83
Interrupt Mask Bit..................................... 26
interrupt mask level .................................. 25
interrupt priority register........................... 69
Interrupts
ADI ..................................................... 484
Arithmetic Operations Instructions....... 34
Bit Manipulation Instructions ............... 37
Block Data Transfer Instructions .......... 41
Branch Instructions ............................... 39
CMIA.................................................. 373
CMIB .................................................. 373
Rev. 3.00 Feb 22, 2006 page 620 of 624
REJ09B0281-0300
Data Transfer Instructions..................... 33
Logic Operations Instructions ............... 36
NMI....................................................... 97
NMI Interrupt........................................ 81
OVI ..................................................... 373
Shift Instructions ................................... 36
SWDTEND ......................................... 163
System Control Instructions.................. 40
TCI0V ................................................. 314
TCI1U ................................................. 314
TCI1V ................................................. 314
TCI2U ................................................. 314
TCI2V ................................................. 314
TCI3V ................................................. 314
TCI4U ................................................. 314
TCI4V ................................................. 314
TCI5U ................................................. 314
TCI5V ................................................. 314
TGI0A................................................. 314
TGI0B ................................................. 314
TGI0C ................................................. 314
TGI0D................................................. 314
TGI1A................................................. 314
TGI1B ................................................. 314
TGI2A................................................. 314
TGI2B ................................................. 314
TGI3A................................................. 314
TGI3B ................................................. 314
TGI3C ................................................. 314
TGI3D................................................. 314
TGI4A................................................. 314
TGI4B ................................................. 314
TGI5A................................................. 314
TGI5B ................................................. 314
WOVI.................................................. 388
List of Registers ...................................... 557
Bit configurations................................ 557
Register addresses ............................... 557
Register Addresses (Address Order) ... 558
Index
Register Bits........................................ 566
Register states ..................................... 557
Register States in Each Operating Mode
........................................................ 576
MCU Operating Modes ............................ 51
Multiply-Accumulate Register.................. 27
On-Board Programming Modes.............. 515
open-drain control register...................... 173
Operation Field ......................................... 41
port register............................................. 173
Program Counter (PC) .............................. 25
Programmable Pulse Generator .............. 335
Non-Overlapping Pulse Output........... 349
output trigger....................................... 342
RAM ....................................................... 499
Register Field............................................ 41
Registers
ABWCR...................... 102, 560, 569, 578
ADCR ......................... 479, 563, 573, 581
ADCSR ....................... 477, 563, 573, 581
ADDR ......................... 476, 572, 573, 581
ASTCR ....................... 103, 560, 569, 578
BCR ............................ 112, 560, 569, 578
BRR ............ 411, 562, 563, 572, 580, 581
CRA ............................ 150, 558, 566, 576
CRB .................................... 150, 566, 576
CSACR ....................... 110, 560, 569, 578
DACR01 ..................... 494, 563, 573, 581
DACR23 ..................... 494, 564, 573, 581
DADR ......................... 493, 563, 573, 581
DAR............................ 149, 558, 566, 576
DTCER ............... 150, 560, 561, 570, 578
DTVECR .................... 151, 561, 570, 578
EBR1 .......................... 511, 564, 574, 582
EBR2 .......................... 512, 564, 574, 582
FLMCR1..................... 508, 564, 574, 582
FLMCR2 ..................... 510, 564, 574, 582
IER ................................ 75, 561, 570, 578
INTCR........................... 72, 561, 570, 578
IPR ............... 73, 83, 84, 85, 86, 558, 566,
567, 576
IrCR............................. 420, 558, 567, 576
ISCR.............................. 76, 558, 567, 576
ISR ................................ 79, 561, 570, 578
ITSR........................ 80, 98, 558, 567, 576
MDCR........................... 52, 561, 570, 579
MRA ........................... 147, 558, 566, 576
MRB............................ 149, 558, 566, 576
MSTPCR..................... 548, 561, 570, 579
NDER.......................... 338, 561, 570, 579
NDR ............................ 339, 561, 570, 579
P1DDR........................ 178, 558, 567, 576
P1DR........................... 179, 562, 571, 580
P2DDR........................ 188, 558, 567, 576
P2DR........................... 189, 562, 571, 580
P3DDR........................ 198, 558, 567, 576
P3DR........................... 199, 562, 571, 580
P3ODR........................ 200, 559, 568, 577
P5DDR........................ 204, 558, 567, 576
P5DR........................... 204, 562, 571, 580
P6DDR........................ 208, 559, 567, 576
P6DR........................... 209, 562, 571, 580
P7DDR........................ 212, 559, 567, 576
P7DR........................... 213, 562, 571, 580
P8DDR........................ 214, 559, 567, 576
P8DR........................... 215, 562, 571, 580
PADDR ....................... 218, 559, 567, 576
PADR .......................... 219, 562, 571, 580
PAODR ....................... 220, 559, 568, 577
PAPCR ........................ 220, 559, 568, 577
PBDDR ....................... 223, 559, 567, 576
PBDR .......................... 224, 562, 571, 580
PBPCR ........................ 225, 559, 568, 577
PCDDR ....................... 227, 559, 567, 576
PCDR .......................... 227, 562, 571, 580
PCPCR ........................ 228, 559, 568, 577
Rev. 3.00 Feb 22, 2006 page 621 of 624
REJ09B0281-0300
Index
PCR............................. 342, 561, 570, 579
PDDDR....................... 230, 559, 567, 577
PDDR.......................... 231, 562, 571, 580
PDPCR........................ 232, 559, 568, 577
PEDDR ....................... 234, 559, 567, 577
PEDR .......................... 235, 562, 571, 580
PEPCR ........................ 236, 559, 568, 577
PFCR0 ........................ 245, 559, 567, 577
PFCR1 ........................ 220, 559, 567, 577
PFCR2 ........................ 200, 559, 568, 577
PFDDR ....................... 238, 559, 567, 577
PFDR .......................... 239, 562, 571, 580
PGDDR....................... 242, 559, 567, 577
PGDR.......................... 244, 562, 571, 580
PHDDR....................... 247, 562, 572, 580
PHDR.......................... 248, 562, 572, 580
PLLCR........................ 535, 561, 570, 579
PMR............................ 343, 561, 570, 579
PODRH....................... 339, 561, 570, 579
PODRL ....................... 339, 561, 570, 579
PORT1 ........................ 179, 561, 571, 579
PORT2 ........................ 189, 561, 571, 579
PORT3 ........................ 199, 561, 571, 579
PORT4 ........................ 203, 561, 571, 579
PORT5 ........................ 205, 561, 571, 579
PORT6 ........................ 209, 561, 571, 579
PORT7 ........................ 213, 562, 571, 579
PORT8 ........................ 215, 562, 571, 579
PORTA ....................... 219, 562, 571, 579
PORTB ....................... 224, 562, 571, 579
PORTC ....................... 228, 562, 571, 579
PORTD ....................... 231, 562, 571, 579
PORTE ....................... 235, 562, 571, 579
PORTF........................ 239, 562, 571, 579
PORTG ....................... 244, 562, 571, 579
PORTH ....................... 248, 562, 571, 580
RAMER ...................... 513, 560, 569, 578
RDNCR .............. 108, 132, 560, 569, 578
RDR .................... 398, 563, 572, 580, 581
RSR..................................................... 398
Rev. 3.00 Feb 22, 2006 page 622 of 624
REJ09B0281-0300
RSTCSR...................... 385, 564, 574, 582
SAR............................. 149, 558, 566, 576
SBYCR ....................... 546, 561, 570, 579
SCKCR ....................... 534, 561, 570, 579
SCMR ................. 410, 563, 572, 580, 581
SCR............. 402, 562, 563, 572, 580, 581
SEMR.......................... 421, 558, 566, 576
SMR ............ 398, 562, 563, 572, 580, 581
SSIER.................................... 81, 558, 576
SSR ..................... 405, 562, 563, 572, 580
SYSCR.......................... 52, 561, 570, 579
TCNT ......... 287, 360, 383, 559, 560, 568,
569, 573, 574, 575, 581, 582
TCOR.................................................. 360
TCORA ............................... 564, 573, 581
TCORB ............................... 564, 573, 581
TCR.... 258, 361, 559, 560, 564, 565, 568,
569, 573, 574, 577, 578, 581, 582
TCSR .. 363, 383, 564, 573, 574, 581, 582
TDR ............ 398, 562, 563, 572, 580, 581
TGR ........... 279, 287, 297, 559, 568, 569,
574, 575, 577, 582
TIER........... 282, 559, 560, 565, 568, 569,
574, 577, 578, 582
TIOR ............... 265, 560, 565, 568, 569, 5
74, 577, 578, 582
TIORH ........ 559, 564, 568, 574, 577, 582
TIORL......... 559, 564, 568, 574, 577, 582
TMDR........ 263, 559, 560, 565, 568, 569,
574, 577, 578, 582
TSR ......... 284, 398, 559, 560, 565, 568, 5
69, 574, 577, 582
TSTR........................... 287, 564, 574, 582
TSYR .......................... 288, 564, 574, 582
WTCR......................... 103, 560, 569, 578
Reset.......................................................... 61
Serial Communication Interface ............. 393
Asynchronous Mode ........................... 423
Bit Rate ............................................... 411
Index
Break................................................... 466
Clocked Synchronous Mode ............... 440
framing error ....................................... 430
Mark State........................................... 466
overrun error ....................................... 430
parity error .......................................... 430
stack pointer (SP)...................................... 24
vector number for the Data Transfer
Controller
vector number for the software activation
interrupt...........................................151
Watchdog Timer .....................................381
Interval Timer Mode ...........................387
Watchdog Timer Mode .......................386
Trace Bit ................................................... 25
TRAPA instruction ................................... 44
Rev. 3.00 Feb 22, 2006 page 623 of 624
REJ09B0281-0300
Index
Rev. 3.00 Feb 22, 2006 page 624 of 624
REJ09B0281-0300
Renesas 16-Bit Single-Chip Microcomputer
Hardware Manual
H8S/2668 Group, H8S/2667 F-ZTAT™
Publication Date: 1st Edition, September 2001
Rev.3.00, February 22, 2006
Published by:
Sales Strategic Planning Div.
Renesas Technology Corp.
Edited by:
Customer Support Department
Global Strategic Communication Div.
Renesas Solutions Corp.
©2006. Renesas Technology Corp., All rights reserved. Printed in Japan.
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H8S/2668 Group, H8S/2667 F-ZTAT™
Hardware Manual