DATA SHEET MOS FIELD EFFECT TRANSISTOR NP84N075EUE, NP84N075KUE NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE SWITCHING N-CHANNEL POWER MOS FET DESCRIPTION These products are N-channel MOS Field Effect Transistors designed for high current switching applications. <R> ORDERING INFORMATION PART NUMBER NP84N075EUE-E1-AY Note1, 2 NP84N075EUE-E2-AY Note1, 2 NP84N075KUE-E1-AY Note1 NP84N075KUE-E2-AY Note1 NP84N075CUE-S12-AZ Note1, 2 NP84N075DUE-S12-AY Note1, 2 NP84N075MUE-S18-AY Note1 NP84N075NUE-S18-AY Note1 LEAD PLATING PACKING PACKAGE TO-263 (MP-25ZJ) typ. 1.4 g Pure Sn (Tin) Tape 800 p/reel TO-263 (MP-25ZK) typ. 1.5 g Sn-Ag-Cu Pure Sn (Tin) TO-220 (MP-25) typ. 1.9 g Tube 50 p/tube Notes 1. Pb-free (This product does not contain Pb in the external electrode.) 2. Not for new design TO-262 (MP-25 Fin Cut) typ. 1.8 g TO-220 (MP-25K) typ. 1.9 g TO-262 (MP-25SK) typ. 1.8 g (TO-220) FEATURES • Channel temperature 175 degree rated • Super low on-state resistance RDS(on) = 12.5 mΩ MAX. (VGS = 10 V, ID = 42 A) • Low input capacitance (TO-262) Ciss = 5600 pF TYP. (TO-263) The information in this document is subject to change without notice. Before using this document, please confirm that this is the latest version. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. Document No. D14675EJ4V0DS00 (4th edition) Date Published October 2007 NS Printed in Japan The mark <R> shows major revised points. The revised points can be easily searched by copying an "<R>" in the PDF file and specifying it in the "Find what:" field. 2002, 2007 NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE ABSOLUTE MAXIMUM RATINGS (TA = 25°C) Drain to Source Voltage (VGS = 0 V) VDSS 75 V Gate to Source Voltage (VDS = 0 V) VGSS ±20 V ID(DC) ±84 A ID(pulse) ±260 A Drain Current (DC) (TC = 25°C) Drain Current (pulse) Note1 Note2 Total Power Dissipation (TA = 25°C) PT1 1.8 W Total Power Dissipation (TC = 25°C) PT2 200 W Channel Temperature Tch 175 °C Tstg −55 to +175 °C Single Avalanche Current Note3 IAS 19/52/73 A Single Avalanche Energy Note3 EAS 333/250/50 mJ Storage Temperature Notes 1. Calculated constant current according to MAX. allowable channel temperature. 2. PW ≤ 10 μs, Duty cycle ≤ 1% 3. Starting Tch = 25°C, VDD = 35 V, RG = 25 Ω, VGS = 20 → 0 V (See Figure 4.) THERMAL RESISTANCE Channel to Case Thermal Resistance Rth(ch-C) 0.75 °C/W Channel to Ambient Thermal Resistance Rth(ch-A) 83.3 °C/W 2 Data Sheet D14675EJ4V0DS NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE ELECTRICAL CHARACTERISTICS (TA = 25°C) CHARACTERISTICS SYMBOL TEST CONDITIONS MIN. TYP. MAX. UNIT Zero Gate Voltage Drain Current IDSS VDS = 75 V, VGS = 0 V 10 μA Gate Leakage Current IGSS VGS = ±20 V, VDS = 0 V ±100 nA Gate to Source Threshold Voltage VGS(th) VDS = VGS, ID = 250 μA 2.0 3.0 4.0 V Forward Transfer Admittance | yfs | VDS = 10 V, ID = 42 A 21 43 Drain to Source On-state Resistance RDS(on) VGS = 10 V, ID = 42 A Input Capacitance Ciss Output Capacitance S 9.3 12.5 mΩ VDS = 25 V, 5600 8400 pF Coss VGS = 0 V, 530 800 pF Reverse Transfer Capacitance Crss f = 1 MHz 270 490 pF Turn-on Delay Time td(on) VDD = 38 V, ID = 42 A, 30 66 ns Rise Time tr VGS = 10 V, 21 53 ns Turn-off Delay Time td(off) RG = 0 Ω 72 150 ns Fall Time tf 12 30 ns Total Gate Charge QG VDD = 60 V, 100 150 nC Gate to Source Charge QGS VGS = 10 V, 24 nC Gate to Drain Charge QGD ID = 84 A 35 nC Body Diode Forward Voltage VF(S-D) IF = 84 A, VGS = 0 V 1.0 V Reverse Recovery Time trr IF = 84 A, VGS = 0 V, 70 ns Reverse Recovery Charge Qrr di/dt = 100 A/μs 200 nC TEST CIRCUIT 2 SWITCHING TIME TEST CIRCUIT 1 AVALANCHE CAPABILITY D.U.T. RG = 25 Ω D.U.T. L RL PG. 50 Ω VDD VGS = 20 V → 0 V RG PG. VGS VGS Wave Form 0 90% 90% BVDSS VDS ID ID VGS 0 ID Starting Tch 10% 0 10% Wave Form τ VDD 90% VDD ID IAS VGS 10% τ = 1 μs Duty Cycle ≤ 1% tr td(off) td(on) ton tf toff TEST CIRCUIT 3 GATE CHARGE D.U.T. PG. IG = 2 mA RL 50 Ω VDD Data Sheet D14675EJ4V0DS 3 NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE TYPICAL CHARACTERISTICS (TA = 25°C) Figure2. TOTAL POWER DISSIPATION vs. CASE TEMPERATURE Figure1. DERATING FACTOR OF FORWARD BIAS SAFE OPERATING AREA PT - Total Power Dissipation - W dT - Percentage of Rated Power - % 280 100 80 60 40 20 0 0 25 50 75 240 200 160 120 80 40 0 100 125 150 175 200 25 0 ID - Drain Current - A D R (V ID(DC) DC Po Lim we r ite Di d ss ipa tio n GS 10 PW 10 0μ s EAS - Single Avalanche Energy - mJ 350 100 =1 0μ s 1m s 1 0.1 0.1 TC = 25°C Single Pulse 1 100 125 150 175 200 Figure4. SINGLE AVALANCHE ENERGY DERATING FACTOR Figure3. FORWARD BIAS SAFE OPERATING AREA 1000 d ite im ) )L 0V on 1 ( S = 75 TC - Case Temperature - °C TC - Case Temperature - °C ID(pulse) 50 10 333 mJ 300 250 mJ 250 200 IAS = 19 A 52 A 73 A 150 100 100 VDS - Drain to Source Voltage - V 50 50 mJ 0 25 50 75 100 125 150 175 Starting Tch - Starting Channel Temperature - °C Figure5. TRANSIENT THERMAL RESISTANCE vs. PULSE WIDTH rth(t) - Transient Thermal Resistance - °C/W 1000 100 Rth(ch-A) = 83.3°C/W 10 1 Rth(ch-C) = 0.75°C/W 0.1 0.01 10 μ Single Pulse 100 μ 1m 10 m 100 m 1 PW - Pulse Width - s 4 Data Sheet D14675EJ4V0DS 10 100 1000 NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE Figure7. DRAIN CURRENT vs. DRAIN TO SOURCE VOLTAGE Figure6. FORWARD TRANSFER CHARACTERISTICS ID - Drain Current - A 1000 400 Pulsed ID - Drain Current - A 100 10 TA = −55°C 25°C 75°C 150°C 175°C 1 0.1 2 3 4 6 5 Pulsed 320 240 VGS = 10 V 160 80 0 7 2 0 10 TA = 175°C 75°C 25°C −55°C 0.1 0.01 0.01 0.1 1 10 100 RDS(on) - Drain to Source On-state Resistance - mΩ ID - Drain Current - A Figure10. DRAIN TO SOURCE ON-STATE RESISTANCE vs. DRAIN CURRENT Pulsed 30 20 VGS = 10 V 10 0 1 10 100 1000 RDS(on) - Drain to Source On-state Resistance - mΩ Figure8. FORWARD TRANSFER ADMITTANCE vs. DRAIN CURRENT 100 VDS = 10 V Pulsed 1 6 4 8 VDS - Drain to Source Voltage - V VGS(th) - Gate to Source Threshold Voltage - V | yfs | - Forward Transfer Admittance - S VGS - Gate to Source Voltage - V Figure9. DRAIN TO SOURCE ON-STATE RESISTANCE vs. GATE TO SOURCE VOLTAGE 20 Pulsed 10 ID = 42 A 0 0 2 4 6 8 10 12 14 16 18 20 VGS - Gate to Source Voltage - V Figure11. GATE TO SOURCE THRESHOLD VOLTAGE vs. CHANNEL TEMPERATURE VDS = VGS ID = 250 μA 4.0 3.0 2.0 1.0 0 ID - Drain Current - A Data Sheet D14675EJ4V0DS −50 0 50 100 150 Tch - Channel Temperature - °C 5 Figure13. SOURCE TO DRAIN DIODE FORWARD VOLTAGE Figure12. DRAIN TO SOURCE ON-STATE RESISTANCE vs. CHANNEL TEMPERATURE 30 Pulsed 25 VGS = 10 V 15 10 5 −50 50 0 100 0V 10 1 0.1 0 150 Figure15. SWITCHING CHARACTERISTICS td(on), tr, td(off), tf - Switching Time - ns Ciss 1000 Coss Crss VGS = 0 V f = 1 MHz 10 0.1 1 10 tf td(off) 100 td(on) tr 10 VDD = 38 V VGS = 10 V RG = 0 Ω 1 0.1 100 Figure16. REVERSE RECOVERY TIME vs. DIODE FORWARD CURRENT 10 Figure17. DYNAMIC INPUT/OUTPUT CHARACTERISTICS VDS - Drain to Source Voltage - V trr - Reverse Recovery Time - ns 10 1.0 10 VGS 80 8 VDD = 60 V 38 V 15 V 60 6 40 4 VDS 20 100 0 2 ID = 84 A 0 20 40 60 80 QG - Gate Charge - nC IF - Diode Forward Current - A 6 100 100 di/dt = 100 A/μs VGS = 0 V 100 1 0.1 10 1 ID - Drain Current - A VDS - Drain to Source Voltage - V 1000 1.5 1000 10000 100 1.0 0.5 VF(S-D) - Source to Drain Voltage - V Tch - Channel Temperature - °C Figure14. CAPACITANCE vs. DRAIN TO SOURCE VOLTAGE Ciss, Coss, Crss - Capacitance - pF VGS = 10 V 100 ID = 42 A 0 Pulsed Data Sheet D14675EJ4V0DS 100 0 120 VGS - Gate to Source Voltage - V 20 1000 IF - Diode Forward Current - A RDS(on) - Drain to Source On-state Resistance - mΩ NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE PACKAGE DRAWINGS (Unit: mm) Note 1.3 ± 0.2 10.0 ± 0.3 No plating 7.88 MIN. 4 2 3 1.4 ± 0.2 0.7 ± 0.2 2.54 TYP. 9.15 ± 0.3 8.0 TYP. 8.5 ± 0.2 1 5.7 ± 0.4 1.0 ± 0.5 4 4.45 ± 0.2 0.025 to 0.25 P. .5R 0 TY R 0.8 2.54 TYP. P. TY 0.5 ± 0.2 0.75 ± 0.2 0.5 ± 2.8 ± 0.2 1.Gate 2.Drain 3.Source 4.Fin (Drain) 1 2 1.Gate 2.Drain 2.5 3.Source 15.5 MAX. 5.9 MIN. 4 1 0.75 ± 0.1 2.54 TYP. 1.3 ± 0.2 12.7 MIN. 6.0 MAX. 1 2 3 0.5 ± 0.2 2.8 ± 0.2 0.75 ± 0.3 2.54 TYP. 2 3 1.0 ± 0.5 10 TYP. Note 4.8 MAX. 1.3 ± 0.2 8.5 ± 0.2 1.3 ± 0.2 4.Fin (Drain) 12.7 MIN. 4.8 MAX. φ 3.6 ± 0.2 10.0 TYP. 1.3 ± 0.2 3 4)TO-262 (MP-25 Fin Cut) 4 8ο 0.25 Note 10.6 MAX. 0.2 0 to 2.54 3)TO-220 (MP-25) 1.3 ± 0.2 2.54 ± 0.25 4.8 MAX. 10 TYP. 1.35 ± 0.3 2)TO-263 (MP-25ZK) 15.25 ± 0.5 1)TO-263 (MP-25ZJ) 3.0 ± 0.3 <R> 0.5 ± 0.2 2.8 ± 0.2 2.54 TYP. 1.Gate 2.Drain 3.Source 4.Fin (Drain) 2.54 TYP. 1.Gate 2.Drain 3.Source 4.Fin (Drain) Note Not for new design Data Sheet D14675EJ4V0DS 7 NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE 1 2 3 0.8 ± 0.1 0.5 ± 0.2 2.5 ± 0.2 2.54 TYP. 1.3 ± 0.2 10.1 ± 0.3 4 4.45 ± 0.2 1.27 ± 0.2 3.1 ± 0.3 15.9 MAX. 1.27 ± 0.2 2.54 TYP. 10.0 ± 0.2 13.7 ± 0.3 3 13.7 ± 0.3 1 2 4.45 ± 0.2 1.3 ± 0.2 3.1 ± 0.2 4 φ 3.8 ± 0.2 6.3 ± 0.3 2.8 ± 0.3 10.0 ± 0.2 8.9 ± 0.2 1.2 ± 0.3 6)TO-262 (MP-25SK) 5)TO-220 (MP-25K) 0.8 ± 0.1 0.5 ± 0.2 2.54 TYP. 1.Gate 2.Drain 3.Source 4.Fin (Drain) 2.54 TYP. 2.5 ± 0.2 1.Gate 2.Drain 3.Source 4.Fin (Drain) EQUIVALENT CIRCUIT Drain Gate Body Diode Source Remark Strong electric field, when exposed to this device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. 8 Data Sheet D14675EJ4V0DS NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE <R> TAPE INFORMATION There are two types (-E1, -E2) of taping depending on the direction of the device. Draw-out side <R> Reel side MARKING INFORMATION NEC 84N075 UE <R> Pb-free plating marking Abbreviation of part number Lot code RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.html) Soldering Method Soldering Conditions Infrared reflow Maximum temperature (Package's surface temperature): 260°C or below MP-25ZJ, MP-25ZK Time at maximum temperature: 10 seconds or less Time of temperature higher than 220°C: 60 seconds or less Preheating time at 160 to 180°C: 60 to 120 seconds Recommended Condition Symbol IR60-00-3 Maximum number of reflow processes: 3 times Maximum chlorine content of rosin flux (percentage mass): 0.2% or less Wave soldering Maximum temperature (Solder temperature): 260°C or below MP-25, MP-25K, MP-25SK, Time: 10 seconds or less MP-25 Fin Cut Maximum chlorine content of rosin flux: 0.2% (wt.) or less Partial heating Maximum temperature (Pin temperature): 350°C or below MP-25ZJ, MP-25ZK, Time (per side of the device): 3 seconds or less MP-25K, MP-25SK Maximum chlorine content of rosin flux: 0.2% (wt.) or less Partial heating Maximum temperature (Pin temperature): 300°C or below MP-25, MP-25 Fin Cut Time (per side of the device): 3 seconds or less THDWS P350 P300 Maximum chlorine content of rosin flux: 0.2% (wt.) or less Caution Do not use different soldering methods together (except for partial heating). Data Sheet D14675EJ4V0DS 9 NP84N075EUE, NP84N075KUE, NP84N075CUE, NP84N075DUE, NP84N075MUE, NP84N075NUE • The information in this document is current as of October, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products. Not all products and/or types are available in every country. Please check with an NEC Electronics sales representative for availability and additional information. • No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Electronics. 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