HD74LV10A Triple 3-input Positive NAND Gates REJ03D0233–0300Z (Previous ADE-205-251A (Z)) Rev.3.00 May 24, 2004 Description The HD74LV10A performs the Boolean functions Y = A•B•C or Y = A+B+C in positive logic. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • • • • • • • VCC = 2.0 V to 5.5 V operation All inputs VIH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) All outputs VO (Max.) = 5.5 V (@VCC = 0 V) Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) Typical VOH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) Output current ±6 mA (@VCC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV10AFPEL SOP–14 pin(JEITA) FP–14DAV FP EL (2,000 pcs/reel) HD74LV10ARPEL HD74LV10ATELL SOP–14 pin(JEDEC) TSSOP–14 pin FP–14DNV TTP–14DV RP T EL (2,500 pcs/reel) ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs A B C Output Y H L X X H X L X H X X L L H H H Note: H: High level L: Low level X: Immaterial Rev.3.00, May 24, 2004, page 1 of 1 HD74LV10A Pin Arrangement 14 VCC 1A 1 1B 2 13 1C 2A 3 12 1Y 2B 4 11 3C 2C 5 10 3B 6 9 3A GND 7 8 3Y 2Y (Top view) Absolute Maximum Ratings Item Symbol Ratings Unit Supply voltage range Input voltage range*1 Output voltage range*1, 2 VCC VI VO V V V Input clamp current Output clamp current Continuous output current IIK IOK IO Continuous current through VCC or GND ICC or IGND –0.5 to 7.0 –0.5 to 7.0 –0.5 to VCC + 0.5 –0.5 to 7.0 –20 ±50 ±25 ±50 Maximum power dissipation at 3 Ta = 25°C (in still air)* PT Storage temperature Tstg 785 500 –65 to 150 mA mA mA mA mW Conditions Output: H or L VCC: OFF VI < 0 VO < 0 or VO > VCC VO = 0 to VCC SOP TSSOP °C Notes: The absolute maximum ratings are values, which must not individually be exceeded, and furthermore, no two of which may be realized at the same time. 1. The input and output voltage ratings may be exceeded even if the input and output clamp-current ratings are observed. 2. This value is limited to 5.5 V maximum. 3. The maximum package power dissipation was calculated using a junction temperature of 150°C. Rev.3.00, May 24, 2004, page 2 of 7 HD74LV10A Recommended Operating Conditions Item Symbol Min Max Unit Supply voltage range VCC Input voltage range Output voltage range Output current VI VO IOH 2.0 0 0 — — — — — — — — 0 0 0 5.5 5.5 VCC –50 –2 –6 –12 50 2 6 12 200 100 20 V V V µA mA –40 85 °C IOL Input transition rise or fall rate ∆t /∆v Operating free-air temperature Ta Conditions VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.0 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V VCC = 2.3 to 2.7 V VCC = 3.0 to 3.6 V VCC = 4.5 to 5.5 V µA mA ns/V Note: Unused or floating inputs must be held high or low. Logic Diagram A B C Rev.3.00, May 24, 2004, page 3 of 7 Y HD74LV10A DC Electrical Characteristics Ta = –40 to 85°C Item Symbol VCC (V)* Min Typ Max Unit Input voltage VIH 1.5 VCC × 0.7 VCC × 0.7 VCC × 0.7 — — — — VCC – 0.1 2.0 2.48 3.8 — — — — — — — — — — — — — — — — — — — — — — — — — — — — 0.5 VCC × 0.3 VCC × 0.3 VCC × 0.3 — — — — 0.1 0.4 0.44 0.55 ±1 20 V Input current Quiescent supply current IIN ICC 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 2.0 2.3 to 2.7 3.0 to 3.6 4.5 to 5.5 Min to Max 2.3 3.0 4.5 Min to Max 2.3 3.0 4.5 0 to 5.5 5.5 Output leakage current IOFF 0 — — Input capacitance CIN 3.3 — 3.5 VIL Output voltage VOH VOL Test Conditions µA µA IOH = –50 µA IOH = –2 mA IOH = –6 mA IOH = –12 mA IOL = 50 µA IOL = 2 mA IOL = 6 mA IOL = 12 mA VIN = 5.5 V or GND VIN = VCC or GND, IO = 0 5 µA VI or VO = 0 V to 5.5 V — pF VI = VCC or GND V Note: For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. Switching Characteristics VCC = 2.5 ± 0.2 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL — — 8.0 10.4 13.0 17.1 1.0 1.0 15.5 20.5 ns Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF A, B, or C Y VCC = 3.3 ± 0.3 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL — — 5.7 8.2 8.4 11.9 1.0 1.0 10.0 13.5 ns Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF A, B, or C Y Test Conditions FROM (Input) TO (Output) CL = 15 pF CL = 50 pF A, B, or C Y VCC = 5.0 ± 0.5 V Ta = 25°C Ta = –40 to 85°C Item Symbol Min Typ Max Min Max Unit Propagation delay time tPLH tPHL — — 3.9 5.4 5.9 7.9 1.0 1.0 7.0 9.0 ns Rev.3.00, May 24, 2004, page 4 of 7 HD74LV10A Operating Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Test Conditions Power dissipation capacitance CPD 3.3 5.0 — — 9.5 11.0 — — pF f = 10 MHz Noise Characteristics CL = 50 pF Ta = 25°C Item Symbol VCC (V) Min Typ Max Unit Quiet output, maximum dynamic VOL VOL (P) 3.3 — 0.2 0.8 V Quiet output, minimum dynamic VOL VOL (V) 3.3 — –0.1 –0.8 Quiet output, minimum dynamic VOH VOH (V) 3.3 — 3.2 — High-level dynamic input voltage VIH (D) 3.3 2.31 — — Low-level dynamic inout voltage VIL (D) 3.3 — — 0.99 Test Circuit Measurement point CL* Note: C L includes the probe and jig capacitance. Rev.3.00, May 24, 2004, page 5 of 7 V Test Conditions HD74LV10A • Waveform − 1 tr Input 10% tf 90% 50% VCC 90% 50% VCC VCC 10% 0V t PHL t PLH VOH In phase output 50% VCC 50% VCC VOL t PHL t PLH VOH 50% VCC Out of phase output 50% VCC VOL Notes: 1. Input waveform: PRR ≤ 1 MHz, Zo = 50 Ω, tr ≤ 3 ns, tf ≤ 3 ns 2. The output are measured one at a time with one transition per measurement. Package Dimensions As of January, 2003 Unit: mm 10.06 10.5 Max 8 5.5 14 1 1.27 *0.40 ± 0.06 0.10 ± 0.10 1.42 Max *0.20 ± 0.05 2.20 Max 7 0.20 7.80 +– 0.30 1.15 0˚ – 8˚ 0.70 ± 0.20 0.15 0.12 M *Ni/Pd/Au plating Rev.3.00, May 24, 2004, page 6 of 7 Package Code JEDEC JEITA Mass (reference value) FP-14DAV — Conforms 0.23 g HD74LV10A As of January, 2003 Unit: mm 8.65 9.05 Max 8 1 7 *0.20 ± 0.05 0.635 Max 1.75 Max 3.95 14 + 0.10 6.10 – 0.30 1.08 + 0.11 0˚ – 8˚ + 0.67 0.14 – 0.04 1.27 *0.40 ± 0.06 0.60 – 0.20 0.15 0.25 M Package Code JEDEC JEITA Mass (reference value) *Ni/Pd/Au plating FP-14DNV Conforms Conforms 0.13 g As of January, 2003 Unit: mm 4.40 5.00 5.30 Max 14 8 1 7 0.65 1.0 *0.20 ± 0.05 0.13 M 6.40 ± 0.20 *Ni/Pd/Au plating Rev.3.00, May 24, 2004, page 7 of 7 0.07 +0.03 –0.04 0.10 *0.15 ± 0.05 1.10 Max 0.83 Max 0˚ – 8˚ 0.50 ± 0.10 Package Code JEDEC JEITA Mass (reference value) TTP-14DV — — 0.05 g Sales Strategic Planning Div. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Keep safety first in your circuit designs! 1. Renesas Technology Corp. puts the maximum effort into making semiconductor products better and more reliable, but there is always the possibility that trouble may occur with them. Trouble with semiconductors may lead to personal injury, fire or property damage. Remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placement of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. Notes regarding these materials 1. These materials are intended as a reference to assist our customers in the selection of the Renesas Technology Corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to Renesas Technology Corp. or a third party. 2. Renesas Technology Corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. All information contained in these materials, including product data, diagrams, charts, programs and algorithms represents information on products at the time of publication of these materials, and are subject to change by Renesas Technology Corp. without notice due to product improvements or other reasons. It is therefore recommended that customers contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor for the latest product information before purchasing a product listed herein. The information described here may contain technical inaccuracies or typographical errors. Renesas Technology Corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. Please also pay attention to information published by Renesas Technology Corp. by various means, including the Renesas Technology Corp. Semiconductor home page (http://www.renesas.com). 4. When using any or all of the information contained in these materials, including product data, diagrams, charts, programs, and algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. Renesas Technology Corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. Renesas Technology Corp. semiconductors are not designed or manufactured for use in a device or system that is used under circumstances in which human life is potentially at stake. Please contact Renesas Technology Corp. or an authorized Renesas Technology Corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerospace, nuclear, or undersea repeater use. 6. The prior written approval of Renesas Technology Corp. is necessary to reprint or reproduce in whole or in part these materials. 7. If these products or technologies are subject to the Japanese export control restrictions, they must be exported under a license from the Japanese government and cannot be imported into a country other than the approved destination. Any diversion or reexport contrary to the export control laws and regulations of Japan and/or the country of destination is prohibited. 8. Please contact Renesas Technology Corp. for further details on these materials or the products contained therein. http://www.renesas.com RENESAS SALES OFFICES Renesas Technology America, Inc. 450 Holger Way, San Jose, CA 95134-1368, U.S.A Tel: <1> (408) 382-7500 Fax: <1> (408) 382-7501 Renesas Technology Europe Limited. Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, United Kingdom Tel: <44> (1628) 585 100, Fax: <44> (1628) 585 900 Renesas Technology Europe GmbH Dornacher Str. 3, D-85622 Feldkirchen, Germany Tel: <49> (89) 380 70 0, Fax: <49> (89) 929 30 11 Renesas Technology Hong Kong Ltd. 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Hong Kong Tel: <852> 2265-6688, Fax: <852> 2375-6836 Renesas Technology Taiwan Co., Ltd. FL 10, #99, Fu-Hsing N. Rd., Taipei, Taiwan Tel: <886> (2) 2715-2888, Fax: <886> (2) 2713-2999 Renesas Technology (Shanghai) Co., Ltd. 26/F., Ruijin Building, No.205 Maoming Road (S), Shanghai 200020, China Tel: <86> (21) 6472-1001, Fax: <86> (21) 6415-2952 Renesas Technology Singapore Pte. Ltd. 1, Harbour Front Avenue, #06-10, Keppel Bay Tower, Singapore 098632 Tel: <65> 6213-0200, Fax: <65> 6278-8001 © 2004. Renesas Technology Corp., All rights reserved. Printed in Japan. Colophon .1.0