FAN21SV06 — TinyBuck™
6 A, 24V Single-Input Integrated Synchronous Buck
Regulator with Synchronization Capability
Features
Single-Supply Operation with 6 A Output Current
Over 94% Efficiency
Fully Synchronous Operation with Integrated
Description
The FAN210SV06 TinyBuckTM is a highly efficient,
small-footprint, programmable-frequency, 6 A integrated
synchronous buck regulator.
Schottky Diode on Low-Side MOSFET Boosts
Efficiency
Single Supply Device for VIN > 6.5 V – 24 V
Wide Input Range with Dual Supply: 3.0 V to 24 V
5x6 mm, 25-pin, 3-pad MLP
Programmable Frequency Operation (200-600 KHz)
Externally Synchronizable Clock with Master/Slave
Provisions
Output Voltage Range: 0.8 V to 80%VIN
Power-Good Signal
Accepts Ceramic Capacitors on Output
External Compensation for Flexible Design
Starts Up on Pre-Bias Outputs
Integrated Bootstrap Diode
Programmable Over-Current Protection
Under-Voltage, Over-Voltage, and ThermalShutdown Protections
Applications
Servers & Telecom
Graphics Cards & Displays
High-End Computing Systems
Set-Top Boxes & Game Consoles
FAN21SV06 contains both synchronous MOSFETs and
a controller/driver with optimized interconnects in one
package, which enables designers to solve high-current
requirements in a small area with minimal external
components, thereby saving cost. On-board internal 5 V
regulator enables single-supply operation for input
voltages >6.5 V.
The FAN21SV06 can be configured to drive multiple
slave devices OR synchronize to an external system
clock. In slave mode, FAN21SV06 may be set up to be
free-running in the absence of a master clock signal.
External compensation, programmable switching
frequency, and current-limit features allow for design
optimization and flexibility. High-frequency operation
allows for all ceramic solutions.
Fairchild’s advanced BiCMOS power process combined
with low-RDS(ON) internal MOSFETs and a thermally
efficient MLP package provide the ability to dissipate
high power in a small package. Integration helps to
minimize critical inductances making layout simpler and
more efficient compared to discrete solutions.
Output over-voltage, under-voltage, over-current and
thermal-shutdown protections help protect the device
from damage during fault conditions. FAN21SV06
prevents pre-biased output discharge during startup in
point-of-load applications.
Related Resources
TinyCalc™ Calculator Design ToolAN-6033 —
Point-of-Load Regulation
FAN21SV06 Design Guide
AN-8022 — TinyCalc™ Calculator
Ordering Information
Operating
Temperature Range
Package
Packing
Method
FAN21SV06MPX
-10°C to 85°C
Molded Leadless Package (MLP) 5x6 mm
Tape and Reel
FAN21SV06EMPX
-40°C to 85°C
Molded Leadless Package (MLP) 5x6mm
Tape and Reel
Part Number
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
www.fairchildsemi.com
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
November 2012
IN
VIN
CHF
CIN
Boot
Diode
5V_Reg
BOOT
C4
Reg
Q1
R5
CBOOT
VIN_Reg
Enable
PWM
+
DRIVER
RRAMP
COUT
PGND
POWER
MOSFETS
EN
RILIM
L
Q2
RAMP
Power
Good
OUT
SW
C5
CLK
ILIM
RT
R1
FB
RT
R3
AGND
COMP
C3
C1
RBIAS
C2
R2
Figure 1. Typical Application, Master, VIN=6.5 V to 24 V
Block Diagram
VIN_Reg
Reg
5V
5V_Reg
IILIM
ILIM
Current Limit
Comparator
VIN
Int ref
COMP
Error
Amplifier
FB
SS
CBOOT
R
PWM
Comparator
Q
S
Gate
Drive
Circuit
VOUT
SW
L
VREF
COUT
CLK
OSC
EN
BOOT
Boot
Diode
RAMP
GEN
Summing
Amplifier
Current
Sense
AGND
PGND
RAMP
Figure 2. Block Diagram
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Typical Application Diagram
www.fairchildsemi.com
2
Figure 3. MLP 5x6 mm Pin Configuration (Bottom View)
Pad / Pin Definitions
Pad / Pin
Name
Description
P1, 6-12
SW
Switching Node. Junction of high-side and low-side MOSFETs.
P2, 3-5
VIN
Power Input Voltage. Supply voltage for the converter.
P3, 21-23
PGND
Power Ground. Power return and Q2 source.
1
BOOT
High-Side Drive BOOT Voltage. Connect through capacitor (CBOOT) to SW. The IC has an
internal synchronous bootstrap diode to recharge the capacitor on this pin to 5 V.
2
VIN_Reg
Regulator Input Voltage. Input voltage to the internal regulator. Connect to input voltage
>6.5 V with 1 µF bypass capacitor at the pin.
13
PGOOD
Power-Good. An open-drain output that pulls LOW when the voltage on the FB pin is
outside the limits specified in the electrical specs. PGOOD does not assert HIGH until the
fault latch is enabled.
14
EN
15
5V_Reg
5V Regulator Output. Internal regulator output that provides power for the IC’s logic and
analog circuitry. This pin should be connected to AGND through a >2.2 µf X5R/X7R
capacitor.
16
AGND
Analog Ground. The signal ground for the IC. All internal control voltages are referred to
this pin. Tie this pin to the ground island/plane through the lowest impedance connection.
17
ILIM
Current Limit. A resistor (RILIM) from this pin to AGND can be used to program the currentlimit trip threshold lower than the internal default setting.
18
RT
Oscillator Frequency and Master/Slave Set. Connecting a resistor (RT) to AGND sets the
oscillator frequency and configures the CLK pin as an output (master). Tying this pin to
5 V_Reg through a resistor configures the CLK signal as an input (slave) and establishes
the free-running oscillator frequency.
19
FB
Output Voltage Feedback. Connect through a resistor divider to the output voltage.
20
COMP
Compensation. Error amplifier output. Connect the external compensation network
between this pin and FB.
24
CLK
Clock. Bi-directional signal pin, depending on master/slave configuration. When configured
as a master, this pin represents the clock output that connects directly to the slave(s) for
synchronizing with 180° phase shift.
25
RAMP
Ramp Amplitude. A resistor (RRAMP) connected from this pin to VIN sets the internal ramp
amplitude and also provides voltage feedforward functionality.
ENABLE. Enables operation when pulled to logic HIGH or left open. Toggling EN resets the
regulator after a latched-fault condition. This input has an internal pull-up. When a latched
fault occurs, EN is discharged by a current sink.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Pin Configuration
www.fairchildsemi.com
3
Stresses exceeding the absolute maximum ratings may damage the device. The device may not function or be
operable above the recommended operating conditions and stressing the parts to these levels is not recommended.
In addition, extended exposure to stresses above the recommended operating conditions may affect device reliability.
The absolute maximum ratings are stress ratings only.
Parameter
VIN, VIN_Reg to
AGND
5V_Reg to AGND
Conditions
Min.
Max.
Units
AGND=PGND
28
V
AGND=PGND
6
V
35
V
-0.5
6.0
V
-0.5
24.0
V
-5
30
V
-0.3
6.0
V
BOOT to PGND
BOOT to SW
SW to PGND
Continuous
Transient (t < 20 ns, f < 600 KHz)
All other pins
ESD
Human Body Model, JESD22-A114
1.5
Charged Device Model, JESD22-C101
2.5
kV
Recommended Operating Conditions
The Recommended Operating Conditions table defines the conditions for actual device operation. Recommended
operating conditions are specified to ensure optimal performance to the datasheet specifications. Fairchild does not
recommend exceeding them or designing to Absolute Maximum Ratings.
Symbol
fSW
VIN,
VIN_Reg
Parameter
Conditions
Switching Frequency
Supply Voltage for Power and Bias
TA
Ambient Temperature
TJ
Junction Temperature
Min.
Typ.
200
500
Max Units
600
KHz
VIN to PGND
3.0
24.0
V
VIN_Reg to AGND
6.5
24.0
V
FAN21SV06MX
-10
+85
°C
FAN21SV06EMX
-40
+85
°C
+125
°C
Thermal Information
Symbol
TSTG
Parameter
Min.
Storage Temperature
TL
Lead Soldering Temperature, 30sec
θJC
Thermal Resistance: Junction-to-Case
-65
PD
Max.
Units
+150
°C
+300
°C
P1 (Q2)
4
°C/W
P2 (Q1)
7
°C/W
4
°C/W
P3
θJ-PCB
Typ.
(1)
Thermal Resistance: Junction-to-Mounting Surface
(1)
Total Power Dissipation in the package, TA=25°C
(1)
35
°C/W
2.8
W
Note:
1. Typical thermal resistance when mounted on a four-layer, two-ounce PCB, as shown in Figure 37. Actual results
are dependent upon mounting method and surface related to the design.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Absolute Maximum Ratings
www.fairchildsemi.com
4
Recommended operating conditions, using the circuit in Figure 1, with VIN, VIN_Reg=12 V, unless otherwise noted.
Parameter
Power Supplies
Operating Current
(VIN+VIN_Reg)
VIN_Reg Operating Current
VIN_Reg Quiescent Current
VIN_Reg Standby Current
5V_Reg Output Voltage
5V_Reg Max Current Load
VIN_Reg UVLO Threshold
Reference
Reference Voltage measured
at FB (See Figure 4 for
Temperature Coefficient)
Oscillator
Frequency
Frequency in Slave Mode
compared to Master Mode
Conditions
Min.
VIN=12 V, 5 V_Reg open, CLK open,
fSW =500 KHz, No Load
EN=High, 5 V_Reg open, CLK open,
fSW =500 KHz
EN=High, FB=0.9 V
EN=0, VIN=12 V
Internal VCC Regulator, No Load
(6.5 V <VIN_Reg<24 V)
Units
22
30
mA
4
4.7
Rising VIN, VIN=VIN_Reg
Falling VIN, VIN=VIN_Reg
mA
5
1
5.3
mA
mA
V
5
mA
5.6
6.3
5
V
V
5.0
VIN_Reg=12 V)
FAN21SV06M, 25°C
794
800
806
mV
FAN21SV06EM, 25°C
795
800
805
mV
RT=50 kΩ to GND (Master Mode)
255
300
345
KHz
RT=24 kΩ to GND (Master Mode)
540
600
660
KHz
RT=24 kΩ to 50kΩ to 5 V_Reg
(Slave Mode)
-15
+15
%
65
85
ns
%
VIN=6.5 V, fSW =600 KHz
40
80
16 VIN, 1.8 VOUT, RT=30 kΩ, RRAMP=200 kΩ
0.5
Master (RT to GND)
Master, VCLK=0.4 V
Master, VCLK=2 V
Slave: VCLK > 2 V
Slave: VCLK=1 V
Slave
70
0.25
-2.5
50
-230
1.73
Frequency=500 KHz
VIN_Reg > 6.5 V
5V_Reg=5 V, VCOMP=2.2 V
5V_Reg=5 V, VCOMP=1.2 V
VFB=0.8 V, 25°C
80
12
0.4
1.5
0.8
-850
Note:
2. Specifications guaranteed by design and characterization; not production tested.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
Max.
11
(2)
Minimum On-Time
Duty Cycle
Ramp Amplitude,
Peak–to-Peak(2)
Minimum Off-Time (2)
Synchronization
CLK Output Pulse Width
CLK Output Sink Current
CLK Output Source Current
CLK Input Pulse Width
CLK Input Source Current
CLK Input Threshold, Rising
Soft-Start
VOUT to Regulation (T0.8)
Fault Enable/SSOK (T1.0)
Error Amplifier
DC Gain (2)
Gain Bandwidth Product(2)
Output Voltage Swing (VCOMP)
Output Current, Sourcing
Output Current, Sinking
FB Bias Current
Typ.
V
100
150
ns
85
100
0.35
-2.0
-200
1.83
-170
1.93
ns
mA
mA
ns
µA
V
2.5
3.1
ms
ms
85
15
dB
MHz
V
mA
mA
nA
2.2
1.2
-650
4.0
2.5
1.5
-450
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Electrical Characteristics
www.fairchildsemi.com
5
Recommended operating conditions using the circuit in Figure 1 with VIN, VIN_Reg=12 V, unless otherwise noted.
Parameter
Control Functions
EN Threshold, Rising
EN Hysteresis
EN Pull-Up Current
EN Discharge Current
Conditions
VIN_Reg >6.5 V
Auto-Restart Mode, VIN_Reg>6.5 V
Min.
Typ.
Max.
Units
1.35
250
-6
1
2.00
V
mV
µA
µA
800
1000
-11.0
+10.0
0.2
-8.0
+13.5
0.4
1.0
KΩ
%VREF
%VREF
V
µA
7
9
11
A
-11
-10
155
30
115
73
250
250
-9
µA
°C
°C
%VOUT
%VOUT
mV
mV
-8
FB OK Drive Resistance
PGOOD LOW Threshold
PGOOD Low Voltage
PGOOD Leakage Current
Protection and Shutdown
Current Limit
ILIM Current
Over-Temperature Shutdown
Over-Temperature Hysteresis
Over-Voltage Threshold
Under-Voltage Shutdown
Fault-Discharge Threshold
Fault-Discharge Hysteresis
(3)
FB < VREF, 2 Consecutive Clock Cycles
FB > VREF, 2 Consecutive Clock Cycles(3)
IOUT < 2 mA
VPGOOD=5 V
RILIM Open, fsw=500 KHz,, VOUT=1.8 V,
Rramp=200 kΩ, 16 Consecutive Clock
Cycles(3)
VIN_Reg > 6.5 V, 25°C
Internal Temperature
2 Consecutive Clock Cycles(3)
16 Consecutive Clock Cycles(3)
Measured at FB pin
Measured at FB pin (VFB ~50 mV)
Note:
3. Delay times are not tested in production. Guaranteed by design.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
-14.5
+6.5
110
68
-4
120
78
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Electrical Characteristics (Continued)
www.fairchildsemi.com
6
1.20
1.005
1.10
I FB
V FB
1.010
1.000
0.995
1.00
0.90
0.990
0.80
-50
0
50
100
150
-50
0
Temperature (oC)
Figure 4. Reference Voltage (VFB) vs. Temperature,
Normalized
150
1.02
1200
1.01
Frequency
Frequency (KHz)
100
Figure 5. Reference Bias Current (IFB) vs.
Temperature, Normalized
1500
900
600
600KHz
1.00
300KHz
0.99
300
0.98
0
0
20
40
60
80
100
120
-50
140
0
50
100
150
o
RT (KΩ)
Temperature ( C)
Figure 6. Frequency vs. RT (Master)
Figure 7.
Frequency vs. Temperature, Normalized
1.04
1.60
1.40
1.02
1.20
I ILIM
RDS
50
Temperature (oC)
1.00
o
Q1 ~0.32 %/ C
0.80
1.00
0.98
Q2 ~0.35 %/oC
0.96
0.60
-50
0
50
100
150
-50
50
100
Temperature ( C)
Temperature ( C)
Figure 9.
Figure 8. RDS vs. Temperature, Normalized
(5 V_Reg=VGS=5 V)
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
0
o
o
ILIM Current (IILIM) vs. Temperature,
Normalized
150
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Typical Characteristics
www.fairchildsemi.com
7
Figure 10. Single-Supply Application Circuit: 1.8 VOUT, 500 KHz, Master
FAN21SV06
5V_Reg
+5V
2.2u
10K
X5R
PGOOD
2.49K
62
COMP
2.49K
4.7n
2
100K
3.3n
VIN_Reg
X7R
24
X5R
20
25
1
19
RAMP
BOOT
* Cooper Industries
DR1050-2R2-R
4.7n
ILIM
EN
200K
RT
0.1u
17
VOUT
SW
14
2.2u *
18
1.5
30.1K
4.99K
4 x 22u
AGND
4.7n
3 x 4.7u
1.0u
56p
FB
3.3-8 VIN
2.2
13
VOUT
CLK
6.5-24 V
VIN
15
PGND
16
390p
X5R
Figure 11. Dual-Supply Application Circuit: 1.2 VOUT, 600 KHz, Master 3.3 V – 8 V Input
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Application Circuit
www.fairchildsemi.com
8
Typical operating characteristics using the circuit shown in Figure 10, unless otherwise specified.
95
95
3.3V_Eff 8-24V_300Khz
1.8V_Eff 8-24V_300Khz
90
Efficiency (%)
Efficiency (%)
90
85
80
85
80
8V
8V
12V
75
12V
75
16V
16V
20V
20V
24V
0
1
2
3
4
5
24V
70
70
0
6
1
2
3
Load (A)
Load (A)
Figure 12.
1.8 VOUT Efficiency Over VIN vs. Load
No Load
% Change in ouput voltage as
compared to set value at 0 Amps
% Change in ouput voltage as
com pared to set value at 6.5V
Load Regulation
0.5A
0.1
0.05
0
10
15
6
0.15
Line Regulation
0.15
5
5
Figure 13. 3.3 VOUT Efficiency vs. Load
(Circuit Value Changes)
0.2
0
4
20
25
-0.05
-0.1
0.1
0.05
0
0
1
2
3
4
5
6
7
-0.05
-0.1
-0.15
12V Input
-0.15
16V Input
-0.2
Load (A)
-0.2
Input Voltage (V)
Figure 14. 1.8 VOUT Line Regulation
Figure 15. 1.8 VOUT Load Regulation
90
90
Peak CaseTempr over Mosfet Location
@ Room Tempr - 3.3V Output, 500Khz
80
70
Temperature (Deg C)
70
Temperature (Deg C)
Peak CaseTempr over Mosfet Location
@ Room Tempr - 5V Output, 300Khz
80
60
50
40
30
20
50
40
30
12Vin_HS
20
12Vin_LS
10
24Vin_HS
10
60
14V_HS
14V_LS
0
24Vin_LS
0
1
1
2
3
Load (A)
4
5
6
3
4
5
6
Load (A)
Figure 16. Peak Case Temp over MOSFET Locations
3.3 V Output, 12 V and 24 V Input (500 KHz)
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
2
Figure 17. Peak Case Temp. Over MOSFET Locations
5 V Output (300 KHz)
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Typical Performance Characteristics
www.fairchildsemi.com
9
Typical operating characteristics using the circuit shown in Figure 10. VIN=12 V, unless otherwise specified.
VOUT
VOUT
EN
CLK
IOUT
PGood
Figure 18. CLK and VOUT at Startup
Figure 19. Transient Response, 3-6 A Load
VOUT
EN
SW
SW
Figure 20. Startup on Pre-Bias
Figure 21. Restart on Fault
VOUT
CLK
CLK
SW
EN
PGood
Figure 23. Slave (500 KHz Free-Run to 600 KHz
Synchronization)
Figure 22. Shutdown, 1 A Load
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
10
Typical operating characteristics using the circuit shown in Figure 10, unless otherwise specified.
95
95
1.8V_Eff 8-24V_600Khz
90
Efficiency (%)
Efficiency (%)
90
85
80
85
3.3V_Eff 8-24V_600Khz
80
8V
8V
12V
75
12V
75
16V
16V
20V
20V
24V
24V
70
0
1
2
3
Load (A)
4
5
70
0
6
1
Figure 24. 1.8 VOUT Efficiency 600 KHz
2
3
Load (A)
4
5
6
Figure 25. 3.3 VOUT Efficiency 600 KHz
3
5V_PWRLOSS_12-24V_300Khz
95
2.5
2
5V_Eff12-24V_300Khz
Power Loss (W)
Efficiency (%)
90
Using DR1050-2R2-R
Inductor from Cooper
85
80
Using DR1050-2R2-R
Inductor from Cooper
1.5
1
12V
12V
16V
75
0.5
20V
16V
20V
24V
24V
70
0
1
2
3
Load (A)
4
5
0
6
0
Figure 26. 5 VOUT Efficiency 300 KHz
(Circuit Values Change)
1
2
3
Load (A)
4
5
6
Figure 27. Device Power Loss (5 VOUT, 300 KHz)
(Circuit Values Change)
95
7
Vout Vs Load Current
Input Voltage = 20V
Temperature rise = 80DegC
1.8V_Eff, 12V Input
6
90
Load Current (A)
Efficiency (%)
5
85
80
3
2
300Khz
400Khz
75
4
20Vin_500Khz
20Vin_600Khz
1
500Khz
600Khz
0
70
0
0
1
2
3
4
5
6
Figure 28. 1.8 VOUT Efficiency Over fSW
(Circuit Values Change)
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
1
2
3
4
5
6
7
8
9
10
11
12
13
Vout (V)
Load (A)
Figure 29. Typical Output Operating Area Based on
Thermal Limitations (Circuit Values Change)
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Typical Performance Characteristics (Continued)
www.fairchildsemi.com
11
Soft-Start
PWM Generation
FAN21SV06 uses an internal digital soft-start circuit to
slowly ramp up the output voltage and limit inrush
current during startup. When 5 V_Reg is in regulation
and EN is high, the circuit releases SS and enables the
PWM regulator. Soft-start time is a function of switching
frequency (number of clock cycles).
Refer to Figure 2 for the PWM control mechanism.
FAN21SV06 uses the summing-mode method of control
to generate the PWM pulses. An amplified currentsense signal is summed with an internally generated
ramp and the combined signal is compared with the
output of the error amplifier to generate the pulse width
to drive the high-side MOSFET. Sensed current from the
previous cycle is used to modulate the output of the
summing block. The output of the summing block is also
compared against a voltage threshold set by the RLIM
resistor to limit the inductor current on a cycle-by-cycle
basis. The controller facilitates external compensation
for enhanced flexibility.
Once internal SS ramp has charged to 0.8 V (T0.8), the
output voltage is in regulation. Until SS ramp reaches
1.0 V (T1.0), only over-current-protection circuit is active
during soft-start and all other output protections are
inhibited.
In dual-supply operation mode, it is necessary to apply
VIN before VIN_Reg reaches its UVLO threshold to
avoid skipping the soft-start cycle.
Initialization
Once VIN_Reg voltage exceeds the UVLO threshold
and EN is high, the IC checks for an open or shorted FB
pin before releasing the internal soft-start ramp (SS).
If R1 is open (Figure 1), error amplifier output (COMP) is
forced LOW and no pulses are generated. After the SS
ramp times out (T1.0), an under-voltage fault occurs.
If the parallel combination of R1 and RBIAS is ≤ 1 kΩ, the
internal SS ramp is not released and the regulator does
not start.
Internal Regulator
FAN21SV06 facilitates single-supply operation for input
voltages >6.5 V. At startup, the output of the internal
regulator tracks the input voltage and comes into
regulation (5 V) when VIN_Reg exceeds the UVLO
threshold. The EN pin is released at the same time. The
output voltage of the internal regulator (5 V_Reg) is set
to 5 V. The internal regulator supplies power to all the
control circuits including the drivers.
For applications with VIN<6.5 V, FAN21SV06 can be
used if VIN_Reg is provided with a separate low-power
source >6.5 V. VIN_Reg supply should come up after
VIN during dual-supply operation. The VIN_Reg pin
should always be decoupled with at least 1 µF ceramic
capacitor (see Figure 11).
Figure 30. Typical Soft-Start Timing Diagram
Since VCC is used to drive the internal MOSFET gates,
high peak currents are present on the 5V_Reg pin.
Connect a >2.2 µf X5R or X7R decoupling capacitor
between the 5 V_Reg pin and PGND.
Startup on Pre-Bias
In addition to supplying power for the control circuits
internally, 5 V_Reg output can be used as a reference
voltage for other applications requiring low noise
reference voltage. 5 V_Reg is capable of sourcing up to
5 mA of output current.
The regulator does not allow the low-side MOSFET to
operate in full synchronous mode until SS reaches 95%
of VREF (~0.76 V). This enables the regulator to startup
on a pre-biased output and ensures that output is not
discharged during the soft-start cycle.
VIN_Reg UVLO or toggling the EN pin discharges the
SS and resets the IC.
When EN is pulled LOW externally, 5 V_Reg output is
still present but the IC is in standby mode with no
switching.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
Protections
The converter output is monitored and protected against
extreme overload, short-circuit, over-voltage, and undervoltage conditions.
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Circuit Operation
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12
If FB remains below the under-voltage threshold for 16
consecutive clock cycles, the fault latch is set and the
converter shuts down. This fault is prevented from
setting the fault latch during soft-start.
Over-Voltage Protection
If FB exceeds 115% • VREF for two consecutive clock
cycles, the fault latch is set and shutdown occurs.
Figure 31.
A shorted high-side MOSFET condition is detected
when SW voltage exceeds ~0.7 V while the low-side
MOSFET is fully enhanced. The fault latch is set
immediately upon detection.
Enable Control with Latch Option
Power Good (PGOOD) Signal
PGOOD is an open-drain output that asserts LOW when
VOUT is out of regulation, as measured at the FB pin.
The thresholds are specified in the Electrical
Specifications section. PGOOD does not assert HIGH
until soft start is complete (T1.0).
These two fault conditions are allowed to set the fault
latch at any time, including during soft-start.
Over-Temperature Protection
Application Information
The chip incorporates an over-temperature-protection
circuit that sets the fault latch when a die temperature of
about 155°C is reached. The IC is allowed to restart
when the die temperature falls below 125°C.
Setting the Output Voltage
After a fault, EN pin is discharged with 1 µA current pull
down to a 1.1 V threshold before the internal 800 kΩ pull
up is restored. A new soft-start cycle begins when EN
charges above 1.35 V.
The output voltage of the regulator can be set from
0.8 V to ~80% of VIN by an external resistor divider (R1
and RBIAS in Figure 1). For output voltages >3.3 V,
output current rating may need to be de-rated depending
on the ambient temperature, power dissipated in the
package and the PCB layout. (Refer to Thermal
Information table and Figure 29.)
Depending on the external circuit, the FAN21SV06 can
be configured to remain latched off or automatically
restart after a fault, as listed in Table 1.
The internal reference is set to 0.8 V with 650 nA
sourced from the FB pin to ensure that the regulator
does not start if the pin is left open.
EN / Auto-Restart
Table 1.
The external resistor divider is calculated using:
Fault / Restart Configurations
V
− 0 .8 V
0 .8 V
= OUT
+ 650nA
R BIAS
R1
(1)
EN pin
Controller / Restart State
Pull to GND
Standby
Connected to
5 V_Reg
No restart – latched OFF
Open
Immediate restart after fault
Setting the Clock Frequency
Cap to GND
New soft-start cycle after:
EN is HIGH (Auto Restart Mode)
Oscillator frequency is determined by a resistor, RT, that is
connected between the (RT)pin and AGND (Master Mode)
or 5 V_Reg (Slave Mode):
Connect RBIAS between FB and AGND.
With EN left open, restart is immediate.
f( KHz ) =
If auto-restart is not desired, tie the EN pin high with a
logic gate to keep the 1 µA current sink from discharging
EN to 1.1 V. Figure 31 shows one method to pull up EN
to VCC for a latch configuration.
10 6
( 65 • RT ) + 135
(2)
where RT is expressed in kΩ.
RT (KΩ ) =
(106 / f ) − 135
65
(3)
where frequency (f) is expressed in KHz. In slave mode,
the switching frequency is about 10% slower for the
same RT.
The regulator does not start if RT is open in Master
mode.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Under-Voltage Protection
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13
Typically the inductor value is chosen based on ripple
current (ΔIL) which is chosen between 10 to 35% of the
maximum DC load. Regulator designs that require fast
transient response use a higher ripple-current setting
while regulator designs that require higher efficiency
keep ripple current on the low side and operate at a
lower switching frequency.
ΔIL =
VOUT • (1 - D)
L•f
VRILIM = 10µA*RILIM
To calculate RILIM:
RILIM = VRILIM/ 10µA
(4)
VOUT • (1 - D)
ΔIL • f
RILIM = (VBOT + VRMPEAK)/ 10µA
(5)
As a starting point, set the internal ramp amplitude
(∆VRAMP) to 0.5 V. RRAMP is approximately:
RRAMP (KΩ ) =
18 x10 − 6 • VIN • f
(9)
RILIM = {0.96 + (ILOAD * RDSON *KT*8)} +
{D*(VIN – 1.8)/(fSW *0.03*RRAMP)}/10µA
Setting the Ramp-Resistor Value
(VIN − 1.8) • VOUT
(8)
The voltage VRILIM is made up of two components, VBOT
(which relates to the current through the low-side
MOSFET) and VRMPEAK (which relates to the peak
current through the inductor). Combining those two
voltage terms results in:
where f is the oscillator frequency, and
L=
(7)
−2
(10)
where:
VBOT = 0.96 + (ILOAD * RDSON *KT*8);
VRMPEAK = D*(VIN – 1.8)/(fSW *0.03*RRAMP);
(6)
ILOAD = the desired maximum load current;
where frequency (f) is expressed in KHz.
RDSON = the nominal RDSON of the low-side MOSFET;
Refer to AN-6033 — FAN21SV06 Design Guide to
determine the optimal RRAMP value.
KT = the normalized temperature coefficient for the
low-side MOSFET (on datasheet graph);
Setting the Current Limit
D = VOUT/VIN duty cycle;
The current limit system involves two comparators. The
MAX ILIMIT comparator is used with a VILIM fixed-voltage
reference and represents the maximum current limit
allowable. This reference voltage is temperature
compensated to reflect the RDSON variation of the lowside MOSFET. The ADJUST ILIMIT comparator is used
where the current limit needs to be set lower than the
VILIM fixed reference. The 10 µA current source does not
track the RDSON changes over temperature, so change is
added into the equations for calculating the ADJUST
ILIMIT comparator reference voltage, as is shown below.
Figure 32 shows a simplified schematic of the overcurrent system.
fSW = Clock frequency in kHz; and
RAMP
VERR
+
_
RRAMP = chosen ramp resistor value in kΩ.
After 16 consecutive, pulse-by-pulse, current-limit
cycles, the fault latch is set and the regulator shuts
down. Cycling VCC or EN restores operation after a
normal soft-start cycle (refer to the Auto-Restart
section).
The over-current protection fault latch is active during
the soft-start cycle. Use 1% resistor for RILIM.
Loop Compensation
The control loop is compensated using a feedback
network around the error amplifier. Figure 33 shows a
complete Type-3 compensation network. Type-2
compensation eliminates R3 and C3.
PWM
COMP
PWM
VCC
VILIM
+
_
MAX
ILIMIT
10µA
ILIM
+
_
ADJUST
ILIMIT
ILIMTRIP
RILIM
Figure 32. Current-Limit System Schematic
Figure 33. Compensation Network
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Since the ILIM voltage is set by a 10 µA current source
into the RILIM resistor, the basic equation for setting the
reference voltage is:
Calculating the Inductor Value
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14
RRAMP provides feedforward compensation for changes
in VIN. With a fixed RRAMP value, the modulator gain
increases as VIN is reduced, which could make it difficult
to compensate the loop. For low-input-voltage-range
designs (3 V to 8 V), RRAMP and the compensation
component values are going to be different as compared
to designs with VIN between 8 V and 24 V.
Figure 34. Synchronization Timing Diagram
Master/Slave Configuration
When first enabled, the IC determines if it is configured as
a master or slave for synchronization, depending on how
RT is connected.
Table 2. Master / Slave Configuration
RT to:
Master / Slave
GND
Master
5V_Reg
Slave, free-running
CLK Pin
Figure 35. Slave-CLK-Input Block Diagram
One or more slaves can be connected directly to a master
or system clock to achieve a 180o phase shift.
Output
Input
Slaves free-run in the absence of an external clock signal
input when RT is connected to 5 V_Reg, allowing
regulation to be maintained. It is not recommended to
leave RT open when running in slave mode to avoid
noise pick up on the clock pin.
Slave free-running frequency should be set at least 25%
lower than the incoming synchronizing pulse frequency.
Maximum synchronizing clock frequency is recommended
to be below 600 KHz.
Figure 36. Slaves with 180o Phase Shift
Since the synchronizing circuit utilizes a narrow reset
pulse, the actual phase delay is slightly more than 180o.
Synchronization
The FAN21SV06 is not intended for use in single-output,
multi-phase regulator applications.
The synchronization method employed by the
FAN21SV06 also provides the following features for
maximum flexibility.
PCB Layout
Good PCB layout and careful attention to temperature
rise is essential for reliable operation of the regulator.
Four-layer PCB with 2-ounce copper on the top and
bottom side and thermal vias connecting the layers is
recommended. Keep power traces wide and short to
minimize losses and ringing. Do not connect AGND to
PGND below the IC. Connect AGND pin to PGND at the
output OR to the PGND plane.
Synchronization to an external system clock
Multiple FAN21SV06s can be synchronized to a
single master or system clock
Independently programmable phase adjustment for
one or multiple slaves
Free-running capability in the absence of system
clock or, if the master is disabled/faulted, the slaves
can continue to regulate at a lower frequency
The FAN21SV06 master outputs an 85ns-wide clock
(CLK) signal, delayed 180o from its leading PWM edge.
This feature allows out-of-phase operation for the slaves,
thereby reducing the input capacitance requirements
when more than one converter is operating on the same
input supply. The leading SW-node edge is delayed
~40 ns from the rising PWM signal.
On a slave, synchronization is rising-edge triggered. The
CLK input pin has a 1.8 V threshold and a 200 µA current
source pull-up.
In Master mode, the clock signals go out after power-good
signal asserts high. Likewise, in Slave mode
synchronization to an external clock signal occurs after
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
Figure 37. Recommended PCB Layout
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
the power-good signal goes high. Until then, the converter
operates in free-run mode.
Since the FAN21SV06 employs summing current-mode
architecture, Type-2 compensation can be used for
many applications. For applications that require wide
loop bandwidth and/or use very low-ESR output
capacitors, Type-3 compensation may be required.
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15
2X
TOP VIEW
2X
RECOMMENDED LAND PATTERN
ALL VALUES TYPICAL EXCEPT WHERE NOTED
SIDE VIEW
SEATING
PLANE
OPTIONAL LEAD DESIGN
(LEADS# 1, 24 & 25 ONLY)
SCALE: 1.5X
A) DIMENSIONS ARE IN MILLIMETERS.
B) DIMENSIONS AND TOLERANCES PER
ASME Y14.5M, 1994
C) DIMENSIONS DO NOT INCLUDE MOLD
FLASH OR BURRS.
D) DESIGN BASED ON JEDEC MO-220
VARIATION WJHC
E) TERMINALS ARE SYMMETRICAL AROUND THE
X & Y AXIS EXCEPT WHERE DEPOPULATED.
F) DRAWING FILENAME: MKT-MLP25AREV3
BOTTOM VIEW
Figure 38. 5x6mm Molded Leadless Package (MLP)
Package drawings are provided as a service to customers considering Fairchild components. Drawings may change in any manner
without notice. Please note the revision and/or date on the drawing and contact a Fairchild Semiconductor representative to verify or
obtain the most recent revision. Package specifications do not expand the terms of Fairchild’s worldwide terms and conditions, specifically the
warranty therein, which covers Fairchild products.
Always visit Fairchild Semiconductor’s online packaging area for the most recent package drawings:
http://www.fairchildsemi.com/packaging/.
© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
Physical Dimensions
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16
FAN21SV06 — TinyBuck™ 6 A, 24 V Single-Input Integrated Synchronous Buck Regulator, Synchronization Capability
17
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© 2006 Fairchild Semiconductor Corporation
FAN21SV06 Rev. 1.0.3