CY62167EV30 MoBL® 16-Mbit (1M x 16 / 2M x 8) Static RAM Features • • • • TSOP I package configurable as 1M x 16 or as 2M x 8 SRAM Very high speed: 45 ns Wide voltage range: 2.20V–3.60V Ultra low standby power — Typical standby current: 1.5 µA — Maximum standby current: 12 µA • Ultra low active power • • • • — Typical active current: 2.2 mA @ f = 1 MHz Easy memory expansion with CE1, CE2, and OE features Automatic power down when deselected CMOS for optimum speed/power Offered in Pb-free 48-ball BGA and 48-pin TSOP I packages Functional Description[1] The CY62167EV30 is a high performance CMOS static RAM organized as 1M words by 16 bits / 2M words by 8 bits. This device features advanced circuit design to provide an ultra low active current. This is ideal for providing More Battery Life™ (MoBL®) in portable applications such as cellular telephones. The device also has an automatic power down feature that significantly reduces power consumption by 99% when addresses are not toggling. Place the device into standby mode when deselected (CE1 HIGH or CE2 LOW or both BHE and BLE are HIGH). The input and output pins (IO0 through IO15) are placed in a high-impedance state when: the device is deselected (CE1 HIGH or CE2 LOW), outputs are disabled (OE HIGH), both Byte High Enable and Byte Low Enable are disabled (BHE, BLE HIGH), or a write operation is in progress (CE1 LOW, CE2 HIGH and WE LOW). To write to the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Write Enable (WE) input LOW. If Byte Low Enable (BLE) is LOW, then data from IO pins (IO0 through IO7) is written into the location specified on the address pins (A0 through A19). If Byte High Enable (BHE) is LOW, then data from the IO pins (IO8 through IO15) is written into the location specified on the address pins (A0 through A19). To read from the device, take Chip Enables (CE1 LOW and CE2 HIGH) and Output Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then data from the memory location specified by the address pins will appear on IO0 to IO7. If Byte High Enable (BHE) is LOW, then data from memory will appear on IO8 to IO15. See the “Truth Table” on page 10 for a complete description of read and write modes. Logic Block Diagram 1M × 16 / 2M x 8 RAM Array SENSE AMPS A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 ROW DECODER DATA IN DRIVERS IO0–IO7 IO8–IO15 COLUMN DECODER Power Down Circuit CE1 A11 A12 A13 A14 A15 A16 A17 A18 A19 CE2 BHE BYTE BHE WE CE2 OE CE1 BLE BLE Note 1. For best practice recommendations, refer to the Cypress application note AN1064, SRAM System Guidelines. Cypress Semiconductor Corporation Document #: 38-05446 Rev. *C • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600 Revised June 04, 2007 [+] Feedback CY62167EV30 MoBL® Pin Configuration[2, 3, 4] 48-Ball FBGA Top View 1 2 3 4 5 6 BLE OE A0 A1 A2 CE2 A IO 8 BHE A3 A4 CE1 IO 0 B IO 9 IO 10 A5 A6 IO 1 IO 2 C VSS IO11 A17 A7 IO3 VCC D VCC IO 12 NC A16 IO 4 Vss E IO 14 IO 13 A14 A15 IO 5 IO 6 F IO 15 A19 A12 A13 WE IO 7 G A18 A8 A9 A10 A11 NC H 48-Pin TSOP I Top View A15 A14 A13 A12 A11 A10 A9 A8 A19 NC WE CE2 NC BHE BLE A18 A17 A7 A6 A5 A4 A3 A2 A1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 A16 BYTE Vss IO15/A20 IO7 IO14 IO6 IO13 IO5 IO12 IO4 Vcc IO11 IO3 IO10 IO2 IO9 IO1 IO8 IO0 OE Vss CE1 A0 Product Portfolio Power Dissipation Product Speed (ns) VCC Range (V) Operating ICC (mA) f = 1 MHz CY62167EV30LL Min Typ[5] Max 2.20 3.0 3.60 45 Standby ISB2 (µA) f = fmax Typ[5] Max Typ[5] Max Typ[5] Max 2.2 4.0 25 30 1.5 12 Notes 2. NC pins are not connected on the die. 3. The BYTE pin in the 48-TSOPI package has to be tied to VCC to use the device as a 1M X 16 SRAM. The 48-TSOPI package can also be used as a 2M X 8 SRAM by tying the BYTE signal to VSS. In the 2M x 8 configuration, Pin 45 is A20, while BHE, BLE and IO8 to IO14 pins are not used. 4. Ball H6 for the FBGA package can be used to upgrade to a 32M density. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ), TA = 25°C. Document #: 38-05446 Rev. *C Page 2 of 13 [+] Feedback CY62167EV30 MoBL® DC Input Voltage[6, 7] .......... –0.3V to 3.9V (VCC(max) + 0.3V Maximum Ratings Exceeding the maximum ratings may impair the useful life of the device. These user guidelines are not tested. Storage Temperature ................................ –65°C to + 150°C Output Current into Outputs (LOW) ............................ 20 mA Static Discharge Voltage........................................... >2001V (MIL-STD-883, Method 3015) Latch up Current...................................................... >200 mA Ambient Temperature with Power Applied............................................ –55°C to + 125°C Operating Range Supply Voltage to Ground Potential .............................. –0.3V to 3.9V (VCC(max) + 0.3V Device DC Voltage Applied to Outputs in High Z State[6, 7] .............. –0.3V to 3.9V (VCC(max) + 0.3V Range Ambient Temperature VCC[8] CY62167EV30LL Industrial –40°C to +85°C 2.2V to 3.6V Electrical Characteristics Over the Operating Range Parameter Description VOH Output HIGH Voltage VOL Output LOW Voltage VIH Input HIGH Voltage VIL Input LOW Voltage Test Conditions 45 ns Min Typ[5] Unit Max 2.2 < VCC < 2.7 IOH = –0.1 mA 2.0 2.7 < VCC < 3.6 IOH = –1.0 mA 2.4 2.2 < VCC < 2.7 IOL = 0.1 mA 0.4 V 2.7 < VCC < 3.6 IOL = 2.1mA 0.4 V 1.8 VCC + 0.3V V 2.7 < VCC < 3.6 2.2 VCC + 0.3V V 2.2 < VCC < 2.7 –0.3 0.6 V –0.3 0.8 V 2.2 < VCC < 2.7 2.7 < VCC < 3.6 For FBGA package For TSOP I package V V [9] –0.3 V 0.7 IIX Input Leakage Current GND < VI < VCC –1 +1 µA IOZ Output Leakage Current GND < VO < VCC, Output Disabled –1 +1 µA ICC VCC Operating Supply Current f = fMAX = 1/tRC 25 30 mA 2.2 4.0 mA VCC = VCC(max) IOUT = 0 mA CMOS levels f = 1 MHz ISB1 Automatic CE Power Down CE1 > VCC − 0.2V or CE2 < 0.2V Current—CMOS Inputs VIN > VCC − 0.2V, VIN < 0.2V, f = fMAX (Address and Data Only), f = 0 (OE, WE, BHE and BLE), VCC = 3.60V 1.5 12 µA ISB2[10] Automatic CE Power Down CE1 > VCC − 0.2V or CE2 < 0.2V, Current—CMOS Inputs VIN > VCC − 0.2V or VIN < 0.2V, f = 0, VCC = 3.60V 1.5 12 µA Capacitance[11] Parameter Description CIN Input Capacitance COUT Output Capacitance Test Conditions TA = 25°C, f = 1 MHz, VCC = VCC(typ) Max Unit 10 pF 10 pF Notes 6. VIL(min) = –2.0V for pulse durations less than 20 ns. 7. VIH(max) = VCC + 0.75V for pulse durations less than 20 ns. 8. Full Device AC operation assumes a 100 µs ramp time from 0 to VCC (min) and 200 µs wait time after VCC stabilization. 9. Under DC conditions the device meets a VIL of 0.8V. However, in dynamic conditions Input LOW Voltage applied to the device must not be higher than 0.7V. This is applicable to TSOP I package only. 10. Only chip enables (CE1 and CE2), byte enables (BHE and BLE) and BYTE need to be tied to CMOS levels to meet the ISB2 / ICCDR spec. Other inputs can be left floating. 11. Tested initially and after any design or process changes that may affect these parameters. Document #: 38-05446 Rev. *C Page 3 of 13 [+] Feedback CY62167EV30 MoBL® Thermal Resistance[11] Parameter Description Test Conditions ΘJA Thermal Resistance (Junction to Ambient) ΘJC Thermal Resistance (Junction to Case) Still Air, soldered on a 3 × 4.5 inch, two-layer printed circuit board BGA TSOP I Unit 55 60 °C/W 16 4.3 °C/W AC Test Loads and Waveforms R1 VCC OUTPUT VCC 30 pF GND R2 10% ALL INPUT PULSES 90% 90% 10% Fall Time = 1 V/ns Rise Time = 1 V/ns INCLUDING JIG AND SCOPE Equivalent to: THÉVENIN EQUIVALENT RTH OUTPUT V Parameters 2.2V to 2.7V 2.7V to 3.6V Unit R1 16667 1103 Ω R2 15385 1554 Ω RTH 8000 645 Ω VTH 1.20 1.75 V Data Retention Characteristics Over the Operating Range Parameter Description Conditions VDR VCC for Data Retention ICCDR[10] Data Retention Current tCDR[11] Chip Deselect to Data Retention Time tR[12] Operation Recovery Time Min Typ[5] Max Unit 10 µA 1.5 V VCC = 1.5V, CE1 > VCC − 0.2V, CE2 < 0.2V, VIN > VCC − 0.2V or VIN < 0.2V 0 ns tRC ns Data Retention Waveform[13] VCC VCC(min) tCDR DATA RETENTION MODE VDR > 1.5 V VCC(min) tR CE1 or BHE.BLE or CE2 Notes 12. Full device operation requires linear VCC ramp from VDR to VCC(min) > 100 µs or stable at VCC(min) > 100 µs. 13. BHE.BLE is the AND of both BHE and BLE. Chip can be deselected by either disabling the chip enable signals or by disabling both BHE and BLE. Document #: 38-05446 Rev. *C Page 4 of 13 [+] Feedback CY62167EV30 MoBL® Switching Characteristics Over the Operating Range[14, 15] Parameter Description 45 ns Min Max Unit READ CYCLE tRC Read Cycle Time tAA Address to Data Valid tOHA Data Hold from Address Change tACE CE1 LOW and CE2 HIGH to Data Valid 45 ns tDOE OE LOW to Data Valid 22 ns tLZOE OE LOW to LOW Z[16] 45 45 10 OE HIGH to High Z ns 18 Z[16] tLZCE CE1 LOW and CE2 HIGH to Low tHZCE CE1 HIGH and CE2 LOW to High Z[16, 17] tPU CE1 LOW and CE2 HIGH to Power Up tPD CE1 HIGH and CE2 LOW to Power Down tDBE BLE / BHE LOW to Data Valid tLZBE BLE / BHE LOW to Low Z[16] tHZBE BLE / BHE HIGH to HIGH Z[16, 17] ns ns 5 [16, 17] tHZOE ns 10 ns ns 18 0 ns ns 45 45 10 ns ns ns 18 ns [18] WRITE CYCLE tWC Write Cycle Time 45 ns tSCE CE1 LOW and CE2 HIGH to Write End 35 ns tAW Address Setup to Write End 35 ns tHA Address Hold from Write End 0 ns tSA Address Setup to Write Start 0 ns tPWE WE Pulse Width 35 ns tBW BLE / BHE LOW to Write End 35 ns tSD Data Setup to Write End 25 ns tHD Data Hold from Write End 0 tHZWE WE LOW to High-Z[16, 17] tLZWE WE HIGH to Low-Z [16] ns 18 10 ns ns Notes 14. Test conditions for all parameters other than tri-state parameters assume signal transition time of 1 V/ns, timing reference levels of VCC(typ)/2, input pulse levels of 0 to VCC(typ), and output loading of the specified IOL/IOH as shown in “AC Test Loads and Waveforms” on page 4. 15. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. See application note AN13842 for further clarification. 16. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZBE is less than tLZBE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 17. tHZOE, tHZCE, tHZBE, and tHZWE transitions are measured when the outputs enter a high impedance state. 18. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE or BLE or both = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input setup and hold timing should be referenced to the edge of the signal that terminates the write. Document #: 38-05446 Rev. *C Page 5 of 13 [+] Feedback CY62167EV30 MoBL® Switching Waveforms Figure 1 shows address transition controlled read cycle waveforms.[19, 20] Figure 1. Read Cycle No. 1 tRC RC ADDRESS tOHA DATA OUT tAA PREVIOUS DATA VALID DATA VALID Figure 2 shows OE controlled read cycle waveforms.[20, 21] Figure 2. Read Cycle No. 2 ADDRESS tRC CE1 tPD tHZCE CE2 tACE BHE/BLE tDBE tHZBE tLZBE OE tHZOE tDOE DATA OUT tLZOE HIGH IMPEDANCE HIGH IMPEDANCE DATA VALID tLZCE VCC SUPPLY CURRENT tPU 50% 50% ICC ISB Notes 19. The device is continuously selected. OE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. 20. WE is HIGH for read cycle. 21. Address valid before or similar to CE1, BHE, BLE transition LOW and CE2 transition HIGH. Document #: 38-05446 Rev. *C Page 6 of 13 [+] Feedback CY62167EV30 MoBL® Switching Waveforms (continued) Figure 3 shows WE controlled write cycle waveforms.[18, 22, 23] Figure 3. Write Cycle No. 1 tWC ADDRESS tSCE CE1 CE2 tAW tHA tSA WE tPWE tBW BHE/BLE OE tHD tSD DATA IO NOTE 24 VALID DATA tHZOE Notes 22. Data IO is high impedance if OE = VIH. 23. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state. 24. During this period the IOs are in output state. Do not apply input signals. Document #: 38-05446 Rev. *C Page 7 of 13 [+] Feedback CY62167EV30 MoBL® Switching Waveforms (continued) Figure 4 shows CE1 or CE2 controlled write cycle waveforms.[18, 22, 23] Figure 4. Write Cycle No. 2 tWC ADDRESS tSCE CE1 CE2 tSA tAW tHA tPWE WE tBW BHE/BLE OE DATA IO tHD tSD NOTE 24 VALID DATA tHZOE Figure 5 shows WE controlled, OE LOW write cycle waveforms.[23] Figure 5. Write Cycle No. 3 tWC ADDRESS tSCE CE1 CE2 tBW BHE/BLE tAW tSA tHA tPWE WE tSD DATA IO NOTE 24 VALID DATA tHZWE Document #: 38-05446 Rev. *C tHD tLZWE Page 8 of 13 [+] Feedback CY62167EV30 MoBL® Switching Waveforms (continued) Figure 6 shows BHE/BLE controlled, OE LOW write cycle waveforms.[23] Figure 6. Write Cycle No. 4 tWC ADDRESS CE1 CE2 tSCE tAW tHA tBW BHE/BLE tSA tPWE WE tSD DATA IO NOTE 24 Document #: 38-05446 Rev. *C tHD VALID DATA Page 9 of 13 [+] Feedback CY62167EV30 MoBL® Truth Table CE1 CE2 WE OE BHE BLE H X X X X X X L X X X X Inputs/Outputs Mode Power High Z Deselect/Power-Down Standby (ISB) High Z Deselect/Power Down Standby (ISB) X X X X H H High Z Deselect/Power Down Standby (ISB) L H H L L L Data Out (IO0–IO15) Read Active (ICC) L H H L H L Data Out (IO0–IO7); High Z (IO8–IO15) Read Active (ICC) L H H L L H High Z (IO0–IO7); Data Out (IO8–IO15) Read Active (ICC) L H H H L H High Z Output Disabled Active (ICC) L H H H H L High Z Output Disabled Active (ICC) L H H H L L High Z Output Disabled Active (ICC) L H L X L L Data In (IO0–IO15) Write Active (ICC) L H L X H L Data In (IO0–IO7); High Z (IO8–IO15) Write Active (ICC) L H L X L H High Z (IO0–IO7); Data In (IO8–IO15) Write Active (ICC) Ordering Information Speed (ns) 45 Ordering Code Package Diagram Package Type CY62167EV30LL-45BVXI 51-85150 48-ball Fine Pitch Ball Grid Array (Pb-free) CY62167EV30LL-45ZXI 51-85183 48-pin TSOP I (Pb-free) Document #: 38-05446 Rev. *C Operating Range Industrial Page 10 of 13 [+] Feedback CY62167EV30 MoBL® Package Diagrams Figure 7. 48-Ball VFBGA (6 x 8 x 1 mm), 51-85150 BOTTOM VIEW TOP VIEW A1 CORNER Ø0.05 M C Ø0.25 M C A B A1 CORNER Ø0.30±0.05(48X) 2 3 4 5 6 6 5 4 3 2 1 C C E F G D E 2.625 D 0.75 A B 5.25 A B 8.00±0.10 8.00±0.10 1 F G H H A 1.875 A B 0.75 6.00±0.10 3.75 6.00±0.10 0.10 C 0.21±0.05 0.25 C 0.55 MAX. B 0.15(4X) Document #: 38-05446 Rev. *C 1.00 MAX 0.26 MAX. SEATING PLANE C 51-85150-*D Page 11 of 13 [+] Feedback CY62167EV30 MoBL® Package Diagrams (continued) Figure 8. 48-Pin TSOP I (12 mm x 18.4 mm x 1.0 mm), 51-85183 DIMENSIONS IN INCHES[MM] MIN. MAX. JEDEC # MO-142 0.037[0.95] 0.041[1.05] N 1 0.020[0.50] TYP. 0.472[12.00] 0.007[0.17] 0.011[0.27] 0.002[0.05] 0.006[0.15] 0.724 [18.40] 0.047[1.20] MAX. SEATING PLANE 0.004[0.10] 0.787[20.00] 0.004[0.10] 0.008[0.21] 0.010[0.25] GAUGE PLANE 0°-5° 0.020[0.50] 0.028[0.70] 51-85183-*A Document #: 38-05446 Rev. *C Page 12 of 13 [+] Feedback CY62167EV30 MoBL® Document History Page Document Title: CY62167EV30 MoBL® 16-Mbit (1M x 16 / 2M x 8) Static RAM Document Number: 38-05446 REV. ECN NO. Issue Date Orig. of Change ** 202600 01/23/04 AJU New Data Sheet *A 463674 See ECN NXR Converted from Advance Information to Preliminary Removed ‘L’ bin and 35 ns speed bin from product offering Modified Data sheet to include x8 configurability. Changed ball E3 in FBGA pinout from DNU to NC Changed the ISB2(Typ) value from 1.3 µA to 1.5 µA Changed the ICC(Max) value from 40 mA to 25 mA Changed Vcc stabilization time in footnote #9 from 100 µs to 200 µs Changed the AC Test Load Capacitance value from 50 pF to 30 pF Corrected typo in Data Retention Characteristics (tR) from 100 µs to tRC ns Changed tOHA, tLZCE, tLZBE, and tLZWE from 6 ns to 10 ns Changed tLZOE from 3 ns to 5 ns. Changed tHZOE, tHZCE, tHZBE, and tHZWE from 15 ns to 18 ns Changed tSCE, tAW, and tBW from 40 ns to 35 ns Changed tPE from 30 ns to 35 ns Changed tSD from 20 ns to 25 ns Updated 48 ball FBGA Package Information. Updated the Ordering Information table *B 469169 See ECN NSI Minor Change: Moved to external web *C 1130323 See ECN VKN Converted from preliminary to final Changed ICC max spec from 2.8 mA to 4.0 mA for f=1MHz Changed ICC typ spec from 22 mA to 25 mA for f=fmax Changed ICC max spec from 25 mA to 30 mA for f=fmax Added VIL spec for TSOP I package and footnote# 9 Added footnote# 10 related to ISB2 and ICCDR Changed ISB1 and ISB2 spec from 8.5 µA to 12 µA Changed ICCDR spec from 8 µA to 10 µA Added footnote# 15 related to AC timing parameters Document #: 38-05446 Rev. *C Description of Change Page 13 of 13 [+] Feedback