TI1 OPA569AIDWPR Rail-to-rail i/o, 2a power amplifier Datasheet

OPA
56 9
OPA569
SBOS264A – DECEMBER 2002 – REVISED DECEMBER 2003
Rail-to-Rail I/O, 2A
POWER AMPLIFIER
FEATURES
DESCRIPTION
●
●
●
●
●
HIGH OUTPUT CURRENT: 2A
OUTPUT SWINGS TO: 150mV of Rails with IO = 2A
THERMAL PROTECTION
ADJUSTABLE CURRENT LIMIT
TWO FLAGS: Current Limit and Temperature
Warning
The OPA569 is a low-cost, high-current, operational amplifier
designed for driving a wide variety of loads while operating on
low-voltage supplies. It operates from either single or dual
supplies for design flexibility and has rail-to-rail swing on the
input and output. Typical output swing is within 150mV of the
supply rails, with output current of 2A. Output swing closer to
the rails is achievable with lighter loads.
● LOW SUPPLY VOLTAGE OPERATION: 2.7V to 5.5V
● SHUTDOWN FUNCTION WITH OUTPUT DISABLE
● SMALL POWER PACKAGE: SO-20 PowerPAD™
The OPA569 is unity-gain stable, has low dc errors, is easy
to use, and free from the phase inversion problems found in
some power amplifiers. High performance is maintained at
voltage swings near the output rails.
APPLICATIONS
The OPA569 provides an accurate user-selected current
limit that is set with an external resistor, or digitally adjusted
via a Digital-to-Analog Converter.
●
●
●
●
●
●
THERMOELECTRIC COOLER DRIVER
LASER DIODE PUMP DRIVER
VALVE, ACTUATOR DRIVER
SYNCHRO, SERVO DRIVER
TRANSDUCER EXCITATION
GENERAL LINEAR POWER BOOSTER FOR
OP AMPS
● PARALLELING OPTION FOR HIGHER
CURRENT APPLICATIONS
Current
Thermal Limit
Flag Enable
Flag
V+
7
5
(1)
4
8
2
OPA569
19
+In
6
17, 18
3
Current
Limit
Set
Two flags are provided: one for warning of thermal overstress, and one for current limit condition. The Thermal Flag
pin can be connected to the Enable pin to provide a thermal
shutdown solution.
Parallel Out 1
14, 15
9
VO
Parallel Out 2
I = IO/475
NOTE: (1) Connect
for thermal protection.
RSET
V–
The IMONITOR pin provides a 1:475 bidirectional copy of the
output current. This eliminates the need for a series current
shunt resistor, allowing more voltage to be applied to the
load. This pin can be used for simple monitoring, or feedback
control to establish constant output current.
Packaged in the Texas Instruments PowerPAD™ package,
it is small and easy to heat-sink. The OPA569 is specified for
operation over the industrial temperature range, –40°C to
+85°C.
12,13
–In
The OPA569 output can be independently disabled using the
Enable pin, saving power and protecting the load.
IMONITOR
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PowerPAD is a trademark of Texas Instruments. All other trademarks are the property of their respective owners.
Copyright © 2002-2003, Texas Instruments Incorporated
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
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ABSOLUTE MAXIMUM RATINGS(1)
Supply Voltage ................................................................................. +7.5V
Output Current ............................................................... See SOA Curves
Signal Input Terminals (pins 2, 5, 6, and 9):
Voltage(2) ............................................... (V–) – 0.5V to (V+) + 0.5V
Current(2) ................................................................................ ±10mA
Output Short-Circuit(3) ........ Continuous when thermal protection enabled
Current Monitor (pin 19) Short-Circuit ..................................... Continuous
Enable Pin (pin 8) .......................................... (V–) – 0.5V to (V–) + 7.5V
PowerPAD (pins 1, 10, 11, 20, and pad) ...... (V–) – 0.5V to (V–) + 0.5V
Current Limit Set (pin 3) ................................. (V–) – 0.5V to (V+) + 0.5V
Operating Temperature .................................................. –55°C to +125°C
Storage Temperature ..................................................... –65°C to +150°C
Junction Temperature .................................................................... +150°C
Lead Temperature (soldering, 10s) ............................................... +300°C
ELECTROSTATIC
DISCHARGE SENSITIVITY
This integrated circuit can be damaged by ESD. Texas
Instruments recommends that all integrated circuits be handled
with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits
may be more susceptible to damage because very small
parametric changes could cause the device not to meet its
published specifications.
NOTE: (1) Stresses above these ratings may cause permanent damage.
Exposure to absolute maximum conditions for extended periods may degrade device reliability. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those specified is
not implied. (2) Input terminals are diode-clamped to the power-supply rails.
Input signals that can swing more than 0.5V beyond the supply rails should
be current limited to 10mA or less. (3) Short-circuit to ground.
PACKAGE/ORDERING INFORMATION
For the most current package and ordering information, see
the Package Option Addendum located at the end of this
data sheet.
PIN CONFIGURATION
PIN DESCRIPTIONS
Top View
PIN #
NAME
1, 10, 11, 20
PowerPAD
2
Parallel Out 1
SO
OPA569
PowerPAD(1)
1
20 PowerPAD(1)
Parallel Out 1
2
19 IMONITOR
Current Limit Set
3
Current Limit Flag
4
–In
5
+In
6
Thermal Flag
7
Enable
Parallel Out 2
18 V–(3)
Metal
PowerPAD
Heat Sink
(Located
on
bottom
side)
15 VO(3)
Connection for Paralleling Multiple
Amplifiers
3
Current Limit Set
Current Limit Set Pin
4
Current Limit Flag
Indicates When Part is in Current
Limit (Active LOW).
5
–In
6
+In
7
Thermal Flag
Indicates Thermal Stress (Active
LOW)
8
Enable
Enabled HIGH. Shut down LOW.
9
Parallel Out 2
Connection for Paralleling Multiple
Amplifiers
17 V–(3)
16 NC(2)
DESCRIPTION
PowerPAD Connection Pins
Inverting Input
Noninverting Input
12, 13
V+
14 VO(3)
14, 15
VO
Output
8
13 V+(3)
16
NC
No Internal Connection
9
12 V+(3)
PowerPAD(1) 10
11 PowerPAD(1)
17, 18
V–
19
IMONITOR
Positive Power-Supply Voltage
Negative Power-Supply Voltage
Provides 1:475 Bidirectional Copy
of Output Current.
NOTES: (1) PowerPAD pins 1, 10, 11, and 20 and the
PowerPAD should be connected to the most negative
supply (V–) in either single or split supply configurations.
(2) NC means no internal connection.
(3) The following pin pairs must be connected together:
12 and 13; 14 and 15; 17 and 18.
2
OPA569
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SBOS264A
ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TCASE = +25°C, RL = 1kΩ, and connected to VS /2, unless otherwise noted.
OPA569
PARAMETER
OFFSET VOLTAGE
Input Offset Voltage
vs Temperature
vs Power Supply
CONDITION
VOS
dVOS /dT
PSRR
INPUT BIAS CURRENT
Input Bias Current
vs Temperature
Input Offset Current
IO = 0V, VS = +5V
TA = –40°C to +85°C
VS = +2.7V to +5.5V, VCM = (V–) +0.55V
IOS
in
Linear Operation
VS = +5V, –0.1V < VCM < 3.2V
VS = +5V, –0.1V < VCM < 5.1V
(V–) – 0.1
80
60
INPUT IMPEDANCE
Differential
Common-Mode
OPEN-LOOP GAIN
Open-Loop Voltage Gain
FREQUENCY RESPONSE
Gain Bandwidth Product
Slew Rate
Full-Power Bandwidth(1)
Settling Time: ±0.1%
Total Harmonic Distortion + Noise(2)
AOL
GBW
SR
Maximum Continuous Current Output: dc (4)
Capacitive Load Drive (5)
Output Disabled
Output Impedance
0.2V < VO < 4.8V, RL = 1kΩ, VS = +5V
0.3V < VO < 4.7V, RL = 1.15Ω, VS = +5V
100
G = +1, VO = 4.0V Step
G = –1, VO = 4.0V Step
THD+N
OUTPUT
Voltage Output Swing from Rail
VO
MAX
UNITS
±0.5
±2
12
60
mV
µV/°C
µV/V
±1
(doubles every 10°C)
±2
±10
pA
±10
pA
12
8
0.6
en
VCM
CMRR
TYP
±1.3
IB
NOISE
Input Voltage Noise Density, f = 1kHz
f = 0.1Hz to 10Hz
Current Noise Density, f = 1kHz
INPUT VOLTAGE RANGE
Common-Mode Voltage Range
Common-Mode Rejection Ratio
MIN
RL = 1kΩ, AOL > 100dB
IO = ±2A, VS = +5V, AOL > 80dB (3)
CLOAD
(V–) + 0.2
(V–) + 0.3
nV/√Hz
µVp-p
fA/√Hz
100
80
(V+) + 0.1
V
dB
dB
1013 || 4.5
1013 || 9
Ω || pF
Ω || pF
126
90
dB
dB
1.2
1.2
See Typical Characteristics
5
See Typical Characteristics
MHz
V/µs
(VS) ± 0.02
(VS) ± 0.15
µs
(V+) – 0.2
(V+) – 0.3
2.4
V
V
A
See Typical Characteristics
12M || 570
Ω || pF
±0.2 to ±2.2
ILIMIT = ISET • 9800
RSET = 9800 (1.18V/ILIMIT)
±3
±10
±3
±15
(V–) + 1.05
(V–) + 1.18
(V–) + 1.3
A
A
Ω
%
%
V
IM = IO /475
±3
±10
±3
±15
See Discussion on Current Monitor Section
A
%
%
CURRENT LIMIT
Output Current Limit (6)
Current Limit Equation
RSET Equation
Current Limit Tolerance (7), Positive
Negative
Voltage on Current Limit Set Pin Tolerance (8)
OUTPUT CURRENT MONITOR (Pin 19)
Output Current Monitor
Output Current Monitor Tolerance (9), Positive
Negative
Compliance Voltage Range
Externally Adjustable
ILIMIT = 1A
ILIMIT = 1A
IM
IO = +1A, RMONITOR = 400Ω
IO = –1A, RMONITOR = 400Ω
Linear Operation
NOTES: (1) See typical characteristic “Maximum Output Voltage vs Frequency.” (2) See the typical characteristic “Total Harmonic Distortion + Noise vs Frequency.”
(3) Swing to the rail is measured in final test. Under those conditions, the AOL is derived from characterization. (4) See Safe Operating Area (SOA) plots. (5) See typical
characteristic, “Overshoot vs Load Capacitance.” (6) External current limit setting resistor is required. See Figure 1. (7) ILIMIT is the value of the desired current limit
and is equal to 9800 (ISET), where ISET is the current through the Current Limit Set pin (pin 3). Errors from this parameter can be calibrated out—see Applications
Information section. (8) VSET is a voltage reference that equals the difference between the voltage of the Current Limit Set pin and V–, and is referenced to the negative
rail. Errors from this parameter can be calibrated out—see Applications Information section. (9) % Tolerance = [(IOUT/475) – IMONITOR] • 100/IMONITOR.
OPA569
SBOS264A
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3
ELECTRICAL CHARACTERISTICS: VS = +2.7V to +5.5V (Cont.)
Boldface limits apply over the specified temperature range, TA = –40°C to +85°C.
At TCASE = +25°C, RL = 1kΩ, and connected to VS /2, unless otherwise noted.
OPA569
PARAMETER
ENABLE/SHUTDOWN INPUT (Pin 8)
Enable Pin Bias Current
HIGH (Output enabled)
LOW (Output disabled)
Output Disable Time
Output Enable Time
CONDITION
VSD
VSD
THERMAL FLAG PIN (Pin 7)
Junction Temperature:
TJ
Alarm (Thermal Flag pin LOW)
Return to Normal Operation (Thermal Flag pin HIGH)
Thermal Flag Pin Voltage
CURRENT LIMIT FLAG PIN (Pin 4)
Current Limit Flag Pin Voltage
POWER SUPPLY
Specified Voltage Range
Operating Voltage Range
Quiescent Current(10)
Thermal Overstress
Normal Operation
Normal Operation Ipin 7 = +25µA
During Thermal Overstress, Ipin 7 = –25µA
Normal Operation, Ipin 4 = +25µA
During Current Limit, Ipin 4 = –25µA
VS
IQ
Quiescent Current in Shutdown Mode
TEMPERATURE RANGE
Specified Range
Operating Range
Storage Range
Thermal Resistance, Junction-to-Case
Thermal Resistance, Junction-to-Ambient
VSD = 0V
Pin Open or Forced HIGH
Pin Forced LOW
RL = 1Ω
RL = 1Ω
TYP
MAX
UNITS
(V–) + 0.8
0.5
15
µA
V
V
µs
µs
+147
+130
V+
V–
(V–) + 0.8
°C
°C
V
V
V+
V–
(V–) + 0.8
V
V
0.2
(V–) + 2.5
(V+) – 0.8V
(V+) – 0.8V
+2.7
+2.7
IO = 0, ILIMIT = 200mA, VS = 5V
IO = 0, ILIMIT = 2A, VS = 5V
IO = 0, VSD = 0.8V, VS = 5V
Junction Temperature
Junction Temperature
θJC
θJA
MIN
2oz Trace and 9in2 Copper Pad
with Solder
+3.4
+9
+0.01
–40
–55
–65
+5.5
+5.5
+6
+11
V
V
mA
mA
mA
+85
+125
+150
°C
°C
°C
°C/W
°C/W
0.37
21.5
NOTE: (10) Quiescent current is a function of the current limit setting. See application section, “Adjustable Current Limit and Current Limit Flag Pin.”
4
OPA569
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SBOS264A
TYPICAL CHARACTERISTICS
At TA = +25°C, VS = +5V, unless otherwise noted.
POWER-SUPPLY AND COMMON-MODE
REJECTION RATIO vs FREQUENCY
0
160
–20
140
–40
120
–60
100
–80
80
–100
60
–120
40
–140
20
–160
0
–180
CMRR
100
0.1
1
10
100
1k
10k
100k
1M
60
40
0
1
10M
100
1k
10k
OUTPUT SWING TO POSITIVE RAIL
vs SUPPLY VOLTAGE
OUTPUT SWING TO NEGATIVE RAIL
vs SUPPLY VOLTAGE
250
250
Swing to Rail (mV)
300
IOUT = 2A
150
IOUT = 1A
100
10
Frequency (Hz)
300
200
PSRR
Frequency (Hz)
IOUT = 200mA
50
100k
IOUT = –2A
200
150
IOUT = –1A
100
50
IOUT = –200mA
0
0
2.7
3.0
3.5
4.0
4.5
5.0
5.5
2.7
3.0
3.5
4.0
4.5
5.0
Supply Voltage (V)
Supply Voltage (V)
OUTPUT SWING TO POSITIVE RAIL
vs TEMPERATURE
OUTPUT SWING TO NEGATIVE RAIL
vs TEMPERATURE
300
5.5
300
250
250
VS = 2.7V, IO = 2A
Swing to Rail (mV)
Swing to Rail (mV)
80
20
–200
–20
Swing to Rail (mV)
120
PSRR and CMRR (dB)
180
Phase (°)
AOL (dB)
OPEN-LOOP GAIN AND PHASE vs FREQUENCY
200
VS = 5V, IO = 2A
150
VS = 2.7V, IO = 1A
100
VS = 5V, IO = 1A
50
VS = 2.7V, IO = 200mA
VS = 5V, IO = 200mA
VS = 5V, IO = 2A
200
VS = 2.7V, IO = 2A
150
VS = 5V, IO = 1A
VS = 2.7V, IO = 1A
100
50
0
VS = 5V, IO = 200mA
VS = 2.7V, IO = 200mA
0
–55
–35
–15
5
25
45
65
85
–55
Temperature (°C)
–15
5
25
45
65
85
Temperature (°C)
OPA569
SBOS264A
–35
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5
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
INPUT VOLTAGE NOISE SPECTRAL DENSITY
vs FREQUENCY
0.1Hz TO 10Hz INPUT VOLTAGE NOISE
Input Voltage Noise (nV√Hz)
1000
1µV/div
100
10
1
10
100
1k
10k
1s/div
100k
Frequency (Hz)
TOTAL HARMONIC DISTORTION+NOISE
vs FREQUENCY
MAXIMUM OUTPUT VOLTAGE vs FREQUENCY
10
6
VS = 5V
RL = 1kΩ
1
4
RL = 1Ω
3
RL = 1kΩ
RL = 2Ω
THD+N (%)
Output Voltage (Vp-p)
5
0.1
RL = 8Ω
2
0.01
VS = 2.7V
1
RL = 1kΩ
RL = 1Ω
0.001
0
100
1k
10k
100k
20
1M
100
1k
10k 20k
Frequency (Hz)
Frequency (Hz)
QUIESCENT CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs SUPPLY VOLTAGE
10
10
8
Quiescent Current (mA)
Quiescent Current (mA)
Current Limit = 2A
Current Limit = 1A
6
Current Limit = 200mA
4
2
IQ (ILIMIT = 2A)
6
4
IQ (ILIMIT = 200mA)
2
0
0
2.7
3
3.5
4
4.5
5
5.5
–55
–35
–15
5
25
45
65
85
105
125
Temperature (°C)
Supply Voltage (V)
6
8
OPA569
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SBOS264A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
SHUTDOWN CURRENT vs TEMPERATURE
12
10
10
Shutdown Current (µA)
Shutdown Current (µA)
SHUTDOWN CURRENT vs SUPPLY VOLTAGE
12
8
ILIMIT = 200mA, 1A, and 2A
6
4
2
8
6
4
2
0
0
2.7
3
3.5
4
4.5
5
–55
5.5
–35
–15
5
Supply Voltage (V)
10
10000
8
1000
Input Bias Current (pA)
Quiescent Current (mA)
85
105
125
INPUT BIAS CURRENT vs TEMPERATURE
QUIESCENT CURRENT vs CURRENT LIMIT SETTING
6
4
2
100
10
1
0.1
0.01
0
0
0.5
1
1.5
2
2.5
–55
–35
–15
5
Current Limit Setting (A)
1.8
1.8
1.6
1.6
1.4
1.4
Slew Rate (V/µs)
2
SR–
1
0.8
SR+
0.6
45
65
85
105
125
SLEW RATE vs TEMPERATURE
2
1.2
25
Temperature (°C)
SLEW RATE vs LOAD RESISTANCE
Slew Rate (V/µs)
25
45
65
Temperature (°C)
1.2
1
0.8
0.6
0.4
0.4
0.2
0.2
0
SR+
SR–
0
1
10
100
1000
Load Resistance (Ω)
–35
–15
5
25
45
65
85
105
125
Temperature (°C)
OPA569
SBOS264A
–55
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7
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
VOLTAGE ON CURRENT LIMIT SET PIN
vs TEMPERATURE
VOLTAGE ON CURRENT LIMIT SET PIN
vs SUPPLY VOLTAGE
1.2
1.25
Current Limit = 200mA
1.2
[VSET – (V–)]
[VSET – (V–)] (V)
1.19
1.18
1.17
Current Limit = 1A
1.15
Current Limit = 2A
1.1
1.16
1.05
–55
–35
–15
5
25
45
65
85
105
125
2.7
Temperature (°C)
3
3.5
4
OFFSET VOLTAGE
PRODUCTION DISTRIBUTION
5
5.5
OFFSET VOLTAGE DRIFT
PRODUCTION DISTRIBUTION
Typical Production
Distribution of
Packaged Units.
–10
–9
–8
–7
–6
–5
–4
–3
–2
–1
0
1
2
3
4
5
6
7
8
9
10
Offset Voltage (mV)
Drift (µV/°C)
SMALL-SIGNAL STEP RESPONSE
(G = +1, RL = 1kΩ)
LARGE-SIGNAL STEP RESPONSE
(G = +1, RL = 1kΩ)
1V/div
50mV/div
–2
–1.8
–1.6
–1.4
–1.2
–1.0
–0.8
–0.6
–0.4
–0.2
0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2
Population
Population
Typical Production
Distribution of
Packaged Units.
10µs/div
8
4.5
Supply Voltage (V)
20µs/div
OPA569
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SBOS264A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
LARGE-SIGNAL STEP RESPONSE
(G = +1, RL = 10Ω)
1V/div
50mV/div
SMALL-SIGNAL STEP RESPONSE
(G = +1, RL = 10Ω)
20µs/div
SMALL-SIGNAL STEP RESPONSE
(G = +1, RL = 1Ω)
LARGE-SIGNAL STEP RESPONSE
(G = +1, RL = 1Ω)
1V/div
50mV/div
10µs/div
20µs/div
20µs/div
ENABLE
(10Ω Load)
ENABLE
(1Ω Load)
2V/div
2V/div
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Output Driven to +2V
1V/div
1V/div
Output Driven to +2V
10µs/div
4µs/div
OPA569
SBOS264A
Enable/Disable 0.8 to 2.5V
Above Negative Supply
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9
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
DISABLE
(1Ω Load)
2V/div
2V/div
DISABLE
(10Ω Load)
Enable/Disable 0.8 to 2.5V
Above Negative Supply
Output Driven
to +2V
1V/div
200ns/div
POWER ON
(1Ω Load)
POWER OFF
(1Ω Load)
5V/div
200ns/div
Supply 5V to 0V
1V/div
Supply 0V to 5V
Output Driven to +2V
Output Driven to +2V
1ms/div
IN AND OUT OF CURRENT LIMIT TRANSIENT
(RL = 0.75Ω, Current Limit = 2A)
IN AND OUT OF CURRENT LIMIT TRANSIENT
(RL = 7.5Ω, Current Limit = 200mA)
VOUT
(2V/div)
1ms/div
Current Limit Flag
(5V/div)
Current Limit Flag
(5V/div)
VOUT
(2V/div)
1V/div
5V/div
1V/div
Output Driven to +2V
200µs/div
200µs/div
10
Enable/Disable 0.8 to 2.5V
Above Negative Supply
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SBOS264A
TYPICAL CHARACTERISTICS (Cont.)
At TA = +25°C, VS = +5V, unless otherwise noted.
NO PHASE INVERSION WITH INPUTS
LARGER THAN SUPPLY VOLTAGE
(G = +1, RL = 10Ω)
OVERLOAD RECOVERY
(G = +1)
1V/div
1V/div
VIN
VOUT
VOUT
VIN
40µs/div
1ms/div
CURRENT MONITOR AND CURRENT LIMIT ERROR
vs SUPPLY VOLTAGE
CURRENT MONITOR AND CURRENT
LIMIT ERROR vs TEMPERATURE
15
15
10
ILIMIT–
Current Monitor and
Current Limit Error (%)
Current Monitor and
Current Limit Error (%)
10
ILIMIT+
5
0
IMONITOR–
IMONITOR+
–5
–10
IMONITOR–
0
ILIMIT+
ILIMIT–
–5
–10
–15
–15
2.7
3
3.5
4
4.5
5
5.5
–55
–35
–15
5
25
45
65
Supply Voltage (V)
Temperature (°C)
CURRENT MONITOR AND CURRENT LIMIT ERROR
vs OUTPUT CURRENT
OVERSHOOT vs LOAD CAPACITANCE
(G = +1, RL = 1kΩ)
15
85
50
10
IMONITOR–
5
0
40
ILIMIT–
IMONITOR+
Overshoot (%)
Current Monitor and
Current Limit Error (%)
IMONITOR+
5
ILIMIT+
–5
30
20
10
–10
–15
0
0.2
0.4
0.6
0.8
1
1.2
1.4
1.6
1.8
2
10
Output Current (A)
1k
10k
Load Capacitance (pF)
OPA569
SBOS264A
100
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11
APPLICATIONS INFORMATION
R1
R2
BASIC CONFIGURATION
V+
Figure 1 shows the OPA569 connected as a basic noninverting amplifier; however, the OPA569 can be used in
virtually any op amp configuration. A current limit setting
resistor (RSET, in Figure 1) is essential to the OPA569’s
operation, and cannot be omitted.
47µF
0.1µF
12,
13
5
Power-supply terminals should be bypassed with low series
impedance capacitors. Using a larger tantalum and smaller
ceramic type in parallel is recommended. Power-supply
wiring should have low series impedance.
VIN
6
47µF
17,
18
47µF
NOTES: (1) RSET sets the current
limit value from 0.2A to 2.2A.
RSET can be a potentiometer to
easily adjust current limit and
calibrate out errors at the current
limit node. (2) Enable—pull LOW
to disable output.
ADJUSTABLE CURRENT LIMIT AND CURRENT
LIMIT FLAG PIN
As illustrated in Figure 2, the simplest method of setting the
current limit is to connect a resistor or potentiometer between
Current
Limit Set
0.1µF
The OPA569 operates with excellent performance from a
single (+2.7V to +5.5V) supply or from dual supplies. Power
supply voltages do not need to be equal as long as the total
voltage remains below 5.5V. Parameters that vary significantly with operating voltage are shown in the typical characteristics section.
IMONITOR
RSET(1)
Enable(2)
Setting the current limit
VO
3 19
8
POWER SUPPLIES
The OPA569 provides over-current protection to the load
through its accurate, user-adjustable current limit (pin 3). The
current limit value, ILIMIT, can be set from 0.2A to 2.2A by
controlling the current through the Current Limit Set pin. The
current limit, ILIMIT, will be 9800 ISET; where ISET is the current
through the Current Limit Set pin. Setting the current limit
requires no special power resistors. The output current does
not flow through this pin.
14,
15
OPA569
RSET (Ω)
ILIMIT (A)
23.2k
11.5k
7.68k
5.76k
0.5
1.0
1.5
2.0
V–
FIGURE 1. Basic Connections.
the current limit set pin and V–, the negative supply, according to the formula:
ILIMIT = 9800 • (1.18V/RSET)
Alternatively, the output current limit can be set by applying
a voltage source in series with a resistance using the equation:
ILIMIT = 9800 • [(1.18V – VADJUST)/RSET]
The voltage source will be referenced to V–.
5
5
14,
15
14,
15
1.18V
6
1.18V
6
ILIMIT = 9800 (1.18V/RSET)
ILIMIT = 9800 (1.18V – VADJUST)
3
3
17,
18
RSET
17,
18
RPOT
RSET
VADJUST(1)
V–
V–
(a) Resistor or Potentiometer Method
(b) Resistor/Voltage Source Method
Putting a set resistor in series with the potentiometer
will prevent potential short-circuit on pin.
NOTE: (1) This voltage source must be able to
sink the current from the Current Limit Set pin,
which is ILIMIT/9800.
FIGURE 2. Setting the Current Limit—Resistor Method.
12
OPA569
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Current Limit Accuracy
CURRENT MONITOR
Internally separate circuits monitor the positive and negative
current limits. Each circuit output is compared to a single
internal reference that is set by the user with an external
resistor or a resistor/voltage source combination. The OPA569
employs a patented circuit technique to achieve an accurate
and stable current limit throughout the full output range. The
initial accuracy of the current limit is typically within 3%;
however, due to internal matching limitations, the error can
be as much as 15%. The variation of the current limit with
factors such as output current level, output voltage and
temperature is shown in the Typical Characteristics section.
The OPA569 features an accurate output current monitor
(IMONITOR) without requiring the use of series resistance with
the load. This increases efficiency significantly and provides
better overall swing-to-supply performance.
When the accuracy of one current limit (sourcing or sinking)
is more important than the other, it is possible to set its
accuracy to better than 1% by adjusting the external resistor
or the applied voltage. The accuracy of the other current limit
will still be affected by internal matching.
Some restrictions apply when using the current monitor
function. When the main amplifier is sourcing current, the
current monitor circuit must be sourcing current. Likewise,
when the main amplifier is sinking current, the current monitor circuit must also be sinking current. Additionally, the
swing on the IMONITOR pin is smaller than the output swing.
When the amplifier is sourcing current, the voltage of the
Current Monitor pin must be at least two hundred millivolts
less than the output voltage of the amplifier. Conversely,
when the amplifier is sinking current, the voltage of the
Current Monitor pin must be at least two hundred millivolts
greater than the output voltage of the amplifier. Resistive
loads are able to meet these restrictions. Other types of
loads may cause invalid current monitor values.
Current Limit Flag Pin
The OPA569 features a Current Limit Flag pin (pin 4) that
can be monitored to determine when the part is in current
limit. The output signal of the current limit flag pin is compatible to standard logic in single supply applications. The
output signal is a CMOS logic gate that switches from V+ to
V– to indicate that the amplifier is in current limit. This flag
output pin can source and sink up to 25µA. Additional
parasitic capacitance between pins 3 and 4 can cause
instability at the edge of the current limit. Avoid routing these
traces in parallel close to each other.
Quiescent Current Dependence on the
Current Limit Setting
The OPA569 is a low power amplifier, with a typical 3.4mA
quiescent current (with the current limit configured for 200mA).
The quiescent current varies with the current limit setting—
it increases 0.5mA for each additional 200mA increase in
the current limit, as shown in Figure 3.
An internal circuit creates a 1:475 copy of the output current.
This copy of the output current can be monitored independently or it can be used in applications such as current
control drive, setting non-symmetric positive and negative
current limits or paralleling two or more devices for increased
output current drive. When not being used, the Current
Monitor pin may be left floating.
A simple way to monitor the load current and meet these
requirements is to connect a resistor (with resistance less
than 400 • RL) from the IMONITOR pin to the same potential to
which the other side of the load is connected. Another
method is to use a transimpedance amplifier, as shown in
Figure 4. This circuit must assure that the potential of the
IMONITOR pin remains in the valid voltage range by connecting
it to the same potential to which the load is connected—most
likely ground for dual supply or mid-supply for single-supply
applications.
+2.5V
QUIESCENT CURRENT vs CURRENT LIMIT SETTING
12,
13
10
Quiescent Current (mA)
–In
5
8
OPA569
+In
14,
15
IO
VO
6
6
RL
19 IMONITOR
17,
18
4
–2.5V
2
IO/475
OPA348
VO = –1V
at IO = 1A
0
0
0.5
1
1.5
2
R = 475Ω
2.5
Current Limit Setting (A)
C
FIGURE 3. Quiescent Current vs Current Limit Setting.
FIGURE 4. Transimpedance Amplifier to Monitor Load
Current.
OPA569
SBOS264A
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13
The accuracy of the current copy is reduced with small output
currents. An internal circuit monitors the direction of the
output current and enables the positive or the negative
current monitoring circuitry accordingly. There is an approximate 20µs delay in the change of current direction. The
switching point is near quiescent conditions and may cause
current monitor inaccuracy with small output currents.
V+
(a) +5V
(b) HCT or TTL In
12,
13
5
6
OPA569
8
(1)
14,
15
VO
Enable
17,
18
ENABLE PIN—OUTPUT DISABLE
The Enable pin can disable the OPA569 within microseconds. When disabled, the amplifier draws less than 10µA and
its output enters a high-impedance state that allows multiplexing. It is important to note that when the amplifier is
disabled, the Thermal Flag pin circuitry continues to operate.
This feature allows use of the Thermal Flag pin output to
implement thermal protection strategies. For more details,
please see the section on thermal protection.
The OPA569 Enable pin has an internal pull-up circuit, so it
does not have to be connected to the positive supply for
normal operation. To disable the amplifier, the Enable pin
must be connected to no more than (V–) + 0.8V. To enable
the amplifier, either allow the Enable pin to float or connect
it to at least (V–) + 2.5V.
The Enable pin is referenced to the negative supply (V–).
Therefore, shutdown operation is slightly different in singlesupply and dual-supply applications.
In single-supply operation, V– typically equals common
ground, thus the enable/disable logic signal and the OPA569
Enable pin are referenced to the same potential. In this
configuration, the logic level and the OPA569 Enable pin can
simply be tied together. Disable occurs for voltage levels of
less than 0.8V. The OPA569 is enabled at logic levels
greater than 2.5V.
In dual-supply operation, the logic level is referenced to a
logic ground. However, the OPA569 Enable pin is still referenced to V–. To disable the OPA569, the voltage level of the
logic signal needs to be level-shifted. This can be done using
an optocoupler, as shown in Figure 5.
Examples of output behavior during disabled and enabled
conditions with various load impedances are shown in the
typical characteristics section. Please note that this behavior
is a function of board layout, load impedances and bypass
strategies. For sensitive loads, the use of a low-pass filter or
other protection strategy is recommended.
14
4N38
Optocoupler
V–
(a) HCT or
TTL In
(b)
NOTE: (1) Optional—may be required
to limit leakage current of optocoupler
at high temperatures.
FIGURE 5. OPA569 Shutdown Configuration for Dual
Supplies.
ENSURING MICROCONTROLLER COMPATIBILITY
Not all microcontrollers output the same logic state after
power-up or reset. 8051-type microcontrollers, for example,
output logic HIGH levels on their ports while other models
power up with logic LOW levels after reset.
In configuration (a) shown in Figure 5, the enable/disable
signal is applied on the cathode side of the photodiode within
the optocoupler. A logic HIGH level causes the OPA569 to
be enabled, and a logic LOW level disables the OPA569. In
configuration (b) of Figure 5, with the logic signal applied on
the anode side, a high level disables the OPA569 and a low
level enables the op amp.
RAIL TO RAIL OUTPUT RANGE
The OPA569 has a class AB output stage with common
source transistors that are used to achieve rail-to-rail output
swing. It was designed to be able to swing closer to the rail
than other existing linear amplifiers, even with high output
current levels. A quick way to estimate the output swing with
various output current requirements is by using the equation:
VSWING [typical] = 0.1 • IO
Plots of the Output Swing vs Output Current, Supply Voltage,
and Temperature are provided in the typical characteristics
section.
OPA569
www.ti.com
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RAIL TO RAIL INPUT RANGE
The input common-mode voltage range of the OPA569
extends 100mV beyond the supply rails. This is achieved by
a complementary input stage with an N-channel input differential pair in parallel with a P-channel differential pair. The
N-channel input pair is active for input voltages close to the
positive rail while the P-channel input pair is active for input
voltages close to the negative rail. The transition point is
typically at (V+) – 1.3V, and there is a small transition region
around the switching point where both transistors are on. It
is important to note that the two input pairs can have offsets
of different signs and magnitudes. Therefore, as the transition point is crossed, the offset of the amplifier changes. This
offset shift accounts for the reduced common-mode rejection
ratio over the full input common-mode range.
OUTPUT PROTECTION
Reactive and EMF-generating loads can return load current
to the amplifier, causing the output voltage to exceed the
power-supply voltage. This damaging condition can be
avoided with clamp diodes from the output terminal to the
power supplies, as shown in Figure 6. Schottky rectifier
diodes with a 3A or greater continuous rating are recommended.
THERMAL FLAG PIN
The OPA569 has thermal sensing circuitry that provides a
warning signal when the die temperature exceeds safe limits.
Unless the Thermal Flag is connected to the Enable pin,
when this flag is triggered, the part continues to operate even
+V
12,
13
–In
OPA569
+In
3
17,
18
14,
15
Current
Limit
Set
though the junction temperature exceeds 150°C. This allows
maximum usable operation in very harsh conditions but
degrades reliability. The Thermal Flag pin can be used to
provide for orderly system shutdown before failure occurs. It
can be also used to evaluate the thermal environment to
determine need for and appropriate design of a shutdown
mechanism.
The thermal flag output signal is from a CMOS logic gate that
switches from V+ to V– to indicate that the amplifier is in
thermal limit. This flag output pin can source and sink up to
25µA. The Thermal Flag pin is HIGH during normal operation. Power dissipated in the amplifier will cause the junction
temperature to rise. When the junction temperature exceeds
150°C, the Thermal Flag pin will go LOW, and remain LOW
until the amplifier has cooled to 130°C. Despite this hysteresis, with a method of orderly shutdown, the Thermal Flag
pin can cycle on and off, depending on load and signal
conditions. This limits the dissipation of the amplifier but may
have an undesirable effect on the load. This temperature
range exceeds the absolute maximum temperature rating
and is intended to protect the device from excessive temperatures that can cause damage. Brief and infrequent
excursions in this temperature range are likely to be tolerated, but are not recommended.
It is possible to connect the Thermal Flag pin directly to the
Enable pin for automatic shutdown protection. When both
thermal shutdown and the amplifier enable/disable functions
are desired, the externally generated control signal and the
Thermal Flag pin outputs should be combined with an AND
gate, as shown on Figure 7. The temperature protection was
designed to protect against overload conditions. It was not
intended to replace proper heatsinking. Continuously running
the OPA569 in and out of thermal shutdown will degrade
reliability.
On
Output Protection Diode
Disable
VO
AND
Thermal
Flag Pin
Output Protection Diode
Enable Pin
7
RSET
5
6
8
OPA569
14,
15
–V
FIGURE 6. Output Protection Diode.
FIGURE 7. Enable/Shutdown Control Using Thermal Flag Pin
and External Control Signal.
OPA569
SBOS264A
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15
Any tendency to activate the thermal protection circuit indicates excessive power dissipation or an inadequate heat
sink. For reliable, long term, continuous operation, the junction temperature should be limited to 125°C maximum. To
estimate the margin of safety in a complete design (including
heat sink), increase the ambient temperature until the thermal protection is triggered. Use worst-case loading and
signal conditions. For good, long-term reliability, thermal
protection should trigger more than 25°C above the maximum expected ambient conditions of your application. This
produces a junction temperature of 125°C at the maximum
expected ambient condition.
SAFE OPERATING AREA AT ROOM TEMPERATURE
Output Current (A)
10
Copper—soldered,
with 250lfm airflow.
1
Copper—soldered,
with 150lfm airflow.
0.1
0
1
2
3
4
5
6
VS – VOUT (V)
FIGURE 8. Safe Operating Area at Room Temperature.
Power dissipation depends on power supply, signal and load
conditions. It is dominated by the power dissipation of the
output transistors. For DC signals, power dissipation is equal
to the product of output current, IOUT and the output voltage
across the conducting output transistor (VS-VOUT). Dissipation with AC signals is lower. Application Bulletin AB-039
(SBOA022) explains how to calculate or measure power
dissipation with unusual signals and loads and can be found
at the TI web site (www.ti.com).
SAFE OPERATING AREA AT VARIOUS
AMBIENT TEMPERATURES
Output Current (A)
10
Output short-circuits are particularly demanding for the amplifier because the full supply voltage is seen across the
conducting transistor. It is very important to note that the
temperature protection will not shut the part down in overtemperature conditions, unless the Thermal Flag pin is connected to the Enable pin; see the section on Thermal Flag.
Figure 8 shows the safe operating area at room temperature
with various heatsinking efforts. Note that the safe output
current decreases as (VS – VOUT) increases. Figure 9 shows
the safe operating area at various temperatures with the
PowerPAD being soldered to a 2 oz copper pad.
The OPA569 has a junction-to-ambient thermal resistance
(θJA) value of 21.6°C/W when soldered to 2oz copper plane.
This value can be further decreased to 12°C/W by the
addition of forced air. Figure 10 shows the junction-toambient thermal resistance of the DWP-20 package.
Current is limited by
the maximum output
current.
TA = 0°C
TA = –40°C
1
TA = +125°C
TA = +85°C
TA = +25°C
0.1
0
1
2
3
4
5
6
VS – VOUT (V)
FIGURE 9. Safe Operating Area at Various Ambient Temperatures. PowerPAD soldered to a 2oz copper pad.
The power that can be safely dissipated in the package is
related to the ambient temperature and the heatsink design.
The PowerPAD package was specifically designed to provide excellent power dissipation, but board layout greatly
influences the heat dissipation of the package. Refer to
the “PowerPAD Thermally Enhanced Package” section for
further details.
16
Copper—soldered,
with 500lfm airflow.
Copper—soldered,
without forced air.
Fast transients of large output current swings (for example
switching quickly from sourcing 2A to sinking 2A) may cause
a glitch on the Thermal Flag pin. When switching large
currents is expected, the use of extra bypass between the
supplies or a low-pass filter on the Thermal Flag pin is
recommended.
POWER DISSIPATION AND
SAFE OPERATING AREA
Current is limited by the
maximum output current.
HEATSINKING METHOD
θJA
The part is soldered to a 2 oz copper pad under the
exposed pad.
21.6
Soldered to copper pad with forced airflow (150lfm).
15.1
Soldered to copper pad with forced airflow (250lfm).
13.2
Soldered to copper pad with forced airflow (500lfm).
12.0
FIGURE 10. Junction-to-Ambient Thermal Resistance with
Various Heatsinking Efforts.
OPA569
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SBOS264A
Junction temperature should be kept below 125°C for reliable
operation. The junction temperature can be calculated by:
THERMAL RESISTANCE vs COPPER AREA
35
Thermal Resistance, θJA (°C/W)
TJ = TA + PDθJA
where θJA = θJC + θCA
TJ = Junction Temperature (°C)
TA = Ambient Temperature (°C)
PD = Power Dissipated (W)
θJA = Junction-to-Ambient Thermal Resistance
θJC = Junction-to-Case Thermal Resistance
θCA = Case-to-Air Thermal Resistance
For applications with limited board size, refer to Figure 12 for
the approximate thermal resistance relative to heatsink area.
Increasing the heatsink area beyond 2in2 provides little
improvement in thermal resistance. To achieve the 21.5°C/W
stated in the Electrical Characteristics, a copper plane size of
9in2 was used. The SO-20 PowerPAD package is well suited
for continuous power levels, as shown in Figure 11. Higher
power levels may be achieved in applications with a low
on/off duty cycle.
25
20
15
OPA569
Surface-Mount Package
10
The Maximum Power Dissipation vs Temperature for the
heatsinking methods listed in Figure 10 is shown in Figure 11.
To appropriately determine required heatsink area, required
power dissipation should be calculated and the relationship
between power dissipation and thermal resistance should be
considered to minimize shutdown conditions and allow for
proper long-term operation (junction temperature of 125°C).
Once the heatsink area has been selected, worst-case load
conditions should be tested to ensure proper thermal protection.
30
0
1
2
5
FEEDBACK CAPACITOR IMPROVES RESPONSE
For optimum settling time and stability with higher impedance
feedback networks (RF > 50kΩ), it may be necessary to add
a feedback capacitor across the feedback resistor, RF, as
shown in Figure 13. This capacitor compensates for the zero
created by the feedback network impedance and the OPA569
input capacitance (and any parasitic layout capacitance).
The effect becomes more significant with higher impedance
networks.
The size of the capacitor needed is estimated using the
equation:
RIN • CIN = RF • CF
where CIN is the sum of the input capacitance of the OPA569
plus the parasitic layout capacitance.
CF
14
Power Dissipated in Package (W)
4
FIGURE 12. Thermal Resistance vs Circuit Board Copper
Area.
MAXIMUM POWER DISSIPATION
vs TEMPERATURE
TJ = 150°C
3
Copper Area (inches2)
With 250lfm Airlow
12
RIN
With 150lfm Airlow
RF
VIN
10
V+
With 500lfm Airlow
8
12,
13
6
5
Without Forced Air
CIN
4
RIN • CIN = RF • CF
2
14,
15
VOUT
OPA569
6
CL
CIN
0
–55
–30
–5
20
45
70
95
120
17,
18
Temperature (°C)
V–
FIGURE 11. Maximum Power Dissipation vs Temperature.
Where CIN is equal to the OPA569’s input
capacitance (approximately 9pF) plus any
parasitic layout capacitance.
FIGURE 13. Feedback Capacitor for use with Higher Impedance Networks.
OPA569
SBOS264A
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17
PARALLEL OPERATION
PowerPAD THERMALLY ENHANCED PACKAGE
The OPA569 allows parallel operation of multiple op amps to
extend output current capability or improve the output voltage swing to the rail. Special internal circuitry causes the
load current to be shared equally between two (or more) op
amps.
The OPA569 uses the SO-20 PowerPAD package, a thermally enhanced, standard size IC package designed to
eliminate the use of bulky heatsinks and slugs traditionally
used in thermal packages. This package can be easily
mounted using standard PCB assembly techniques.
Figure 14 shows two ways to connect the input terminals.
When the amplifier inputs are connected in parallel, the
effective offset voltage is averaged and the bandwidth and
slew rate performance are the same as that of a single
amplifier. It is also possible to use one amplifier to be the
“master” and connect the other inputs to a voltage within the
common-mode input range of the amplifier; however, slew
rate and bandwidth performance will be degraded.
The PowerPAD package is designed so that the leadframe
die pad (or thermal pad) is exposed on the bottom of the IC,
as shown in Figure 15. This provides an extremely low
thermal resistance (θJC) path between the die and the
exterior of the package. The thermal pad on the bottom of
the IC can then be soldered directly to the PCB, using the
PCB as a heatsink. In addition, plated-through holes (vias)
provide a low thermal resistance heat flow path to the back
side of the PCB.
For best performance, keep additional capacitance at the
Parallel Out pins to a minimum and avoid routing these lines
close to other lines that might see large voltage swings.
Soldering the PowerPAD to the PCB ia always recommended, even with applications that have low power dissipation. This provides the necessary thermal and mechanical
connection between the leadframe die pad and the PCB.
V+
12,
13
5
2
OPA569
6 (A1)
9
VIN
Leadframe (Copper Alloy)
Parallel Out 1
IC (Silicon)
14,
15
Die Attach (Epoxy)
Parallel Out 2
17,
18
V–
V+
12,
13
Parallel Out 1
Leadframe Die Pad
Exposed at Base of the Package
5
2
14,
15
OPA569
6 (A2)
9
Parallel Out 2
17,
18
Mold Compound (Epoxy)
RL
FIGURE 15. Section View of a PowerPAD Package.
V–
(a) Inputs connected in parallel.
PowerPAD Assembly Process
1. The PowerPAD must be connected to the most negative
supply voltage of the device, which will be ground in singlesupply applications and V– in split-supply applications.
V+
12,
13
5
VIN
2
OPA569
6 (A1)
9
17,
18
Parallel Out 1
2. Prepare the PCB with a top-side etch pattern, as shown in
Figure 16. There should be etch for the leads as well as
etch for the thermal land.
14,
15
Parallel Out 2
3. Place the recommended number of plated-through holes
(or thermal vias) in the area of the thermal pad. These
holes should be 13 mils in diameter. They are kept small
so that solder wicking through the holes is not a problem
during reflow. The minimum recommended number of
holes for the SO-20 PowerPAD package is 24, as shown
in Figure 16.
V–
V+
12,
13
Parallel Out 1
5
2
14,
15
OPA569
6 (A2)
9
Parallel Out 2
17,
18
V–
(b) Amplifier A1 as “master”, A2 as “slave”.
RL
4. It is recommended, but not required, to place a small
number of additional holes under the package and outside
the thermal pad area. These holes provide an additional
heat path between the copper land and the ground plane.
They may be larger because they are not in the area to be
soldered, so wicking is not a problem. This is illustrated in
Figure 16.
FIGURE 14. Parallel Operation.
18
OPA569
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SBOS264A
Thermal Land
299 mils x 510 mils
Minimum Area (7.59mm x 12.95mm)
(Copper)
9. With these preparatory steps in place, the PowerPAD IC
is simply placed in position and run through the solder
reflow operation as any standard surface-mount component. This results in a part that is properly installed.
OPTIONAL:
Additional 4 vias outside of
thermal pad area but under
the package
(Via diameter = 25 mils)
For detailed information on the PowerPAD package including
thermal modeling considerations and repair procedures,
please see Technical Brief SLMA002, “PowerPAD Thermally
Enhanced Package,” located at www.ti.com.
REQUIRED:
Thermal pad area: 140 mils x 176 mils
(3.56mm x 4.47mm) with 24 vias
(Via diameter = 13 mils)
FIGURE 16. 20-Pin DWP PowerPAD PCB Etch and Via Pattern.
5. Connect all holes, including those within the thermal pad
area and outside the pad area, to the internal ground
plane or other internal copper plane for single supply
applications, and V– for split-supply applications.
6. When laying out these holes to the ground plane, do not
use the typical web or spoke via connection methodology,
as shown in Figure 17. Web connections have a high
thermal resistance connection that is useful for slowing
the heat transfer during soldering operations. This makes
soldering the vias that have ground plane connections
easier. However, in this application, low thermal resistance is desired for the most efficient heat transfer.
Therefore, the holes under the PowerPAD package should
make their connection to the internal ground plane with a
complete connection around the entire circumference of
the plated-through hole.
LAYOUT GUIDELINES
The OPA569 is a power amplifier that requires proper layout
for best performance. Figure 18 shows an example layout.
Refinements to this example layout may be required based
on assembly process requirements.
Keep power-supply leads as short as possible. This will keep
inductance low and resistive losses at a minimum. A minimum of 18 gauge wire thickness is recommended for powersupply leads. The wire length should be less than 8 inches.
Proper power-supply bypassing with low ESR capacitors is
essential to achieve good performance. A parallel combination of 100nF ceramic and 47µF tantalum bypass capacitors
will provide low impedance over a wide frequency range.
Bypass capacitors should be placed as close as practical to
the power-supply pins of the OPA569.
PCB traces conducting high currents, such as from output to
load or from the power-supply connector to the power-supply
pins of the OPA569 should be kept as wide and short as
possible.
The twenty-four holes in the landing pattern for the OPA569
are for the thermal vias that connect the PowerPAD of the
OPA569 to the heatsink area on the PCB. The additional four
larger vias further enhance the heat conduction into the
heatsink area. All traces conducting high currents are very
wide for lowest inductance and minimal resistive losses. Note
that the negative supply (–V) pin on the OPA569 can be
connected through the PowerPAD to allow for maximum
trace width for high current paths.
Current
Limit Set
Parellel
Out 1
IMONITOR
V–
Pin 1
Solid Via
RECOMMENDED
Web or Spoke Via
NOT RECOMMENDED
V–
Current Limit Flag
–In
VOUT
+In
Thermal Flag
Enable
FIGURE 17. Via Connection.
7. The top-side solder mask should leave the terminals of the
pad connections and the thermal pad area exposed. The
thermal pad area should leave the 13 mil holes exposed.
The larger holes outside the thermal pad area should be
covered with solder mask.
8. Apply solder paste to the exposed thermal pad area and
all of the package terminals.
NOTE: Avoid routing Current
Limit Set and Current Limit
Flag traces closely in parallel.
FIGURE 18. 20-Pin DWP PowerPAD PCB Etch and Via
Pattern.
OPA569
SBOS264A
V+
Parallel Out 2
www.ti.com
19
APPLICATION CIRCUITS
R2
4.99kΩ
fO = 10kHz
0.0033µF
+1V
0V
R1
49.9kΩ
0mA
–100mA
12,
13
5
VIN
6
OPA569
(1)
R3
49.9kΩ
14,
15
VO
RSHUNT
1Ω
IO
3
RSET
17,
18
0V
–2.5V
Luxeon Star-0
High-Power LED
–5V
4.99kΩ
Feedback for Constant Current,
1V Input per 100mA Output as Shown.
NOTE: (1) Bypass as recommended.
FIGURE 19. Grounded Anode LED Driver.
1kΩ
1kΩ
5V
5V
5
VIN
6
12,
13
OPA569
3
17,
18
12,
13
(1)
14,
15
14,
15
TEC
19
IMONITOR
Current
Limit
Set
VTEC
+
RSET
IM = +
Heat/Cool
VTEC = 2 (VIN – VSET)
ITEC
5
OPA569
Current
Limit 3
Set
–
(1)
RSET
475
6
VSET
17,
18
RM
VM
NOTE: (1) Bypass as recommended.
Optional to
monitor the
load current.
FIGURE 20. Bridge Tied Load Driver.
NOTE: Total Supply Must
be < 5.5V Cooling/Heating.
+3.3V
12,
13
5
VIN
6
(1)
OPA569
IL
14,
15
19
17,
18
TEC
IMONITOR
RMONITOR
–1.2V
NOTE: (1) Bypass as recommended.
FIGURE 21. Single Power Amplifier Driving Bidirectional Current through a TEC using Asymmetrical Bipolar Power Supplies.
20
OPA569
www.ti.com
SBOS264A
1kΩ
1kΩ
+5V(1)
+5V(1)
2
3
VIN
5
7
OPA335
6
6
12,
13
OPA569
2A max
14,
15
RL
17,
18
4
NOTE: (1) Bypass as recommended.
FIGURE 22. Power Booster for Precision Op Amp.
C1
3.3nF
+5V
2
1
3pF
+5V
1
REF3025
+2.5V
R2
10kΩ
1MΩ
(1)
R1
10kΩ
12,
13
5
+0.5V
6
8pF
14,
15
OPA569
2
19
3
LED
17,
18
3
R3
2.5kΩ
C2
0.01µF
4
RMONITOR(3)
RSET(2)
5
PD
Luxeon
Star –0
High
Power
LED
VB
OPT101(4)
8
3
NOTE: (1) Bypass as recommended.
(2) RSET establishes current limit.
Glass Microscope Slide
(3) RMONITOR used to measure LED current.
(4) OPT101 Pin Numbers for DIP Package.
Approximately
92% light
available for application.
LED
≈ 8%
Optical Calibration
OPT101
FIGURE 23. LED Output Regulation Circuit for Constant Optical Power.
OPA569
SBOS264A
www.ti.com
21
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2014
PACKAGING INFORMATION
Orderable Device
Status
(1)
Package Type Package Pins Package
Drawing
Qty
Eco Plan
Lead/Ball Finish
MSL Peak Temp
(2)
(6)
(3)
Op Temp (°C)
Device Marking
(4/5)
OPA569AIDWP
ACTIVE SO PowerPAD
DWP
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
OPA569A
OPA569AIDWPG4
ACTIVE SO PowerPAD
DWP
20
25
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
OPA569A
OPA569AIDWPR
ACTIVE SO PowerPAD
DWP
20
1000
Green (RoHS
& no Sb/Br)
CU NIPDAU
Level-2-260C-1 YEAR
-55 to 125
OPA569A
OPA569AIDWPRG4
ACTIVE SO PowerPAD
DWP
20
TBD
Call TI
Call TI
-55 to 125
(1)
The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2)
Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3)
MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4)
There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5)
Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6)
Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Addendum-Page 1
Samples
PACKAGE OPTION ADDENDUM
www.ti.com
7-Nov-2014
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
Addendum-Page 2
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device
OPA569AIDWPR
Package Package Pins
Type Drawing
SO
Power
PAD
DWP
20
SPQ
Reel
Reel
A0
Diameter Width (mm)
(mm) W1 (mm)
1000
330.0
24.4
Pack Materials-Page 1
10.8
B0
(mm)
K0
(mm)
P1
(mm)
W
Pin1
(mm) Quadrant
13.3
2.7
12.0
24.0
Q1
PACKAGE MATERIALS INFORMATION
www.ti.com
24-Jul-2013
*All dimensions are nominal
Device
Package Type
Package Drawing
Pins
SPQ
Length (mm)
Width (mm)
Height (mm)
OPA569AIDWPR
SO PowerPAD
DWP
20
1000
367.0
367.0
45.0
Pack Materials-Page 2
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