MDTIC MDT10P65 8-bit micro-controller Datasheet

MDT10P65
1. General Description
This OTP-Based 8-bit micro-controller
uses a fully static CMOS technology
process to achieve higher speed and
smaller size with the low power
consumption and high noise immunity. On
chip memory includes 4K words of
EPROM, and 192 bytes of static RAM.
3. Applications
The application areas of this MDT10P65
range from appliance motor control and high
speed automotive to low power remote
transmitters/receivers
and
telecommunications processors, such as
Remote controller, small instruments, toy,
automobile and keyboard … etc.
2. Features
RISC CPU
Fully static design
37 single word instructions
4K x 14 program memory.
192 bytes RAM for data
35 bi-directional I/O
Eight level hardware stacks
Watchdog timer with on-chip RC
oscillator.
Interrupt capability
Timer0 : 8-bit timer with 8-bit
prescaler
Timer1 : 8-bit timer with 8-bit compare
register. This timer can be used as
carrier generator.
Sleep mode for power saving.
PB and PD with port change wake-up
interrupt.
PS : timer1 counter PC0 clock in low to high
the counter data increase
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P.1
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2011/8 Ver1.9
MDT10P65
4. Pin Diagram
MDT10P65SD42 pin Shrink PDIP
PA6 1
42 PA7
/RES 2
41 PB7
PA0 3
40 PB6
PA1 4
39 PB5
PA2 5
38 PB4
PA3 6
37 PB3
PA4/T0CLK 7
36 PB2
PA5 8
35 PB1
PE0 9
34 PB0/IRQ
PE1 10
33 VDD
PE2 11
32 VSS
VDD 12
31 PD7
VSS 13
30 PD6
OSC1 14
29 PD5
OSC2 15
28 PD4
PC0/T1OSCO 16
27 PC7
PC1/T1OSCI 17
26 PC6
PC2 18
25 PC5
PC3 19
24 PC4
PD0 20
23 PD3
PD1 21
22 PD2
MDT10P65A1Q
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P.2
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MDT10P65A2Q
2011/8 Ver1.9
MDT10P65
5. Pin function description
Pin name
Type Buffer type
OSC1
OSC2
/RES(MCLRB)
I
O
I
ST
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
TTL
TTL
TTL
TTL
ST
TTL
TTL
TTL
PB0/IQR
PB1
PB2
PB3
PB4
PB5
PB6
PB7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST/TTL
TTL
TTL
TTL
TTL
TTL
TTL
TTL
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
PD0-PD7
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
ST
ST
ST
ST
ST
ST
ST
ST
ST
PE0
PE1
PE2
Vdd
I/O
I/O
I/O
ST
ST
ST
Vss
Description
Oscillator input
Oscillator out
Reset input with 130K ohm pull-up
Bi-directional I/O port A. Port A can be software
programmed for internal 45K ohm pull-up on all pins
except PA5. The pull-up resistance on PA5 is 100K ohm.
Can be clock input to Timer0.
Bi-directional I/O port B. Port B can be software
programmed for internal 25K ohm pull-up on all pins.
PB0-PB7 can generate interrupt on pin state change.
Can be the external interrupt pin.
Bi-directional I/O port C. Port C can be software
programmed for internal 100K pull-up on all pins.
Can be Timer1 oscillator output or Timer1 clock input.
Can be Timer1 oscillator input.
Bi-directional port. All pins can generate interrupt on pin
state change. Port D can be software programmed for
internal 100K pull-up on all pins.
Bi-directional port E. Port E can be software programmed
for internal 100K pull-up on all pins.
Power input
Ground pin
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P. 3
2007/9
Ver. 1.8
MDT10P65
6. Memory Mapping
6.1Program memory :
0000h
0001h
0002h
0003h
0004h
Reset Vector
Peripheral interrupt
Vector
0005h
Program memory
(Page 0)
07FFh
0800h
Program memory
(Page 1)
0FFFh
6.2Register file map :
BANK 0
00h
IAR
01h
RTCC
02h
PCL
03h STATUS
04h
MSR
05h PORT A
06h PORT B
07h PORT C
08h PORT D
09h PORT E
0Ah
PCH
0Bh
INTS
0Ch
PIFB1
0Dh
PIFB2
0Eh
TMR1L
0Fh
10h
T1STA
11h
12h
13h
14h
15h
CCP1L
16h
17h CCP1CTL
18h
BANK 1
IAR
TMR
PCL
STATUS
MSR
CPIO A
CPIO B
CPIO C
CPIO D
CPIO E
PCH
INTS
PIEB1
PIEB2
PSTA
PPHE
1Fh
20h
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
9Fh
A0h
General
Purpose
Register
General
Purpose
Register
7Fh
FFh
Unimplemented memory location.
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P. 4
2007/9
Ver. 1.8
MDT10P65
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
Indirect addressing register
Timer0 register
Program counter low byte
Status register
Bit 0 : Carry
1 : Digit carry
2 : Zero flag
3 : Power-down
4 : WDT time-out
5 : Register bank select (For direct addressing)
=0 Bank 0 (00h-7Fh)
=1 Bank 1 (80h-FFh)
7-6 : Always read as zero.
Memory select register
Port A data register
Port B data register
Port C data register
Port D data register
Port E data register
Bit 2-0 – Port E data register.
7-3 – Unimplemented. Always set as 0.
Program memory segment register
Interrupt control register
Bit 0 – PB port change interrupt flag bit.
1 – PB0/IRQ external interrupt flag bit.
2 – Timer0 overflow interrupt flag bit.
3 – PB port change interrupt enable bit.
4 – PB0/IRQ external interrupt enable bit.
5 – Timer0 overflow interrupt enable bit.
6 – Peripheral interrupt enable bit.
7 – Global interrupt enable bit.
Peripheral interrupt flag register 1.
Bit 0 – Timer1 overflow interrupt flag bit
7-1 – Unimplemented. Always read as 0.
Peripheral interrupt flag register 2.
Bit 6-0 – Unimplemented. Read as zero.
7 – PD port change interrupt flag bit
Timer1 data register low byte.
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P. 5
2007/9
Ver. 1.8
MDT10P65
0F
10
Unimplemented..
Timer1 control register
Bit 0 – Timer1 enable bit
1 – Timer1 clock source select
2 – Timer 1 external clock synchronization control bit
3 – Timer 1 oscillator enable control bit
5-4 – Timer 1 prescaler select bits
7-6 – Unimplemented. Always read as 0.
11-14 Unimplemented.
15
Timer1 compare register
16
Unimplemented.
17
Timer1 compare control register
Bit 7-1 –Unimplemented. Always set as 0.
0 – compare enable bit
18-1F Unimplemented.
20-7F General purpose register
80
Same as register 00.
81
TMR register
Bit 2-0 – Prescaler rate select bits
3 – Prescaler assign bit
4 – Timer 0 edge select bit
5 – Timer 0 clock source select bit
6 – PB0/IRQ interrupt edge select bit
7 – Port B pull-up enable bit.
82-84 Same as 02H-04H.
85
Port A data direction register.
86
Port B data direction register.
87
Port C data direction register.
88
Port D data direction register.
89
Port E data direction register.
Bit 2-0 – Port E data direction register.
7-3 – Unimplemented. Always set as 0.
8A -8B Same as 0AH-0BH.
8C
Peripheral interrupt control register 1.
Bit 0 – Timer1 overflow interrupt enable bit.
7-1 – Unimplemented. Always set these bits to 0.
8D
Peripheral interrupt control register 2
Bit 6-0 – Unimplemented.
7 – PD port change interrupt enable bit.
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P. 6
2007/9
Ver. 1.8
MDT10P65
8E
Power control register.
Bit 0 –Unimplemented. Always read as 0.
1 – Power-on reset status bit.
7-2 – Unimplemented. Always read as 0.
8F
Unimplemented.
90
PPHE register . ( “ 0 ” Enable ; “ 1 ” Disable )
Bit 0-3 – Unimplemented.
4 – PA port pull-up enable bit.
5 – PC port pull-up enable bit.
6 – PD port pull-up enable bit.
7 – PE port pull-up enable bit.
91-9F Unimplemented.
A0-FF General purpose register.
7. Timer1 CCP Mode
CCP1CTL
Enable
CCP1L
Input
COMPARATOR
TMR1L
1 / 2 Output
PA7
TRISA< 7 >
Output Enable
Clear TMR1L
PA7
Input
Output
Default
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P. 7
2007/9
Ver. 1.8
MDT10P65
8. Reset Condition for all Registers
Register
Address
Power-On Reset,
Power range
/MCLR or WDT Reset Wake-up from SLEEP
detector Reset
IAR
00h(80h)
0000 0000
0000 0000
uuuu uuuu
RTCC
01h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PCL
02h(82h)
0000 0000
0000 0000
0000 0100
STATUS
03h(83h)
0001 1xxx
000# #uuu
000# #uuu
MSR
04h(84h)
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT A
05h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT B
06h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT C
07h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT D
08h
xxxx xxxx
uuuu uuuu
uuuu uuuu
PORT E
09h
---- -xxx
---- -uuu
---- -uuu
PCH
0Ah(8Ah)
---- 0000
---- 0000
---- uuuu
INTS
0Bh(8Bh)
0000 0001
0000 0001
uuuu uuuu
PIFB1
0Ch
---- ---x
---- ---u
---- ---u
PIFB2
0Dh
1--- ----
1--- ----
u--- ----
TMR1L
0Eh
xxxx xxxx
Uuuu uuuu
Uuuu uuuu
T1STA
10h
--00 0000
--00 0000
--uu uuuu
CCP1L
15h
Xxxx xxxx
uuuu uuuu
--uu uuuu
CCP1CTL
17h
---- ---0
---- ---0
---- ---u
TMR
81h
1111 1111
1111 1111
uuuu uuuu
CPIO A
85h
1111 1111
1111 1111
uuuu uuuu
CPIO B
86h
1111 1111
1111 1111
uuuu uuuu
CPIO C
87h
1111 1111
1111 1111
uuuu uuuu
CPIO D
88h
1111 1111
1111 1111
uuuu uuuu
CPIO E
89h
---- -111
---- -111
---- -uuu
PIEB1
8Ch
---- ---0
---- ---0
---- ---u
PIEB2
8Dh
0--- ----
0--- ----
u--- ----
PSTA
8Eh
---- --#-
---- --u-
---- --u-
PPHE
90h
1111 ----
1111 ----
uuuu ----
Note : u = unchanged, x = unknown, - = unimplemented, read as “0”
# = value depends on the condition of the following table
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P. 8
2007/9
Ver. 1.8
MDT10P65
Condition
Status
bit 4
Status
bit 3
PSTA
bit 1
POWR ON RESET
1
1
0
/MCLR reset (not during SLEEP)
u
u
u
/MCLR reset during SLEEP
1
0
u
WDT reset (not during SLEEP)
0
1
u
WDT reset during SLEEP
0
0
u
Interrupt Wake-up during SLEEP
1
0
u
9. Instruction Set
Instruction Code
Mnemonic
Operands
Function
Operation
Status
010000 00000000 NOP
010000 00000001 CLRWT
No operation
None
Clear Watchdog timer
0→WT
TF, PF
010000 00000010 SLEEP
Sleep mode
TF, PF
010000 00000011 TMODE
010000 00000rrr CPIO R
Load W to TMODE register
0→WT,
stop OSC
W→TMODE
Control I/O port register
W→CPIO
None
010001 1rrrrrrr STWR R
011000 trrrrrrr LDR R, t
Store W to register
W→R
Load register
R→t
Z
111010 iiiiiiii LDWI I
Load immediate to W
010111 trrrrrrr SWAPR R, t Swap halves register
I→W
None
[R(0~3) ↔
R(4~7)]→t
None
011001 trrrrrrr INCR R, t Increment register
011010 trrrrrrr INCRSZ R, t Increment register, skip if
zero
011011 trrrrrrr ADDWR R, t Add W and register
011100 trrrrrrr SUBWR R, t Subtract W from register
R + 1→t
Z
R + 1→t
None
W + R→t
C, HC, Z
011101 trrrrrrr DECR R, t
011110 trrrrrrr DECRSZ R,
t
010010 trrrrrrr ANDWR R, t
110100 iiiiiiii ANDWI i
Decrement register
R ﹣1→t
Z
Decrement register, skip if
zero
AND W and register
R ﹣1→t
None
R ∩ W→t
Z
AND W and immediate
i ∩ W→W
Z
R ∪ W→t
Z
i ∪ W→W
Z
010011 trrrrrrr IORWR R, t Inclu. OR W and register
110101 iiiiiiii IORWI i
Inclu. OR W and immediate
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P. 9
None
r
None
C, HC, Z
R ﹣W→t
(R+/W+1→t)
2007/9
Ver. 1.8
MDT10P65
Mnemonic
Function
Operation
Operands
010100 trrrrrrr XORWR R, t Exclu. OR W and register
R ♁ W→t
110110 iiiiiiii XORWI i Exclu. OR W and immediate i ♁ W→W
011111 trrrrrrr COMR R, t Complement register
/R→t
Instruction Code
Status
Z
Z
Z
010110 trrrrrrr RRR
R, t Rotate right register
R(n) →
R(n-1), C→
R(7),
R(0)→C
C
010101 trrrrrrr RLR
R, t
Rotate left register
R(n)→r(n+1),
C→R(0),
R(7)→C
C
Clear working register
0→W
Z
Clear register
0→R
Z
010000 1xxxxxxx CLRW
010001 0rrrrrrr CLRR
0000bb brrrrrrr BCR
0010bb brrrrrrr BSR
R
R, b Bit clear
0→R(b)
None
R, b Bit set
1→R(b)
None
Skip if R(b)=0
None
Skip if R(b)=1
None
n→PC,
PC+1→Stack
None
Long JUMP to address
n→PC
None
Return, place immediate to
W
Stack→PC,
i→W
None
110111 iiiiiiii ADDWI
Add immediate to W
PC+1→PC,
W+i→W
C,HC,Z
111000 iiiiiiii SUBWI
Subtract W from immediate
i-W→W
C,HC,Z
010000 00001001 RTFI
Return from interrupt
Stack→PC,
1→GIS
None
010000 00000100 RET
Return from subroutine
Stack→PC
None
0001bb brrrrrrr BTSC R, b Bit Test, skip if clear
0011bb brrrrrrr BTSS R, b Bit Test, skip if set
100nnn nnnnnnnn LCALL n
Long CALL subroutine
101nnn nnnnnnnn LJUMP n
110001 iiiiiiii RTWI i
Note :
W
WT
TMODE
CPIO
TF
PF
PC
OSC
:
:
:
:
:
:
:
:
Working register
Watchdog timer
TMODE mode register
Control I/O port register
Timer overflow flag
Power loss flag
Program Counter
Oscillator
b
t
:
:
0
1
R :
C :
HC :
Z :
Bit position
Target
: Working register
: General register
General register address
Carry flag
Half carry
Zero flag
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P. 10
2007/9
Ver. 1.8
MDT10P65
Inclu.
Exclu.
AND
:
:
:
Inclusive ‘∪’
Exclusive ‘♁’
Logic AND ‘∩’
/
x
i
:
:
:
Complement
Don’t care
Immediate data ( 8 bits )
n
:
Immediate address
10. Electrical Characteristics
(A) Operating Voltage & Frequency
Vdd ﹕2.3 V ~ 5.5 V
Frequency﹕0 Hz ~ 20 MHz
(B) Input Voltage
@ Vdd=5.0 V, Temperature=25 ℃
Port
Min.
Max.
PA0~3 & 5~7, PB
Vss
1.0 V
PA4,PC,PD,PE,/MCLR
Vss
0.8 V
PA0~3 & 5~7,PB
2.0V
Vdd
PA4,PC,PD,PD,PE, /MCLR
3.4V
Vdd
Vil
Vih
*Threshold Voltage :
Port A0~3 & 5~7, Port B Vth=1.61v
Port A4, Port C, Port D, Port E, /MCLR Vil=1.12 V, Vih=3.07 V
(Schmitt Trigger)
(C) Output Voltage
@ Vdd=5.0 V, Temperature=25 ℃, the typical value as followings :
PA4~7, PB, PC, PD, PE Port
PA0~3
Ioh=-20.0 mA
Voh=3.45V
Iol=20.0 mA
Vol=0.47V
Ioh=-5.0 mA
Voh=4.61V
Iol=5.0 mA
Vol=0.18V
Iol =5.6mA Vol =0.6V ; Iol =8.3mA Vol =0.87V
(D) Leakage Current
@ Vdd=5.0 V, Temperature=25 ℃, the typical value as followings :
Iil
- 1.0 μA (Max.)
Iih
+ 1.0 μA (Max.)
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P. 11
2007/9
Ver. 1.8
MDT10P65
(E) Sleep Current
@WDT-Enable, Temperature=25 ℃, the typical value as followings :
Vdd=2.3 V
Idd=1.5 μA
Vdd=2.5 V
Idd=2.2 μA
Vdd=3.0 V
Idd=3.9 μA
Vdd=4.0 V
Idd=9.6 μA
Vdd=5.0 V
Idd=21 μA
Vdd=5.5 V
Idd=30 μA
@WDT-Disable, Temperature=25 ℃, the typical value as followings :
Vdd=2.3 V ~ 5.5 V, Idd<0.1 μA
(F) Operating Current / Voltage
Temperature=25℃, the typical value as followings :
(i) OSC Type=RC ; WDT-Enable; PED---Disable @ Vdd=5.0 V
Cext. (F)
3P
20P
100P
Rext. (Ohm)
Frequency (Hz)
4.7 K
12.8 M
1.30 m
10.0 K
6.54 M
741 u
47.0 K
1.48 M
259 μ
100.0 K
705 K
181 μ
300.0 K
241 K
133 μ
470.0 K
151 K
125 μ
4.7 K
6.11 M
695 μ
10.0 K
3.17 M
441 μ
47.0 K
716 K
180 μ
100.0 K
339 K
149 μ
300.0 K
116 K
126 μ
470.0 K
73 K
122 μ
4.7 K
2.03 M
310 μ
10.0 K
1.02 M
205 μ
47.0 K
223 K
129 μ
100.0 K
105 K
118 μ
300.0 K
35.5 K
111 μ
470.0 K
22.4 K
110 μ
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P. 12
Current (A)
2007/9
Ver. 1.8
MDT10P65
Cext. (F)
300P
(ii)
Rext. (Ohm)
Frequency (Hz)
Current (A)
4.7 K
816 K
181 μ
10.0 K
400 K
141 μ
47.0 K
90 K
112 μ
100.0 K
40.8 K
108 μ
300.0 K
13.8 K
105 μ
470.0 K
8.7 K
99 μ
OSC Type=LF (C=10 p);
Voltage/Frequency
(iii)
WDT-Disable PED ---Disable
32 K
455 K
1M
Sleep
2.3 V
10 uA
X
35 uA
<1uA
2.5 V
13 uA
X
41 uA
<1uA
3.0 V
19 uA
40.8 uA
52 uA
<1uA
4.0 V
38 uA
62.5 uA
85 uA
<1uA
5.0 V
65 uA
99.1 uA
121 uA
<1uA
5.5 V
76 uA
128.3 uA
162 uA
<1uA
OSC Type=XT (C=10 p);
Voltage/Frequency
WDT-Enable PED – Enable
1M
4M
10 M
Sleep
2.3 V
59 uA
174 uA
369 uA
1.5 μA
2.5 V
73 uA
205 uA
418 uA
2.2 μA
3.0 V
110 uA
274 uA
561 uA
3.9 μA
4.0 V
263 uA
464 uA
891 uA
9.6 μA
5.0 V
489 uA
704 uA
1.23 mA
21 μA
5.5 V
862 uA
1.00 mA
1.64 mA
30 μA
This specification are subject to be changed without notice. Any latest information
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P. 13
2007/9
Ver. 1.8
MDT10P65
(iv) OSC Type=HF (C=10 p);
WDT-Enable
Voltage/Frequency
PED – Enable
4M
10 M
20 M
Sleep
2.3 V
192 uA
396 uA
734uA
1.5 μA
2.5 V
222 uA
462 uA
841uA
2.2 μA
3.0 V
314 uA
622 uA
1068 uA
3.9 μA
4.0 V
532 uA
985 uA
1.62 mA
9.6 μA
5.0 V
803 uA
1.40 mA
2.37 mA
21 μA
5.5 V
1.19 mA
1.81 mA
3.08 mA
30 μA
(G) Pull_High Resistance
@ Input Mode : Vdd=5.0 V
PA7
PA6
PA5
PA4
PA3
PA2
PA1
PA0
46.7KΩ 46.2KΩ 96.1KΩ 47.6KΩ 47.1KΩ 47.1KΩ 46.7KΩ 46.2KΩ
PB 7~0
PC 7~0
PD 7~0
PE 2~0
26.4KΩ
92.5KΩ
92.5KΩ
92.5KΩ
p.s. : It is only a reference value for the Pull High Resistance, and the accurate
value of the Resistance depends on the various parameter of the Process.
But the variation of the value will be not more than 20%.
(H) Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd=5.0 V
Vpr
= 1.2
V ~ 1.5 V
Vpr ﹕Vdd (Power Supply)
(I) The basic WDT time-out cycle time
@Temperature=25 ℃, the typical value as followings :
Voltage (V)
Basic WDT time-out cycle time (ms)
2.3
26.4
3.0
22.8
4.0
20.1
5.0
18.46
5.5
17.9
This specification are subject to be changed without notice. Any latest information
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P. 14
2007/9
Ver. 1.8
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